- patches.fixes/patch-2.6.11-rc1: 2.6.11-rc1.
[linux-flexiantxendom0-3.2.10.git] / drivers / ide / pci / pdc202xx_old.h
1 #ifndef PDC202XX_H
2 #define PDC202XX_H
3
4 #include <linux/config.h>
5 #include <linux/pci.h>
6 #include <linux/ide.h>
7
8 #ifndef SPLIT_BYTE
9 #define SPLIT_BYTE(B,H,L)       ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
10 #endif
11
12 #define PDC202XX_DEBUG_DRIVE_INFO               0
13
14 static const char *pdc_quirk_drives[] = {
15         "QUANTUM FIREBALLlct08 08",
16         "QUANTUM FIREBALLP KA6.4",
17         "QUANTUM FIREBALLP KA9.1",
18         "QUANTUM FIREBALLP LM20.4",
19         "QUANTUM FIREBALLP KX13.6",
20         "QUANTUM FIREBALLP KX20.5",
21         "QUANTUM FIREBALLP KX27.3",
22         "QUANTUM FIREBALLP LM20.5",
23         NULL
24 };
25
26 /* A Register */
27 #define SYNC_ERRDY_EN   0xC0
28
29 #define SYNC_IN         0x80    /* control bit, different for master vs. slave drives */
30 #define ERRDY_EN        0x40    /* control bit, different for master vs. slave drives */
31 #define IORDY_EN        0x20    /* PIO: IOREADY */
32 #define PREFETCH_EN     0x10    /* PIO: PREFETCH */
33
34 #define PA3             0x08    /* PIO"A" timing */
35 #define PA2             0x04    /* PIO"A" timing */
36 #define PA1             0x02    /* PIO"A" timing */
37 #define PA0             0x01    /* PIO"A" timing */
38
39 /* B Register */
40
41 #define MB2             0x80    /* DMA"B" timing */
42 #define MB1             0x40    /* DMA"B" timing */
43 #define MB0             0x20    /* DMA"B" timing */
44
45 #define PB4             0x10    /* PIO_FORCE 1:0 */
46
47 #define PB3             0x08    /* PIO"B" timing */     /* PIO flow Control mode */
48 #define PB2             0x04    /* PIO"B" timing */     /* PIO 4 */
49 #define PB1             0x02    /* PIO"B" timing */     /* PIO 3 half */
50 #define PB0             0x01    /* PIO"B" timing */     /* PIO 3 other half */
51
52 /* C Register */
53 #define IORDYp_NO_SPEED 0x4F
54 #define SPEED_DIS       0x0F
55
56 #define DMARQp          0x80
57 #define IORDYp          0x40
58 #define DMAR_EN         0x20
59 #define DMAW_EN         0x10
60
61 #define MC3             0x08    /* DMA"C" timing */
62 #define MC2             0x04    /* DMA"C" timing */
63 #define MC1             0x02    /* DMA"C" timing */
64 #define MC0             0x01    /* DMA"C" timing */
65
66 static int init_setup_pdc202ata4(struct pci_dev *dev, ide_pci_device_t *d);
67 static int init_setup_pdc20265(struct pci_dev *, ide_pci_device_t *);
68 static int init_setup_pdc202xx(struct pci_dev *, ide_pci_device_t *);
69 static unsigned int init_chipset_pdc202xx(struct pci_dev *, const char *);
70 static void init_hwif_pdc202xx(ide_hwif_t *);
71 static void init_dma_pdc202xx(ide_hwif_t *, unsigned long);
72
73 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
74         {       /* 0 */
75                 .name           = "PDC20246",
76                 .init_setup     = init_setup_pdc202ata4,
77                 .init_chipset   = init_chipset_pdc202xx,
78                 .init_hwif      = init_hwif_pdc202xx,
79                 .init_dma       = init_dma_pdc202xx,
80                 .channels       = 2,
81                 .autodma        = AUTODMA,
82 #ifndef CONFIG_PDC202XX_FORCE
83                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
84 #endif
85                 .bootable       = OFF_BOARD,
86                 .extra          = 16,
87         },{     /* 1 */
88                 .name           = "PDC20262",
89                 .init_setup     = init_setup_pdc202ata4,
90                 .init_chipset   = init_chipset_pdc202xx,
91                 .init_hwif      = init_hwif_pdc202xx,
92                 .init_dma       = init_dma_pdc202xx,
93                 .channels       = 2,
94                 .autodma        = AUTODMA,
95 #ifndef CONFIG_PDC202XX_FORCE
96                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
97 #endif
98                 .bootable       = OFF_BOARD,
99                 .extra          = 48,
100                 .flags          = IDEPCI_FLAG_FORCE_PDC,
101         },{     /* 2 */
102                 .name           = "PDC20263",
103                 .init_setup     = init_setup_pdc202ata4,
104                 .init_chipset   = init_chipset_pdc202xx,
105                 .init_hwif      = init_hwif_pdc202xx,
106                 .init_dma       = init_dma_pdc202xx,
107                 .channels       = 2,
108                 .autodma        = AUTODMA,
109 #ifndef CONFIG_PDC202XX_FORCE
110                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
111 #endif
112                 .bootable       = OFF_BOARD,
113                 .extra          = 48,
114         },{     /* 3 */
115                 .name           = "PDC20265",
116                 .init_setup     = init_setup_pdc20265,
117                 .init_chipset   = init_chipset_pdc202xx,
118                 .init_hwif      = init_hwif_pdc202xx,
119                 .init_dma       = init_dma_pdc202xx,
120                 .channels       = 2,
121                 .autodma        = AUTODMA,
122 #ifndef CONFIG_PDC202XX_FORCE
123                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
124 #endif
125                 .bootable       = OFF_BOARD,
126                 .extra          = 48,
127                 .flags          = IDEPCI_FLAG_FORCE_PDC,
128         },{     /* 4 */
129                 .name           = "PDC20267",
130                 .init_setup     = init_setup_pdc202xx,
131                 .init_chipset   = init_chipset_pdc202xx,
132                 .init_hwif      = init_hwif_pdc202xx,
133                 .init_dma       = init_dma_pdc202xx,
134                 .channels       = 2,
135                 .autodma        = AUTODMA,
136 #ifndef CONFIG_PDC202XX_FORCE
137                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
138 #endif
139                 .bootable       = OFF_BOARD,
140                 .extra          = 48,
141         }
142 };
143
144 #endif /* PDC202XX_H */