1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
34 /* General customization:
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20020828"
43 #define DRIVER_MAJOR 1
44 #define DRIVER_MINOR 11
45 #define DRIVER_PATCHLEVEL 0
47 #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
48 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
50 typedef struct drm_radeon_freelist {
53 struct drm_radeon_freelist *next;
54 struct drm_radeon_freelist *prev;
55 } drm_radeon_freelist_t;
57 typedef struct drm_radeon_ring_buffer {
68 } drm_radeon_ring_buffer_t;
70 typedef struct drm_radeon_depth_clear_t {
72 u32 rb3d_zstencilcntl;
74 } drm_radeon_depth_clear_t;
76 struct drm_radeon_driver_file_fields {
77 int64_t radeon_fb_delta;
81 struct mem_block *next;
82 struct mem_block *prev;
85 DRMFILE filp; /* 0: free, -1: heap, other: real files */
88 typedef struct drm_radeon_private {
89 drm_radeon_ring_buffer_t ring;
90 drm_radeon_sarea_t *sarea_priv;
96 unsigned long gart_buffers_offset;
101 drm_radeon_freelist_t *head;
102 drm_radeon_freelist_t *tail;
104 volatile u32 *scratch;
112 unsigned long phys_pci_gart;
113 dma_addr_t bus_pci_gart;
117 int freelist_timeouts;
120 int last_frame_reads;
121 int last_clear_reads;
131 unsigned int front_offset;
132 unsigned int front_pitch;
133 unsigned int back_offset;
134 unsigned int back_pitch;
137 unsigned int depth_offset;
138 unsigned int depth_pitch;
140 u32 front_pitch_offset;
141 u32 back_pitch_offset;
142 u32 depth_pitch_offset;
144 drm_radeon_depth_clear_t depth_clear;
146 unsigned long fb_offset;
147 unsigned long mmio_offset;
148 unsigned long ring_offset;
149 unsigned long ring_rptr_offset;
150 unsigned long buffers_offset;
151 unsigned long gart_textures_offset;
153 drm_local_map_t *sarea;
154 drm_local_map_t *mmio;
155 drm_local_map_t *cp_ring;
156 drm_local_map_t *ring_rptr;
157 drm_local_map_t *gart_textures;
159 struct mem_block *gart_heap;
160 struct mem_block *fb_heap;
163 wait_queue_head_t swi_queue;
164 atomic_t swi_emitted;
166 } drm_radeon_private_t;
168 typedef struct drm_radeon_buf_priv {
170 } drm_radeon_buf_priv_t;
173 extern int radeon_cp_init( DRM_IOCTL_ARGS );
174 extern int radeon_cp_start( DRM_IOCTL_ARGS );
175 extern int radeon_cp_stop( DRM_IOCTL_ARGS );
176 extern int radeon_cp_reset( DRM_IOCTL_ARGS );
177 extern int radeon_cp_idle( DRM_IOCTL_ARGS );
178 extern int radeon_cp_resume( DRM_IOCTL_ARGS );
179 extern int radeon_engine_reset( DRM_IOCTL_ARGS );
180 extern int radeon_fullscreen( DRM_IOCTL_ARGS );
181 extern int radeon_cp_buffers( DRM_IOCTL_ARGS );
183 extern void radeon_freelist_reset( drm_device_t *dev );
184 extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
186 extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
188 extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
189 extern int radeon_do_cleanup_cp( drm_device_t *dev );
190 extern int radeon_do_cleanup_pageflip( drm_device_t *dev );
193 extern int radeon_cp_clear( DRM_IOCTL_ARGS );
194 extern int radeon_cp_swap( DRM_IOCTL_ARGS );
195 extern int radeon_cp_vertex( DRM_IOCTL_ARGS );
196 extern int radeon_cp_indices( DRM_IOCTL_ARGS );
197 extern int radeon_cp_texture( DRM_IOCTL_ARGS );
198 extern int radeon_cp_stipple( DRM_IOCTL_ARGS );
199 extern int radeon_cp_indirect( DRM_IOCTL_ARGS );
200 extern int radeon_cp_vertex2( DRM_IOCTL_ARGS );
201 extern int radeon_cp_cmdbuf( DRM_IOCTL_ARGS );
202 extern int radeon_cp_getparam( DRM_IOCTL_ARGS );
203 extern int radeon_cp_setparam( DRM_IOCTL_ARGS );
204 extern int radeon_cp_flip( DRM_IOCTL_ARGS );
206 extern int radeon_mem_alloc( DRM_IOCTL_ARGS );
207 extern int radeon_mem_free( DRM_IOCTL_ARGS );
208 extern int radeon_mem_init_heap( DRM_IOCTL_ARGS );
209 extern void radeon_mem_takedown( struct mem_block **heap );
210 extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap );
213 extern int radeon_irq_emit( DRM_IOCTL_ARGS );
214 extern int radeon_irq_wait( DRM_IOCTL_ARGS );
216 extern int radeon_emit_and_wait_irq(drm_device_t *dev);
217 extern int radeon_wait_irq(drm_device_t *dev, int swi_nr);
218 extern int radeon_emit_irq(drm_device_t *dev);
220 extern void radeon_do_release(drm_device_t *dev);
221 extern int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
222 extern irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS );
223 extern void radeon_driver_irq_preinstall( drm_device_t *dev );
224 extern void radeon_driver_irq_postinstall( drm_device_t *dev );
225 extern void radeon_driver_irq_uninstall( drm_device_t *dev );
226 extern void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp);
227 extern void radeon_driver_pretakedown(drm_device_t *dev);
228 extern int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv);
229 extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv);
231 extern int radeon_preinit( struct drm_device *dev, unsigned long flags );
232 extern int radeon_postinit( struct drm_device *dev, unsigned long flags );
233 extern int radeon_postcleanup( struct drm_device *dev );
235 /* Flags for stats.boxes
237 #define RADEON_BOX_DMA_IDLE 0x1
238 #define RADEON_BOX_RING_FULL 0x2
239 #define RADEON_BOX_FLIP 0x4
240 #define RADEON_BOX_WAIT_IDLE 0x8
241 #define RADEON_BOX_TEXTURE_LOAD 0x10
245 /* Register definitions, register access macros and drmAddMap constants
246 * for Radeon kernel driver.
249 #define RADEON_AGP_COMMAND 0x0f60
250 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
251 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
252 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
253 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
254 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
255 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
256 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
258 #define RADEON_BUS_CNTL 0x0030
259 # define RADEON_BUS_MASTER_DIS (1 << 6)
261 #define RADEON_CLOCK_CNTL_DATA 0x000c
262 # define RADEON_PLL_WR_EN (1 << 7)
263 #define RADEON_CLOCK_CNTL_INDEX 0x0008
264 #define RADEON_CONFIG_APER_SIZE 0x0108
265 #define RADEON_CRTC_OFFSET 0x0224
266 #define RADEON_CRTC_OFFSET_CNTL 0x0228
267 # define RADEON_CRTC_TILE_EN (1 << 15)
268 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
269 #define RADEON_CRTC2_OFFSET 0x0324
270 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
272 #define RADEON_RB3D_COLOROFFSET 0x1c40
273 #define RADEON_RB3D_COLORPITCH 0x1c48
275 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
276 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
277 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
278 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
279 # define RADEON_GMC_BRUSH_NONE (15 << 4)
280 # define RADEON_GMC_DST_16BPP (4 << 8)
281 # define RADEON_GMC_DST_24BPP (5 << 8)
282 # define RADEON_GMC_DST_32BPP (6 << 8)
283 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
284 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
285 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
286 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
287 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
288 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
289 # define RADEON_ROP3_S 0x00cc0000
290 # define RADEON_ROP3_P 0x00f00000
291 #define RADEON_DP_WRITE_MASK 0x16cc
292 #define RADEON_DST_PITCH_OFFSET 0x142c
293 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
294 # define RADEON_DST_TILE_LINEAR (0 << 30)
295 # define RADEON_DST_TILE_MACRO (1 << 30)
296 # define RADEON_DST_TILE_MICRO (2 << 30)
297 # define RADEON_DST_TILE_BOTH (3 << 30)
299 #define RADEON_SCRATCH_REG0 0x15e0
300 #define RADEON_SCRATCH_REG1 0x15e4
301 #define RADEON_SCRATCH_REG2 0x15e8
302 #define RADEON_SCRATCH_REG3 0x15ec
303 #define RADEON_SCRATCH_REG4 0x15f0
304 #define RADEON_SCRATCH_REG5 0x15f4
305 #define RADEON_SCRATCH_UMSK 0x0770
306 #define RADEON_SCRATCH_ADDR 0x0774
308 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
310 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
311 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
312 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
315 #define RADEON_GEN_INT_CNTL 0x0040
316 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
317 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
318 # define RADEON_SW_INT_ENABLE (1 << 25)
320 #define RADEON_GEN_INT_STATUS 0x0044
321 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
322 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
323 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
324 # define RADEON_SW_INT_TEST (1 << 25)
325 # define RADEON_SW_INT_TEST_ACK (1 << 25)
326 # define RADEON_SW_INT_FIRE (1 << 26)
328 #define RADEON_HOST_PATH_CNTL 0x0130
329 # define RADEON_HDP_SOFT_RESET (1 << 26)
330 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
331 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
333 #define RADEON_ISYNC_CNTL 0x1724
334 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
335 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
336 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
337 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
338 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
339 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
341 #define RADEON_RBBM_GUICNTL 0x172c
342 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
343 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
344 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
345 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
347 #define RADEON_MC_AGP_LOCATION 0x014c
348 #define RADEON_MC_FB_LOCATION 0x0148
349 #define RADEON_MCLK_CNTL 0x0012
350 # define RADEON_FORCEON_MCLKA (1 << 16)
351 # define RADEON_FORCEON_MCLKB (1 << 17)
352 # define RADEON_FORCEON_YCLKA (1 << 18)
353 # define RADEON_FORCEON_YCLKB (1 << 19)
354 # define RADEON_FORCEON_MC (1 << 20)
355 # define RADEON_FORCEON_AIC (1 << 21)
357 #define RADEON_PP_BORDER_COLOR_0 0x1d40
358 #define RADEON_PP_BORDER_COLOR_1 0x1d44
359 #define RADEON_PP_BORDER_COLOR_2 0x1d48
360 #define RADEON_PP_CNTL 0x1c38
361 # define RADEON_SCISSOR_ENABLE (1 << 1)
362 #define RADEON_PP_LUM_MATRIX 0x1d00
363 #define RADEON_PP_MISC 0x1c14
364 #define RADEON_PP_ROT_MATRIX_0 0x1d58
365 #define RADEON_PP_TXFILTER_0 0x1c54
366 #define RADEON_PP_TXOFFSET_0 0x1c5c
367 #define RADEON_PP_TXFILTER_1 0x1c6c
368 #define RADEON_PP_TXFILTER_2 0x1c84
370 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
371 # define RADEON_RB2D_DC_FLUSH (3 << 0)
372 # define RADEON_RB2D_DC_FREE (3 << 2)
373 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
374 # define RADEON_RB2D_DC_BUSY (1 << 31)
375 #define RADEON_RB3D_CNTL 0x1c3c
376 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
377 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
378 # define RADEON_DITHER_ENABLE (1 << 2)
379 # define RADEON_ROUND_ENABLE (1 << 3)
380 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
381 # define RADEON_DITHER_INIT (1 << 5)
382 # define RADEON_ROP_ENABLE (1 << 6)
383 # define RADEON_STENCIL_ENABLE (1 << 7)
384 # define RADEON_Z_ENABLE (1 << 8)
385 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
386 #define RADEON_RB3D_DEPTHPITCH 0x1c28
387 #define RADEON_RB3D_PLANEMASK 0x1d84
388 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
389 #define RADEON_RB3D_ZCACHE_MODE 0x3250
390 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
391 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
392 # define RADEON_RB3D_ZC_FREE (1 << 2)
393 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
394 # define RADEON_RB3D_ZC_BUSY (1 << 31)
395 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
396 # define RADEON_Z_TEST_MASK (7 << 4)
397 # define RADEON_Z_TEST_ALWAYS (7 << 4)
398 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
399 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
400 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
401 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
402 # define RADEON_Z_WRITE_ENABLE (1 << 30)
403 #define RADEON_RBBM_SOFT_RESET 0x00f0
404 # define RADEON_SOFT_RESET_CP (1 << 0)
405 # define RADEON_SOFT_RESET_HI (1 << 1)
406 # define RADEON_SOFT_RESET_SE (1 << 2)
407 # define RADEON_SOFT_RESET_RE (1 << 3)
408 # define RADEON_SOFT_RESET_PP (1 << 4)
409 # define RADEON_SOFT_RESET_E2 (1 << 5)
410 # define RADEON_SOFT_RESET_RB (1 << 6)
411 # define RADEON_SOFT_RESET_HDP (1 << 7)
412 #define RADEON_RBBM_STATUS 0x0e40
413 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
414 # define RADEON_RBBM_ACTIVE (1 << 31)
415 #define RADEON_RE_LINE_PATTERN 0x1cd0
416 #define RADEON_RE_MISC 0x26c4
417 #define RADEON_RE_TOP_LEFT 0x26c0
418 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
419 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
420 #define RADEON_RE_STIPPLE_DATA 0x1ccc
422 #define RADEON_SCISSOR_TL_0 0x1cd8
423 #define RADEON_SCISSOR_BR_0 0x1cdc
424 #define RADEON_SCISSOR_TL_1 0x1ce0
425 #define RADEON_SCISSOR_BR_1 0x1ce4
426 #define RADEON_SCISSOR_TL_2 0x1ce8
427 #define RADEON_SCISSOR_BR_2 0x1cec
428 #define RADEON_SE_COORD_FMT 0x1c50
429 #define RADEON_SE_CNTL 0x1c4c
430 # define RADEON_FFACE_CULL_CW (0 << 0)
431 # define RADEON_BFACE_SOLID (3 << 1)
432 # define RADEON_FFACE_SOLID (3 << 3)
433 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
434 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
435 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
436 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
437 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
438 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
439 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
440 # define RADEON_FOG_SHADE_FLAT (1 << 14)
441 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
442 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
443 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
444 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
445 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
446 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
447 #define RADEON_SE_CNTL_STATUS 0x2140
448 #define RADEON_SE_LINE_WIDTH 0x1db8
449 #define RADEON_SE_VPORT_XSCALE 0x1d98
450 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
451 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
452 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
453 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
454 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
455 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
456 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
457 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
458 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
459 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
460 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
461 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
462 #define RADEON_SURFACE_CNTL 0x0b00
463 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
464 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
465 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
466 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
467 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
468 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
469 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
470 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
471 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
472 #define RADEON_SURFACE0_INFO 0x0b0c
473 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
474 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
475 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
476 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
477 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
478 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
479 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
480 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
481 #define RADEON_SURFACE1_INFO 0x0b1c
482 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
483 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
484 #define RADEON_SURFACE2_INFO 0x0b2c
485 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
486 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
487 #define RADEON_SURFACE3_INFO 0x0b3c
488 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
489 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
490 #define RADEON_SURFACE4_INFO 0x0b4c
491 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
492 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
493 #define RADEON_SURFACE5_INFO 0x0b5c
494 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
495 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
496 #define RADEON_SURFACE6_INFO 0x0b6c
497 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
498 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
499 #define RADEON_SURFACE7_INFO 0x0b7c
500 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
501 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
502 #define RADEON_SW_SEMAPHORE 0x013c
504 #define RADEON_WAIT_UNTIL 0x1720
505 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
506 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
507 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
508 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
510 #define RADEON_RB3D_ZMASKOFFSET 0x1c34
511 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
512 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
513 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
517 #define RADEON_CP_ME_RAM_ADDR 0x07d4
518 #define RADEON_CP_ME_RAM_RADDR 0x07d8
519 #define RADEON_CP_ME_RAM_DATAH 0x07dc
520 #define RADEON_CP_ME_RAM_DATAL 0x07e0
522 #define RADEON_CP_RB_BASE 0x0700
523 #define RADEON_CP_RB_CNTL 0x0704
524 # define RADEON_BUF_SWAP_32BIT (2 << 16)
525 #define RADEON_CP_RB_RPTR_ADDR 0x070c
526 #define RADEON_CP_RB_RPTR 0x0710
527 #define RADEON_CP_RB_WPTR 0x0714
529 #define RADEON_CP_RB_WPTR_DELAY 0x0718
530 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
531 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
533 #define RADEON_CP_IB_BASE 0x0738
535 #define RADEON_CP_CSQ_CNTL 0x0740
536 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
537 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
538 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
539 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
540 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
541 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
542 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
544 #define RADEON_AIC_CNTL 0x01d0
545 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
546 #define RADEON_AIC_STAT 0x01d4
547 #define RADEON_AIC_PT_BASE 0x01d8
548 #define RADEON_AIC_LO_ADDR 0x01dc
549 #define RADEON_AIC_HI_ADDR 0x01e0
550 #define RADEON_AIC_TLB_ADDR 0x01e4
551 #define RADEON_AIC_TLB_DATA 0x01e8
553 /* CP command packets */
554 #define RADEON_CP_PACKET0 0x00000000
555 # define RADEON_ONE_REG_WR (1 << 15)
556 #define RADEON_CP_PACKET1 0x40000000
557 #define RADEON_CP_PACKET2 0x80000000
558 #define RADEON_CP_PACKET3 0xC0000000
559 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
560 # define RADEON_WAIT_FOR_IDLE 0x00002600
561 # define RADEON_3D_DRAW_VBUF 0x00002800
562 # define RADEON_3D_DRAW_IMMD 0x00002900
563 # define RADEON_3D_DRAW_INDX 0x00002A00
564 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
565 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
566 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
567 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
568 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
570 #define RADEON_CP_PACKET_MASK 0xC0000000
571 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
572 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
573 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
574 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
576 #define RADEON_VTX_Z_PRESENT (1 << 31)
577 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
579 #define RADEON_PRIM_TYPE_NONE (0 << 0)
580 #define RADEON_PRIM_TYPE_POINT (1 << 0)
581 #define RADEON_PRIM_TYPE_LINE (2 << 0)
582 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
583 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
584 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
585 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
586 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
587 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
588 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
589 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
590 #define RADEON_PRIM_TYPE_MASK 0xf
591 #define RADEON_PRIM_WALK_IND (1 << 4)
592 #define RADEON_PRIM_WALK_LIST (2 << 4)
593 #define RADEON_PRIM_WALK_RING (3 << 4)
594 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
595 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
596 #define RADEON_MAOS_ENABLE (1 << 7)
597 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
598 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
599 #define RADEON_NUM_VERTICES_SHIFT 16
601 #define RADEON_COLOR_FORMAT_CI8 2
602 #define RADEON_COLOR_FORMAT_ARGB1555 3
603 #define RADEON_COLOR_FORMAT_RGB565 4
604 #define RADEON_COLOR_FORMAT_ARGB8888 6
605 #define RADEON_COLOR_FORMAT_RGB332 7
606 #define RADEON_COLOR_FORMAT_RGB8 9
607 #define RADEON_COLOR_FORMAT_ARGB4444 15
609 #define RADEON_TXFORMAT_I8 0
610 #define RADEON_TXFORMAT_AI88 1
611 #define RADEON_TXFORMAT_RGB332 2
612 #define RADEON_TXFORMAT_ARGB1555 3
613 #define RADEON_TXFORMAT_RGB565 4
614 #define RADEON_TXFORMAT_ARGB4444 5
615 #define RADEON_TXFORMAT_ARGB8888 6
616 #define RADEON_TXFORMAT_RGBA8888 7
617 #define RADEON_TXFORMAT_Y8 8
618 #define RADEON_TXFORMAT_VYUY422 10
619 #define RADEON_TXFORMAT_YVYU422 11
620 #define RADEON_TXFORMAT_DXT1 12
621 #define RADEON_TXFORMAT_DXT23 14
622 #define RADEON_TXFORMAT_DXT45 15
624 #define R200_PP_TXCBLEND_0 0x2f00
625 #define R200_PP_TXCBLEND_1 0x2f10
626 #define R200_PP_TXCBLEND_2 0x2f20
627 #define R200_PP_TXCBLEND_3 0x2f30
628 #define R200_PP_TXCBLEND_4 0x2f40
629 #define R200_PP_TXCBLEND_5 0x2f50
630 #define R200_PP_TXCBLEND_6 0x2f60
631 #define R200_PP_TXCBLEND_7 0x2f70
632 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
633 #define R200_PP_TFACTOR_0 0x2ee0
634 #define R200_SE_VTX_FMT_0 0x2088
635 #define R200_SE_VAP_CNTL 0x2080
636 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
637 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
638 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
639 #define R200_PP_TXFILTER_5 0x2ca0
640 #define R200_PP_TXFILTER_4 0x2c80
641 #define R200_PP_TXFILTER_3 0x2c60
642 #define R200_PP_TXFILTER_2 0x2c40
643 #define R200_PP_TXFILTER_1 0x2c20
644 #define R200_PP_TXFILTER_0 0x2c00
645 #define R200_PP_TXOFFSET_5 0x2d78
646 #define R200_PP_TXOFFSET_4 0x2d60
647 #define R200_PP_TXOFFSET_3 0x2d48
648 #define R200_PP_TXOFFSET_2 0x2d30
649 #define R200_PP_TXOFFSET_1 0x2d18
650 #define R200_PP_TXOFFSET_0 0x2d00
652 #define R200_PP_CUBIC_FACES_0 0x2c18
653 #define R200_PP_CUBIC_FACES_1 0x2c38
654 #define R200_PP_CUBIC_FACES_2 0x2c58
655 #define R200_PP_CUBIC_FACES_3 0x2c78
656 #define R200_PP_CUBIC_FACES_4 0x2c98
657 #define R200_PP_CUBIC_FACES_5 0x2cb8
658 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
659 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
660 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
661 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
662 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
663 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
664 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
665 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
666 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
667 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
668 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
669 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
670 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
671 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
672 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
673 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
674 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
675 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
676 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
677 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
678 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
679 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
680 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
681 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
682 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
683 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
684 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
685 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
686 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
687 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
689 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
690 #define R200_SE_VTE_CNTL 0x20b0
691 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
692 #define R200_PP_TAM_DEBUG3 0x2d9c
693 #define R200_PP_CNTL_X 0x2cc4
694 #define R200_SE_VAP_CNTL_STATUS 0x2140
695 #define R200_RE_SCISSOR_TL_0 0x1cd8
696 #define R200_RE_SCISSOR_TL_1 0x1ce0
697 #define R200_RE_SCISSOR_TL_2 0x1ce8
698 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
699 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
700 #define R200_SE_VTX_STATE_CNTL 0x2180
701 #define R200_RE_POINTSIZE 0x2648
702 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
704 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
705 #define RADEON_PP_TEX_SIZE_1 0x1d0c
706 #define RADEON_PP_TEX_SIZE_2 0x1d14
709 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
710 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
711 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
712 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
713 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
714 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
715 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
716 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
717 #define R200_3D_DRAW_IMMD_2 0xC0003500
718 #define R200_SE_VTX_FMT_1 0x208c
719 #define R200_RE_CNTL 0x1c50
721 #define R200_RB3D_BLENDCOLOR 0x3218
724 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
726 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
727 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
728 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
729 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
730 #define RADEON_LAST_DISPATCH 1
732 #define RADEON_MAX_VB_AGE 0x7fffffff
733 #define RADEON_MAX_VB_VERTS (0xffff)
735 #define RADEON_RING_HIGH_MARK 128
737 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
738 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
739 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
740 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
742 #define RADEON_WRITE_PLL( addr, val ) \
744 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
745 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
746 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
749 extern int RADEON_READ_PLL( drm_device_t *dev, int addr );
752 #define CP_PACKET0( reg, n ) \
753 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
754 #define CP_PACKET0_TABLE( reg, n ) \
755 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
756 #define CP_PACKET1( reg0, reg1 ) \
757 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
758 #define CP_PACKET2() \
760 #define CP_PACKET3( pkt, n ) \
761 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
764 /* ================================================================
765 * Engine control helper macros
768 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
769 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
770 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
771 RADEON_WAIT_HOST_IDLECLEAN) ); \
774 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
775 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
776 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
777 RADEON_WAIT_HOST_IDLECLEAN) ); \
780 #define RADEON_WAIT_UNTIL_IDLE() do { \
781 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
782 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
783 RADEON_WAIT_3D_IDLECLEAN | \
784 RADEON_WAIT_HOST_IDLECLEAN) ); \
787 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
788 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
789 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
792 #define RADEON_FLUSH_CACHE() do { \
793 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
794 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
797 #define RADEON_PURGE_CACHE() do { \
798 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
799 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
802 #define RADEON_FLUSH_ZCACHE() do { \
803 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
804 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
807 #define RADEON_PURGE_ZCACHE() do { \
808 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
809 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
813 /* ================================================================
817 /* Perfbox functionality only.
819 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
821 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
822 u32 head = GET_RING_HEAD( dev_priv ); \
823 if (head == dev_priv->ring.tail) \
824 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
828 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
830 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
831 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
832 int __ret = radeon_do_cp_idle( dev_priv ); \
833 if ( __ret ) return __ret; \
834 sarea_priv->last_dispatch = 0; \
835 radeon_freelist_reset( dev ); \
839 #define RADEON_DISPATCH_AGE( age ) do { \
840 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
844 #define RADEON_FRAME_AGE( age ) do { \
845 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
849 #define RADEON_CLEAR_AGE( age ) do { \
850 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
855 /* ================================================================
859 #define RADEON_VERBOSE 0
861 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
863 #define BEGIN_RING( n ) do { \
864 if ( RADEON_VERBOSE ) { \
865 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
868 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
870 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
872 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
873 ring = dev_priv->ring.start; \
874 write = dev_priv->ring.tail; \
875 mask = dev_priv->ring.tail_mask; \
878 #define ADVANCE_RING() do { \
879 if ( RADEON_VERBOSE ) { \
880 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
881 write, dev_priv->ring.tail ); \
883 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
885 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
886 ((dev_priv->ring.tail + _nr) & mask), \
889 dev_priv->ring.tail = write; \
892 #define COMMIT_RING() do { \
893 /* Flush writes to ring */ \
894 DRM_MEMORYBARRIER(); \
895 GET_RING_HEAD( dev_priv ); \
896 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
897 /* read from PCI bus to ensure correct posting */ \
898 RADEON_READ( RADEON_CP_RB_RPTR ); \
901 #define OUT_RING( x ) do { \
902 if ( RADEON_VERBOSE ) { \
903 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
904 (unsigned int)(x), write ); \
906 ring[write++] = (x); \
910 #define OUT_RING_REG( reg, val ) do { \
911 OUT_RING( CP_PACKET0( reg, 0 ) ); \
916 #define OUT_RING_USER_TABLE( tab, sz ) do { \
918 int __user *_tab = (tab); \
920 if (write + _size > mask) { \
921 int i = (mask+1) - write; \
922 if (DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \
924 return DRM_ERR(EFAULT); \
930 if (_size && DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \
932 return DRM_ERR(EFAULT); \
939 #endif /* __RADEON_DRV_H__ */