arch/ia64/kernel/mca.c

   1 /*
   2  * File:        mca.c
   3  * Purpose:     Generic MCA handling layer
   4  *
   5  * Updated for latest kernel
   6  * Copyright (C) 2003 Hewlett-Packard Co
   7  *      David Mosberger-Tang <davidm@hpl.hp.com>
   8  *
   9  * Copyright (C) 2002 Dell Inc.
  10  * Copyright (C) Matt Domsch (Matt_Domsch@dell.com)
  11  *
  12  * Copyright (C) 2002 Intel
  13  * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
  14  *
  15  * Copyright (C) 2001 Intel
  16  * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
  17  *
  18  * Copyright (C) 2000 Intel
  19  * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com)
  20  *
  21  * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
  22  * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
  23  *
  24  * 03/04/15 D. Mosberger Added INIT backtrace support.
  25  * 02/03/25 M. Domsch   GUID cleanups
  26  *
  27  * 02/01/04 J. Hall     Aligned MCA stack to 16 bytes, added platform vs. CPU
  28  *                      error flag, set SAL default return values, changed
  29  *                      error record structure to linked list, added init call
  30  *                      to sal_get_state_info_size().
  31  *
  32  * 01/01/03 F. Lewis    Added setup of CMCI and CPEI IRQs, logging of corrected
  33  *                      platform errors, completed code for logging of
  34  *                      corrected & uncorrected machine check errors, and
  35  *                      updated for conformance with Nov. 2000 revision of the
  36  *                      SAL 3.0 spec.
  37  * 00/03/29 C. Fleckenstein  Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
  38  *                           added min save state dump, added INIT handler.
  39  *
  40  * 2003-12-08 Keith Owens <kaos@sgi.com>
  41  *            smp_call_function() must not be called from interrupt context (can
  42  *            deadlock on tasklist_lock).  Use keventd to call smp_call_function().
  43  *
  44  * 2004-02-01 Keith Owens <kaos@sgi.com>
  45  *            Avoid deadlock when using printk() for MCA and INIT records.
  46  *            Delete all record printing code, moved to salinfo_decode in user space.
  47  *            Mark variables and functions static where possible.
  48  *            Delete dead variables and functions.
  49  *            Reorder to remove the need for forward declarations and to consolidate
  50  *            related code.
  51  */
  52 #include <linux/config.h>
  53 #include <linux/types.h>
  54 #include <linux/init.h>
  55 #include <linux/sched.h>
  56 #include <linux/interrupt.h>
  57 #include <linux/irq.h>
  58 #include <linux/kallsyms.h>
  59 #include <linux/smp_lock.h>
  60 #include <linux/bootmem.h>
  61 #include <linux/acpi.h>
  62 #include <linux/timer.h>
  63 #include <linux/module.h>
  64 #include <linux/kernel.h>
  65 #include <linux/smp.h>
  66 #include <linux/workqueue.h>
  67
  68 #include <asm/delay.h>
  69 #include <asm/machvec.h>
  70 #include <asm/page.h>
  71 #include <asm/ptrace.h>
  72 #include <asm/system.h>
  73 #include <asm/sal.h>
  74 #include <asm/mca.h>
  75
  76 #include <asm/irq.h>
  77 #include <asm/hw_irq.h>
  78
  79 #if defined(IA64_MCA_DEBUG_INFO)
  80 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
  81 #else
  82 # define IA64_MCA_DEBUG(fmt...)
  83 #endif
  84
  85 /* Used by mca_asm.S */
  86 ia64_mca_sal_to_os_state_t      ia64_sal_to_os_handoff_state;
  87 ia64_mca_os_to_sal_state_t      ia64_os_to_sal_handoff_state;
  88 u64                             ia64_mca_proc_state_dump[512];
  89 u64                             ia64_mca_stack[1024] __attribute__((aligned(16)));
  90 u64                             ia64_mca_stackframe[32];
  91 u64                             ia64_mca_bspstore[1024];
  92 u64                             ia64_init_stack[KERNEL_STACK_SIZE/8] __attribute__((aligned(16)));
  93 u64                             ia64_mca_serialize;
  94
  95 /* In mca_asm.S */
  96 extern void                     ia64_monarch_init_handler (void);
  97 extern void                     ia64_slave_init_handler (void);
  98
  99 static ia64_mc_info_t           ia64_mc_info;
 100
 101 struct ia64_mca_tlb_info ia64_mca_tlb_list[NR_CPUS];
 102
 103 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
 104 #define MIN_CPE_POLL_INTERVAL (2*60*HZ)  /* 2 minutes */
 105 #define CMC_POLL_INTERVAL     (1*60*HZ)  /* 1 minute */
 106 #define CPE_HISTORY_LENGTH    5
 107 #define CMC_HISTORY_LENGTH    5
 108
 109 static struct timer_list cpe_poll_timer;
 110 static struct timer_list cmc_poll_timer;
 111 /*
 112  * This variable tells whether we are currently in polling mode.
 113  * Start with this in the wrong state so we won't play w/ timers
 114  * before the system is ready.
 115  */
 116 static int cmc_polling_enabled = 1;
 117
 118 /*
 119  * Clearing this variable prevents CPE polling from getting activated
 120  * in mca_late_init.  Use it if your system doesn't provide a CPEI,
 121  * but encounters problems retrieving CPE logs.  This should only be
 122  * necessary for debugging.
 123  */
 124 static int cpe_poll_enabled = 1;
 125
 126 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
 127
 128 static int mca_init;
 129
 130 /*
 131  * IA64_MCA log support
 132  */
 133 #define IA64_MAX_LOGS           2       /* Double-buffering for nested MCAs */
 134 #define IA64_MAX_LOG_TYPES      4   /* MCA, INIT, CMC, CPE */
 135
 136 typedef struct ia64_state_log_s
 137 {
 138         spinlock_t      isl_lock;
 139         int             isl_index;
 140         unsigned long   isl_count;
 141         ia64_err_rec_t  *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
 142 } ia64_state_log_t;
 143
 144 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
 145
 146 #define IA64_LOG_ALLOCATE(it, size) \
 147         {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
 148                 (ia64_err_rec_t *)alloc_bootmem(size); \
 149         ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
 150                 (ia64_err_rec_t *)alloc_bootmem(size);}
 151 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
 152 #define IA64_LOG_LOCK(it)      spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
 153 #define IA64_LOG_UNLOCK(it)    spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
 154 #define IA64_LOG_NEXT_INDEX(it)    ia64_state_log[it].isl_index
 155 #define IA64_LOG_CURR_INDEX(it)    1 - ia64_state_log[it].isl_index
 156 #define IA64_LOG_INDEX_INC(it) \
 157     {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
 158     ia64_state_log[it].isl_count++;}
 159 #define IA64_LOG_INDEX_DEC(it) \
 160     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
 161 #define IA64_LOG_NEXT_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
 162 #define IA64_LOG_CURR_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
 163 #define IA64_LOG_COUNT(it)         ia64_state_log[it].isl_count
 164
 165 /*
 166  * ia64_log_init
 167  *      Reset the OS ia64 log buffer
 168  * Inputs   :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
 169  * Outputs      :       None
 170  */
 171 static void
 172 ia64_log_init(int sal_info_type)
 173 {
 174         u64     max_size = 0;
 175
 176         IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
 177         IA64_LOG_LOCK_INIT(sal_info_type);
 178
 179         // SAL will tell us the maximum size of any error record of this type
 180         max_size = ia64_sal_get_state_info_size(sal_info_type);
 181         if (!max_size)
 182                 /* alloc_bootmem() doesn't like zero-sized allocations! */
 183                 return;
 184
 185         // set up OS data structures to hold error info
 186         IA64_LOG_ALLOCATE(sal_info_type, max_size);
 187         memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
 188         memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
 189 }
 190
 191 /*
 192  * ia64_log_get
 193  *
 194  *      Get the current MCA log from SAL and copy it into the OS log buffer.
 195  *
 196  *  Inputs  :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
 197  *              irq_safe    whether you can use printk at this point
 198  *  Outputs :   size        (total record length)
 199  *              *buffer     (ptr to error record)
 200  *
 201  */
 202 static u64
 203 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
 204 {
 205         sal_log_record_header_t     *log_buffer;
 206         u64                         total_len = 0;
 207         int                         s;
 208
 209         IA64_LOG_LOCK(sal_info_type);
 210
 211         /* Get the process state information */
 212         log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
 213
 214         total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
 215
 216         if (total_len) {
 217                 IA64_LOG_INDEX_INC(sal_info_type);
 218                 IA64_LOG_UNLOCK(sal_info_type);
 219                 if (irq_safe) {
 220                         IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. "
 221                                        "Record length = %ld\n", __FUNCTION__, sal_info_type, total_len);
 222                 }
 223                 *buffer = (u8 *) log_buffer;
 224                 return total_len;
 225         } else {
 226                 IA64_LOG_UNLOCK(sal_info_type);
 227                 return 0;
 228         }
 229 }
 230
 231 /*
 232  *  ia64_mca_log_sal_error_record
 233  *
 234  *  This function retrieves a specified error record type from SAL
 235  *  and wakes up any processes waiting for error records.
 236  *
 237  *  Inputs  :   sal_info_type   (Type of error record MCA/CMC/CPE/INIT)
 238  */
 239 static void
 240 ia64_mca_log_sal_error_record(int sal_info_type)
 241 {
 242         u8 *buffer;
 243         u64 size;
 244         int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA && sal_info_type != SAL_INFO_TYPE_INIT;
 245 #ifdef IA64_MCA_DEBUG_INFO
 246         static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
 247 #endif
 248
 249         size = ia64_log_get(sal_info_type, &buffer, irq_safe);
 250         if (!size)
 251                 return;
 252
 253         salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
 254
 255         if (irq_safe)
 256                 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
 257                         smp_processor_id(),
 258                         sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
 259
 260         /* Clear logs from corrected errors in case there's no user-level logger */
 261         if (sal_info_type == SAL_INFO_TYPE_CPE || sal_info_type == SAL_INFO_TYPE_CMC)
 262                 ia64_sal_clear_state_info(sal_info_type);
 263 }
 264
 265 /*
 266  * platform dependent error handling
 267  */
 268 #ifndef PLATFORM_MCA_HANDLERS
 269
 270 #ifdef CONFIG_ACPI
 271
 272 static int cpe_vector = -1;
 273
 274 static irqreturn_t
 275 ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs)
 276 {
 277         static unsigned long    cpe_history[CPE_HISTORY_LENGTH];
 278         static int              index;
 279         static spinlock_t       cpe_history_lock = SPIN_LOCK_UNLOCKED;
 280
 281         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
 282                        __FUNCTION__, cpe_irq, smp_processor_id());
 283
 284         /* SAL spec states this should run w/ interrupts enabled */
 285         local_irq_enable();
 286
 287         /* Get the CPE error record and log it */
 288         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
 289
 290         spin_lock(&cpe_history_lock);
 291         if (!cpe_poll_enabled && cpe_vector >= 0) {
 292
 293                 int i, count = 1; /* we know 1 happened now */
 294                 unsigned long now = jiffies;
 295
 296                 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
 297                         if (now - cpe_history[i] <= HZ)
 298                                 count++;
 299                 }
 300
 301                 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
 302                 if (count >= CPE_HISTORY_LENGTH) {
 303
 304                         cpe_poll_enabled = 1;
 305                         spin_unlock(&cpe_history_lock);
 306                         disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
 307
 308                         /*
 309                          * Corrected errors will still be corrected, but
 310                          * make sure there's a log somewhere that indicates
 311                          * something is generating more than we can handle.
 312                          */
 313                         printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
 314
 315                         mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
 316
 317                         /* lock already released, get out now */
 318                         return IRQ_HANDLED;
 319                 } else {
 320                         cpe_history[index++] = now;
 321                         if (index == CPE_HISTORY_LENGTH)
 322                                 index = 0;
 323                 }
 324         }
 325         spin_unlock(&cpe_history_lock);
 326         return IRQ_HANDLED;
 327 }
 328
 329 #endif /* CONFIG_ACPI */
 330
 331 static void
 332 show_min_state (pal_min_state_area_t *minstate)
 333 {
 334         u64 iip = minstate->pmsa_iip + ((struct ia64_psr *)(&minstate->pmsa_ipsr))->ri;
 335         u64 xip = minstate->pmsa_xip + ((struct ia64_psr *)(&minstate->pmsa_xpsr))->ri;
 336
 337         printk("NaT bits\t%016lx\n", minstate->pmsa_nat_bits);
 338         printk("pr\t\t%016lx\n", minstate->pmsa_pr);
 339         printk("b0\t\t%016lx ", minstate->pmsa_br0); print_symbol("%s\n", minstate->pmsa_br0);
 340         printk("ar.rsc\t\t%016lx\n", minstate->pmsa_rsc);
 341         printk("cr.iip\t\t%016lx ", iip); print_symbol("%s\n", iip);
 342         printk("cr.ipsr\t\t%016lx\n", minstate->pmsa_ipsr);
 343         printk("cr.ifs\t\t%016lx\n", minstate->pmsa_ifs);
 344         printk("xip\t\t%016lx ", xip); print_symbol("%s\n", xip);
 345         printk("xpsr\t\t%016lx\n", minstate->pmsa_xpsr);
 346         printk("xfs\t\t%016lx\n", minstate->pmsa_xfs);
 347         printk("b1\t\t%016lx ", minstate->pmsa_br1);
 348         print_symbol("%s\n", minstate->pmsa_br1);
 349
 350         printk("\nstatic registers r0-r15:\n");
 351         printk(" r0- 3 %016lx %016lx %016lx %016lx\n",
 352                0UL, minstate->pmsa_gr[0], minstate->pmsa_gr[1], minstate->pmsa_gr[2]);
 353         printk(" r4- 7 %016lx %016lx %016lx %016lx\n",
 354                minstate->pmsa_gr[3], minstate->pmsa_gr[4],
 355                minstate->pmsa_gr[5], minstate->pmsa_gr[6]);
 356         printk(" r8-11 %016lx %016lx %016lx %016lx\n",
 357                minstate->pmsa_gr[7], minstate->pmsa_gr[8],
 358                minstate->pmsa_gr[9], minstate->pmsa_gr[10]);
 359         printk("r12-15 %016lx %016lx %016lx %016lx\n",
 360                minstate->pmsa_gr[11], minstate->pmsa_gr[12],
 361                minstate->pmsa_gr[13], minstate->pmsa_gr[14]);
 362
 363         printk("\nbank 0:\n");
 364         printk("r16-19 %016lx %016lx %016lx %016lx\n",
 365                minstate->pmsa_bank0_gr[0], minstate->pmsa_bank0_gr[1],
 366                minstate->pmsa_bank0_gr[2], minstate->pmsa_bank0_gr[3]);
 367         printk("r20-23 %016lx %016lx %016lx %016lx\n",
 368                minstate->pmsa_bank0_gr[4], minstate->pmsa_bank0_gr[5],
 369                minstate->pmsa_bank0_gr[6], minstate->pmsa_bank0_gr[7]);
 370         printk("r24-27 %016lx %016lx %016lx %016lx\n",
 371                minstate->pmsa_bank0_gr[8], minstate->pmsa_bank0_gr[9],
 372                minstate->pmsa_bank0_gr[10], minstate->pmsa_bank0_gr[11]);
 373         printk("r28-31 %016lx %016lx %016lx %016lx\n",
 374                minstate->pmsa_bank0_gr[12], minstate->pmsa_bank0_gr[13],
 375                minstate->pmsa_bank0_gr[14], minstate->pmsa_bank0_gr[15]);
 376
 377         printk("\nbank 1:\n");
 378         printk("r16-19 %016lx %016lx %016lx %016lx\n",
 379                minstate->pmsa_bank1_gr[0], minstate->pmsa_bank1_gr[1],
 380                minstate->pmsa_bank1_gr[2], minstate->pmsa_bank1_gr[3]);
 381         printk("r20-23 %016lx %016lx %016lx %016lx\n",
 382                minstate->pmsa_bank1_gr[4], minstate->pmsa_bank1_gr[5],
 383                minstate->pmsa_bank1_gr[6], minstate->pmsa_bank1_gr[7]);
 384         printk("r24-27 %016lx %016lx %016lx %016lx\n",
 385                minstate->pmsa_bank1_gr[8], minstate->pmsa_bank1_gr[9],
 386                minstate->pmsa_bank1_gr[10], minstate->pmsa_bank1_gr[11]);
 387         printk("r28-31 %016lx %016lx %016lx %016lx\n",
 388                minstate->pmsa_bank1_gr[12], minstate->pmsa_bank1_gr[13],
 389                minstate->pmsa_bank1_gr[14], minstate->pmsa_bank1_gr[15]);
 390 }
 391
 392 static void
 393 fetch_min_state (pal_min_state_area_t *ms, struct pt_regs *pt, struct switch_stack *sw)
 394 {
 395         u64 *dst_banked, *src_banked, bit, shift, nat_bits;
 396         int i;
 397
 398         /*
 399          * First, update the pt-regs and switch-stack structures with the contents stored
 400          * in the min-state area:
 401          */
 402         if (((struct ia64_psr *) &ms->pmsa_ipsr)->ic == 0) {
 403                 pt->cr_ipsr = ms->pmsa_xpsr;
 404                 pt->cr_iip = ms->pmsa_xip;
 405                 pt->cr_ifs = ms->pmsa_xfs;
 406         } else {
 407                 pt->cr_ipsr = ms->pmsa_ipsr;
 408                 pt->cr_iip = ms->pmsa_iip;
 409                 pt->cr_ifs = ms->pmsa_ifs;
 410         }
 411         pt->ar_rsc = ms->pmsa_rsc;
 412         pt->pr = ms->pmsa_pr;
 413         pt->r1 = ms->pmsa_gr[0];
 414         pt->r2 = ms->pmsa_gr[1];
 415         pt->r3 = ms->pmsa_gr[2];
 416         sw->r4 = ms->pmsa_gr[3];
 417         sw->r5 = ms->pmsa_gr[4];
 418         sw->r6 = ms->pmsa_gr[5];
 419         sw->r7 = ms->pmsa_gr[6];
 420         pt->r8 = ms->pmsa_gr[7];
 421         pt->r9 = ms->pmsa_gr[8];
 422         pt->r10 = ms->pmsa_gr[9];
 423         pt->r11 = ms->pmsa_gr[10];
 424         pt->r12 = ms->pmsa_gr[11];
 425         pt->r13 = ms->pmsa_gr[12];
 426         pt->r14 = ms->pmsa_gr[13];
 427         pt->r15 = ms->pmsa_gr[14];
 428         dst_banked = &pt->r16;          /* r16-r31 are contiguous in struct pt_regs */
 429         src_banked = ms->pmsa_bank1_gr;
 430         for (i = 0; i < 16; ++i)
 431                 dst_banked[i] = src_banked[i];
 432         pt->b0 = ms->pmsa_br0;
 433         sw->b1 = ms->pmsa_br1;
 434
 435         /* construct the NaT bits for the pt-regs structure: */
 436 #       define PUT_NAT_BIT(dst, addr)                                   \
 437         do {                                                            \
 438                 bit = nat_bits & 1; nat_bits >>= 1;                     \
 439                 shift = ((unsigned long) addr >> 3) & 0x3f;             \
 440                 dst = ((dst) & ~(1UL << shift)) | (bit << shift);       \
 441         } while (0)
 442
 443         /* Rotate the saved NaT bits such that bit 0 corresponds to pmsa_gr[0]: */
 444         shift = ((unsigned long) &ms->pmsa_gr[0] >> 3) & 0x3f;
 445         nat_bits = (ms->pmsa_nat_bits >> shift) | (ms->pmsa_nat_bits << (64 - shift));
 446
 447         PUT_NAT_BIT(sw->caller_unat, &pt->r1);
 448         PUT_NAT_BIT(sw->caller_unat, &pt->r2);
 449         PUT_NAT_BIT(sw->caller_unat, &pt->r3);
 450         PUT_NAT_BIT(sw->ar_unat, &sw->r4);
 451         PUT_NAT_BIT(sw->ar_unat, &sw->r5);
 452         PUT_NAT_BIT(sw->ar_unat, &sw->r6);
 453         PUT_NAT_BIT(sw->ar_unat, &sw->r7);
 454         PUT_NAT_BIT(sw->caller_unat, &pt->r8);  PUT_NAT_BIT(sw->caller_unat, &pt->r9);
 455         PUT_NAT_BIT(sw->caller_unat, &pt->r10); PUT_NAT_BIT(sw->caller_unat, &pt->r11);
 456         PUT_NAT_BIT(sw->caller_unat, &pt->r12); PUT_NAT_BIT(sw->caller_unat, &pt->r13);
 457         PUT_NAT_BIT(sw->caller_unat, &pt->r14); PUT_NAT_BIT(sw->caller_unat, &pt->r15);
 458         nat_bits >>= 16;        /* skip over bank0 NaT bits */
 459         PUT_NAT_BIT(sw->caller_unat, &pt->r16); PUT_NAT_BIT(sw->caller_unat, &pt->r17);
 460         PUT_NAT_BIT(sw->caller_unat, &pt->r18); PUT_NAT_BIT(sw->caller_unat, &pt->r19);
 461         PUT_NAT_BIT(sw->caller_unat, &pt->r20); PUT_NAT_BIT(sw->caller_unat, &pt->r21);
 462         PUT_NAT_BIT(sw->caller_unat, &pt->r22); PUT_NAT_BIT(sw->caller_unat, &pt->r23);
 463         PUT_NAT_BIT(sw->caller_unat, &pt->r24); PUT_NAT_BIT(sw->caller_unat, &pt->r25);
 464         PUT_NAT_BIT(sw->caller_unat, &pt->r26); PUT_NAT_BIT(sw->caller_unat, &pt->r27);
 465         PUT_NAT_BIT(sw->caller_unat, &pt->r28); PUT_NAT_BIT(sw->caller_unat, &pt->r29);
 466         PUT_NAT_BIT(sw->caller_unat, &pt->r30); PUT_NAT_BIT(sw->caller_unat, &pt->r31);
 467 }
 468
 469 static void
 470 init_handler_platform (pal_min_state_area_t *ms,
 471                        struct pt_regs *pt, struct switch_stack *sw)
 472 {
 473         struct unw_frame_info info;
 474
 475         /* if a kernel debugger is available call it here else just dump the registers */
 476
 477         /*
 478          * Wait for a bit.  On some machines (e.g., HP's zx2000 and zx6000, INIT can be
 479          * generated via the BMC's command-line interface, but since the console is on the
 480          * same serial line, the user will need some time to switch out of the BMC before
 481          * the dump begins.
 482          */
 483         printk("Delaying for 5 seconds...\n");
 484         udelay(5*1000000);
 485         show_min_state(ms);
 486
 487         printk("Backtrace of current task (pid %d, %s)\n", current->pid, current->comm);
 488         fetch_min_state(ms, pt, sw);
 489         unw_init_from_interruption(&info, current, pt, sw);
 490         ia64_do_show_stack(&info, NULL);
 491
 492 #ifdef CONFIG_SMP
 493         /* read_trylock() would be handy... */
 494         if (!tasklist_lock.write_lock)
 495                 read_lock(&tasklist_lock);
 496 #endif
 497         {
 498                 struct task_struct *g, *t;
 499                 do_each_thread (g, t) {
 500                         if (t == current)
 501                                 continue;
 502
 503                         printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
 504                         show_stack(t, NULL);
 505                 } while_each_thread (g, t);
 506         }
 507 #ifdef CONFIG_SMP
 508         if (!tasklist_lock.write_lock)
 509                 read_unlock(&tasklist_lock);
 510 #endif
 511
 512         printk("\nINIT dump complete.  Please reboot now.\n");
 513         while (1);                      /* hang city if no debugger */
 514 }
 515
 516 #ifdef CONFIG_ACPI
 517 /*
 518  * ia64_mca_register_cpev
 519  *
 520  *  Register the corrected platform error vector with SAL.
 521  *
 522  *  Inputs
 523  *      cpev        Corrected Platform Error Vector number
 524  *
 525  *  Outputs
 526  *      None
 527  */
 528 static void
 529 ia64_mca_register_cpev (int cpev)
 530 {
 531         /* Register the CPE interrupt vector with SAL */
 532         struct ia64_sal_retval isrv;
 533
 534         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
 535         if (isrv.status) {
 536                 printk(KERN_ERR "Failed to register Corrected Platform "
 537                        "Error interrupt vector with SAL (status %ld)\n", isrv.status);
 538                 return;
 539         }
 540
 541         IA64_MCA_DEBUG("%s: corrected platform error "
 542                        "vector %#x registered\n", __FUNCTION__, cpev);
 543 }
 544 #endif /* CONFIG_ACPI */
 545
 546 #endif /* PLATFORM_MCA_HANDLERS */
 547
 548 /*
 549  * ia64_mca_cmc_vector_setup
 550  *
 551  *  Setup the corrected machine check vector register in the processor.
 552  *  (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
 553  *  This function is invoked on a per-processor basis.
 554  *
 555  * Inputs
 556  *      None
 557  *
 558  * Outputs
 559  *      None
 560  */
 561 void
 562 ia64_mca_cmc_vector_setup (void)
 563 {
 564         cmcv_reg_t      cmcv;
 565
 566         cmcv.cmcv_regval        = 0;
 567         cmcv.cmcv_mask          = 1;        /* Mask/disable interrupt at first */
 568         cmcv.cmcv_vector        = IA64_CMC_VECTOR;
 569         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 570
 571         IA64_MCA_DEBUG("%s: CPU %d corrected "
 572                        "machine check vector %#x registered.\n",
 573                        __FUNCTION__, smp_processor_id(), IA64_CMC_VECTOR);
 574
 575         IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
 576                        __FUNCTION__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
 577 }
 578
 579 /*
 580  * ia64_mca_cmc_vector_disable
 581  *
 582  *  Mask the corrected machine check vector register in the processor.
 583  *  This function is invoked on a per-processor basis.
 584  *
 585  * Inputs
 586  *      dummy(unused)
 587  *
 588  * Outputs
 589  *      None
 590  */
 591 static void
 592 ia64_mca_cmc_vector_disable (void *dummy)
 593 {
 594         cmcv_reg_t      cmcv;
 595
 596         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
 597
 598         cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
 599         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 600
 601         IA64_MCA_DEBUG("%s: CPU %d corrected "
 602                        "machine check vector %#x disabled.\n",
 603                        __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
 604 }
 605
 606 /*
 607  * ia64_mca_cmc_vector_enable
 608  *
 609  *  Unmask the corrected machine check vector register in the processor.
 610  *  This function is invoked on a per-processor basis.
 611  *
 612  * Inputs
 613  *      dummy(unused)
 614  *
 615  * Outputs
 616  *      None
 617  */
 618 static void
 619 ia64_mca_cmc_vector_enable (void *dummy)
 620 {
 621         cmcv_reg_t      cmcv;
 622
 623         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
 624
 625         cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
 626         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 627
 628         IA64_MCA_DEBUG("%s: CPU %d corrected "
 629                        "machine check vector %#x enabled.\n",
 630                        __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
 631 }
 632
 633 /*
 634  * ia64_mca_cmc_vector_disable_keventd
 635  *
 636  * Called via keventd (smp_call_function() is not safe in interrupt context) to
 637  * disable the cmc interrupt vector.
 638  */
 639 static void
 640 ia64_mca_cmc_vector_disable_keventd(void *unused)
 641 {
 642         on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0);
 643 }
 644
 645 /*
 646  * ia64_mca_cmc_vector_enable_keventd
 647  *
 648  * Called via keventd (smp_call_function() is not safe in interrupt context) to
 649  * enable the cmc interrupt vector.
 650  */
 651 static void
 652 ia64_mca_cmc_vector_enable_keventd(void *unused)
 653 {
 654         on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0);
 655 }
 656
 657 /*
 658  * ia64_mca_wakeup_ipi_wait
 659  *
 660  *      Wait for the inter-cpu interrupt to be sent by the
 661  *      monarch processor once it is done with handling the
 662  *      MCA.
 663  *
 664  *  Inputs  :   None
 665  *  Outputs :   None
 666  */
 667 static void
 668 ia64_mca_wakeup_ipi_wait(void)
 669 {
 670         int     irr_num = (IA64_MCA_WAKEUP_VECTOR >> 6);
 671         int     irr_bit = (IA64_MCA_WAKEUP_VECTOR & 0x3f);
 672         u64     irr = 0;
 673
 674         do {
 675                 switch(irr_num) {
 676                       case 0:
 677                         irr = ia64_getreg(_IA64_REG_CR_IRR0);
 678                         break;
 679                       case 1:
 680                         irr = ia64_getreg(_IA64_REG_CR_IRR1);
 681                         break;
 682                       case 2:
 683                         irr = ia64_getreg(_IA64_REG_CR_IRR2);
 684                         break;
 685                       case 3:
 686                         irr = ia64_getreg(_IA64_REG_CR_IRR3);
 687                         break;
 688                 }
 689                 cpu_relax();
 690         } while (!(irr & (1UL << irr_bit))) ;
 691 }
 692
 693 /*
 694  * ia64_mca_wakeup
 695  *
 696  *      Send an inter-cpu interrupt to wake-up a particular cpu
 697  *      and mark that cpu to be out of rendez.
 698  *
 699  *  Inputs  :   cpuid
 700  *  Outputs :   None
 701  */
 702 static void
 703 ia64_mca_wakeup(int cpu)
 704 {
 705         platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
 706         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
 707
 708 }
 709
 710 /*
 711  * ia64_mca_wakeup_all
 712  *
 713  *      Wakeup all the cpus which have rendez'ed previously.
 714  *
 715  *  Inputs  :   None
 716  *  Outputs :   None
 717  */
 718 static void
 719 ia64_mca_wakeup_all(void)
 720 {
 721         int cpu;
 722
 723         /* Clear the Rendez checkin flag for all cpus */
 724         for(cpu = 0; cpu < NR_CPUS; cpu++) {
 725                 if (!cpu_online(cpu))
 726                         continue;
 727                 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
 728                         ia64_mca_wakeup(cpu);
 729         }
 730
 731 }
 732
 733 /*
 734  * ia64_mca_rendez_interrupt_handler
 735  *
 736  *      This is handler used to put slave processors into spinloop
 737  *      while the monarch processor does the mca handling and later
 738  *      wake each slave up once the monarch is done.
 739  *
 740  *  Inputs  :   None
 741  *  Outputs :   None
 742  */
 743 static irqreturn_t
 744 ia64_mca_rendez_int_handler(int rendez_irq, void *arg, struct pt_regs *ptregs)
 745 {
 746         unsigned long flags;
 747         int cpu = smp_processor_id();
 748
 749         /* Mask all interrupts */
 750         local_irq_save(flags);
 751
 752         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
 753         /* Register with the SAL monarch that the slave has
 754          * reached SAL
 755          */
 756         ia64_sal_mc_rendez();
 757
 758         /* Wait for the wakeup IPI from the monarch
 759          * This waiting is done by polling on the wakeup-interrupt
 760          * vector bit in the processor's IRRs
 761          */
 762         ia64_mca_wakeup_ipi_wait();
 763
 764         /* Enable all interrupts */
 765         local_irq_restore(flags);
 766         return IRQ_HANDLED;
 767 }
 768
 769 /*
 770  * ia64_mca_wakeup_int_handler
 771  *
 772  *      The interrupt handler for processing the inter-cpu interrupt to the
 773  *      slave cpu which was spinning in the rendez loop.
 774  *      Since this spinning is done by turning off the interrupts and
 775  *      polling on the wakeup-interrupt bit in the IRR, there is
 776  *      nothing useful to be done in the handler.
 777  *
 778  *  Inputs  :   wakeup_irq  (Wakeup-interrupt bit)
 779  *      arg             (Interrupt handler specific argument)
 780  *      ptregs          (Exception frame at the time of the interrupt)
 781  *  Outputs :   None
 782  *
 783  */
 784 static irqreturn_t
 785 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg, struct pt_regs *ptregs)
 786 {
 787         return IRQ_HANDLED;
 788 }
 789
 790 /*
 791  * ia64_return_to_sal_check
 792  *
 793  *      This is function called before going back from the OS_MCA handler
 794  *      to the OS_MCA dispatch code which finally takes the control back
 795  *      to the SAL.
 796  *      The main purpose of this routine is to setup the OS_MCA to SAL
 797  *      return state which can be used by the OS_MCA dispatch code
 798  *      just before going back to SAL.
 799  *
 800  *  Inputs  :   None
 801  *  Outputs :   None
 802  */
 803
 804 static void
 805 ia64_return_to_sal_check(int recover)
 806 {
 807
 808         /* Copy over some relevant stuff from the sal_to_os_mca_handoff
 809          * so that it can be used at the time of os_mca_to_sal_handoff
 810          */
 811         ia64_os_to_sal_handoff_state.imots_sal_gp =
 812                 ia64_sal_to_os_handoff_state.imsto_sal_gp;
 813
 814         ia64_os_to_sal_handoff_state.imots_sal_check_ra =
 815                 ia64_sal_to_os_handoff_state.imsto_sal_check_ra;
 816
 817         if (recover)
 818                 ia64_os_to_sal_handoff_state.imots_os_status = IA64_MCA_CORRECTED;
 819         else
 820                 ia64_os_to_sal_handoff_state.imots_os_status = IA64_MCA_COLD_BOOT;
 821
 822         /* Default = tell SAL to return to same context */
 823         ia64_os_to_sal_handoff_state.imots_context = IA64_MCA_SAME_CONTEXT;
 824
 825         ia64_os_to_sal_handoff_state.imots_new_min_state =
 826                 (u64 *)ia64_sal_to_os_handoff_state.pal_min_state;
 827
 828 }
 829
 830 /* Function pointer for extra MCA recovery */
 831 int (*ia64_mca_ucmc_extension)
 832         (void*,ia64_mca_sal_to_os_state_t*,ia64_mca_os_to_sal_state_t*)
 833         = NULL;
 834
 835 int
 836 ia64_reg_MCA_extension(void *fn)
 837 {
 838         if (ia64_mca_ucmc_extension)
 839                 return 1;
 840
 841         ia64_mca_ucmc_extension = fn;
 842         return 0;
 843 }
 844
 845 void
 846 ia64_unreg_MCA_extension(void)
 847 {
 848         if (ia64_mca_ucmc_extension)
 849                 ia64_mca_ucmc_extension = NULL;
 850 }
 851
 852 EXPORT_SYMBOL(ia64_reg_MCA_extension);
 853 EXPORT_SYMBOL(ia64_unreg_MCA_extension);
 854
 855 /*
 856  * ia64_mca_ucmc_handler
 857  *
 858  *      This is uncorrectable machine check handler called from OS_MCA
 859  *      dispatch code which is in turn called from SAL_CHECK().
 860  *      This is the place where the core of OS MCA handling is done.
 861  *      Right now the logs are extracted and displayed in a well-defined
 862  *      format. This handler code is supposed to be run only on the
 863  *      monarch processor. Once the monarch is done with MCA handling
 864  *      further MCA logging is enabled by clearing logs.
 865  *      Monarch also has the duty of sending wakeup-IPIs to pull the
 866  *      slave processors out of rendezvous spinloop.
 867  *
 868  *  Inputs  :   None
 869  *  Outputs :   None
 870  */
 871 void
 872 ia64_mca_ucmc_handler(void)
 873 {
 874         pal_processor_state_info_t *psp = (pal_processor_state_info_t *)
 875                 &ia64_sal_to_os_handoff_state.proc_state_param;
 876         int recover;
 877
 878         /* Get the MCA error record and log it */
 879         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
 880
 881         /* TLB error is only exist in this SAL error record */
 882         recover = (psp->tc && !(psp->cc || psp->bc || psp->rc || psp->uc))
 883         /* other error recovery */
 884            || (ia64_mca_ucmc_extension
 885                 && ia64_mca_ucmc_extension(
 886                         IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
 887                         &ia64_sal_to_os_handoff_state,
 888                         &ia64_os_to_sal_handoff_state));
 889
 890         /*
 891          *  Wakeup all the processors which are spinning in the rendezvous
 892          *  loop.
 893          */
 894         ia64_mca_wakeup_all();
 895
 896         /* Return to SAL */
 897         ia64_return_to_sal_check(recover);
 898 }
 899
 900 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd, NULL);
 901 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd, NULL);
 902
 903 /*
 904  * ia64_mca_cmc_int_handler
 905  *
 906  *  This is corrected machine check interrupt handler.
 907  *      Right now the logs are extracted and displayed in a well-defined
 908  *      format.
 909  *
 910  * Inputs
 911  *      interrupt number
 912  *      client data arg ptr
 913  *      saved registers ptr
 914  *
 915  * Outputs
 916  *      None
 917  */
 918 static irqreturn_t
 919 ia64_mca_cmc_int_handler(int cmc_irq, void *arg, struct pt_regs *ptregs)
 920 {
 921         static unsigned long    cmc_history[CMC_HISTORY_LENGTH];
 922         static int              index;
 923         static spinlock_t       cmc_history_lock = SPIN_LOCK_UNLOCKED;
 924
 925         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
 926                        __FUNCTION__, cmc_irq, smp_processor_id());
 927
 928         /* SAL spec states this should run w/ interrupts enabled */
 929         local_irq_enable();
 930
 931         /* Get the CMC error record and log it */
 932         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
 933
 934         spin_lock(&cmc_history_lock);
 935         if (!cmc_polling_enabled) {
 936                 int i, count = 1; /* we know 1 happened now */
 937                 unsigned long now = jiffies;
 938
 939                 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
 940                         if (now - cmc_history[i] <= HZ)
 941                                 count++;
 942                 }
 943
 944                 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
 945                 if (count >= CMC_HISTORY_LENGTH) {
 946
 947                         cmc_polling_enabled = 1;
 948                         spin_unlock(&cmc_history_lock);
 949                         schedule_work(&cmc_disable_work);
 950
 951                         /*
 952                          * Corrected errors will still be corrected, but
 953                          * make sure there's a log somewhere that indicates
 954                          * something is generating more than we can handle.
 955                          */
 956                         printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
 957
 958                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
 959
 960                         /* lock already released, get out now */
 961                         return IRQ_HANDLED;
 962                 } else {
 963                         cmc_history[index++] = now;
 964                         if (index == CMC_HISTORY_LENGTH)
 965                                 index = 0;
 966                 }
 967         }
 968         spin_unlock(&cmc_history_lock);
 969         return IRQ_HANDLED;
 970 }
 971
 972 /*
 973  *  ia64_mca_cmc_int_caller
 974  *
 975  *      Triggered by sw interrupt from CMC polling routine.  Calls
 976  *      real interrupt handler and either triggers a sw interrupt
 977  *      on the next cpu or does cleanup at the end.
 978  *
 979  * Inputs
 980  *      interrupt number
 981  *      client data arg ptr
 982  *      saved registers ptr
 983  * Outputs
 984  *      handled
 985  */
 986 static irqreturn_t
 987 ia64_mca_cmc_int_caller(int cmc_irq, void *arg, struct pt_regs *ptregs)
 988 {
 989         static int start_count = -1;
 990         unsigned int cpuid;
 991
 992         cpuid = smp_processor_id();
 993
 994         /* If first cpu, update count */
 995         if (start_count == -1)
 996                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
 997
 998         ia64_mca_cmc_int_handler(cmc_irq, arg, ptregs);
 999
1000         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1001
1002         if (cpuid < NR_CPUS) {
1003                 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1004         } else {
1005                 /* If no log record, switch out of polling mode */
1006                 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1007
1008                         printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1009                         schedule_work(&cmc_enable_work);
1010                         cmc_polling_enabled = 0;
1011
1012                 } else {
1013
1014                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1015                 }
1016
1017                 start_count = -1;
1018         }
1019
1020         return IRQ_HANDLED;
1021 }
1022
1023 /*
1024  *  ia64_mca_cmc_poll
1025  *
1026  *      Poll for Corrected Machine Checks (CMCs)
1027  *
1028  * Inputs   :   dummy(unused)
1029  * Outputs  :   None
1030  *
1031  */
1032 static void
1033 ia64_mca_cmc_poll (unsigned long dummy)
1034 {
1035         /* Trigger a CMC interrupt cascade  */
1036         platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1037 }
1038
1039 /*
1040  *  ia64_mca_cpe_int_caller
1041  *
1042  *      Triggered by sw interrupt from CPE polling routine.  Calls
1043  *      real interrupt handler and either triggers a sw interrupt
1044  *      on the next cpu or does cleanup at the end.
1045  *
1046  * Inputs
1047  *      interrupt number
1048  *      client data arg ptr
1049  *      saved registers ptr
1050  * Outputs
1051  *      handled
1052  */
1053 #ifdef CONFIG_ACPI
1054
1055 static irqreturn_t
1056 ia64_mca_cpe_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs)
1057 {
1058         static int start_count = -1;
1059         static int poll_time = MIN_CPE_POLL_INTERVAL;
1060         unsigned int cpuid;
1061
1062         cpuid = smp_processor_id();
1063
1064         /* If first cpu, update count */
1065         if (start_count == -1)
1066                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1067
1068         ia64_mca_cpe_int_handler(cpe_irq, arg, ptregs);
1069
1070         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1071
1072         if (cpuid < NR_CPUS) {
1073                 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1074         } else {
1075                 /*
1076                  * If a log was recorded, increase our polling frequency,
1077                  * otherwise, backoff or return to interrupt mode.
1078                  */
1079                 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1080                         poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1081                 } else if (cpe_vector < 0) {
1082                         poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1083                 } else {
1084                         poll_time = MIN_CPE_POLL_INTERVAL;
1085
1086                         printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1087                         enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1088                         cpe_poll_enabled = 0;
1089                 }
1090
1091                 if (cpe_poll_enabled)
1092                         mod_timer(&cpe_poll_timer, jiffies + poll_time);
1093                 start_count = -1;
1094         }
1095
1096         return IRQ_HANDLED;
1097 }
1098
1099 #endif /* CONFIG_ACPI */
1100
1101 /*
1102  *  ia64_mca_cpe_poll
1103  *
1104  *      Poll for Corrected Platform Errors (CPEs), trigger interrupt
1105  *      on first cpu, from there it will trickle through all the cpus.
1106  *
1107  * Inputs   :   dummy(unused)
1108  * Outputs  :   None
1109  *
1110  */
1111 static void
1112 ia64_mca_cpe_poll (unsigned long dummy)
1113 {
1114         /* Trigger a CPE interrupt cascade  */
1115         platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1116 }
1117
1118 /*
1119  * C portion of the OS INIT handler
1120  *
1121  * Called from ia64_monarch_init_handler
1122  *
1123  * Inputs: pointer to pt_regs where processor info was saved.
1124  *
1125  * Returns:
1126  *   0 if SAL must warm boot the System
1127  *   1 if SAL must return to interrupted context using PAL_MC_RESUME
1128  *
1129  */
1130 void
1131 ia64_init_handler (struct pt_regs *pt, struct switch_stack *sw)
1132 {
1133         pal_min_state_area_t *ms;
1134
1135         oops_in_progress = 1;   /* avoid deadlock in printk, but it makes recovery dodgy */
1136         console_loglevel = 15;  /* make sure printks make it to console */
1137
1138         printk(KERN_INFO "Entered OS INIT handler. PSP=%lx\n",
1139                 ia64_sal_to_os_handoff_state.proc_state_param);
1140
1141         /*
1142          * Address of minstate area provided by PAL is physical,
1143          * uncacheable (bit 63 set). Convert to Linux virtual
1144          * address in region 6.
1145          */
1146         ms = (pal_min_state_area_t *)(ia64_sal_to_os_handoff_state.pal_min_state | (6ul<<61));
1147
1148         init_handler_platform(ms, pt, sw);      /* call platform specific routines */
1149 }
1150
1151 static int __init
1152 ia64_mca_disable_cpe_polling(char *str)
1153 {
1154         cpe_poll_enabled = 0;
1155         return 1;
1156 }
1157
1158 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1159
1160 static struct irqaction cmci_irqaction = {
1161         .handler =      ia64_mca_cmc_int_handler,
1162         .flags =        SA_INTERRUPT,
1163         .name =         "cmc_hndlr"
1164 };
1165
1166 static struct irqaction cmcp_irqaction = {
1167         .handler =      ia64_mca_cmc_int_caller,
1168         .flags =        SA_INTERRUPT,
1169         .name =         "cmc_poll"
1170 };
1171
1172 static struct irqaction mca_rdzv_irqaction = {
1173         .handler =      ia64_mca_rendez_int_handler,
1174         .flags =        SA_INTERRUPT,
1175         .name =         "mca_rdzv"
1176 };
1177
1178 static struct irqaction mca_wkup_irqaction = {
1179         .handler =      ia64_mca_wakeup_int_handler,
1180         .flags =        SA_INTERRUPT,
1181         .name =         "mca_wkup"
1182 };
1183
1184 #ifdef CONFIG_ACPI
1185 static struct irqaction mca_cpe_irqaction = {
1186         .handler =      ia64_mca_cpe_int_handler,
1187         .flags =        SA_INTERRUPT,
1188         .name =         "cpe_hndlr"
1189 };
1190
1191 static struct irqaction mca_cpep_irqaction = {
1192         .handler =      ia64_mca_cpe_int_caller,
1193         .flags =        SA_INTERRUPT,
1194         .name =         "cpe_poll"
1195 };
1196 #endif /* CONFIG_ACPI */
1197
1198 /*
1199  * ia64_mca_init
1200  *
1201  *  Do all the system level mca specific initialization.
1202  *
1203  *      1. Register spinloop and wakeup request interrupt vectors
1204  *
1205  *      2. Register OS_MCA handler entry point
1206  *
1207  *      3. Register OS_INIT handler entry point
1208  *
1209  *  4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1210  *
1211  *  Note that this initialization is done very early before some kernel
1212  *  services are available.
1213  *
1214  *  Inputs  :   None
1215  *
1216  *  Outputs :   None
1217  */
1218 void __init
1219 ia64_mca_init(void)
1220 {
1221         ia64_fptr_t *mon_init_ptr = (ia64_fptr_t *)ia64_monarch_init_handler;
1222         ia64_fptr_t *slave_init_ptr = (ia64_fptr_t *)ia64_slave_init_handler;
1223         ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1224         int i;
1225         s64 rc;
1226         struct ia64_sal_retval isrv;
1227         u64 timeout = IA64_MCA_RENDEZ_TIMEOUT;  /* platform specific */
1228
1229         IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__);
1230
1231         /* Clear the Rendez checkin flag for all cpus */
1232         for(i = 0 ; i < NR_CPUS; i++)
1233                 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1234
1235         /*
1236          * Register the rendezvous spinloop and wakeup mechanism with SAL
1237          */
1238
1239         /* Register the rendezvous interrupt vector with SAL */
1240         while (1) {
1241                 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1242                                               SAL_MC_PARAM_MECHANISM_INT,
1243                                               IA64_MCA_RENDEZ_VECTOR,
1244                                               timeout,
1245                                               SAL_MC_PARAM_RZ_ALWAYS);
1246                 rc = isrv.status;
1247                 if (rc == 0)
1248                         break;
1249                 if (rc == -2) {
1250                         printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1251                                 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1252                         timeout = isrv.v0;
1253                         continue;
1254                 }
1255                 printk(KERN_ERR "Failed to register rendezvous interrupt "
1256                        "with SAL (status %ld)\n", rc);
1257                 return;
1258         }
1259
1260         /* Register the wakeup interrupt vector with SAL */
1261         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1262                                       SAL_MC_PARAM_MECHANISM_INT,
1263                                       IA64_MCA_WAKEUP_VECTOR,
1264                                       0, 0);
1265         rc = isrv.status;
1266         if (rc) {
1267                 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1268                        "(status %ld)\n", rc);
1269                 return;
1270         }
1271
1272         IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__);
1273
1274         ia64_mc_info.imi_mca_handler        = ia64_tpa(mca_hldlr_ptr->fp);
1275         /*
1276          * XXX - disable SAL checksum by setting size to 0; should be
1277          *      ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1278          */
1279         ia64_mc_info.imi_mca_handler_size       = 0;
1280
1281         /* Register the os mca handler with SAL */
1282         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1283                                        ia64_mc_info.imi_mca_handler,
1284                                        ia64_tpa(mca_hldlr_ptr->gp),
1285                                        ia64_mc_info.imi_mca_handler_size,
1286                                        0, 0, 0)))
1287         {
1288                 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1289                        "(status %ld)\n", rc);
1290                 return;
1291         }
1292
1293         IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__,
1294                        ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1295
1296         /*
1297          * XXX - disable SAL checksum by setting size to 0, should be
1298          * size of the actual init handler in mca_asm.S.
1299          */
1300         ia64_mc_info.imi_monarch_init_handler           = ia64_tpa(mon_init_ptr->fp);
1301         ia64_mc_info.imi_monarch_init_handler_size      = 0;
1302         ia64_mc_info.imi_slave_init_handler             = ia64_tpa(slave_init_ptr->fp);
1303         ia64_mc_info.imi_slave_init_handler_size        = 0;
1304
1305         IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__,
1306                        ia64_mc_info.imi_monarch_init_handler);
1307
1308         /* Register the os init handler with SAL */
1309         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
1310                                        ia64_mc_info.imi_monarch_init_handler,
1311                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1312                                        ia64_mc_info.imi_monarch_init_handler_size,
1313                                        ia64_mc_info.imi_slave_init_handler,
1314                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1315                                        ia64_mc_info.imi_slave_init_handler_size)))
1316         {
1317                 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
1318                        "(status %ld)\n", rc);
1319                 return;
1320         }
1321
1322         IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__);
1323
1324         /*
1325          *  Configure the CMCI/P vector and handler. Interrupts for CMC are
1326          *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
1327          */
1328         register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
1329         register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
1330         ia64_mca_cmc_vector_setup();       /* Setup vector on BSP */
1331
1332         /* Setup the MCA rendezvous interrupt vector */
1333         register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
1334
1335         /* Setup the MCA wakeup interrupt vector */
1336         register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
1337
1338 #ifdef CONFIG_ACPI
1339         /* Setup the CPEI/P vector and handler */
1340         cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
1341         register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
1342 #endif
1343
1344         /* Initialize the areas set aside by the OS to buffer the
1345          * platform/processor error states for MCA/INIT/CMC
1346          * handling.
1347          */
1348         ia64_log_init(SAL_INFO_TYPE_MCA);
1349         ia64_log_init(SAL_INFO_TYPE_INIT);
1350         ia64_log_init(SAL_INFO_TYPE_CMC);
1351         ia64_log_init(SAL_INFO_TYPE_CPE);
1352
1353         mca_init = 1;
1354         printk(KERN_INFO "MCA related initialization done\n");
1355 }
1356
1357 /*
1358  * ia64_mca_late_init
1359  *
1360  *      Opportunity to setup things that require initialization later
1361  *      than ia64_mca_init.  Setup a timer to poll for CPEs if the
1362  *      platform doesn't support an interrupt driven mechanism.
1363  *
1364  *  Inputs  :   None
1365  *  Outputs :   Status
1366  */
1367 static int __init
1368 ia64_mca_late_init(void)
1369 {
1370         if (!mca_init)
1371                 return 0;
1372
1373         /* Setup the CMCI/P vector and handler */
1374         init_timer(&cmc_poll_timer);
1375         cmc_poll_timer.function = ia64_mca_cmc_poll;
1376
1377         /* Unmask/enable the vector */
1378         cmc_polling_enabled = 0;
1379         schedule_work(&cmc_enable_work);
1380
1381         IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __FUNCTION__);
1382
1383 #ifdef CONFIG_ACPI
1384         /* Setup the CPEI/P vector and handler */
1385         init_timer(&cpe_poll_timer);
1386         cpe_poll_timer.function = ia64_mca_cpe_poll;
1387
1388         {
1389                 irq_desc_t *desc;
1390                 unsigned int irq;
1391
1392                 if (cpe_vector >= 0) {
1393                         /* If platform supports CPEI, enable the irq. */
1394                         cpe_poll_enabled = 0;
1395                         for (irq = 0; irq < NR_IRQS; ++irq)
1396                                 if (irq_to_vector(irq) == cpe_vector) {
1397                                         desc = irq_descp(irq);
1398                                         desc->status |= IRQ_PER_CPU;
1399                                         setup_irq(irq, &mca_cpe_irqaction);
1400                                 }
1401                         ia64_mca_register_cpev(cpe_vector);
1402                         IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", __FUNCTION__);
1403                 } else {
1404                         /* If platform doesn't support CPEI, get the timer going. */
1405                         if (cpe_poll_enabled) {
1406                                 ia64_mca_cpe_poll(0UL);
1407                                 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __FUNCTION__);
1408                         }
1409                 }
1410         }
1411 #endif
1412
1413         return 0;
1414 }
1415
1416 device_initcall(ia64_mca_late_init);