drivers/ide/pci/pdc202xx_old.h

   1 #ifndef PDC202XX_H
   2 #define PDC202XX_H
   3
   4 #include <linux/config.h>
   5 #include <linux/pci.h>
   6 #include <linux/ide.h>
   7
   8 #define DISPLAY_PDC202XX_TIMINGS
   9
  10 #ifndef SPLIT_BYTE
  11 #define SPLIT_BYTE(B,H,L)       ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
  12 #endif
  13
  14 #define PDC202XX_DEBUG_DRIVE_INFO               0
  15 #define PDC202XX_DECODE_REGISTER_INFO           0
  16
  17 static const char *pdc_quirk_drives[] = {
  18         "QUANTUM FIREBALLlct08 08",
  19         "QUANTUM FIREBALLP KA6.4",
  20         "QUANTUM FIREBALLP KA9.1",
  21         "QUANTUM FIREBALLP LM20.4",
  22         "QUANTUM FIREBALLP KX13.6",
  23         "QUANTUM FIREBALLP KX20.5",
  24         "QUANTUM FIREBALLP KX27.3",
  25         "QUANTUM FIREBALLP LM20.5",
  26         NULL
  27 };
  28
  29 static inline u8 *pdc202xx_pio_verbose (u32 drive_pci)
  30 {
  31         if ((drive_pci & 0x000ff000) == 0x000ff000) return("NOTSET");
  32         if ((drive_pci & 0x00000401) == 0x00000401) return("PIO 4");
  33         if ((drive_pci & 0x00000602) == 0x00000602) return("PIO 3");
  34         if ((drive_pci & 0x00000803) == 0x00000803) return("PIO 2");
  35         if ((drive_pci & 0x00000C05) == 0x00000C05) return("PIO 1");
  36         if ((drive_pci & 0x00001309) == 0x00001309) return("PIO 0");
  37         return("PIO ?");
  38 }
  39
  40 static inline u8 *pdc202xx_dma_verbose (u32 drive_pci)
  41 {
  42         if ((drive_pci & 0x00036000) == 0x00036000) return("MWDMA 2");
  43         if ((drive_pci & 0x00046000) == 0x00046000) return("MWDMA 1");
  44         if ((drive_pci & 0x00056000) == 0x00056000) return("MWDMA 0");
  45         if ((drive_pci & 0x00056000) == 0x00056000) return("SWDMA 2");
  46         if ((drive_pci & 0x00068000) == 0x00068000) return("SWDMA 1");
  47         if ((drive_pci & 0x000BC000) == 0x000BC000) return("SWDMA 0");
  48         return("PIO---");
  49 }
  50
  51 static inline u8 *pdc202xx_ultra_verbose (u32 drive_pci, u16 slow_cable)
  52 {
  53         if ((drive_pci & 0x000ff000) == 0x000ff000)
  54                 return("NOTSET");
  55         if ((drive_pci & 0x00012000) == 0x00012000)
  56                 return((slow_cable) ? "UDMA 2" : "UDMA 4");
  57         if ((drive_pci & 0x00024000) == 0x00024000)
  58                 return((slow_cable) ? "UDMA 1" : "UDMA 3");
  59         if ((drive_pci & 0x00036000) == 0x00036000)
  60                 return("UDMA 0");
  61         return(pdc202xx_dma_verbose(drive_pci));
  62 }
  63
  64 /* A Register */
  65 #define SYNC_ERRDY_EN   0xC0
  66
  67 #define SYNC_IN         0x80    /* control bit, different for master vs. slave drives */
  68 #define ERRDY_EN        0x40    /* control bit, different for master vs. slave drives */
  69 #define IORDY_EN        0x20    /* PIO: IOREADY */
  70 #define PREFETCH_EN     0x10    /* PIO: PREFETCH */
  71
  72 #define PA3             0x08    /* PIO"A" timing */
  73 #define PA2             0x04    /* PIO"A" timing */
  74 #define PA1             0x02    /* PIO"A" timing */
  75 #define PA0             0x01    /* PIO"A" timing */
  76
  77 /* B Register */
  78
  79 #define MB2             0x80    /* DMA"B" timing */
  80 #define MB1             0x40    /* DMA"B" timing */
  81 #define MB0             0x20    /* DMA"B" timing */
  82
  83 #define PB4             0x10    /* PIO_FORCE 1:0 */
  84
  85 #define PB3             0x08    /* PIO"B" timing */     /* PIO flow Control mode */
  86 #define PB2             0x04    /* PIO"B" timing */     /* PIO 4 */
  87 #define PB1             0x02    /* PIO"B" timing */     /* PIO 3 half */
  88 #define PB0             0x01    /* PIO"B" timing */     /* PIO 3 other half */
  89
  90 /* C Register */
  91 #define IORDYp_NO_SPEED 0x4F
  92 #define SPEED_DIS       0x0F
  93
  94 #define DMARQp          0x80
  95 #define IORDYp          0x40
  96 #define DMAR_EN         0x20
  97 #define DMAW_EN         0x10
  98
  99 #define MC3             0x08    /* DMA"C" timing */
 100 #define MC2             0x04    /* DMA"C" timing */
 101 #define MC1             0x02    /* DMA"C" timing */
 102 #define MC0             0x01    /* DMA"C" timing */
 103
 104 #if PDC202XX_DECODE_REGISTER_INFO
 105
 106 #define REG_A           0x01
 107 #define REG_B           0x02
 108 #define REG_C           0x04
 109 #define REG_D           0x08
 110
 111 static void decode_registers (u8 registers, u8 value)
 112 {
 113         u8      bit = 0, bit1 = 0, bit2 = 0;
 114
 115         switch(registers) {
 116                 case REG_A:
 117                         bit2 = 0;
 118                         printk("A Register ");
 119                         if (value & 0x80) printk("SYNC_IN ");
 120                         if (value & 0x40) printk("ERRDY_EN ");
 121                         if (value & 0x20) printk("IORDY_EN ");
 122                         if (value & 0x10) printk("PREFETCH_EN ");
 123                         if (value & 0x08) { printk("PA3 ");bit2 |= 0x08; }
 124                         if (value & 0x04) { printk("PA2 ");bit2 |= 0x04; }
 125                         if (value & 0x02) { printk("PA1 ");bit2 |= 0x02; }
 126                         if (value & 0x01) { printk("PA0 ");bit2 |= 0x01; }
 127                         printk("PIO(A) = %d ", bit2);
 128                         break;
 129                 case REG_B:
 130                         bit1 = 0;bit2 = 0;
 131                         printk("B Register ");
 132                         if (value & 0x80) { printk("MB2 ");bit1 |= 0x80; }
 133                         if (value & 0x40) { printk("MB1 ");bit1 |= 0x40; }
 134                         if (value & 0x20) { printk("MB0 ");bit1 |= 0x20; }
 135                         printk("DMA(B) = %d ", bit1 >> 5);
 136                         if (value & 0x10) printk("PIO_FORCED/PB4 ");
 137                         if (value & 0x08) { printk("PB3 ");bit2 |= 0x08; }
 138                         if (value & 0x04) { printk("PB2 ");bit2 |= 0x04; }
 139                         if (value & 0x02) { printk("PB1 ");bit2 |= 0x02; }
 140                         if (value & 0x01) { printk("PB0 ");bit2 |= 0x01; }
 141                         printk("PIO(B) = %d ", bit2);
 142                         break;
 143                 case REG_C:
 144                         bit2 = 0;
 145                         printk("C Register ");
 146                         if (value & 0x80) printk("DMARQp ");
 147                         if (value & 0x40) printk("IORDYp ");
 148                         if (value & 0x20) printk("DMAR_EN ");
 149                         if (value & 0x10) printk("DMAW_EN ");
 150
 151                         if (value & 0x08) { printk("MC3 ");bit2 |= 0x08; }
 152                         if (value & 0x04) { printk("MC2 ");bit2 |= 0x04; }
 153                         if (value & 0x02) { printk("MC1 ");bit2 |= 0x02; }
 154                         if (value & 0x01) { printk("MC0 ");bit2 |= 0x01; }
 155                         printk("DMA(C) = %d ", bit2);
 156                         break;
 157                 case REG_D:
 158                         printk("D Register ");
 159                         break;
 160                 default:
 161                         return;
 162         }
 163         printk("\n        %s ", (registers & REG_D) ? "DP" :
 164                                 (registers & REG_C) ? "CP" :
 165                                 (registers & REG_B) ? "BP" :
 166                                 (registers & REG_A) ? "AP" : "ERROR");
 167         for (bit=128;bit>0;bit/=2)
 168                 printk("%s", (value & bit) ? "1" : "0");
 169         printk("\n");
 170 }
 171
 172 #endif /* PDC202XX_DECODE_REGISTER_INFO */
 173
 174 #define set_2regs(a, b)                                 \
 175         do {                                            \
 176                 hwif->OUTB((a + adj), indexreg);        \
 177                 hwif->OUTB(b, datareg);                 \
 178         } while(0)
 179
 180 #define set_ultra(a, b, c)                              \
 181         do {                                            \
 182                 set_2regs(0x10,(a));                    \
 183                 set_2regs(0x11,(b));                    \
 184                 set_2regs(0x12,(c));                    \
 185         } while(0)
 186
 187 #define set_ata2(a, b)                                  \
 188         do {                                            \
 189                 set_2regs(0x0e,(a));                    \
 190                 set_2regs(0x0f,(b));                    \
 191         } while(0)
 192
 193 #define set_pio(a, b, c)                                \
 194         do {                                            \
 195                 set_2regs(0x0c,(a));                    \
 196                 set_2regs(0x0d,(b));                    \
 197                 set_2regs(0x13,(c));                    \
 198         } while(0)
 199
 200 #define DISPLAY_PDC202XX_TIMINGS
 201
 202 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
 203 #include <linux/stat.h>
 204 #include <linux/proc_fs.h>
 205
 206 static u8 pdc202xx_proc;
 207
 208 static int pdc202xx_get_info(char *, char **, off_t, int);
 209
 210 static ide_pci_host_proc_t pdc202xx_procs[] = {
 211         {
 212                 .name           = "pdc202xx",
 213                 .set            = 1,
 214                 .get_info       = pdc202xx_get_info,
 215                 .parent         = NULL,
 216         },
 217 };
 218 #endif /* DISPLAY_PDC202XX_TIMINGS && CONFIG_PROC_FS */
 219
 220
 221 static void init_setup_pdc202ata4(struct pci_dev *dev, ide_pci_device_t *d);
 222 static void init_setup_pdc20265(struct pci_dev *, ide_pci_device_t *);
 223 static void init_setup_pdc202xx(struct pci_dev *, ide_pci_device_t *);
 224 static unsigned int init_chipset_pdc202xx(struct pci_dev *, const char *);
 225 static void init_hwif_pdc202xx(ide_hwif_t *);
 226 static void init_dma_pdc202xx(ide_hwif_t *, unsigned long);
 227
 228 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
 229         {       /* 0 */
 230                 .vendor         = PCI_VENDOR_ID_PROMISE,
 231                 .device         = PCI_DEVICE_ID_PROMISE_20246,
 232                 .name           = "PDC20246",
 233                 .init_setup     = init_setup_pdc202ata4,
 234                 .init_chipset   = init_chipset_pdc202xx,
 235                 .init_iops      = NULL,
 236                 .init_hwif      = init_hwif_pdc202xx,
 237                 .init_dma       = init_dma_pdc202xx,
 238                 .channels       = 2,
 239                 .autodma        = AUTODMA,
 240 #ifdef CONFIG_PDC202XX_FORCE
 241                 .enablebits     = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
 242 #else /* !CONFIG_PDC202XX_FORCE */
 243                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
 244 #endif
 245                 .bootable       = OFF_BOARD,
 246                 .extra          = 16,
 247         },{     /* 1 */
 248                 .vendor         = PCI_VENDOR_ID_PROMISE,
 249                 .device         = PCI_DEVICE_ID_PROMISE_20262,
 250                 .name           = "PDC20262",
 251                 .init_setup     = init_setup_pdc202ata4,
 252                 .init_chipset   = init_chipset_pdc202xx,
 253                 .init_iops      = NULL,
 254                 .init_hwif      = init_hwif_pdc202xx,
 255                 .init_dma       = init_dma_pdc202xx,
 256                 .channels       = 2,
 257                 .autodma        = AUTODMA,
 258 #ifdef CONFIG_PDC202XX_FORCE
 259                 .enablebits     = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
 260 #else /* !CONFIG_PDC202XX_FORCE */
 261                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
 262 #endif
 263                 .bootable       = OFF_BOARD,
 264                 .extra          = 48,
 265         },{     /* 2 */
 266                 .vendor         = PCI_VENDOR_ID_PROMISE,
 267                 .device         = PCI_DEVICE_ID_PROMISE_20263,
 268                 .name           = "PDC20263",
 269                 .init_setup     = init_setup_pdc202ata4,
 270                 .init_chipset   = init_chipset_pdc202xx,
 271                 .init_iops      = NULL,
 272                 .init_hwif      = init_hwif_pdc202xx,
 273                 .init_dma       = init_dma_pdc202xx,
 274                 .channels       = 2,
 275                 .autodma        = AUTODMA,
 276 #ifdef CONFIG_PDC202XX_FORCE
 277                 .enablebits     = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
 278 #else /* !CONFIG_PDC202XX_FORCE */
 279                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
 280 #endif
 281                 .bootable       = OFF_BOARD,
 282                 .extra          = 48,
 283         },{     /* 3 */
 284                 .vendor         = PCI_VENDOR_ID_PROMISE,
 285                 .device         = PCI_DEVICE_ID_PROMISE_20265,
 286                 .name           = "PDC20265",
 287                 .init_setup     = init_setup_pdc20265,
 288                 .init_chipset   = init_chipset_pdc202xx,
 289                 .init_hwif      = init_hwif_pdc202xx,
 290                 .init_dma       = init_dma_pdc202xx,
 291                 .channels       = 2,
 292                 .autodma        = AUTODMA,
 293 #ifdef CONFIG_PDC202XX_FORCE
 294                 .enablebits     = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
 295 #else /* !CONFIG_PDC202XX_FORCE */
 296                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
 297 #endif
 298                 .bootable       = OFF_BOARD,
 299                 .extra          = 48,
 300         },{     /* 4 */
 301                 .vendor         = PCI_VENDOR_ID_PROMISE,
 302                 .device         = PCI_DEVICE_ID_PROMISE_20267,
 303                 .name           = "PDC20267",
 304                 .init_setup     = init_setup_pdc202xx,
 305                 .init_chipset   = init_chipset_pdc202xx,
 306                 .init_iops      = NULL,
 307                 .init_hwif      = init_hwif_pdc202xx,
 308                 .init_dma       = init_dma_pdc202xx,
 309                 .channels       = 2,
 310                 .autodma        = AUTODMA,
 311 #ifdef CONFIG_PDC202XX_FORCE
 312                 .enablebits     = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
 313 #else /* !CONFIG_PDC202XX_FORCE */
 314                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
 315 #endif
 316                 .bootable       = OFF_BOARD,
 317                 .extra          = 48,
 318         },{
 319                 .vendor         = 0,
 320                 .device         = 0,
 321                 .channels       = 0,
 322                 .bootable       = EOL,
 323         }
 324 };
 325
 326 #endif /* PDC202XX_H */