2 * Copyright (C) 2010 - 2011 Samsung Electronics Co., Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
14 #include <linux/platform_device.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/types.h>
18 #include <linux/videodev2.h>
21 #include <media/media-entity.h>
22 #include <media/videobuf2-core.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-mem2mem.h>
26 #include <media/v4l2-mediabus.h>
27 #include <media/s5p_fimc.h>
29 #include "regs-fimc.h"
31 #define err(fmt, args...) \
32 printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
34 #define dbg(fmt, args...) \
35 pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
37 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
38 #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
39 #define MAX_FIMC_CLOCKS 2
40 #define FIMC_MODULE_NAME "s5p-fimc"
41 #define FIMC_MAX_DEVS 4
42 #define FIMC_MAX_OUT_BUFS 4
43 #define SCALER_MAX_HRATIO 64
44 #define SCALER_MAX_VRATIO 64
45 #define DMA_MIN_SIZE 8
46 #define FIMC_CAMIF_MAX_HEIGHT 0x2000
48 /* indices to the clocks array */
72 #define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
73 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
75 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
76 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
77 #define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
87 S5P_FIMC_RGB565 = 0x10,
91 S5P_FIMC_YCBCR420 = 0x20,
96 S5P_FIMC_YCBCR444_LOCAL,
100 #define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
101 #define fimc_fmt_is_jpeg(x) (!!((x) & 0x40))
103 #define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
104 __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
106 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
107 #define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
109 /* The embedded image effect selection */
110 #define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
111 #define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
112 #define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
113 #define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
114 #define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
115 #define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
117 /* The hardware context state. */
118 #define FIMC_PARAMS (1 << 0)
119 #define FIMC_SRC_ADDR (1 << 1)
120 #define FIMC_DST_ADDR (1 << 2)
121 #define FIMC_SRC_FMT (1 << 3)
122 #define FIMC_DST_FMT (1 << 4)
123 #define FIMC_DST_CROP (1 << 5)
124 #define FIMC_CTX_M2M (1 << 16)
125 #define FIMC_CTX_CAP (1 << 17)
126 #define FIMC_CTX_SHUT (1 << 18)
128 /* Image conversion flags */
129 #define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
130 #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
131 #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
132 #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
133 #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
134 #define FIMC_SCAN_MODE_INTERLACED (1 << 2)
136 * YCbCr data dynamic range for RGB-YUV color conversion.
137 * Y/Cb/Cr: (0 ~ 255) */
138 #define FIMC_COLOR_RANGE_WIDE (0 << 3)
139 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
140 #define FIMC_COLOR_RANGE_NARROW (1 << 3)
143 * struct fimc_fmt - the driver's internal color format data
144 * @mbus_code: Media Bus pixel code, -1 if not applicable
145 * @name: format description
146 * @fourcc: the fourcc code for this format, 0 if not applicable
147 * @color: the corresponding fimc_color_fmt
148 * @memplanes: number of physically non-contiguous data planes
149 * @colplanes: number of physically contiguous data planes
150 * @depth: per plane driver's private 'number of bits per pixel'
151 * @flags: flags indicating which operation mode format applies to
154 enum v4l2_mbus_pixelcode mbus_code;
160 u8 depth[VIDEO_MAX_PLANES];
162 #define FMT_FLAGS_CAM (1 << 0)
163 #define FMT_FLAGS_M2M (1 << 1)
167 * struct fimc_dma_offset - pixel offset information for DMA
168 * @y_h: y value horizontal offset
169 * @y_v: y value vertical offset
170 * @cb_h: cb value horizontal offset
171 * @cb_v: cb value vertical offset
172 * @cr_h: cr value horizontal offset
173 * @cr_v: cr value vertical offset
175 struct fimc_dma_offset {
185 * struct fimc_effect - color effect information
187 * @pat_cb: cr value when type is "arbitrary"
188 * @pat_cr: cr value when type is "arbitrary"
197 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
198 * @scaleup_h: flag indicating scaling up horizontally
199 * @scaleup_v: flag indicating scaling up vertically
200 * @copy_mode: flag indicating transparent DMA transfer (no scaling
201 * and color format conversion)
202 * @enabled: flag indicating if the scaler is used
203 * @hfactor: horizontal shift factor
204 * @vfactor: vertical shift factor
205 * @pre_hratio: horizontal ratio of the prescaler
206 * @pre_vratio: vertical ratio of the prescaler
207 * @pre_dst_width: the prescaler's destination width
208 * @pre_dst_height: the prescaler's destination height
209 * @main_hratio: the main scaler's horizontal ratio
210 * @main_vratio: the main scaler's vertical ratio
211 * @real_width: source pixel (width - offset)
212 * @real_height: source pixel (height - offset)
215 unsigned int scaleup_h:1;
216 unsigned int scaleup_v:1;
217 unsigned int copy_mode:1;
218 unsigned int enabled:1;
232 * struct fimc_addr - the FIMC physical address set for DMA
233 * @y: luminance plane physical address
234 * @cb: Cb plane physical address
235 * @cr: Cr plane physical address
244 * struct fimc_vid_buffer - the driver's video buffer
245 * @vb: v4l videobuf buffer
246 * @list: linked list structure for buffer queue
247 * @paddr: precalculated physical address set
248 * @index: buffer index for the output DMA engine
250 struct fimc_vid_buffer {
251 struct vb2_buffer vb;
252 struct list_head list;
253 struct fimc_addr paddr;
258 * struct fimc_frame - source/target frame properties
259 * @f_width: image full width (virtual screen size)
260 * @f_height: image full height (virtual screen size)
261 * @o_width: original image width as set by S_FMT
262 * @o_height: original image height as set by S_FMT
263 * @offs_h: image horizontal pixel offset
264 * @offs_v: image vertical pixel offset
265 * @width: image pixel width
266 * @height: image pixel weight
267 * @payload: image size in bytes (w x h x bpp)
268 * @paddr: image frame buffer physical addresses
269 * @dma_offset: DMA offset in bytes
270 * @fmt: fimc color format pointer
281 unsigned long payload[VIDEO_MAX_PLANES];
282 struct fimc_addr paddr;
283 struct fimc_dma_offset dma_offset;
284 struct fimc_fmt *fmt;
288 * struct fimc_m2m_device - v4l2 memory-to-memory device data
289 * @vfd: the video device node for v4l2 m2m mode
290 * @m2m_dev: v4l2 memory-to-memory device data
291 * @ctx: hardware context data
292 * @refcnt: the reference counter
294 struct fimc_m2m_device {
295 struct video_device *vfd;
296 struct v4l2_m2m_dev *m2m_dev;
297 struct fimc_ctx *ctx;
301 #define FIMC_SD_PAD_SINK 0
302 #define FIMC_SD_PAD_SOURCE 1
303 #define FIMC_SD_PADS_NUM 2
306 * struct fimc_vid_cap - camera capture device information
307 * @ctx: hardware context data
308 * @vfd: video device node for camera capture mode
309 * @subdev: subdev exposing the FIMC processing block
310 * @vd_pad: fimc video capture node pad
311 * @sd_pads: fimc video processing block pads
312 * @mf: media bus format at the FIMC camera input (and the scaler output) pad
313 * @pending_buf_q: the pending buffer queue head
314 * @active_buf_q: the queue head of buffers scheduled in hardware
315 * @vbq: the capture am video buffer queue
316 * @active_buf_cnt: number of video buffers scheduled in hardware
317 * @buf_index: index for managing the output DMA buffers
318 * @frame_count: the frame counter for statistics
319 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
320 * @input_index: input (camera sensor) index
321 * @refcnt: driver's private reference counter
322 * @input: capture input type, grp_id of the attached subdev
323 * @user_subdev_api: true if subdevs are not configured by the host driver
325 struct fimc_vid_cap {
326 struct fimc_ctx *ctx;
327 struct vb2_alloc_ctx *alloc_ctx;
328 struct video_device *vfd;
329 struct v4l2_subdev *subdev;
330 struct media_pad vd_pad;
331 struct v4l2_mbus_framefmt mf;
332 struct media_pad sd_pads[FIMC_SD_PADS_NUM];
333 struct list_head pending_buf_q;
334 struct list_head active_buf_q;
335 struct vb2_queue vbq;
338 unsigned int frame_count;
339 unsigned int reqbufs_count;
343 bool user_subdev_api;
347 * struct fimc_pix_limit - image pixel size limits in various IP configurations
349 * @scaler_en_w: max input pixel width when the scaler is enabled
350 * @scaler_dis_w: max input pixel width when the scaler is disabled
351 * @in_rot_en_h: max input width with the input rotator is on
352 * @in_rot_dis_w: max input width with the input rotator is off
353 * @out_rot_en_w: max output width with the output rotator on
354 * @out_rot_dis_w: max output width with the output rotator off
356 struct fimc_pix_limit {
366 * struct samsung_fimc_variant - camera interface variant information
368 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
369 * @has_inp_rot: set if has input rotator
370 * @has_out_rot: set if has output rotator
371 * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
372 * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
373 * are present in this IP revision
374 * @has_cam_if: set if this instance has a camera input interface
375 * @pix_limit: pixel size constraints for the scaler
376 * @min_inp_pixsize: minimum input pixel size
377 * @min_out_pixsize: minimum output pixel size
378 * @hor_offs_align: horizontal pixel offset aligment
379 * @out_buf_count: the number of buffers in output DMA sequence
381 struct samsung_fimc_variant {
382 unsigned int pix_hoff:1;
383 unsigned int has_inp_rot:1;
384 unsigned int has_out_rot:1;
385 unsigned int has_cistatus2:1;
386 unsigned int has_mainscaler_ext:1;
387 unsigned int has_cam_if:1;
388 struct fimc_pix_limit *pix_limit;
396 * struct samsung_fimc_driverdata - per device type driver data for init time.
398 * @variant: the variant information for this driver.
399 * @dev_cnt: number of fimc sub-devices available in SoC
400 * @lclk_frequency: fimc bus clock frequency
402 struct samsung_fimc_driverdata {
403 struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
404 unsigned long lclk_frequency;
408 struct fimc_pipeline {
409 struct media_pipeline *pipe;
410 struct v4l2_subdev *sensor;
411 struct v4l2_subdev *csis;
417 * struct fimc_dev - abstraction for FIMC entity
418 * @slock: the spinlock protecting this data structure
419 * @lock: the mutex protecting this data structure
420 * @pdev: pointer to the FIMC platform device
421 * @pdata: pointer to the device platform data
422 * @variant: the IP variant information
423 * @id: FIMC device index (0..FIMC_MAX_DEVS)
424 * @num_clocks: the number of clocks managed by this device instance
425 * @clock: clocks required for FIMC operation
426 * @regs: the mapped hardware registers
427 * @regs_res: the resource claimed for IO registers
428 * @irq: FIMC interrupt number
429 * @irq_queue: interrupt handler waitqueue
430 * @v4l2_dev: root v4l2_device
431 * @m2m: memory-to-memory V4L2 device information
432 * @vid_cap: camera capture device information
433 * @state: flags used to synchronize m2m and capture mode operation
434 * @alloc_ctx: videobuf2 memory allocator context
435 * @pipeline: fimc video capture pipeline data structure
440 struct platform_device *pdev;
441 struct s5p_platform_fimc *pdata;
442 struct samsung_fimc_variant *variant;
445 struct clk *clock[MAX_FIMC_CLOCKS];
447 struct resource *regs_res;
449 wait_queue_head_t irq_queue;
450 struct v4l2_device *v4l2_dev;
451 struct fimc_m2m_device m2m;
452 struct fimc_vid_cap vid_cap;
454 struct vb2_alloc_ctx *alloc_ctx;
455 struct fimc_pipeline pipeline;
459 * fimc_ctx - the device context data
460 * @slock: spinlock protecting this data structure
461 * @s_frame: source frame properties
462 * @d_frame: destination frame properties
463 * @out_order_1p: output 1-plane YCBCR order
464 * @out_order_2p: output 2-plane YCBCR order
465 * @in_order_1p input 1-plane YCBCR order
466 * @in_order_2p: input 2-plane YCBCR order
467 * @in_path: input mode (DMA or camera)
468 * @out_path: output mode (DMA or FIFO)
469 * @scaler: image scaler properties
470 * @effect: image effect
471 * @rotation: image clockwise rotation in degrees
472 * @hflip: indicates image horizontal flip if set
473 * @vflip: indicates image vertical flip if set
474 * @flags: additional flags for image conversion
475 * @state: flags to keep track of user configuration
476 * @fimc_dev: the FIMC device this context applies to
477 * @m2m_ctx: memory-to-memory device context
478 * @fh: v4l2 file handle
479 * @ctrl_handler: v4l2 controls handler
480 * @ctrl_rotate image rotation control
481 * @ctrl_hflip horizontal flip control
482 * @ctrl_vflip vartical flip control
483 * @ctrls_rdy: true if the control handler is initialized
487 struct fimc_frame s_frame;
488 struct fimc_frame d_frame;
493 enum fimc_datapath in_path;
494 enum fimc_datapath out_path;
495 struct fimc_scaler scaler;
496 struct fimc_effect effect;
498 unsigned int hflip:1;
499 unsigned int vflip:1;
502 struct fimc_dev *fimc_dev;
503 struct v4l2_m2m_ctx *m2m_ctx;
505 struct v4l2_ctrl_handler ctrl_handler;
506 struct v4l2_ctrl *ctrl_rotate;
507 struct v4l2_ctrl *ctrl_hflip;
508 struct v4l2_ctrl *ctrl_vflip;
512 #define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)
514 static inline void set_frame_bounds(struct fimc_frame *f, u32 width, u32 height)
517 f->o_height = height;
519 f->f_height = height;
522 static inline void set_frame_crop(struct fimc_frame *f,
523 u32 left, u32 top, u32 width, u32 height)
531 static inline u32 fimc_get_format_depth(struct fimc_fmt *ff)
536 for (i = 0; i < ff->colplanes; i++)
537 depth += ff->depth[i];
541 static inline bool fimc_capture_active(struct fimc_dev *fimc)
546 spin_lock_irqsave(&fimc->slock, flags);
547 ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
548 fimc->state & (1 << ST_CAPT_PEND));
549 spin_unlock_irqrestore(&fimc->slock, flags);
553 static inline void fimc_ctx_state_lock_set(u32 state, struct fimc_ctx *ctx)
557 spin_lock_irqsave(&ctx->slock, flags);
559 spin_unlock_irqrestore(&ctx->slock, flags);
562 static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
567 spin_lock_irqsave(&ctx->slock, flags);
568 ret = (ctx->state & mask) == mask;
569 spin_unlock_irqrestore(&ctx->slock, flags);
573 static inline int tiled_fmt(struct fimc_fmt *fmt)
575 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
578 static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
580 u32 cfg = readl(dev->regs + S5P_CIGCTRL);
581 cfg |= S5P_CIGCTRL_IRQ_CLR;
582 writel(cfg, dev->regs + S5P_CIGCTRL);
585 static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
587 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
589 cfg |= S5P_CISCCTRL_SCALERSTART;
591 cfg &= ~S5P_CISCCTRL_SCALERSTART;
592 writel(cfg, dev->regs + S5P_CISCCTRL);
595 static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
597 u32 cfg = readl(dev->regs + S5P_MSCTRL);
599 cfg |= S5P_MSCTRL_ENVID;
601 cfg &= ~S5P_MSCTRL_ENVID;
602 writel(cfg, dev->regs + S5P_MSCTRL);
605 static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
607 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
608 cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
609 writel(cfg, dev->regs + S5P_CIIMGCPT);
613 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
614 * @mask: each bit corresponds to one of 32 output buffer registers set
615 * 1 to include buffer in the sequence, 0 to disable
617 * This function mask output DMA ring buffers, i.e. it allows to configure
618 * which of the output buffer address registers will be used by the DMA
621 static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
623 writel(mask, dev->regs + S5P_CIFCNTSEQ);
626 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
627 enum v4l2_buf_type type)
629 struct fimc_frame *frame;
631 if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
632 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
633 frame = &ctx->s_frame;
635 return ERR_PTR(-EINVAL);
636 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
637 frame = &ctx->d_frame;
639 v4l2_err(ctx->fimc_dev->v4l2_dev,
640 "Wrong buffer/video queue type (%d)\n", type);
641 return ERR_PTR(-EINVAL);
647 /* Return an index to the buffer actually being written. */
648 static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
652 if (dev->variant->has_cistatus2) {
653 reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
654 return reg > 0 ? --reg : reg;
656 reg = readl(dev->regs + S5P_CISTATUS);
657 return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
658 S5P_CISTATUS_FRAMECNT_SHIFT;
662 /* -----------------------------------------------------*/
664 void fimc_hw_reset(struct fimc_dev *fimc);
665 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
666 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
667 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
668 void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
669 void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
670 void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
671 void fimc_hw_set_mainscaler(struct fimc_ctx *ctx);
672 void fimc_hw_en_capture(struct fimc_ctx *ctx);
673 void fimc_hw_set_effect(struct fimc_ctx *ctx, bool active);
674 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
675 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
676 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
677 void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
678 void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
680 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
681 struct s5p_fimc_isp_info *cam);
682 int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
683 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
684 struct s5p_fimc_isp_info *cam);
685 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
686 struct s5p_fimc_isp_info *cam);
688 /* -----------------------------------------------------*/
690 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
691 struct v4l2_fmtdesc *f);
692 int fimc_ctrls_create(struct fimc_ctx *ctx);
693 void fimc_ctrls_delete(struct fimc_ctx *ctx);
694 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active);
695 int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f);
696 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
697 struct v4l2_pix_format_mplane *pix);
698 struct fimc_fmt *fimc_find_format(u32 *pixelformat, u32 *mbus_code,
699 unsigned int mask, int index);
701 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
702 int dw, int dh, int rotation);
703 int fimc_set_scaler_info(struct fimc_ctx *ctx);
704 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
705 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
706 struct fimc_frame *frame, struct fimc_addr *paddr);
707 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f);
708 void fimc_set_yuv_order(struct fimc_ctx *ctx);
709 void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f);
710 void fimc_capture_irq_handler(struct fimc_dev *fimc, bool done);
712 int fimc_register_m2m_device(struct fimc_dev *fimc,
713 struct v4l2_device *v4l2_dev);
714 void fimc_unregister_m2m_device(struct fimc_dev *fimc);
715 int fimc_register_driver(void);
716 void fimc_unregister_driver(void);
718 /* -----------------------------------------------------*/
720 int fimc_register_capture_device(struct fimc_dev *fimc,
721 struct v4l2_device *v4l2_dev);
722 void fimc_unregister_capture_device(struct fimc_dev *fimc);
723 int fimc_capture_ctrls_create(struct fimc_dev *fimc);
724 int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
725 struct fimc_vid_buffer *fimc_vb);
726 void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
728 int fimc_capture_suspend(struct fimc_dev *fimc);
729 int fimc_capture_resume(struct fimc_dev *fimc);
730 int fimc_capture_config_update(struct fimc_ctx *ctx);
732 /* Locking: the caller holds fimc->slock */
733 static inline void fimc_activate_capture(struct fimc_ctx *ctx)
735 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
736 fimc_hw_en_capture(ctx);
739 static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
741 fimc_hw_en_lastirq(fimc, true);
742 fimc_hw_dis_capture(fimc);
743 fimc_hw_enable_scaler(fimc, false);
744 fimc_hw_en_lastirq(fimc, false);
748 * Add buf to the capture active buffers queue.
749 * Locking: Need to be called with fimc_dev::slock held.
751 static inline void active_queue_add(struct fimc_vid_cap *vid_cap,
752 struct fimc_vid_buffer *buf)
754 list_add_tail(&buf->list, &vid_cap->active_buf_q);
755 vid_cap->active_buf_cnt++;
759 * Pop a video buffer from the capture active buffers queue
760 * Locking: Need to be called with fimc_dev::slock held.
762 static inline struct fimc_vid_buffer *
763 active_queue_pop(struct fimc_vid_cap *vid_cap)
765 struct fimc_vid_buffer *buf;
766 buf = list_entry(vid_cap->active_buf_q.next,
767 struct fimc_vid_buffer, list);
768 list_del(&buf->list);
769 vid_cap->active_buf_cnt--;
773 /* Add video buffer to the capture pending buffers queue */
774 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
775 struct fimc_vid_buffer *buf)
777 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
780 /* Add video buffer to the capture pending buffers queue */
781 static inline struct fimc_vid_buffer *
782 pending_queue_pop(struct fimc_vid_cap *vid_cap)
784 struct fimc_vid_buffer *buf;
785 buf = list_entry(vid_cap->pending_buf_q.next,
786 struct fimc_vid_buffer, list);
787 list_del(&buf->list);
791 #endif /* FIMC_CORE_H_ */