1 #ifndef _ASM_X86_IRQ_VECTORS_H
2 #define _ASM_X86_IRQ_VECTORS_H
4 #define MCE_VECTOR 0x12
6 #define IA32_SYSCALL_VECTOR 0x80
8 # define SYSCALL_VECTOR 0x80
11 #define RESCHEDULE_VECTOR 0
12 #define CALL_FUNCTION_VECTOR 1
13 #define CALL_FUNC_SINGLE_VECTOR 2
14 #define SPIN_UNLOCK_VECTOR 3
18 * The maximum number of vectors supported by i386 processors
19 * is limited to 256. For processors other than i386, NR_VECTORS
20 * should be changed accordingly.
22 #define NR_VECTORS 256
24 #define FIRST_VM86_IRQ 3
25 #define LAST_VM86_IRQ 15
28 static inline int invalid_vm86_irq(int irq)
30 return irq < FIRST_VM86_IRQ || irq > LAST_VM86_IRQ;
35 * Size the maximum number of interrupts.
37 * If the irq_desc[] array has a sparse layout, we can size things
38 * generously - it scales up linearly with the maximum number of CPUs,
39 * and the maximum number of IO-APICs, whichever is higher.
41 * In other cases we size more conservatively, to not create too large
45 #define NR_IRQS_LEGACY 16
48 * The flat IRQ space is divided into two regions:
49 * 1. A one-to-one mapping of real physical IRQs. This space is only used
50 * if we have physical device-access privilege. This region is at the
51 * start of the IRQ space so that existing device drivers do not need
52 * to be modified to translate physical IRQ numbers into our IRQ space.
53 * 3. A dynamic mapping of inter-domain and Xen-sourced virtual IRQs. These
54 * are bound using the provided bind/unbind functions.
57 /* PHYSDEVOP_pirq_eoi_gmfn restriction: */
58 #define PIRQ_MAX(n) ((n) < (1 << (PAGE_SHIFT + 3)) - NR_VECTORS \
59 ? (n) : (1 << (PAGE_SHIFT + 3)) - NR_VECTORS)
61 #define IO_APIC_VECTOR_LIMIT PIRQ_MAX(32 * MAX_IO_APICS)
63 #ifdef CONFIG_SPARSE_IRQ
64 # define CPU_VECTOR_LIMIT PIRQ_MAX(64 * NR_CPUS)
66 # define CPU_VECTOR_LIMIT PIRQ_MAX(32 * NR_CPUS)
69 #ifdef CONFIG_X86_IO_APIC
70 # if !defined(NR_CPUS) || !defined(MAX_IO_APICS)
72 # elif defined(CONFIG_SPARSE_IRQ)
74 (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \
75 (NR_VECTORS + CPU_VECTOR_LIMIT) : \
76 (NR_VECTORS + IO_APIC_VECTOR_LIMIT))
79 (CPU_VECTOR_LIMIT < IO_APIC_VECTOR_LIMIT ? \
80 (NR_VECTORS + CPU_VECTOR_LIMIT) : \
81 (NR_VECTORS + IO_APIC_VECTOR_LIMIT))
83 #elif defined(CONFIG_XEN_PCIDEV_FRONTEND)
84 # define NR_PIRQS (NR_VECTORS + CPU_VECTOR_LIMIT)
85 #else /* !CONFIG_X86_IO_APIC: */
86 # define NR_PIRQS NR_IRQS_LEGACY
90 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SPARSE_IRQ)
93 # define nr_pirqs NR_PIRQS
97 #define DYNIRQ_BASE (PIRQ_BASE + nr_pirqs)
98 #define NR_DYNIRQS (64 + CONFIG_XEN_NR_GUEST_DEVICES)
100 #define NR_IRQS (NR_PIRQS + NR_DYNIRQS)
102 #endif /* _ASM_X86_IRQ_VECTORS_H */