1 /* Copyright 1998, 1999, 2000, 2001, 2002, 2003
2 Free Software Foundation, Inc.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
21 /* Extracted from binutils 2.16.91.0.2 (OpenSUSE 10.0) and modified for kdb use.
22 * Any trailing whitespace was removed and #ifdef/ifndef __KERNEL__ added as
24 * Keith Owens <kaos@sgi.com> 15 May 2006
27 /* Logically, this code should be part of libopcode but since some of
28 the operand insertion/extraction functions help bfd to implement
29 relocations, this code is included as part of cpu-ia64.c. This
30 avoids circular dependencies between libopcode and libbfd and also
31 obviates the need for applications to link in libopcode when all
32 they really want is libbfd.
34 --davidm Mon Apr 13 22:14:02 1998 */
38 #else /* __KERNEL__ */
39 #include "../opcodes/ia64-opc.h"
40 #endif /* __KERNEL__ */
42 #define NELEMS(a) ((int) (sizeof (a) / sizeof ((a)[0])))
45 ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
46 ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
48 return "internal error---this shouldn't happen";
52 ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
53 ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
55 return "internal error---this shouldn't happen";
59 ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
60 ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
66 ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
67 ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
73 ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
75 if (value >= 1u << self->field[0].bits)
76 return "register number out of range";
78 *code |= value << self->field[0].shift;
83 ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
85 *valuep = ((code >> self->field[0].shift)
86 & ((1u << self->field[0].bits) - 1));
91 ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
96 for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
98 new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
99 << self->field[i].shift);
100 value >>= self->field[i].bits;
103 return "integer operand out of range";
110 ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
112 BFD_HOST_U_64_BIT value = 0;
113 int i, bits = 0, total = 0;
115 for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
117 bits = self->field[i].bits;
118 value |= ((code >> self->field[i].shift)
119 & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
127 ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
130 return "value not an integer multiple of 8";
131 return ins_immu (self, value >> 3, code);
135 ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
139 result = ext_immu (self, code, valuep);
143 *valuep = *valuep << 3;
148 ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
149 ia64_insn *code, int scale)
151 BFD_HOST_64_BIT svalue = value, sign_bit = 0;
157 for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
159 new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
160 << self->field[i].shift);
161 sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
162 svalue >>= self->field[i].bits;
164 if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
165 return "integer operand out of range";
172 ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
173 ia64_insn *valuep, int scale)
175 int i, bits = 0, total = 0;
176 BFD_HOST_64_BIT val = 0, sign;
178 for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
180 bits = self->field[i].bits;
181 val |= ((code >> self->field[i].shift)
182 & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
186 sign = (BFD_HOST_64_BIT) 1 << (total - 1);
187 val = (val ^ sign) - sign;
189 *valuep = (val << scale);
194 ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
196 return ins_imms_scaled (self, value, code, 0);
200 ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
202 value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
204 return ins_imms_scaled (self, value, code, 0);
208 ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
210 return ext_imms_scaled (self, code, valuep, 0);
214 ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
217 return ins_imms_scaled (self, value, code, 0);
221 ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
224 value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
227 return ins_imms_scaled (self, value, code, 0);
231 ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
233 const char *res = ext_imms_scaled (self, code, valuep, 0);
240 ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
242 return ins_imms_scaled (self, value, code, 1);
246 ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
248 return ext_imms_scaled (self, code, valuep, 1);
252 ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
254 return ins_imms_scaled (self, value, code, 4);
258 ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
260 return ext_imms_scaled (self, code, valuep, 4);
264 ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
266 return ins_imms_scaled (self, value, code, 16);
270 ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
272 return ext_imms_scaled (self, code, valuep, 16);
276 ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
278 ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
279 return ins_immu (self, value ^ mask, code);
283 ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
288 mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
289 result = ext_immu (self, code, valuep);
292 mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
299 ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
302 if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
303 return "count out of range";
305 *code |= value << self->field[0].shift;
310 ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
312 *valuep = ((code >> self->field[0].shift)
313 & ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
318 ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
323 return "count must be in range 1..3";
325 *code |= value << self->field[0].shift;
330 ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
332 *valuep = ((code >> self->field[0].shift) & 0x3) + 1;
337 ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
341 case 0: value = 0; break;
342 case 7: value = 1; break;
343 case 15: value = 2; break;
344 case 16: value = 3; break;
345 default: return "count must be 0, 7, 15, or 16";
347 *code |= value << self->field[0].shift;
352 ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
356 value = (code >> self->field[0].shift) & 0x3;
359 case 0: value = 0; break;
360 case 1: value = 7; break;
361 case 2: value = 15; break;
362 case 3: value = 16; break;
369 ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
371 BFD_HOST_64_BIT val = value;
372 BFD_HOST_U_64_BIT sign = 0;
381 case 1: value = 3; break;
382 case 4: value = 2; break;
383 case 8: value = 1; break;
384 case 16: value = 0; break;
385 default: return "count must be +/- 1, 4, 8, or 16";
387 *code |= (sign | value) << self->field[0].shift;
392 ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
397 val = (code >> self->field[0].shift) & 0x7;
401 case 0: val = 16; break;
402 case 1: val = 8; break;
403 case 2: val = 4; break;
404 case 3: val = 1; break;
413 #define CST IA64_OPND_CLASS_CST
414 #define REG IA64_OPND_CLASS_REG
415 #define IND IA64_OPND_CLASS_IND
416 #define ABS IA64_OPND_CLASS_ABS
417 #define REL IA64_OPND_CLASS_REL
419 #define SDEC IA64_OPND_FLAG_DECIMAL_SIGNED
420 #define UDEC IA64_OPND_FLAG_DECIMAL_UNSIGNED
422 const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
425 { CST, ins_const, ext_const, "NIL", {{ 0, 0}}, 0, "<none>" },
426 { CST, ins_const, ext_const, "ar.csd", {{ 0, 0}}, 0, "ar.csd" },
427 { CST, ins_const, ext_const, "ar.ccv", {{ 0, 0}}, 0, "ar.ccv" },
428 { CST, ins_const, ext_const, "ar.pfs", {{ 0, 0}}, 0, "ar.pfs" },
429 { CST, ins_const, ext_const, "1", {{ 0, 0}}, 0, "1" },
430 { CST, ins_const, ext_const, "8", {{ 0, 0}}, 0, "8" },
431 { CST, ins_const, ext_const, "16", {{ 0, 0}}, 0, "16" },
432 { CST, ins_const, ext_const, "r0", {{ 0, 0}}, 0, "r0" },
433 { CST, ins_const, ext_const, "ip", {{ 0, 0}}, 0, "ip" },
434 { CST, ins_const, ext_const, "pr", {{ 0, 0}}, 0, "pr" },
435 { CST, ins_const, ext_const, "pr.rot", {{ 0, 0}}, 0, "pr.rot" },
436 { CST, ins_const, ext_const, "psr", {{ 0, 0}}, 0, "psr" },
437 { CST, ins_const, ext_const, "psr.l", {{ 0, 0}}, 0, "psr.l" },
438 { CST, ins_const, ext_const, "psr.um", {{ 0, 0}}, 0, "psr.um" },
440 /* register operands: */
441 { REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */
442 "an application register" },
443 { REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */
444 "a branch register" },
445 { REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */
446 "a branch register"},
447 { REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */
448 "a control register"},
449 { REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */
450 "a floating-point register" },
451 { REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */
452 "a floating-point register" },
453 { REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */
454 "a floating-point register" },
455 { REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */
456 "a floating-point register" },
457 { REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */
458 "a predicate register" },
459 { REG, ins_reg, ext_reg, "p", {{ 6, 27}}, 0, /* P2 */
460 "a predicate register" },
461 { REG, ins_reg, ext_reg, "r", {{ 7, 6}}, 0, /* R1 */
462 "a general register" },
463 { REG, ins_reg, ext_reg, "r", {{ 7, 13}}, 0, /* R2 */
464 "a general register" },
465 { REG, ins_reg, ext_reg, "r", {{ 7, 20}}, 0, /* R3 */
466 "a general register" },
467 { REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */
468 "a general register r0-r3" },
470 /* indirect operands: */
471 { IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */
472 "a cpuid register" },
473 { IND, ins_reg, ext_reg, "dbr", {{7, 20}}, 0, /* DBR_R3 */
475 { IND, ins_reg, ext_reg, "dtr", {{7, 20}}, 0, /* DTR_R3 */
477 { IND, ins_reg, ext_reg, "itr", {{7, 20}}, 0, /* ITR_R3 */
479 { IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */
481 { IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */
482 "an indirect memory address" },
483 { IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */
485 { IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */
487 { IND, ins_reg, ext_reg, "pmc", {{7, 20}}, 0, /* PMC_R3 */
489 { IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */
491 { IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */
494 /* immediate operands: */
495 { ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC, /* CCNT5 */
496 "a 5-bit count (0-31)" },
497 { ABS, ins_cnt, ext_cnt, 0, {{ 2, 27 }}, UDEC, /* CNT2a */
498 "a 2-bit count (1-4)" },
499 { ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC, /* CNT2b */
500 "a 2-bit count (1-3)" },
501 { ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC, /* CNT2c */
502 "a count (0, 7, 15, or 16)" },
503 { ABS, ins_immu, ext_immu, 0, {{ 5, 14}}, UDEC, /* CNT5 */
504 "a 5-bit count (0-31)" },
505 { ABS, ins_immu, ext_immu, 0, {{ 6, 27}}, UDEC, /* CNT6 */
506 "a 6-bit count (0-63)" },
507 { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC, /* CPOS6a */
508 "a 6-bit bit pos (0-63)" },
509 { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC, /* CPOS6b */
510 "a 6-bit bit pos (0-63)" },
511 { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC, /* CPOS6c */
512 "a 6-bit bit pos (0-63)" },
513 { ABS, ins_imms, ext_imms, 0, {{ 1, 36}}, SDEC, /* IMM1 */
514 "a 1-bit integer (-1, 0)" },
515 { ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */
516 "a 2-bit unsigned (0-3)" },
517 { ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */
518 "a 7-bit unsigned (0-127)" },
519 { ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */
520 "a 7-bit unsigned (0-127)" },
521 { ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, UDEC, /* SOF */
522 "a frame size (register count)" },
523 { ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, UDEC, /* SOL */
524 "a local register count" },
525 { ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC, /* SOR */
526 "a rotating register count (integer multiple of 8)" },
527 { ABS, ins_imms, ext_imms, 0, /* IMM8 */
528 {{ 7, 13}, { 1, 36}}, SDEC,
529 "an 8-bit integer (-128-127)" },
530 { ABS, ins_immsu4, ext_imms, 0, /* IMM8U4 */
531 {{ 7, 13}, { 1, 36}}, SDEC,
532 "an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
533 { ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1 */
534 {{ 7, 13}, { 1, 36}}, SDEC,
535 "an 8-bit integer (-127-128)" },
536 { ABS, ins_immsm1u4, ext_immsm1, 0, /* IMM8M1U4 */
537 {{ 7, 13}, { 1, 36}}, SDEC,
538 "an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
539 { ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1U8 */
540 {{ 7, 13}, { 1, 36}}, SDEC,
541 "an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
542 { ABS, ins_immu, ext_immu, 0, {{ 2, 33}, { 7, 20}}, 0, /* IMMU9 */
543 "a 9-bit unsigned (0-511)" },
544 { ABS, ins_imms, ext_imms, 0, /* IMM9a */
545 {{ 7, 6}, { 1, 27}, { 1, 36}}, SDEC,
546 "a 9-bit integer (-256-255)" },
547 { ABS, ins_imms, ext_imms, 0, /* IMM9b */
548 {{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
549 "a 9-bit integer (-256-255)" },
550 { ABS, ins_imms, ext_imms, 0, /* IMM14 */
551 {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
552 "a 14-bit integer (-8192-8191)" },
553 { ABS, ins_imms1, ext_imms1, 0, /* IMM17 */
554 {{ 7, 6}, { 8, 24}, { 1, 36}}, 0,
555 "a 17-bit integer (-65536-65535)" },
556 { ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */
557 "a 21-bit unsigned" },
558 { ABS, ins_imms, ext_imms, 0, /* IMM22 */
559 {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
560 "a 22-bit signed integer" },
561 { ABS, ins_immu, ext_immu, 0, /* IMMU24 */
562 {{21, 6}, { 2, 31}, { 1, 36}}, 0,
563 "a 24-bit unsigned" },
564 { ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */
565 "a 44-bit unsigned (least 16 bits ignored/zeroes)" },
566 { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */
567 "a 62-bit unsigned" },
568 { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */
569 "a 64-bit unsigned" },
570 { ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */
571 "an increment (+/- 1, 4, 8, or 16)" },
572 { ABS, ins_cnt, ext_cnt, 0, {{ 4, 27}}, UDEC, /* LEN4 */
573 "a 4-bit length (1-16)" },
574 { ABS, ins_cnt, ext_cnt, 0, {{ 6, 27}}, UDEC, /* LEN6 */
575 "a 6-bit length (1-64)" },
576 { ABS, ins_immu, ext_immu, 0, {{ 4, 20}}, 0, /* MBTYPE4 */
577 "a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
578 { ABS, ins_immu, ext_immu, 0, {{ 8, 20}}, 0, /* MBTYPE8 */
579 "an 8-bit mix type" },
580 { ABS, ins_immu, ext_immu, 0, {{ 6, 14}}, UDEC, /* POS6 */
581 "a 6-bit bit pos (0-63)" },
582 { REL, ins_imms4, ext_imms4, 0, {{ 7, 6}, { 2, 33}}, 0, /* TAG13 */
584 { REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0, /* TAG13b */
586 { REL, ins_imms4, ext_imms4, 0, {{20, 6}, { 1, 36}}, 0, /* TGT25 */
588 { REL, ins_imms4, ext_imms4, 0, /* TGT25b */
589 {{ 7, 6}, {13, 20}, { 1, 36}}, 0,
591 { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */
593 { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */
596 { ABS, ins_const, ext_const, 0, {{0, 0}}, 0, /* LDXMOV */