2 * linux/arch/i386/kernel/head.S -- the 32-bit startup code.
4 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Enhanced CPU detection and feature setting code by Mike Jagdis
7 * and Martin Mares, November 1997.
11 #include <linux/config.h>
12 #include <linux/threads.h>
13 #include <linux/linkage.h>
14 #include <asm/segment.h>
16 #include <asm/pgtable.h>
18 #include <asm/cache.h>
20 #define OLD_CL_MAGIC_ADDR 0x90020
21 #define OLD_CL_MAGIC 0xA33F
22 #define OLD_CL_BASE_ADDR 0x90000
23 #define OLD_CL_OFFSET 0x90022
24 #define NEW_CL_POINTER 0x228 /* Relative to real mode data */
27 * References to members of the new_cpu_data structure.
30 #define CPU_PARAMS new_cpu_data
31 #define X86 CPU_PARAMS+0
32 #define X86_VENDOR CPU_PARAMS+1
33 #define X86_MODEL CPU_PARAMS+2
34 #define X86_MASK CPU_PARAMS+3
35 #define X86_HARD_MATH CPU_PARAMS+6
36 #define X86_CPUID CPU_PARAMS+8
37 #define X86_CAPABILITY CPU_PARAMS+12
38 #define X86_VENDOR_ID CPU_PARAMS+36 /* offset dependent on NCAPINTS */
41 * Initialize page tables
43 #define INIT_PAGE_TABLES \
44 movl $pg0 - __PAGE_OFFSET, %edi; \
45 /* "007" doesn't mean with license to kill, but PRESENT+RW+USER */ \
49 cmp $empty_zero_page - __PAGE_OFFSET, %edi; \
53 * swapper_pg_dir is the main page directory, address 0x00101000
55 * On entry, %esi points to the real-mode code as a 32-bit pointer.
59 #ifdef CONFIG_X86_VISWS
61 * On SGI Visual Workstations boot CPU starts in protected mode.
66 movl $swapper_pg_dir - __PAGE_OFFSET, %eax
73 * Set segments to known values
76 movl $(__BOOT_DS),%eax
86 * New page tables may be in 4Mbyte page mode and may
87 * be using the global pages.
89 * NOTE! If we are on a 486 we may have no cr4 at all!
90 * So we do not try to touch it unless we really have
91 * some bits in it to set. This won't work if the BSP
92 * implements cr4 but this AP does not -- very unlikely
93 * but be warned! The same applies to the pse feature
94 * if not equally supported. --macro
96 * NOTE! We have to correct for the fact that we're
97 * not yet offset PAGE_OFFSET..
99 #define cr4_bits mmu_cr4_features-__PAGE_OFFSET
102 movl %cr4,%eax # Turn on paging options (PSE,PAE,..)
113 movl $swapper_pg_dir-__PAGE_OFFSET,%eax
114 movl %eax,%cr3 /* set the page table pointer.. */
117 movl %eax,%cr0 /* ..and set paging (PG) bit */
118 jmp 1f /* flush the prefetch-queue */
121 jmp *%eax /* make sure eip is relocated */
123 /* Set up the stack pointer */
128 jz 1f /* Initial CPU cleans BSS */
133 #endif /* CONFIG_SMP */
136 * Clear BSS first so that there are no surprises...
137 * No need to cld as DF is already clear from cld above...
140 movl $__bss_start,%edi
141 movl $__bss_stop,%ecx
147 * start system 32-bit setup. We need to re-do some of the things done
148 * in 16-bit mode for the "real" operations.
152 * Initialize eflags. Some BIOS's leave bits like NT set. This would
153 * confuse the debugger if this code is traced.
154 * XXX - best to initialize before switching to protected mode.
159 * Copy bootup parameters out of the way. First 2kB of
160 * _empty_zero_page is for boot parameters, second 2kB
161 * is for the command line.
163 * Note: %esi still has the pointer to the real-mode data.
165 movl $empty_zero_page,%edi
174 movl empty_zero_page+NEW_CL_POINTER,%esi
176 jnz 2f # New command line protocol
177 cmpw $(OLD_CL_MAGIC),OLD_CL_MAGIC_ADDR
179 movzwl OLD_CL_OFFSET,%esi
180 addl $(OLD_CL_BASE_ADDR),%esi
182 movl $empty_zero_page+2048,%edi
189 movl $-1,X86_CPUID # -1 for no CPUID initially
191 /* check if it is 486 or 386. */
193 * XXX - this does a lot of unnecessary setup. Alignment checks don't
194 * apply at our cpl of 0 and the stack ought to be aligned already, and
195 * we don't need to preserve eflags.
198 movb $3,X86 # at least 386
200 popl %eax # get EFLAGS
201 movl %eax,%ecx # save original EFLAGS
202 xorl $0x240000,%eax # flip AC and ID bits in EFLAGS
203 pushl %eax # copy to EFLAGS
205 pushfl # get new EFLAGS
206 popl %eax # put it in eax
207 xorl %ecx,%eax # change in flags
208 pushl %ecx # restore original EFLAGS
210 testl $0x40000,%eax # check if AC bit changed
213 movb $4,X86 # at least 486
214 testl $0x200000,%eax # check if ID bit changed
217 /* get vendor info */
218 xorl %eax,%eax # call CPUID with 0 -> return vendor ID
220 movl %eax,X86_CPUID # save CPUID level
221 movl %ebx,X86_VENDOR_ID # lo 4 chars
222 movl %edx,X86_VENDOR_ID+4 # next 4 chars
223 movl %ecx,X86_VENDOR_ID+8 # last 4 chars
225 orl %eax,%eax # do we have processor info as well?
228 movl $1,%eax # Use the CPUID instruction to get CPU type
230 movb %al,%cl # save reg for future use
231 andb $0x0f,%ah # mask processor family
233 andb $0xf0,%al # mask model
236 andb $0x0f,%cl # mask mask revision
238 movl %edx,X86_CAPABILITY
240 is486: movl $0x50022,%ecx # set AM, WP, NE and MP
243 is386: movl $2,%ecx # set MP
245 andl $0x80000011,%eax # Save PG,PE,ET
253 ljmp $(__KERNEL_CS),$1f
254 1: movl $(__KERNEL_DS),%eax # reload all the segment registers
255 movl %eax,%ss # after changing gdt.
257 movl $(__USER_DS),%eax # DS/ES contains default USER segment
261 xorl %eax,%eax # Clear FS/GS and LDT
265 cld # gcc2 wants the direction flag cleared at all times
269 je 1f # the first CPU calls start_kernel
270 # all other CPUs call initialize_secondary
271 call initialize_secondary
277 jmp L6 # main should never return here, but
278 # just in case, we know what happens.
283 * We depend on ET to be correct. This checks for 287/387.
286 movb $0,X86_HARD_MATH
292 movl %cr0,%eax /* no coprocessor: have to set bits */
293 xorl $4,%eax /* set EM */
297 1: movb $1,X86_HARD_MATH
298 .byte 0xDB,0xE4 /* fsetpm for 287, ignored by 387 */
304 * sets up a idt with 256 entries pointing to
305 * ignore_int, interrupt gates. It doesn't actually load
306 * idt - that can be done only after paging has been enabled
307 * and the kernel moved to PAGE_OFFSET. Interrupts
308 * are enabled elsewhere, when we can be relatively
309 * sure everything is ok.
313 movl $(__KERNEL_CS << 16),%eax
314 movw %dx,%ax /* selector = 0x0010 = cs */
315 movw $0x8E00,%dx /* interrupt gate - dpl=0, present */
328 .long init_thread_union+8192
331 /* This is the default interrupt "handler" :-) */
333 .asciz "Unknown interrupt\n"
342 movl $(__KERNEL_DS),%eax
356 * The IDT and GDT 'descriptors' are a strange 48-bit object
357 * only used by the lidt and lgdt instructions. They are not
358 * like usual segment descriptors - they consist of a 16-bit
359 * segment size, and 32-bit linear address value:
366 .word 0 # 32-bit align idt_desc.address
368 .word IDT_ENTRIES*8-1 # idt contains 256 entries
371 # boot GDT descriptor (later on used by CPU#0):
372 .word 0 # 32 bit align gdt_desc.address
374 .word GDT_ENTRIES*8-1
377 .fill NR_CPUS-1,8,0 # space for the other GDT descriptors
380 * This is initialized to create an identity-mapping at 0-8M (for bootup
381 * purposes) and another mapping of the 0-8M area at virtual address
385 ENTRY(swapper_pg_dir)
388 .fill BOOT_USER_PGD_PTRS-2,4,0
389 /* default: 766 entries */
392 /* default: 254 entries */
393 .fill BOOT_KERNEL_PGD_PTRS-2,4,0
396 * The page tables are initialized to only 8MB here - the final page
397 * tables are set up later depending on memory size.
406 * empty_zero_page must immediately follow the page tables ! (The
407 * initialization loop counts until empty_zero_page)
411 ENTRY(empty_zero_page)
416 * Real beginning of normal "text" segment
422 * This starts the data section. Note that the above is all
423 * in the text section because it has alignment requirements
424 * that we cannot fulfill any other way.
429 * The Global Descriptor Table contains 28 quadwords, per-CPU.
431 #if defined(CONFIG_SMP) || defined(CONFIG_X86_VISWS)
433 * The boot_gdt_table must mirror the equivalent in setup.S and is
434 * used only by the trampoline for booting other CPUs
436 .align L1_CACHE_BYTES
437 ENTRY(boot_gdt_table)
438 .fill GDT_ENTRY_BOOT_CS,8,0
439 .quad 0x00cf9a000000ffff /* kernel 4GB code at 0x00000000 */
440 .quad 0x00cf92000000ffff /* kernel 4GB data at 0x00000000 */
442 .align L1_CACHE_BYTES
444 .quad 0x0000000000000000 /* NULL descriptor */
445 .quad 0x0000000000000000 /* 0x0b reserved */
446 .quad 0x0000000000000000 /* 0x13 reserved */
447 .quad 0x0000000000000000 /* 0x1b reserved */
448 .quad 0x0000000000000000 /* 0x20 unused */
449 .quad 0x0000000000000000 /* 0x28 unused */
450 .quad 0x0000000000000000 /* 0x33 TLS entry 1 */
451 .quad 0x0000000000000000 /* 0x3b TLS entry 2 */
452 .quad 0x0000000000000000 /* 0x43 TLS entry 3 */
453 .quad 0x0000000000000000 /* 0x4b reserved */
454 .quad 0x0000000000000000 /* 0x53 reserved */
455 .quad 0x0000000000000000 /* 0x5b reserved */
457 .quad 0x00cf9a000000ffff /* 0x60 kernel 4GB code at 0x00000000 */
458 .quad 0x00cf92000000ffff /* 0x68 kernel 4GB data at 0x00000000 */
459 .quad 0x00cffa000000ffff /* 0x73 user 4GB code at 0x00000000 */
460 .quad 0x00cff2000000ffff /* 0x7b user 4GB data at 0x00000000 */
462 .quad 0x0000000000000000 /* 0x80 TSS descriptor */
463 .quad 0x0000000000000000 /* 0x88 LDT descriptor */
465 /* Segments used for calling PnP BIOS */
466 .quad 0x00c09a0000000000 /* 0x90 32-bit code */
467 .quad 0x00809a0000000000 /* 0x98 16-bit code */
468 .quad 0x0080920000000000 /* 0xa0 16-bit data */
469 .quad 0x0080920000000000 /* 0xa8 16-bit data */
470 .quad 0x0080920000000000 /* 0xb0 16-bit data */
472 * The APM segments have byte granularity and their bases
473 * and limits are set at run time.
475 .quad 0x00409a0000000000 /* 0xb8 APM CS code */
476 .quad 0x00009a0000000000 /* 0xc0 APM CS 16 code (16 bit) */
477 .quad 0x0040920000000000 /* 0xc8 APM DS data */
479 .quad 0x0000000000000000 /* 0xd0 - unused */
480 .quad 0x0000000000000000 /* 0xd8 - unused */
481 .quad 0x0000000000000000 /* 0xe0 - unused */
482 .quad 0x0000000000000000 /* 0xe8 - unused */
483 .quad 0x0000000000000000 /* 0xf0 - unused */
484 .quad 0x0000000000000000 /* 0xf8 - GDT entry 31: double-fault TSS */
487 .fill (NR_CPUS-1)*GDT_ENTRIES,8,0 /* other CPU's GDT */