arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27 #include <linux/device.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34 #include <asm/timer.h>
  35
  36 #include "perf_event.h"
  37
  38 #if 0
  39 #undef wrmsrl
  40 #define wrmsrl(msr, val)                                        \
  41 do {                                                            \
  42         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  43                         (unsigned long)(val));                  \
  44         native_write_msr((msr), (u32)((u64)(val)),              \
  45                         (u32)((u64)(val) >> 32));               \
  46 } while (0)
  47 #endif
  48
  49 struct x86_pmu x86_pmu __read_mostly;
  50
  51 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  52         .enabled = 1,
  53 };
  54
  55 u64 __read_mostly hw_cache_event_ids
  56                                 [PERF_COUNT_HW_CACHE_MAX]
  57                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  58                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  59 u64 __read_mostly hw_cache_extra_regs
  60                                 [PERF_COUNT_HW_CACHE_MAX]
  61                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  62                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  63
  64 /*
  65  * Propagate event elapsed time into the generic event.
  66  * Can only be executed on the CPU where the event is active.
  67  * Returns the delta events processed.
  68  */
  69 u64 x86_perf_event_update(struct perf_event *event)
  70 {
  71         struct hw_perf_event *hwc = &event->hw;
  72         int shift = 64 - x86_pmu.cntval_bits;
  73         u64 prev_raw_count, new_raw_count;
  74         int idx = hwc->idx;
  75         s64 delta;
  76
  77         if (idx == X86_PMC_IDX_FIXED_BTS)
  78                 return 0;
  79
  80         /*
  81          * Careful: an NMI might modify the previous event value.
  82          *
  83          * Our tactic to handle this is to first atomically read and
  84          * exchange a new raw count - then add that new-prev delta
  85          * count to the generic event atomically:
  86          */
  87 again:
  88         prev_raw_count = local64_read(&hwc->prev_count);
  89         rdmsrl(hwc->event_base, new_raw_count);
  90
  91         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  92                                         new_raw_count) != prev_raw_count)
  93                 goto again;
  94
  95         /*
  96          * Now we have the new raw value and have updated the prev
  97          * timestamp already. We can now calculate the elapsed delta
  98          * (event-)time and add that to the generic event.
  99          *
 100          * Careful, not all hw sign-extends above the physical width
 101          * of the count.
 102          */
 103         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 104         delta >>= shift;
 105
 106         local64_add(delta, &event->count);
 107         local64_sub(delta, &hwc->period_left);
 108
 109         return new_raw_count;
 110 }
 111
 112 /*
 113  * Find and validate any extra registers to set up.
 114  */
 115 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 116 {
 117         struct hw_perf_event_extra *reg;
 118         struct extra_reg *er;
 119
 120         reg = &event->hw.extra_reg;
 121
 122         if (!x86_pmu.extra_regs)
 123                 return 0;
 124
 125         for (er = x86_pmu.extra_regs; er->msr; er++) {
 126                 if (er->event != (config & er->config_mask))
 127                         continue;
 128                 if (event->attr.config1 & ~er->valid_mask)
 129                         return -EINVAL;
 130
 131                 reg->idx = er->idx;
 132                 reg->config = event->attr.config1;
 133                 reg->reg = er->msr;
 134                 break;
 135         }
 136         return 0;
 137 }
 138
 139 static atomic_t active_events;
 140 static DEFINE_MUTEX(pmc_reserve_mutex);
 141
 142 #ifdef CONFIG_X86_LOCAL_APIC
 143
 144 static bool reserve_pmc_hardware(void)
 145 {
 146         int i;
 147
 148         for (i = 0; i < x86_pmu.num_counters; i++) {
 149                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 150                         goto perfctr_fail;
 151         }
 152
 153         for (i = 0; i < x86_pmu.num_counters; i++) {
 154                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 155                         goto eventsel_fail;
 156         }
 157
 158         return true;
 159
 160 eventsel_fail:
 161         for (i--; i >= 0; i--)
 162                 release_evntsel_nmi(x86_pmu_config_addr(i));
 163
 164         i = x86_pmu.num_counters;
 165
 166 perfctr_fail:
 167         for (i--; i >= 0; i--)
 168                 release_perfctr_nmi(x86_pmu_event_addr(i));
 169
 170         return false;
 171 }
 172
 173 static void release_pmc_hardware(void)
 174 {
 175         int i;
 176
 177         for (i = 0; i < x86_pmu.num_counters; i++) {
 178                 release_perfctr_nmi(x86_pmu_event_addr(i));
 179                 release_evntsel_nmi(x86_pmu_config_addr(i));
 180         }
 181 }
 182
 183 #else
 184
 185 static bool reserve_pmc_hardware(void) { return true; }
 186 static void release_pmc_hardware(void) {}
 187
 188 #endif
 189
 190 static bool check_hw_exists(void)
 191 {
 192         u64 val, val_new = 0;
 193         int i, reg, ret = 0;
 194
 195         /*
 196          * Check to see if the BIOS enabled any of the counters, if so
 197          * complain and bail.
 198          */
 199         for (i = 0; i < x86_pmu.num_counters; i++) {
 200                 reg = x86_pmu_config_addr(i);
 201                 ret = rdmsrl_safe(reg, &val);
 202                 if (ret)
 203                         goto msr_fail;
 204                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
 205                         goto bios_fail;
 206         }
 207
 208         if (x86_pmu.num_counters_fixed) {
 209                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 210                 ret = rdmsrl_safe(reg, &val);
 211                 if (ret)
 212                         goto msr_fail;
 213                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 214                         if (val & (0x03 << i*4))
 215                                 goto bios_fail;
 216                 }
 217         }
 218
 219         /*
 220          * Now write a value and read it back to see if it matches,
 221          * this is needed to detect certain hardware emulators (qemu/kvm)
 222          * that don't trap on the MSR access and always return 0s.
 223          */
 224         val = 0xabcdUL;
 225         ret = checking_wrmsrl(x86_pmu_event_addr(0), val);
 226         ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);
 227         if (ret || val != val_new)
 228                 goto msr_fail;
 229
 230         return true;
 231
 232 bios_fail:
 233         /*
 234          * We still allow the PMU driver to operate:
 235          */
 236         printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 237         printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
 238
 239         return true;
 240
 241 msr_fail:
 242         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 243
 244         return false;
 245 }
 246
 247 static void hw_perf_event_destroy(struct perf_event *event)
 248 {
 249         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 250                 release_pmc_hardware();
 251                 release_ds_buffers();
 252                 mutex_unlock(&pmc_reserve_mutex);
 253         }
 254 }
 255
 256 static inline int x86_pmu_initialized(void)
 257 {
 258         return x86_pmu.handle_irq != NULL;
 259 }
 260
 261 static inline int
 262 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 263 {
 264         struct perf_event_attr *attr = &event->attr;
 265         unsigned int cache_type, cache_op, cache_result;
 266         u64 config, val;
 267
 268         config = attr->config;
 269
 270         cache_type = (config >>  0) & 0xff;
 271         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 272                 return -EINVAL;
 273
 274         cache_op = (config >>  8) & 0xff;
 275         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 276                 return -EINVAL;
 277
 278         cache_result = (config >> 16) & 0xff;
 279         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 280                 return -EINVAL;
 281
 282         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 283
 284         if (val == 0)
 285                 return -ENOENT;
 286
 287         if (val == -1)
 288                 return -EINVAL;
 289
 290         hwc->config |= val;
 291         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 292         return x86_pmu_extra_regs(val, event);
 293 }
 294
 295 int x86_setup_perfctr(struct perf_event *event)
 296 {
 297         struct perf_event_attr *attr = &event->attr;
 298         struct hw_perf_event *hwc = &event->hw;
 299         u64 config;
 300
 301         if (!is_sampling_event(event)) {
 302                 hwc->sample_period = x86_pmu.max_period;
 303                 hwc->last_period = hwc->sample_period;
 304                 local64_set(&hwc->period_left, hwc->sample_period);
 305         } else {
 306                 /*
 307                  * If we have a PMU initialized but no APIC
 308                  * interrupts, we cannot sample hardware
 309                  * events (user-space has to fall back and
 310                  * sample via a hrtimer based software event):
 311                  */
 312                 if (!x86_pmu.apic)
 313                         return -EOPNOTSUPP;
 314         }
 315
 316         if (attr->type == PERF_TYPE_RAW)
 317                 return x86_pmu_extra_regs(event->attr.config, event);
 318
 319         if (attr->type == PERF_TYPE_HW_CACHE)
 320                 return set_ext_hw_attr(hwc, event);
 321
 322         if (attr->config >= x86_pmu.max_events)
 323                 return -EINVAL;
 324
 325         /*
 326          * The generic map:
 327          */
 328         config = x86_pmu.event_map(attr->config);
 329
 330         if (config == 0)
 331                 return -ENOENT;
 332
 333         if (config == -1LL)
 334                 return -EINVAL;
 335
 336         /*
 337          * Branch tracing:
 338          */
 339         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 340             !attr->freq && hwc->sample_period == 1) {
 341                 /* BTS is not supported by this architecture. */
 342                 if (!x86_pmu.bts_active)
 343                         return -EOPNOTSUPP;
 344
 345                 /* BTS is currently only allowed for user-mode. */
 346                 if (!attr->exclude_kernel)
 347                         return -EOPNOTSUPP;
 348         }
 349
 350         hwc->config |= config;
 351
 352         return 0;
 353 }
 354
 355 /*
 356  * check that branch_sample_type is compatible with
 357  * settings needed for precise_ip > 1 which implies
 358  * using the LBR to capture ALL taken branches at the
 359  * priv levels of the measurement
 360  */
 361 static inline int precise_br_compat(struct perf_event *event)
 362 {
 363         u64 m = event->attr.branch_sample_type;
 364         u64 b = 0;
 365
 366         /* must capture all branches */
 367         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 368                 return 0;
 369
 370         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 371
 372         if (!event->attr.exclude_user)
 373                 b |= PERF_SAMPLE_BRANCH_USER;
 374
 375         if (!event->attr.exclude_kernel)
 376                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 377
 378         /*
 379          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 380          */
 381
 382         return m == b;
 383 }
 384
 385 int x86_pmu_hw_config(struct perf_event *event)
 386 {
 387         if (event->attr.precise_ip) {
 388                 int precise = 0;
 389
 390                 /* Support for constant skid */
 391                 if (x86_pmu.pebs_active) {
 392                         precise++;
 393
 394                         /* Support for IP fixup */
 395                         if (x86_pmu.lbr_nr)
 396                                 precise++;
 397                 }
 398
 399                 if (event->attr.precise_ip > precise)
 400                         return -EOPNOTSUPP;
 401                 /*
 402                  * check that PEBS LBR correction does not conflict with
 403                  * whatever the user is asking with attr->branch_sample_type
 404                  */
 405                 if (event->attr.precise_ip > 1) {
 406                         u64 *br_type = &event->attr.branch_sample_type;
 407
 408                         if (has_branch_stack(event)) {
 409                                 if (!precise_br_compat(event))
 410                                         return -EOPNOTSUPP;
 411
 412                                 /* branch_sample_type is compatible */
 413
 414                         } else {
 415                                 /*
 416                                  * user did not specify  branch_sample_type
 417                                  *
 418                                  * For PEBS fixups, we capture all
 419                                  * the branches at the priv level of the
 420                                  * event.
 421                                  */
 422                                 *br_type = PERF_SAMPLE_BRANCH_ANY;
 423
 424                                 if (!event->attr.exclude_user)
 425                                         *br_type |= PERF_SAMPLE_BRANCH_USER;
 426
 427                                 if (!event->attr.exclude_kernel)
 428                                         *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 429                         }
 430                 }
 431         }
 432
 433         /*
 434          * Generate PMC IRQs:
 435          * (keep 'enabled' bit clear for now)
 436          */
 437         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 438
 439         /*
 440          * Count user and OS events unless requested not to
 441          */
 442         if (!event->attr.exclude_user)
 443                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 444         if (!event->attr.exclude_kernel)
 445                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 446
 447         if (event->attr.type == PERF_TYPE_RAW)
 448                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 449
 450         return x86_setup_perfctr(event);
 451 }
 452
 453 /*
 454  * Setup the hardware configuration for a given attr_type
 455  */
 456 static int __x86_pmu_event_init(struct perf_event *event)
 457 {
 458         int err;
 459
 460         if (!x86_pmu_initialized())
 461                 return -ENODEV;
 462
 463         err = 0;
 464         if (!atomic_inc_not_zero(&active_events)) {
 465                 mutex_lock(&pmc_reserve_mutex);
 466                 if (atomic_read(&active_events) == 0) {
 467                         if (!reserve_pmc_hardware())
 468                                 err = -EBUSY;
 469                         else
 470                                 reserve_ds_buffers();
 471                 }
 472                 if (!err)
 473                         atomic_inc(&active_events);
 474                 mutex_unlock(&pmc_reserve_mutex);
 475         }
 476         if (err)
 477                 return err;
 478
 479         event->destroy = hw_perf_event_destroy;
 480
 481         event->hw.idx = -1;
 482         event->hw.last_cpu = -1;
 483         event->hw.last_tag = ~0ULL;
 484
 485         /* mark unused */
 486         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 487
 488         /* mark not used */
 489         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 490         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 491
 492         return x86_pmu.hw_config(event);
 493 }
 494
 495 void x86_pmu_disable_all(void)
 496 {
 497         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 498         int idx;
 499
 500         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 501                 u64 val;
 502
 503                 if (!test_bit(idx, cpuc->active_mask))
 504                         continue;
 505                 rdmsrl(x86_pmu_config_addr(idx), val);
 506                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 507                         continue;
 508                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 509                 wrmsrl(x86_pmu_config_addr(idx), val);
 510         }
 511 }
 512
 513 static void x86_pmu_disable(struct pmu *pmu)
 514 {
 515         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 516
 517         if (!x86_pmu_initialized())
 518                 return;
 519
 520         if (!cpuc->enabled)
 521                 return;
 522
 523         cpuc->n_added = 0;
 524         cpuc->enabled = 0;
 525         barrier();
 526
 527         x86_pmu.disable_all();
 528 }
 529
 530 void x86_pmu_enable_all(int added)
 531 {
 532         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 533         int idx;
 534
 535         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 536                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 537
 538                 if (!test_bit(idx, cpuc->active_mask))
 539                         continue;
 540
 541                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 542         }
 543 }
 544
 545 static struct pmu pmu;
 546
 547 static inline int is_x86_event(struct perf_event *event)
 548 {
 549         return event->pmu == &pmu;
 550 }
 551
 552 /*
 553  * Event scheduler state:
 554  *
 555  * Assign events iterating over all events and counters, beginning
 556  * with events with least weights first. Keep the current iterator
 557  * state in struct sched_state.
 558  */
 559 struct sched_state {
 560         int     weight;
 561         int     event;          /* event index */
 562         int     counter;        /* counter index */
 563         int     unassigned;     /* number of events to be assigned left */
 564         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 565 };
 566
 567 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 568 #define SCHED_STATES_MAX        2
 569
 570 struct perf_sched {
 571         int                     max_weight;
 572         int                     max_events;
 573         struct event_constraint **constraints;
 574         struct sched_state      state;
 575         int                     saved_states;
 576         struct sched_state      saved[SCHED_STATES_MAX];
 577 };
 578
 579 /*
 580  * Initialize interator that runs through all events and counters.
 581  */
 582 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **c,
 583                             int num, int wmin, int wmax)
 584 {
 585         int idx;
 586
 587         memset(sched, 0, sizeof(*sched));
 588         sched->max_events       = num;
 589         sched->max_weight       = wmax;
 590         sched->constraints      = c;
 591
 592         for (idx = 0; idx < num; idx++) {
 593                 if (c[idx]->weight == wmin)
 594                         break;
 595         }
 596
 597         sched->state.event      = idx;          /* start with min weight */
 598         sched->state.weight     = wmin;
 599         sched->state.unassigned = num;
 600 }
 601
 602 static void perf_sched_save_state(struct perf_sched *sched)
 603 {
 604         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 605                 return;
 606
 607         sched->saved[sched->saved_states] = sched->state;
 608         sched->saved_states++;
 609 }
 610
 611 static bool perf_sched_restore_state(struct perf_sched *sched)
 612 {
 613         if (!sched->saved_states)
 614                 return false;
 615
 616         sched->saved_states--;
 617         sched->state = sched->saved[sched->saved_states];
 618
 619         /* continue with next counter: */
 620         clear_bit(sched->state.counter++, sched->state.used);
 621
 622         return true;
 623 }
 624
 625 /*
 626  * Select a counter for the current event to schedule. Return true on
 627  * success.
 628  */
 629 static bool __perf_sched_find_counter(struct perf_sched *sched)
 630 {
 631         struct event_constraint *c;
 632         int idx;
 633
 634         if (!sched->state.unassigned)
 635                 return false;
 636
 637         if (sched->state.event >= sched->max_events)
 638                 return false;
 639
 640         c = sched->constraints[sched->state.event];
 641
 642         /* Prefer fixed purpose counters */
 643         if (x86_pmu.num_counters_fixed) {
 644                 idx = X86_PMC_IDX_FIXED;
 645                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 646                         if (!__test_and_set_bit(idx, sched->state.used))
 647                                 goto done;
 648                 }
 649         }
 650         /* Grab the first unused counter starting with idx */
 651         idx = sched->state.counter;
 652         for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_FIXED) {
 653                 if (!__test_and_set_bit(idx, sched->state.used))
 654                         goto done;
 655         }
 656
 657         return false;
 658
 659 done:
 660         sched->state.counter = idx;
 661
 662         if (c->overlap)
 663                 perf_sched_save_state(sched);
 664
 665         return true;
 666 }
 667
 668 static bool perf_sched_find_counter(struct perf_sched *sched)
 669 {
 670         while (!__perf_sched_find_counter(sched)) {
 671                 if (!perf_sched_restore_state(sched))
 672                         return false;
 673         }
 674
 675         return true;
 676 }
 677
 678 /*
 679  * Go through all unassigned events and find the next one to schedule.
 680  * Take events with the least weight first. Return true on success.
 681  */
 682 static bool perf_sched_next_event(struct perf_sched *sched)
 683 {
 684         struct event_constraint *c;
 685
 686         if (!sched->state.unassigned || !--sched->state.unassigned)
 687                 return false;
 688
 689         do {
 690                 /* next event */
 691                 sched->state.event++;
 692                 if (sched->state.event >= sched->max_events) {
 693                         /* next weight */
 694                         sched->state.event = 0;
 695                         sched->state.weight++;
 696                         if (sched->state.weight > sched->max_weight)
 697                                 return false;
 698                 }
 699                 c = sched->constraints[sched->state.event];
 700         } while (c->weight != sched->state.weight);
 701
 702         sched->state.counter = 0;       /* start with first counter */
 703
 704         return true;
 705 }
 706
 707 /*
 708  * Assign a counter for each event.
 709  */
 710 static int perf_assign_events(struct event_constraint **constraints, int n,
 711                               int wmin, int wmax, int *assign)
 712 {
 713         struct perf_sched sched;
 714
 715         perf_sched_init(&sched, constraints, n, wmin, wmax);
 716
 717         do {
 718                 if (!perf_sched_find_counter(&sched))
 719                         break;  /* failed */
 720                 if (assign)
 721                         assign[sched.state.event] = sched.state.counter;
 722         } while (perf_sched_next_event(&sched));
 723
 724         return sched.state.unassigned;
 725 }
 726
 727 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 728 {
 729         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 730         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 731         int i, wmin, wmax, num = 0;
 732         struct hw_perf_event *hwc;
 733
 734         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 735
 736         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 737                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 738                 constraints[i] = c;
 739                 wmin = min(wmin, c->weight);
 740                 wmax = max(wmax, c->weight);
 741         }
 742
 743         /*
 744          * fastpath, try to reuse previous register
 745          */
 746         for (i = 0; i < n; i++) {
 747                 hwc = &cpuc->event_list[i]->hw;
 748                 c = constraints[i];
 749
 750                 /* never assigned */
 751                 if (hwc->idx == -1)
 752                         break;
 753
 754                 /* constraint still honored */
 755                 if (!test_bit(hwc->idx, c->idxmsk))
 756                         break;
 757
 758                 /* not already used */
 759                 if (test_bit(hwc->idx, used_mask))
 760                         break;
 761
 762                 __set_bit(hwc->idx, used_mask);
 763                 if (assign)
 764                         assign[i] = hwc->idx;
 765         }
 766
 767         /* slow path */
 768         if (i != n)
 769                 num = perf_assign_events(constraints, n, wmin, wmax, assign);
 770
 771         /*
 772          * scheduling failed or is just a simulation,
 773          * free resources if necessary
 774          */
 775         if (!assign || num) {
 776                 for (i = 0; i < n; i++) {
 777                         if (x86_pmu.put_event_constraints)
 778                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 779                 }
 780         }
 781         return num ? -EINVAL : 0;
 782 }
 783
 784 /*
 785  * dogrp: true if must collect siblings events (group)
 786  * returns total number of events and error code
 787  */
 788 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 789 {
 790         struct perf_event *event;
 791         int n, max_count;
 792
 793         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 794
 795         /* current number of events already accepted */
 796         n = cpuc->n_events;
 797
 798         if (is_x86_event(leader)) {
 799                 if (n >= max_count)
 800                         return -EINVAL;
 801                 cpuc->event_list[n] = leader;
 802                 n++;
 803         }
 804         if (!dogrp)
 805                 return n;
 806
 807         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 808                 if (!is_x86_event(event) ||
 809                     event->state <= PERF_EVENT_STATE_OFF)
 810                         continue;
 811
 812                 if (n >= max_count)
 813                         return -EINVAL;
 814
 815                 cpuc->event_list[n] = event;
 816                 n++;
 817         }
 818         return n;
 819 }
 820
 821 static inline void x86_assign_hw_event(struct perf_event *event,
 822                                 struct cpu_hw_events *cpuc, int i)
 823 {
 824         struct hw_perf_event *hwc = &event->hw;
 825
 826         hwc->idx = cpuc->assign[i];
 827         hwc->last_cpu = smp_processor_id();
 828         hwc->last_tag = ++cpuc->tags[i];
 829
 830         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 831                 hwc->config_base = 0;
 832                 hwc->event_base = 0;
 833         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 834                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 835                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED);
 836         } else {
 837                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 838                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 839         }
 840 }
 841
 842 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 843                                         struct cpu_hw_events *cpuc,
 844                                         int i)
 845 {
 846         return hwc->idx == cpuc->assign[i] &&
 847                 hwc->last_cpu == smp_processor_id() &&
 848                 hwc->last_tag == cpuc->tags[i];
 849 }
 850
 851 static void x86_pmu_start(struct perf_event *event, int flags);
 852
 853 static void x86_pmu_enable(struct pmu *pmu)
 854 {
 855         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 856         struct perf_event *event;
 857         struct hw_perf_event *hwc;
 858         int i, added = cpuc->n_added;
 859
 860         if (!x86_pmu_initialized())
 861                 return;
 862
 863         if (cpuc->enabled)
 864                 return;
 865
 866         if (cpuc->n_added) {
 867                 int n_running = cpuc->n_events - cpuc->n_added;
 868                 /*
 869                  * apply assignment obtained either from
 870                  * hw_perf_group_sched_in() or x86_pmu_enable()
 871                  *
 872                  * step1: save events moving to new counters
 873                  * step2: reprogram moved events into new counters
 874                  */
 875                 for (i = 0; i < n_running; i++) {
 876                         event = cpuc->event_list[i];
 877                         hwc = &event->hw;
 878
 879                         /*
 880                          * we can avoid reprogramming counter if:
 881                          * - assigned same counter as last time
 882                          * - running on same CPU as last time
 883                          * - no other event has used the counter since
 884                          */
 885                         if (hwc->idx == -1 ||
 886                             match_prev_assignment(hwc, cpuc, i))
 887                                 continue;
 888
 889                         /*
 890                          * Ensure we don't accidentally enable a stopped
 891                          * counter simply because we rescheduled.
 892                          */
 893                         if (hwc->state & PERF_HES_STOPPED)
 894                                 hwc->state |= PERF_HES_ARCH;
 895
 896                         x86_pmu_stop(event, PERF_EF_UPDATE);
 897                 }
 898
 899                 for (i = 0; i < cpuc->n_events; i++) {
 900                         event = cpuc->event_list[i];
 901                         hwc = &event->hw;
 902
 903                         if (!match_prev_assignment(hwc, cpuc, i))
 904                                 x86_assign_hw_event(event, cpuc, i);
 905                         else if (i < n_running)
 906                                 continue;
 907
 908                         if (hwc->state & PERF_HES_ARCH)
 909                                 continue;
 910
 911                         x86_pmu_start(event, PERF_EF_RELOAD);
 912                 }
 913                 cpuc->n_added = 0;
 914                 perf_events_lapic_init();
 915         }
 916
 917         cpuc->enabled = 1;
 918         barrier();
 919
 920         x86_pmu.enable_all(added);
 921 }
 922
 923 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 924
 925 /*
 926  * Set the next IRQ period, based on the hwc->period_left value.
 927  * To be called with the event disabled in hw:
 928  */
 929 int x86_perf_event_set_period(struct perf_event *event)
 930 {
 931         struct hw_perf_event *hwc = &event->hw;
 932         s64 left = local64_read(&hwc->period_left);
 933         s64 period = hwc->sample_period;
 934         int ret = 0, idx = hwc->idx;
 935
 936         if (idx == X86_PMC_IDX_FIXED_BTS)
 937                 return 0;
 938
 939         /*
 940          * If we are way outside a reasonable range then just skip forward:
 941          */
 942         if (unlikely(left <= -period)) {
 943                 left = period;
 944                 local64_set(&hwc->period_left, left);
 945                 hwc->last_period = period;
 946                 ret = 1;
 947         }
 948
 949         if (unlikely(left <= 0)) {
 950                 left += period;
 951                 local64_set(&hwc->period_left, left);
 952                 hwc->last_period = period;
 953                 ret = 1;
 954         }
 955         /*
 956          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 957          */
 958         if (unlikely(left < 2))
 959                 left = 2;
 960
 961         if (left > x86_pmu.max_period)
 962                 left = x86_pmu.max_period;
 963
 964         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 965
 966         /*
 967          * The hw event starts counting from this event offset,
 968          * mark it to be able to extra future deltas:
 969          */
 970         local64_set(&hwc->prev_count, (u64)-left);
 971
 972         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
 973
 974         /*
 975          * Due to erratum on certan cpu we need
 976          * a second write to be sure the register
 977          * is updated properly
 978          */
 979         if (x86_pmu.perfctr_second_write) {
 980                 wrmsrl(hwc->event_base,
 981                         (u64)(-left) & x86_pmu.cntval_mask);
 982         }
 983
 984         perf_event_update_userpage(event);
 985
 986         return ret;
 987 }
 988
 989 void x86_pmu_enable_event(struct perf_event *event)
 990 {
 991         if (__this_cpu_read(cpu_hw_events.enabled))
 992                 __x86_pmu_enable_event(&event->hw,
 993                                        ARCH_PERFMON_EVENTSEL_ENABLE);
 994 }
 995
 996 /*
 997  * Add a single event to the PMU.
 998  *
 999  * The event is added to the group of enabled events
1000  * but only if it can be scehduled with existing events.
1001  */
1002 static int x86_pmu_add(struct perf_event *event, int flags)
1003 {
1004         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1005         struct hw_perf_event *hwc;
1006         int assign[X86_PMC_IDX_MAX];
1007         int n, n0, ret;
1008
1009         hwc = &event->hw;
1010
1011         perf_pmu_disable(event->pmu);
1012         n0 = cpuc->n_events;
1013         ret = n = collect_events(cpuc, event, false);
1014         if (ret < 0)
1015                 goto out;
1016
1017         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1018         if (!(flags & PERF_EF_START))
1019                 hwc->state |= PERF_HES_ARCH;
1020
1021         /*
1022          * If group events scheduling transaction was started,
1023          * skip the schedulability test here, it will be performed
1024          * at commit time (->commit_txn) as a whole
1025          */
1026         if (cpuc->group_flag & PERF_EVENT_TXN)
1027                 goto done_collect;
1028
1029         ret = x86_pmu.schedule_events(cpuc, n, assign);
1030         if (ret)
1031                 goto out;
1032         /*
1033          * copy new assignment, now we know it is possible
1034          * will be used by hw_perf_enable()
1035          */
1036         memcpy(cpuc->assign, assign, n*sizeof(int));
1037
1038 done_collect:
1039         cpuc->n_events = n;
1040         cpuc->n_added += n - n0;
1041         cpuc->n_txn += n - n0;
1042
1043         ret = 0;
1044 out:
1045         perf_pmu_enable(event->pmu);
1046         return ret;
1047 }
1048
1049 static void x86_pmu_start(struct perf_event *event, int flags)
1050 {
1051         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1052         int idx = event->hw.idx;
1053
1054         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1055                 return;
1056
1057         if (WARN_ON_ONCE(idx == -1))
1058                 return;
1059
1060         if (flags & PERF_EF_RELOAD) {
1061                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1062                 x86_perf_event_set_period(event);
1063         }
1064
1065         event->hw.state = 0;
1066
1067         cpuc->events[idx] = event;
1068         __set_bit(idx, cpuc->active_mask);
1069         __set_bit(idx, cpuc->running);
1070         x86_pmu.enable(event);
1071         perf_event_update_userpage(event);
1072 }
1073
1074 void perf_event_print_debug(void)
1075 {
1076         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1077         u64 pebs;
1078         struct cpu_hw_events *cpuc;
1079         unsigned long flags;
1080         int cpu, idx;
1081
1082         if (!x86_pmu.num_counters)
1083                 return;
1084
1085         local_irq_save(flags);
1086
1087         cpu = smp_processor_id();
1088         cpuc = &per_cpu(cpu_hw_events, cpu);
1089
1090         if (x86_pmu.version >= 2) {
1091                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1092                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1093                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1094                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1095                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1096
1097                 pr_info("\n");
1098                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1099                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1100                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1101                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1102                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1103         }
1104         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1105
1106         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1107                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1108                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1109
1110                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1111
1112                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1113                         cpu, idx, pmc_ctrl);
1114                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1115                         cpu, idx, pmc_count);
1116                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1117                         cpu, idx, prev_left);
1118         }
1119         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1120                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1121
1122                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1123                         cpu, idx, pmc_count);
1124         }
1125         local_irq_restore(flags);
1126 }
1127
1128 void x86_pmu_stop(struct perf_event *event, int flags)
1129 {
1130         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1131         struct hw_perf_event *hwc = &event->hw;
1132
1133         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1134                 x86_pmu.disable(event);
1135                 cpuc->events[hwc->idx] = NULL;
1136                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1137                 hwc->state |= PERF_HES_STOPPED;
1138         }
1139
1140         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1141                 /*
1142                  * Drain the remaining delta count out of a event
1143                  * that we are disabling:
1144                  */
1145                 x86_perf_event_update(event);
1146                 hwc->state |= PERF_HES_UPTODATE;
1147         }
1148 }
1149
1150 static void x86_pmu_del(struct perf_event *event, int flags)
1151 {
1152         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1153         int i;
1154
1155         /*
1156          * If we're called during a txn, we don't need to do anything.
1157          * The events never got scheduled and ->cancel_txn will truncate
1158          * the event_list.
1159          */
1160         if (cpuc->group_flag & PERF_EVENT_TXN)
1161                 return;
1162
1163         x86_pmu_stop(event, PERF_EF_UPDATE);
1164
1165         for (i = 0; i < cpuc->n_events; i++) {
1166                 if (event == cpuc->event_list[i]) {
1167
1168                         if (x86_pmu.put_event_constraints)
1169                                 x86_pmu.put_event_constraints(cpuc, event);
1170
1171                         while (++i < cpuc->n_events)
1172                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1173
1174                         --cpuc->n_events;
1175                         break;
1176                 }
1177         }
1178         perf_event_update_userpage(event);
1179 }
1180
1181 int x86_pmu_handle_irq(struct pt_regs *regs)
1182 {
1183         struct perf_sample_data data;
1184         struct cpu_hw_events *cpuc;
1185         struct perf_event *event;
1186         int idx, handled = 0;
1187         u64 val;
1188
1189         perf_sample_data_init(&data, 0);
1190
1191         cpuc = &__get_cpu_var(cpu_hw_events);
1192
1193         /*
1194          * Some chipsets need to unmask the LVTPC in a particular spot
1195          * inside the nmi handler.  As a result, the unmasking was pushed
1196          * into all the nmi handlers.
1197          *
1198          * This generic handler doesn't seem to have any issues where the
1199          * unmasking occurs so it was left at the top.
1200          */
1201         apic_write(APIC_LVTPC, APIC_DM_NMI);
1202
1203         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1204                 if (!test_bit(idx, cpuc->active_mask)) {
1205                         /*
1206                          * Though we deactivated the counter some cpus
1207                          * might still deliver spurious interrupts still
1208                          * in flight. Catch them:
1209                          */
1210                         if (__test_and_clear_bit(idx, cpuc->running))
1211                                 handled++;
1212                         continue;
1213                 }
1214
1215                 event = cpuc->events[idx];
1216
1217                 val = x86_perf_event_update(event);
1218                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1219                         continue;
1220
1221                 /*
1222                  * event overflow
1223                  */
1224                 handled++;
1225                 data.period     = event->hw.last_period;
1226
1227                 if (!x86_perf_event_set_period(event))
1228                         continue;
1229
1230                 if (perf_event_overflow(event, &data, regs))
1231                         x86_pmu_stop(event, 0);
1232         }
1233
1234         if (handled)
1235                 inc_irq_stat(apic_perf_irqs);
1236
1237         return handled;
1238 }
1239
1240 void perf_events_lapic_init(void)
1241 {
1242         if (!x86_pmu.apic || !x86_pmu_initialized())
1243                 return;
1244
1245         /*
1246          * Always use NMI for PMU
1247          */
1248         apic_write(APIC_LVTPC, APIC_DM_NMI);
1249 }
1250
1251 static int __kprobes
1252 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1253 {
1254         if (!atomic_read(&active_events))
1255                 return NMI_DONE;
1256
1257         return x86_pmu.handle_irq(regs);
1258 }
1259
1260 struct event_constraint emptyconstraint;
1261 struct event_constraint unconstrained;
1262
1263 static int __cpuinit
1264 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1265 {
1266         unsigned int cpu = (long)hcpu;
1267         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1268         int ret = NOTIFY_OK;
1269
1270         switch (action & ~CPU_TASKS_FROZEN) {
1271         case CPU_UP_PREPARE:
1272                 cpuc->kfree_on_online = NULL;
1273                 if (x86_pmu.cpu_prepare)
1274                         ret = x86_pmu.cpu_prepare(cpu);
1275                 break;
1276
1277         case CPU_STARTING:
1278                 if (x86_pmu.attr_rdpmc)
1279                         set_in_cr4(X86_CR4_PCE);
1280                 if (x86_pmu.cpu_starting)
1281                         x86_pmu.cpu_starting(cpu);
1282                 break;
1283
1284         case CPU_ONLINE:
1285                 kfree(cpuc->kfree_on_online);
1286                 break;
1287
1288         case CPU_DYING:
1289                 if (x86_pmu.cpu_dying)
1290                         x86_pmu.cpu_dying(cpu);
1291                 break;
1292
1293         case CPU_UP_CANCELED:
1294         case CPU_DEAD:
1295                 if (x86_pmu.cpu_dead)
1296                         x86_pmu.cpu_dead(cpu);
1297                 break;
1298
1299         default:
1300                 break;
1301         }
1302
1303         return ret;
1304 }
1305
1306 static void __init pmu_check_apic(void)
1307 {
1308         if (cpu_has_apic)
1309                 return;
1310
1311         x86_pmu.apic = 0;
1312         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1313         pr_info("no hardware sampling interrupt available.\n");
1314 }
1315
1316 static struct attribute_group x86_pmu_format_group = {
1317         .name = "format",
1318         .attrs = NULL,
1319 };
1320
1321 static int __init init_hw_perf_events(void)
1322 {
1323         struct x86_pmu_quirk *quirk;
1324         struct event_constraint *c;
1325         int err;
1326
1327         pr_info("Performance Events: ");
1328
1329         switch (boot_cpu_data.x86_vendor) {
1330         case X86_VENDOR_INTEL:
1331                 err = intel_pmu_init();
1332                 break;
1333         case X86_VENDOR_AMD:
1334                 err = amd_pmu_init();
1335                 break;
1336         default:
1337                 return 0;
1338         }
1339         if (err != 0) {
1340                 pr_cont("no PMU driver, software events only.\n");
1341                 return 0;
1342         }
1343
1344         pmu_check_apic();
1345
1346         /* sanity check that the hardware exists or is emulated */
1347         if (!check_hw_exists())
1348                 return 0;
1349
1350         pr_cont("%s PMU driver.\n", x86_pmu.name);
1351
1352         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1353                 quirk->func();
1354
1355         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1356                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1357                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1358                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1359         }
1360         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1361
1362         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1363                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1364                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1365                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1366         }
1367
1368         x86_pmu.intel_ctrl |=
1369                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1370
1371         perf_events_lapic_init();
1372         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1373
1374         unconstrained = (struct event_constraint)
1375                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1376                                    0, x86_pmu.num_counters, 0);
1377
1378         if (x86_pmu.event_constraints) {
1379                 /*
1380                  * event on fixed counter2 (REF_CYCLES) only works on this
1381                  * counter, so do not extend mask to generic counters
1382                  */
1383                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1384                         if (c->cmask != X86_RAW_EVENT_MASK
1385                             || c->idxmsk64 == X86_PMC_MSK_FIXED_REF_CYCLES) {
1386                                 continue;
1387                         }
1388
1389                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1390                         c->weight += x86_pmu.num_counters;
1391                 }
1392         }
1393
1394         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1395         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1396
1397         pr_info("... version:                %d\n",     x86_pmu.version);
1398         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1399         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1400         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1401         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1402         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1403         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1404
1405         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1406         perf_cpu_notifier(x86_pmu_notifier);
1407
1408         return 0;
1409 }
1410 early_initcall(init_hw_perf_events);
1411
1412 static inline void x86_pmu_read(struct perf_event *event)
1413 {
1414         x86_perf_event_update(event);
1415 }
1416
1417 /*
1418  * Start group events scheduling transaction
1419  * Set the flag to make pmu::enable() not perform the
1420  * schedulability test, it will be performed at commit time
1421  */
1422 static void x86_pmu_start_txn(struct pmu *pmu)
1423 {
1424         perf_pmu_disable(pmu);
1425         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1426         __this_cpu_write(cpu_hw_events.n_txn, 0);
1427 }
1428
1429 /*
1430  * Stop group events scheduling transaction
1431  * Clear the flag and pmu::enable() will perform the
1432  * schedulability test.
1433  */
1434 static void x86_pmu_cancel_txn(struct pmu *pmu)
1435 {
1436         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1437         /*
1438          * Truncate the collected events.
1439          */
1440         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1441         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1442         perf_pmu_enable(pmu);
1443 }
1444
1445 /*
1446  * Commit group events scheduling transaction
1447  * Perform the group schedulability test as a whole
1448  * Return 0 if success
1449  */
1450 static int x86_pmu_commit_txn(struct pmu *pmu)
1451 {
1452         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1453         int assign[X86_PMC_IDX_MAX];
1454         int n, ret;
1455
1456         n = cpuc->n_events;
1457
1458         if (!x86_pmu_initialized())
1459                 return -EAGAIN;
1460
1461         ret = x86_pmu.schedule_events(cpuc, n, assign);
1462         if (ret)
1463                 return ret;
1464
1465         /*
1466          * copy new assignment, now we know it is possible
1467          * will be used by hw_perf_enable()
1468          */
1469         memcpy(cpuc->assign, assign, n*sizeof(int));
1470
1471         cpuc->group_flag &= ~PERF_EVENT_TXN;
1472         perf_pmu_enable(pmu);
1473         return 0;
1474 }
1475 /*
1476  * a fake_cpuc is used to validate event groups. Due to
1477  * the extra reg logic, we need to also allocate a fake
1478  * per_core and per_cpu structure. Otherwise, group events
1479  * using extra reg may conflict without the kernel being
1480  * able to catch this when the last event gets added to
1481  * the group.
1482  */
1483 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1484 {
1485         kfree(cpuc->shared_regs);
1486         kfree(cpuc);
1487 }
1488
1489 static struct cpu_hw_events *allocate_fake_cpuc(void)
1490 {
1491         struct cpu_hw_events *cpuc;
1492         int cpu = raw_smp_processor_id();
1493
1494         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1495         if (!cpuc)
1496                 return ERR_PTR(-ENOMEM);
1497
1498         /* only needed, if we have extra_regs */
1499         if (x86_pmu.extra_regs) {
1500                 cpuc->shared_regs = allocate_shared_regs(cpu);
1501                 if (!cpuc->shared_regs)
1502                         goto error;
1503         }
1504         return cpuc;
1505 error:
1506         free_fake_cpuc(cpuc);
1507         return ERR_PTR(-ENOMEM);
1508 }
1509
1510 /*
1511  * validate that we can schedule this event
1512  */
1513 static int validate_event(struct perf_event *event)
1514 {
1515         struct cpu_hw_events *fake_cpuc;
1516         struct event_constraint *c;
1517         int ret = 0;
1518
1519         fake_cpuc = allocate_fake_cpuc();
1520         if (IS_ERR(fake_cpuc))
1521                 return PTR_ERR(fake_cpuc);
1522
1523         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1524
1525         if (!c || !c->weight)
1526                 ret = -EINVAL;
1527
1528         if (x86_pmu.put_event_constraints)
1529                 x86_pmu.put_event_constraints(fake_cpuc, event);
1530
1531         free_fake_cpuc(fake_cpuc);
1532
1533         return ret;
1534 }
1535
1536 /*
1537  * validate a single event group
1538  *
1539  * validation include:
1540  *      - check events are compatible which each other
1541  *      - events do not compete for the same counter
1542  *      - number of events <= number of counters
1543  *
1544  * validation ensures the group can be loaded onto the
1545  * PMU if it was the only group available.
1546  */
1547 static int validate_group(struct perf_event *event)
1548 {
1549         struct perf_event *leader = event->group_leader;
1550         struct cpu_hw_events *fake_cpuc;
1551         int ret = -EINVAL, n;
1552
1553         fake_cpuc = allocate_fake_cpuc();
1554         if (IS_ERR(fake_cpuc))
1555                 return PTR_ERR(fake_cpuc);
1556         /*
1557          * the event is not yet connected with its
1558          * siblings therefore we must first collect
1559          * existing siblings, then add the new event
1560          * before we can simulate the scheduling
1561          */
1562         n = collect_events(fake_cpuc, leader, true);
1563         if (n < 0)
1564                 goto out;
1565
1566         fake_cpuc->n_events = n;
1567         n = collect_events(fake_cpuc, event, false);
1568         if (n < 0)
1569                 goto out;
1570
1571         fake_cpuc->n_events = n;
1572
1573         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1574
1575 out:
1576         free_fake_cpuc(fake_cpuc);
1577         return ret;
1578 }
1579
1580 static int x86_pmu_event_init(struct perf_event *event)
1581 {
1582         struct pmu *tmp;
1583         int err;
1584
1585         switch (event->attr.type) {
1586         case PERF_TYPE_RAW:
1587         case PERF_TYPE_HARDWARE:
1588         case PERF_TYPE_HW_CACHE:
1589                 break;
1590
1591         default:
1592                 return -ENOENT;
1593         }
1594
1595         err = __x86_pmu_event_init(event);
1596         if (!err) {
1597                 /*
1598                  * we temporarily connect event to its pmu
1599                  * such that validate_group() can classify
1600                  * it as an x86 event using is_x86_event()
1601                  */
1602                 tmp = event->pmu;
1603                 event->pmu = &pmu;
1604
1605                 if (event->group_leader != event)
1606                         err = validate_group(event);
1607                 else
1608                         err = validate_event(event);
1609
1610                 event->pmu = tmp;
1611         }
1612         if (err) {
1613                 if (event->destroy)
1614                         event->destroy(event);
1615         }
1616
1617         return err;
1618 }
1619
1620 static int x86_pmu_event_idx(struct perf_event *event)
1621 {
1622         int idx = event->hw.idx;
1623
1624         if (!x86_pmu.attr_rdpmc)
1625                 return 0;
1626
1627         if (x86_pmu.num_counters_fixed && idx >= X86_PMC_IDX_FIXED) {
1628                 idx -= X86_PMC_IDX_FIXED;
1629                 idx |= 1 << 30;
1630         }
1631
1632         return idx + 1;
1633 }
1634
1635 static ssize_t get_attr_rdpmc(struct device *cdev,
1636                               struct device_attribute *attr,
1637                               char *buf)
1638 {
1639         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1640 }
1641
1642 static void change_rdpmc(void *info)
1643 {
1644         bool enable = !!(unsigned long)info;
1645
1646         if (enable)
1647                 set_in_cr4(X86_CR4_PCE);
1648         else
1649                 clear_in_cr4(X86_CR4_PCE);
1650 }
1651
1652 static ssize_t set_attr_rdpmc(struct device *cdev,
1653                               struct device_attribute *attr,
1654                               const char *buf, size_t count)
1655 {
1656         unsigned long val = simple_strtoul(buf, NULL, 0);
1657
1658         if (!!val != !!x86_pmu.attr_rdpmc) {
1659                 x86_pmu.attr_rdpmc = !!val;
1660                 smp_call_function(change_rdpmc, (void *)val, 1);
1661         }
1662
1663         return count;
1664 }
1665
1666 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
1667
1668 static struct attribute *x86_pmu_attrs[] = {
1669         &dev_attr_rdpmc.attr,
1670         NULL,
1671 };
1672
1673 static struct attribute_group x86_pmu_attr_group = {
1674         .attrs = x86_pmu_attrs,
1675 };
1676
1677 static const struct attribute_group *x86_pmu_attr_groups[] = {
1678         &x86_pmu_attr_group,
1679         &x86_pmu_format_group,
1680         NULL,
1681 };
1682
1683 static void x86_pmu_flush_branch_stack(void)
1684 {
1685         if (x86_pmu.flush_branch_stack)
1686                 x86_pmu.flush_branch_stack();
1687 }
1688
1689 static struct pmu pmu = {
1690         .pmu_enable             = x86_pmu_enable,
1691         .pmu_disable            = x86_pmu_disable,
1692
1693         .attr_groups    = x86_pmu_attr_groups,
1694
1695         .event_init     = x86_pmu_event_init,
1696
1697         .add                    = x86_pmu_add,
1698         .del                    = x86_pmu_del,
1699         .start                  = x86_pmu_start,
1700         .stop                   = x86_pmu_stop,
1701         .read                   = x86_pmu_read,
1702
1703         .start_txn      = x86_pmu_start_txn,
1704         .cancel_txn     = x86_pmu_cancel_txn,
1705         .commit_txn     = x86_pmu_commit_txn,
1706
1707         .event_idx      = x86_pmu_event_idx,
1708         .flush_branch_stack     = x86_pmu_flush_branch_stack,
1709 };
1710
1711 void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
1712 {
1713         userpg->cap_usr_time = 0;
1714         userpg->cap_usr_rdpmc = x86_pmu.attr_rdpmc;
1715         userpg->pmc_width = x86_pmu.cntval_bits;
1716
1717         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1718                 return;
1719
1720         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1721                 return;
1722
1723         userpg->cap_usr_time = 1;
1724         userpg->time_mult = this_cpu_read(cyc2ns);
1725         userpg->time_shift = CYC2NS_SCALE_FACTOR;
1726         userpg->time_offset = this_cpu_read(cyc2ns_offset) - now;
1727 }
1728
1729 /*
1730  * callchain support
1731  */
1732
1733 static void
1734 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1735 {
1736         /* Ignore warnings */
1737 }
1738
1739 static void backtrace_warning(void *data, char *msg)
1740 {
1741         /* Ignore warnings */
1742 }
1743
1744 static int backtrace_stack(void *data, char *name)
1745 {
1746         return 0;
1747 }
1748
1749 static void backtrace_address(void *data, unsigned long addr, int reliable)
1750 {
1751         struct perf_callchain_entry *entry = data;
1752
1753         perf_callchain_store(entry, addr);
1754 }
1755
1756 static const struct stacktrace_ops backtrace_ops = {
1757         .warning                = backtrace_warning,
1758         .warning_symbol         = backtrace_warning_symbol,
1759         .stack                  = backtrace_stack,
1760         .address                = backtrace_address,
1761         .walk_stack             = print_context_stack_bp,
1762 };
1763
1764 void
1765 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1766 {
1767         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1768                 /* TODO: We don't support guest os callchain now */
1769                 return;
1770         }
1771
1772         perf_callchain_store(entry, regs->ip);
1773
1774         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1775 }
1776
1777 #ifdef CONFIG_COMPAT
1778
1779 #include <asm/compat.h>
1780
1781 static inline int
1782 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1783 {
1784         /* 32-bit process in 64-bit kernel. */
1785         struct stack_frame_ia32 frame;
1786         const void __user *fp;
1787
1788         if (!test_thread_flag(TIF_IA32))
1789                 return 0;
1790
1791         fp = compat_ptr(regs->bp);
1792         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1793                 unsigned long bytes;
1794                 frame.next_frame     = 0;
1795                 frame.return_address = 0;
1796
1797                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1798                 if (bytes != sizeof(frame))
1799                         break;
1800
1801                 if (fp < compat_ptr(regs->sp))
1802                         break;
1803
1804                 perf_callchain_store(entry, frame.return_address);
1805                 fp = compat_ptr(frame.next_frame);
1806         }
1807         return 1;
1808 }
1809 #else
1810 static inline int
1811 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1812 {
1813     return 0;
1814 }
1815 #endif
1816
1817 void
1818 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1819 {
1820         struct stack_frame frame;
1821         const void __user *fp;
1822
1823         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1824                 /* TODO: We don't support guest os callchain now */
1825                 return;
1826         }
1827
1828         fp = (void __user *)regs->bp;
1829
1830         perf_callchain_store(entry, regs->ip);
1831
1832         if (!current->mm)
1833                 return;
1834
1835         if (perf_callchain_user32(regs, entry))
1836                 return;
1837
1838         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1839                 unsigned long bytes;
1840                 frame.next_frame             = NULL;
1841                 frame.return_address = 0;
1842
1843                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1844                 if (bytes != sizeof(frame))
1845                         break;
1846
1847                 if ((unsigned long)fp < regs->sp)
1848                         break;
1849
1850                 perf_callchain_store(entry, frame.return_address);
1851                 fp = frame.next_frame;
1852         }
1853 }
1854
1855 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1856 {
1857         unsigned long ip;
1858
1859         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1860                 ip = perf_guest_cbs->get_guest_ip();
1861         else
1862                 ip = instruction_pointer(regs);
1863
1864         return ip;
1865 }
1866
1867 unsigned long perf_misc_flags(struct pt_regs *regs)
1868 {
1869         int misc = 0;
1870
1871         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1872                 if (perf_guest_cbs->is_user_mode())
1873                         misc |= PERF_RECORD_MISC_GUEST_USER;
1874                 else
1875                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1876         } else {
1877                 if (user_mode(regs))
1878                         misc |= PERF_RECORD_MISC_USER;
1879                 else
1880                         misc |= PERF_RECORD_MISC_KERNEL;
1881         }
1882
1883         if (regs->flags & PERF_EFLAGS_EXACT)
1884                 misc |= PERF_RECORD_MISC_EXACT_IP;
1885
1886         return misc;
1887 }
1888
1889 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
1890 {
1891         cap->version            = x86_pmu.version;
1892         cap->num_counters_gp    = x86_pmu.num_counters;
1893         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
1894         cap->bit_width_gp       = x86_pmu.cntval_bits;
1895         cap->bit_width_fixed    = x86_pmu.cntval_bits;
1896         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
1897         cap->events_mask_len    = x86_pmu.events_mask_len;
1898 }
1899 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);