drivers/gpu/drm/i915/i915_gem_execbuffer.c

   1 /*
   2  * Copyright © 2008,2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Chris Wilson <chris@chris-wilson.co.uk>
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35 #include <linux/dma_remapping.h>
  36
  37 struct change_domains {
  38         uint32_t invalidate_domains;
  39         uint32_t flush_domains;
  40         uint32_t flush_rings;
  41         uint32_t flips;
  42 };
  43
  44 /*
  45  * Set the next domain for the specified object. This
  46  * may not actually perform the necessary flushing/invaliding though,
  47  * as that may want to be batched with other set_domain operations
  48  *
  49  * This is (we hope) the only really tricky part of gem. The goal
  50  * is fairly simple -- track which caches hold bits of the object
  51  * and make sure they remain coherent. A few concrete examples may
  52  * help to explain how it works. For shorthand, we use the notation
  53  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
  54  * a pair of read and write domain masks.
  55  *
  56  * Case 1: the batch buffer
  57  *
  58  *      1. Allocated
  59  *      2. Written by CPU
  60  *      3. Mapped to GTT
  61  *      4. Read by GPU
  62  *      5. Unmapped from GTT
  63  *      6. Freed
  64  *
  65  *      Let's take these a step at a time
  66  *
  67  *      1. Allocated
  68  *              Pages allocated from the kernel may still have
  69  *              cache contents, so we set them to (CPU, CPU) always.
  70  *      2. Written by CPU (using pwrite)
  71  *              The pwrite function calls set_domain (CPU, CPU) and
  72  *              this function does nothing (as nothing changes)
  73  *      3. Mapped by GTT
  74  *              This function asserts that the object is not
  75  *              currently in any GPU-based read or write domains
  76  *      4. Read by GPU
  77  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
  78  *              As write_domain is zero, this function adds in the
  79  *              current read domains (CPU+COMMAND, 0).
  80  *              flush_domains is set to CPU.
  81  *              invalidate_domains is set to COMMAND
  82  *              clflush is run to get data out of the CPU caches
  83  *              then i915_dev_set_domain calls i915_gem_flush to
  84  *              emit an MI_FLUSH and drm_agp_chipset_flush
  85  *      5. Unmapped from GTT
  86  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
  87  *              flush_domains and invalidate_domains end up both zero
  88  *              so no flushing/invalidating happens
  89  *      6. Freed
  90  *              yay, done
  91  *
  92  * Case 2: The shared render buffer
  93  *
  94  *      1. Allocated
  95  *      2. Mapped to GTT
  96  *      3. Read/written by GPU
  97  *      4. set_domain to (CPU,CPU)
  98  *      5. Read/written by CPU
  99  *      6. Read/written by GPU
 100  *
 101  *      1. Allocated
 102  *              Same as last example, (CPU, CPU)
 103  *      2. Mapped to GTT
 104  *              Nothing changes (assertions find that it is not in the GPU)
 105  *      3. Read/written by GPU
 106  *              execbuffer calls set_domain (RENDER, RENDER)
 107  *              flush_domains gets CPU
 108  *              invalidate_domains gets GPU
 109  *              clflush (obj)
 110  *              MI_FLUSH and drm_agp_chipset_flush
 111  *      4. set_domain (CPU, CPU)
 112  *              flush_domains gets GPU
 113  *              invalidate_domains gets CPU
 114  *              wait_rendering (obj) to make sure all drawing is complete.
 115  *              This will include an MI_FLUSH to get the data from GPU
 116  *              to memory
 117  *              clflush (obj) to invalidate the CPU cache
 118  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
 119  *      5. Read/written by CPU
 120  *              cache lines are loaded and dirtied
 121  *      6. Read written by GPU
 122  *              Same as last GPU access
 123  *
 124  * Case 3: The constant buffer
 125  *
 126  *      1. Allocated
 127  *      2. Written by CPU
 128  *      3. Read by GPU
 129  *      4. Updated (written) by CPU again
 130  *      5. Read by GPU
 131  *
 132  *      1. Allocated
 133  *              (CPU, CPU)
 134  *      2. Written by CPU
 135  *              (CPU, CPU)
 136  *      3. Read by GPU
 137  *              (CPU+RENDER, 0)
 138  *              flush_domains = CPU
 139  *              invalidate_domains = RENDER
 140  *              clflush (obj)
 141  *              MI_FLUSH
 142  *              drm_agp_chipset_flush
 143  *      4. Updated (written) by CPU again
 144  *              (CPU, CPU)
 145  *              flush_domains = 0 (no previous write domain)
 146  *              invalidate_domains = 0 (no new read domains)
 147  *      5. Read by GPU
 148  *              (CPU+RENDER, 0)
 149  *              flush_domains = CPU
 150  *              invalidate_domains = RENDER
 151  *              clflush (obj)
 152  *              MI_FLUSH
 153  *              drm_agp_chipset_flush
 154  */
 155 static void
 156 i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj,
 157                                   struct intel_ring_buffer *ring,
 158                                   struct change_domains *cd)
 159 {
 160         uint32_t invalidate_domains = 0, flush_domains = 0;
 161
 162         /*
 163          * If the object isn't moving to a new write domain,
 164          * let the object stay in multiple read domains
 165          */
 166         if (obj->base.pending_write_domain == 0)
 167                 obj->base.pending_read_domains |= obj->base.read_domains;
 168
 169         /*
 170          * Flush the current write domain if
 171          * the new read domains don't match. Invalidate
 172          * any read domains which differ from the old
 173          * write domain
 174          */
 175         if (obj->base.write_domain &&
 176             (((obj->base.write_domain != obj->base.pending_read_domains ||
 177                obj->ring != ring)) ||
 178              (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) {
 179                 flush_domains |= obj->base.write_domain;
 180                 invalidate_domains |=
 181                         obj->base.pending_read_domains & ~obj->base.write_domain;
 182         }
 183         /*
 184          * Invalidate any read caches which may have
 185          * stale data. That is, any new read domains.
 186          */
 187         invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains;
 188         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
 189                 i915_gem_clflush_object(obj);
 190
 191         if (obj->base.pending_write_domain)
 192                 cd->flips |= atomic_read(&obj->pending_flip);
 193
 194         /* The actual obj->write_domain will be updated with
 195          * pending_write_domain after we emit the accumulated flush for all
 196          * of our domain changes in execbuffers (which clears objects'
 197          * write_domains).  So if we have a current write domain that we
 198          * aren't changing, set pending_write_domain to that.
 199          */
 200         if (flush_domains == 0 && obj->base.pending_write_domain == 0)
 201                 obj->base.pending_write_domain = obj->base.write_domain;
 202
 203         cd->invalidate_domains |= invalidate_domains;
 204         cd->flush_domains |= flush_domains;
 205         if (flush_domains & I915_GEM_GPU_DOMAINS)
 206                 cd->flush_rings |= intel_ring_flag(obj->ring);
 207         if (invalidate_domains & I915_GEM_GPU_DOMAINS)
 208                 cd->flush_rings |= intel_ring_flag(ring);
 209 }
 210
 211 struct eb_objects {
 212         int and;
 213         struct hlist_head buckets[0];
 214 };
 215
 216 static struct eb_objects *
 217 eb_create(int size)
 218 {
 219         struct eb_objects *eb;
 220         int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
 221         while (count > size)
 222                 count >>= 1;
 223         eb = kzalloc(count*sizeof(struct hlist_head) +
 224                      sizeof(struct eb_objects),
 225                      GFP_KERNEL);
 226         if (eb == NULL)
 227                 return eb;
 228
 229         eb->and = count - 1;
 230         return eb;
 231 }
 232
 233 static void
 234 eb_reset(struct eb_objects *eb)
 235 {
 236         memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
 237 }
 238
 239 static void
 240 eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
 241 {
 242         hlist_add_head(&obj->exec_node,
 243                        &eb->buckets[obj->exec_handle & eb->and]);
 244 }
 245
 246 static struct drm_i915_gem_object *
 247 eb_get_object(struct eb_objects *eb, unsigned long handle)
 248 {
 249         struct hlist_head *head;
 250         struct hlist_node *node;
 251         struct drm_i915_gem_object *obj;
 252
 253         head = &eb->buckets[handle & eb->and];
 254         hlist_for_each(node, head) {
 255                 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
 256                 if (obj->exec_handle == handle)
 257                         return obj;
 258         }
 259
 260         return NULL;
 261 }
 262
 263 static void
 264 eb_destroy(struct eb_objects *eb)
 265 {
 266         kfree(eb);
 267 }
 268
 269 static int
 270 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
 271                                    struct eb_objects *eb,
 272                                    struct drm_i915_gem_relocation_entry *reloc)
 273 {
 274         struct drm_device *dev = obj->base.dev;
 275         struct drm_gem_object *target_obj;
 276         uint32_t target_offset;
 277         int ret = -EINVAL;
 278
 279         /* we've already hold a reference to all valid objects */
 280         target_obj = &eb_get_object(eb, reloc->target_handle)->base;
 281         if (unlikely(target_obj == NULL))
 282                 return -ENOENT;
 283
 284         target_offset = to_intel_bo(target_obj)->gtt_offset;
 285
 286         /* The target buffer should have appeared before us in the
 287          * exec_object list, so it should have a GTT space bound by now.
 288          */
 289         if (unlikely(target_offset == 0)) {
 290                 DRM_DEBUG("No GTT space found for object %d\n",
 291                           reloc->target_handle);
 292                 return ret;
 293         }
 294
 295         /* Validate that the target is in a valid r/w GPU domain */
 296         if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
 297                 DRM_DEBUG("reloc with multiple write domains: "
 298                           "obj %p target %d offset %d "
 299                           "read %08x write %08x",
 300                           obj, reloc->target_handle,
 301                           (int) reloc->offset,
 302                           reloc->read_domains,
 303                           reloc->write_domain);
 304                 return ret;
 305         }
 306         if (unlikely((reloc->write_domain | reloc->read_domains)
 307                      & ~I915_GEM_GPU_DOMAINS)) {
 308                 DRM_DEBUG("reloc with read/write non-GPU domains: "
 309                           "obj %p target %d offset %d "
 310                           "read %08x write %08x",
 311                           obj, reloc->target_handle,
 312                           (int) reloc->offset,
 313                           reloc->read_domains,
 314                           reloc->write_domain);
 315                 return ret;
 316         }
 317         if (unlikely(reloc->write_domain && target_obj->pending_write_domain &&
 318                      reloc->write_domain != target_obj->pending_write_domain)) {
 319                 DRM_DEBUG("Write domain conflict: "
 320                           "obj %p target %d offset %d "
 321                           "new %08x old %08x\n",
 322                           obj, reloc->target_handle,
 323                           (int) reloc->offset,
 324                           reloc->write_domain,
 325                           target_obj->pending_write_domain);
 326                 return ret;
 327         }
 328
 329         target_obj->pending_read_domains |= reloc->read_domains;
 330         target_obj->pending_write_domain |= reloc->write_domain;
 331
 332         /* If the relocation already has the right value in it, no
 333          * more work needs to be done.
 334          */
 335         if (target_offset == reloc->presumed_offset)
 336                 return 0;
 337
 338         /* Check that the relocation address is valid... */
 339         if (unlikely(reloc->offset > obj->base.size - 4)) {
 340                 DRM_DEBUG("Relocation beyond object bounds: "
 341                           "obj %p target %d offset %d size %d.\n",
 342                           obj, reloc->target_handle,
 343                           (int) reloc->offset,
 344                           (int) obj->base.size);
 345                 return ret;
 346         }
 347         if (unlikely(reloc->offset & 3)) {
 348                 DRM_DEBUG("Relocation not 4-byte aligned: "
 349                           "obj %p target %d offset %d.\n",
 350                           obj, reloc->target_handle,
 351                           (int) reloc->offset);
 352                 return ret;
 353         }
 354
 355         reloc->delta += target_offset;
 356         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
 357                 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
 358                 char *vaddr;
 359
 360                 vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]);
 361                 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
 362                 kunmap_atomic(vaddr);
 363         } else {
 364                 struct drm_i915_private *dev_priv = dev->dev_private;
 365                 uint32_t __iomem *reloc_entry;
 366                 void __iomem *reloc_page;
 367
 368                 /* We can't wait for rendering with pagefaults disabled */
 369                 if (obj->active && in_atomic())
 370                         return -EFAULT;
 371
 372                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 373                 if (ret)
 374                         return ret;
 375
 376                 /* Map the page containing the relocation we're going to perform.  */
 377                 reloc->offset += obj->gtt_offset;
 378                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 379                                                       reloc->offset & PAGE_MASK);
 380                 reloc_entry = (uint32_t __iomem *)
 381                         (reloc_page + (reloc->offset & ~PAGE_MASK));
 382                 iowrite32(reloc->delta, reloc_entry);
 383                 io_mapping_unmap_atomic(reloc_page);
 384         }
 385
 386         /* and update the user's relocation entry */
 387         reloc->presumed_offset = target_offset;
 388
 389         return 0;
 390 }
 391
 392 static int
 393 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
 394                                     struct eb_objects *eb)
 395 {
 396         struct drm_i915_gem_relocation_entry __user *user_relocs;
 397         struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 398         int i, ret;
 399
 400         user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
 401         for (i = 0; i < entry->relocation_count; i++) {
 402                 struct drm_i915_gem_relocation_entry reloc;
 403
 404                 if (__copy_from_user_inatomic(&reloc,
 405                                               user_relocs+i,
 406                                               sizeof(reloc)))
 407                         return -EFAULT;
 408
 409                 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &reloc);
 410                 if (ret)
 411                         return ret;
 412
 413                 if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset,
 414                                             &reloc.presumed_offset,
 415                                             sizeof(reloc.presumed_offset)))
 416                         return -EFAULT;
 417         }
 418
 419         return 0;
 420 }
 421
 422 static int
 423 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
 424                                          struct eb_objects *eb,
 425                                          struct drm_i915_gem_relocation_entry *relocs)
 426 {
 427         const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 428         int i, ret;
 429
 430         for (i = 0; i < entry->relocation_count; i++) {
 431                 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
 432                 if (ret)
 433                         return ret;
 434         }
 435
 436         return 0;
 437 }
 438
 439 static int
 440 i915_gem_execbuffer_relocate(struct drm_device *dev,
 441                              struct eb_objects *eb,
 442                              struct list_head *objects)
 443 {
 444         struct drm_i915_gem_object *obj;
 445         int ret = 0;
 446
 447         /* This is the fast path and we cannot handle a pagefault whilst
 448          * holding the struct mutex lest the user pass in the relocations
 449          * contained within a mmaped bo. For in such a case we, the page
 450          * fault handler would call i915_gem_fault() and we would try to
 451          * acquire the struct mutex again. Obviously this is bad and so
 452          * lockdep complains vehemently.
 453          */
 454         pagefault_disable();
 455         list_for_each_entry(obj, objects, exec_list) {
 456                 ret = i915_gem_execbuffer_relocate_object(obj, eb);
 457                 if (ret)
 458                         break;
 459         }
 460         pagefault_enable();
 461
 462         return ret;
 463 }
 464
 465 #define  __EXEC_OBJECT_HAS_FENCE (1<<31)
 466
 467 static int
 468 pin_and_fence_object(struct drm_i915_gem_object *obj,
 469                      struct intel_ring_buffer *ring)
 470 {
 471         struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 472         bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
 473         bool need_fence, need_mappable;
 474         int ret;
 475
 476         need_fence =
 477                 has_fenced_gpu_access &&
 478                 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 479                 obj->tiling_mode != I915_TILING_NONE;
 480         need_mappable =
 481                 entry->relocation_count ? true : need_fence;
 482
 483         ret = i915_gem_object_pin(obj, entry->alignment, need_mappable);
 484         if (ret)
 485                 return ret;
 486
 487         if (has_fenced_gpu_access) {
 488                 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
 489                         if (obj->tiling_mode) {
 490                                 ret = i915_gem_object_get_fence(obj, ring);
 491                                 if (ret)
 492                                         goto err_unpin;
 493
 494                                 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
 495                                 i915_gem_object_pin_fence(obj);
 496                         } else {
 497                                 ret = i915_gem_object_put_fence(obj);
 498                                 if (ret)
 499                                         goto err_unpin;
 500                         }
 501                 }
 502                 obj->pending_fenced_gpu_access = need_fence;
 503         }
 504
 505         entry->offset = obj->gtt_offset;
 506         return 0;
 507
 508 err_unpin:
 509         i915_gem_object_unpin(obj);
 510         return ret;
 511 }
 512
 513 static int
 514 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
 515                             struct drm_file *file,
 516                             struct list_head *objects)
 517 {
 518         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 519         struct drm_i915_gem_object *obj;
 520         int ret, retry;
 521         bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
 522         struct list_head ordered_objects;
 523
 524         INIT_LIST_HEAD(&ordered_objects);
 525         while (!list_empty(objects)) {
 526                 struct drm_i915_gem_exec_object2 *entry;
 527                 bool need_fence, need_mappable;
 528
 529                 obj = list_first_entry(objects,
 530                                        struct drm_i915_gem_object,
 531                                        exec_list);
 532                 entry = obj->exec_entry;
 533
 534                 need_fence =
 535                         has_fenced_gpu_access &&
 536                         entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 537                         obj->tiling_mode != I915_TILING_NONE;
 538                 need_mappable =
 539                         entry->relocation_count ? true : need_fence;
 540
 541                 if (need_mappable)
 542                         list_move(&obj->exec_list, &ordered_objects);
 543                 else
 544                         list_move_tail(&obj->exec_list, &ordered_objects);
 545
 546                 obj->base.pending_read_domains = 0;
 547                 obj->base.pending_write_domain = 0;
 548         }
 549         list_splice(&ordered_objects, objects);
 550
 551         /* Attempt to pin all of the buffers into the GTT.
 552          * This is done in 3 phases:
 553          *
 554          * 1a. Unbind all objects that do not match the GTT constraints for
 555          *     the execbuffer (fenceable, mappable, alignment etc).
 556          * 1b. Increment pin count for already bound objects.
 557          * 2.  Bind new objects.
 558          * 3.  Decrement pin count.
 559          *
 560          * This avoid unnecessary unbinding of later objects in order to makr
 561          * room for the earlier objects *unless* we need to defragment.
 562          */
 563         retry = 0;
 564         do {
 565                 ret = 0;
 566
 567                 /* Unbind any ill-fitting objects or pin. */
 568                 list_for_each_entry(obj, objects, exec_list) {
 569                         struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 570                         bool need_fence, need_mappable;
 571
 572                         if (!obj->gtt_space)
 573                                 continue;
 574
 575                         need_fence =
 576                                 has_fenced_gpu_access &&
 577                                 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 578                                 obj->tiling_mode != I915_TILING_NONE;
 579                         need_mappable =
 580                                 entry->relocation_count ? true : need_fence;
 581
 582                         if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
 583                             (need_mappable && !obj->map_and_fenceable))
 584                                 ret = i915_gem_object_unbind(obj);
 585                         else
 586                                 ret = pin_and_fence_object(obj, ring);
 587                         if (ret)
 588                                 goto err;
 589                 }
 590
 591                 /* Bind fresh objects */
 592                 list_for_each_entry(obj, objects, exec_list) {
 593                         if (obj->gtt_space)
 594                                 continue;
 595
 596                         ret = pin_and_fence_object(obj, ring);
 597                         if (ret) {
 598                                 int ret_ignore;
 599
 600                                 /* This can potentially raise a harmless
 601                                  * -EINVAL if we failed to bind in the above
 602                                  * call. It cannot raise -EINTR since we know
 603                                  * that the bo is freshly bound and so will
 604                                  * not need to be flushed or waited upon.
 605                                  */
 606                                 ret_ignore = i915_gem_object_unbind(obj);
 607                                 (void)ret_ignore;
 608                                 WARN_ON(obj->gtt_space);
 609                                 break;
 610                         }
 611                 }
 612
 613                 /* Decrement pin count for bound objects */
 614                 list_for_each_entry(obj, objects, exec_list) {
 615                         struct drm_i915_gem_exec_object2 *entry;
 616
 617                         if (!obj->gtt_space)
 618                                 continue;
 619
 620                         entry = obj->exec_entry;
 621                         if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
 622                                 i915_gem_object_unpin_fence(obj);
 623                                 entry->flags &= ~__EXEC_OBJECT_HAS_FENCE;
 624                         }
 625
 626                         i915_gem_object_unpin(obj);
 627
 628                         /* ... and ensure ppgtt mapping exist if needed. */
 629                         if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
 630                                 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
 631                                                        obj, obj->cache_level);
 632
 633                                 obj->has_aliasing_ppgtt_mapping = 1;
 634                         }
 635                 }
 636
 637                 if (ret != -ENOSPC || retry > 1)
 638                         return ret;
 639
 640                 /* First attempt, just clear anything that is purgeable.
 641                  * Second attempt, clear the entire GTT.
 642                  */
 643                 ret = i915_gem_evict_everything(ring->dev, retry == 0);
 644                 if (ret)
 645                         return ret;
 646
 647                 retry++;
 648         } while (1);
 649
 650 err:
 651         list_for_each_entry_continue_reverse(obj, objects, exec_list) {
 652                 struct drm_i915_gem_exec_object2 *entry;
 653
 654                 if (!obj->gtt_space)
 655                         continue;
 656
 657                 entry = obj->exec_entry;
 658                 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
 659                         i915_gem_object_unpin_fence(obj);
 660                         entry->flags &= ~__EXEC_OBJECT_HAS_FENCE;
 661                 }
 662
 663                 i915_gem_object_unpin(obj);
 664         }
 665
 666         return ret;
 667 }
 668
 669 static int
 670 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
 671                                   struct drm_file *file,
 672                                   struct intel_ring_buffer *ring,
 673                                   struct list_head *objects,
 674                                   struct eb_objects *eb,
 675                                   struct drm_i915_gem_exec_object2 *exec,
 676                                   int count)
 677 {
 678         struct drm_i915_gem_relocation_entry *reloc;
 679         struct drm_i915_gem_object *obj;
 680         int *reloc_offset;
 681         int i, total, ret;
 682
 683         /* We may process another execbuffer during the unlock... */
 684         while (!list_empty(objects)) {
 685                 obj = list_first_entry(objects,
 686                                        struct drm_i915_gem_object,
 687                                        exec_list);
 688                 list_del_init(&obj->exec_list);
 689                 drm_gem_object_unreference(&obj->base);
 690         }
 691
 692         mutex_unlock(&dev->struct_mutex);
 693
 694         total = 0;
 695         for (i = 0; i < count; i++)
 696                 total += exec[i].relocation_count;
 697
 698         reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
 699         reloc = drm_malloc_ab(total, sizeof(*reloc));
 700         if (reloc == NULL || reloc_offset == NULL) {
 701                 drm_free_large(reloc);
 702                 drm_free_large(reloc_offset);
 703                 mutex_lock(&dev->struct_mutex);
 704                 return -ENOMEM;
 705         }
 706
 707         total = 0;
 708         for (i = 0; i < count; i++) {
 709                 struct drm_i915_gem_relocation_entry __user *user_relocs;
 710
 711                 user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
 712
 713                 if (copy_from_user(reloc+total, user_relocs,
 714                                    exec[i].relocation_count * sizeof(*reloc))) {
 715                         ret = -EFAULT;
 716                         mutex_lock(&dev->struct_mutex);
 717                         goto err;
 718                 }
 719
 720                 reloc_offset[i] = total;
 721                 total += exec[i].relocation_count;
 722         }
 723
 724         ret = i915_mutex_lock_interruptible(dev);
 725         if (ret) {
 726                 mutex_lock(&dev->struct_mutex);
 727                 goto err;
 728         }
 729
 730         /* reacquire the objects */
 731         eb_reset(eb);
 732         for (i = 0; i < count; i++) {
 733                 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
 734                                                         exec[i].handle));
 735                 if (&obj->base == NULL) {
 736                         DRM_DEBUG("Invalid object handle %d at index %d\n",
 737                                    exec[i].handle, i);
 738                         ret = -ENOENT;
 739                         goto err;
 740                 }
 741
 742                 list_add_tail(&obj->exec_list, objects);
 743                 obj->exec_handle = exec[i].handle;
 744                 obj->exec_entry = &exec[i];
 745                 eb_add_object(eb, obj);
 746         }
 747
 748         ret = i915_gem_execbuffer_reserve(ring, file, objects);
 749         if (ret)
 750                 goto err;
 751
 752         list_for_each_entry(obj, objects, exec_list) {
 753                 int offset = obj->exec_entry - exec;
 754                 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
 755                                                                reloc + reloc_offset[offset]);
 756                 if (ret)
 757                         goto err;
 758         }
 759
 760         /* Leave the user relocations as are, this is the painfully slow path,
 761          * and we want to avoid the complication of dropping the lock whilst
 762          * having buffers reserved in the aperture and so causing spurious
 763          * ENOSPC for random operations.
 764          */
 765
 766 err:
 767         drm_free_large(reloc);
 768         drm_free_large(reloc_offset);
 769         return ret;
 770 }
 771
 772 static int
 773 i915_gem_execbuffer_flush(struct drm_device *dev,
 774                           uint32_t invalidate_domains,
 775                           uint32_t flush_domains,
 776                           uint32_t flush_rings)
 777 {
 778         drm_i915_private_t *dev_priv = dev->dev_private;
 779         int i, ret;
 780
 781         if (flush_domains & I915_GEM_DOMAIN_CPU)
 782                 intel_gtt_chipset_flush();
 783
 784         if (flush_domains & I915_GEM_DOMAIN_GTT)
 785                 wmb();
 786
 787         if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
 788                 for (i = 0; i < I915_NUM_RINGS; i++)
 789                         if (flush_rings & (1 << i)) {
 790                                 ret = i915_gem_flush_ring(&dev_priv->ring[i],
 791                                                           invalidate_domains,
 792                                                           flush_domains);
 793                                 if (ret)
 794                                         return ret;
 795                         }
 796         }
 797
 798         return 0;
 799 }
 800
 801 static bool
 802 intel_enable_semaphores(struct drm_device *dev)
 803 {
 804         if (INTEL_INFO(dev)->gen < 6)
 805                 return 0;
 806
 807         if (i915_semaphores >= 0)
 808                 return i915_semaphores;
 809
 810         /* Disable semaphores on SNB */
 811         if (INTEL_INFO(dev)->gen == 6)
 812                 return 0;
 813
 814         return 1;
 815 }
 816
 817 static int
 818 i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
 819                                struct intel_ring_buffer *to)
 820 {
 821         struct intel_ring_buffer *from = obj->ring;
 822         u32 seqno;
 823         int ret, idx;
 824
 825         if (from == NULL || to == from)
 826                 return 0;
 827
 828         /* XXX gpu semaphores are implicated in various hard hangs on SNB */
 829         if (!intel_enable_semaphores(obj->base.dev))
 830                 return i915_gem_object_wait_rendering(obj);
 831
 832         idx = intel_ring_sync_index(from, to);
 833
 834         seqno = obj->last_rendering_seqno;
 835         if (seqno <= from->sync_seqno[idx])
 836                 return 0;
 837
 838         if (seqno == from->outstanding_lazy_request) {
 839                 struct drm_i915_gem_request *request;
 840
 841                 request = kzalloc(sizeof(*request), GFP_KERNEL);
 842                 if (request == NULL)
 843                         return -ENOMEM;
 844
 845                 ret = i915_add_request(from, NULL, request);
 846                 if (ret) {
 847                         kfree(request);
 848                         return ret;
 849                 }
 850
 851                 seqno = request->seqno;
 852         }
 853
 854         from->sync_seqno[idx] = seqno;
 855
 856         return to->sync_to(to, from, seqno - 1);
 857 }
 858
 859 static int
 860 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips)
 861 {
 862         u32 plane, flip_mask;
 863         int ret;
 864
 865         /* Check for any pending flips. As we only maintain a flip queue depth
 866          * of 1, we can simply insert a WAIT for the next display flip prior
 867          * to executing the batch and avoid stalling the CPU.
 868          */
 869
 870         for (plane = 0; flips >> plane; plane++) {
 871                 if (((flips >> plane) & 1) == 0)
 872                         continue;
 873
 874                 if (plane)
 875                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
 876                 else
 877                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
 878
 879                 ret = intel_ring_begin(ring, 2);
 880                 if (ret)
 881                         return ret;
 882
 883                 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
 884                 intel_ring_emit(ring, MI_NOOP);
 885                 intel_ring_advance(ring);
 886         }
 887
 888         return 0;
 889 }
 890
 891
 892 static int
 893 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
 894                                 struct list_head *objects)
 895 {
 896         struct drm_i915_gem_object *obj;
 897         struct change_domains cd;
 898         int ret;
 899
 900         memset(&cd, 0, sizeof(cd));
 901         list_for_each_entry(obj, objects, exec_list)
 902                 i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
 903
 904         if (cd.invalidate_domains | cd.flush_domains) {
 905                 ret = i915_gem_execbuffer_flush(ring->dev,
 906                                                 cd.invalidate_domains,
 907                                                 cd.flush_domains,
 908                                                 cd.flush_rings);
 909                 if (ret)
 910                         return ret;
 911         }
 912
 913         if (cd.flips) {
 914                 ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips);
 915                 if (ret)
 916                         return ret;
 917         }
 918
 919         list_for_each_entry(obj, objects, exec_list) {
 920                 ret = i915_gem_execbuffer_sync_rings(obj, ring);
 921                 if (ret)
 922                         return ret;
 923         }
 924
 925         return 0;
 926 }
 927
 928 static bool
 929 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
 930 {
 931         return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
 932 }
 933
 934 static int
 935 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
 936                    int count)
 937 {
 938         int i;
 939
 940         for (i = 0; i < count; i++) {
 941                 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
 942                 int length; /* limited by fault_in_pages_readable() */
 943
 944                 /* First check for malicious input causing overflow */
 945                 if (exec[i].relocation_count >
 946                     INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
 947                         return -EINVAL;
 948
 949                 length = exec[i].relocation_count *
 950                         sizeof(struct drm_i915_gem_relocation_entry);
 951                 if (!access_ok(VERIFY_READ, ptr, length))
 952                         return -EFAULT;
 953
 954                 /* we may also need to update the presumed offsets */
 955                 if (!access_ok(VERIFY_WRITE, ptr, length))
 956                         return -EFAULT;
 957
 958                 if (fault_in_pages_readable(ptr, length))
 959                         return -EFAULT;
 960         }
 961
 962         return 0;
 963 }
 964
 965 static void
 966 i915_gem_execbuffer_move_to_active(struct list_head *objects,
 967                                    struct intel_ring_buffer *ring,
 968                                    u32 seqno)
 969 {
 970         struct drm_i915_gem_object *obj;
 971
 972         list_for_each_entry(obj, objects, exec_list) {
 973                   u32 old_read = obj->base.read_domains;
 974                   u32 old_write = obj->base.write_domain;
 975
 976
 977                 obj->base.read_domains = obj->base.pending_read_domains;
 978                 obj->base.write_domain = obj->base.pending_write_domain;
 979                 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
 980
 981                 i915_gem_object_move_to_active(obj, ring, seqno);
 982                 if (obj->base.write_domain) {
 983                         obj->dirty = 1;
 984                         obj->pending_gpu_write = true;
 985                         list_move_tail(&obj->gpu_write_list,
 986                                        &ring->gpu_write_list);
 987                         intel_mark_busy(ring->dev, obj);
 988                 }
 989
 990                 trace_i915_gem_object_change_domain(obj, old_read, old_write);
 991         }
 992 }
 993
 994 static void
 995 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
 996                                     struct drm_file *file,
 997                                     struct intel_ring_buffer *ring)
 998 {
 999         struct drm_i915_gem_request *request;
1000         u32 invalidate;
1001
1002         /*
1003          * Ensure that the commands in the batch buffer are
1004          * finished before the interrupt fires.
1005          *
1006          * The sampler always gets flushed on i965 (sigh).
1007          */
1008         invalidate = I915_GEM_DOMAIN_COMMAND;
1009         if (INTEL_INFO(dev)->gen >= 4)
1010                 invalidate |= I915_GEM_DOMAIN_SAMPLER;
1011         if (ring->flush(ring, invalidate, 0)) {
1012                 i915_gem_next_request_seqno(ring);
1013                 return;
1014         }
1015
1016         /* Add a breadcrumb for the completion of the batch buffer */
1017         request = kzalloc(sizeof(*request), GFP_KERNEL);
1018         if (request == NULL || i915_add_request(ring, file, request)) {
1019                 i915_gem_next_request_seqno(ring);
1020                 kfree(request);
1021         }
1022 }
1023
1024 static int
1025 i915_reset_gen7_sol_offsets(struct drm_device *dev,
1026                             struct intel_ring_buffer *ring)
1027 {
1028         drm_i915_private_t *dev_priv = dev->dev_private;
1029         int ret, i;
1030
1031         if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
1032                 return 0;
1033
1034         ret = intel_ring_begin(ring, 4 * 3);
1035         if (ret)
1036                 return ret;
1037
1038         for (i = 0; i < 4; i++) {
1039                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1040                 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
1041                 intel_ring_emit(ring, 0);
1042         }
1043
1044         intel_ring_advance(ring);
1045
1046         return 0;
1047 }
1048
1049 static int
1050 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1051                        struct drm_file *file,
1052                        struct drm_i915_gem_execbuffer2 *args,
1053                        struct drm_i915_gem_exec_object2 *exec)
1054 {
1055         drm_i915_private_t *dev_priv = dev->dev_private;
1056         struct list_head objects;
1057         struct eb_objects *eb;
1058         struct drm_i915_gem_object *batch_obj;
1059         struct drm_clip_rect *cliprects = NULL;
1060         struct intel_ring_buffer *ring;
1061         u32 exec_start, exec_len;
1062         u32 seqno;
1063         u32 mask;
1064         int ret, mode, i;
1065
1066         if (!i915_gem_check_execbuffer(args)) {
1067                 DRM_DEBUG("execbuf with invalid offset/length\n");
1068                 return -EINVAL;
1069         }
1070
1071         ret = validate_exec_list(exec, args->buffer_count);
1072         if (ret)
1073                 return ret;
1074
1075         switch (args->flags & I915_EXEC_RING_MASK) {
1076         case I915_EXEC_DEFAULT:
1077         case I915_EXEC_RENDER:
1078                 ring = &dev_priv->ring[RCS];
1079                 break;
1080         case I915_EXEC_BSD:
1081                 if (!HAS_BSD(dev)) {
1082                         DRM_DEBUG("execbuf with invalid ring (BSD)\n");
1083                         return -EINVAL;
1084                 }
1085                 ring = &dev_priv->ring[VCS];
1086                 break;
1087         case I915_EXEC_BLT:
1088                 if (!HAS_BLT(dev)) {
1089                         DRM_DEBUG("execbuf with invalid ring (BLT)\n");
1090                         return -EINVAL;
1091                 }
1092                 ring = &dev_priv->ring[BCS];
1093                 break;
1094         default:
1095                 DRM_DEBUG("execbuf with unknown ring: %d\n",
1096                           (int)(args->flags & I915_EXEC_RING_MASK));
1097                 return -EINVAL;
1098         }
1099
1100         mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1101         mask = I915_EXEC_CONSTANTS_MASK;
1102         switch (mode) {
1103         case I915_EXEC_CONSTANTS_REL_GENERAL:
1104         case I915_EXEC_CONSTANTS_ABSOLUTE:
1105         case I915_EXEC_CONSTANTS_REL_SURFACE:
1106                 if (ring == &dev_priv->ring[RCS] &&
1107                     mode != dev_priv->relative_constants_mode) {
1108                         if (INTEL_INFO(dev)->gen < 4)
1109                                 return -EINVAL;
1110
1111                         if (INTEL_INFO(dev)->gen > 5 &&
1112                             mode == I915_EXEC_CONSTANTS_REL_SURFACE)
1113                                 return -EINVAL;
1114
1115                         /* The HW changed the meaning on this bit on gen6 */
1116                         if (INTEL_INFO(dev)->gen >= 6)
1117                                 mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1118                 }
1119                 break;
1120         default:
1121                 DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
1122                 return -EINVAL;
1123         }
1124
1125         if (args->buffer_count < 1) {
1126                 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1127                 return -EINVAL;
1128         }
1129
1130         if (args->num_cliprects != 0) {
1131                 if (ring != &dev_priv->ring[RCS]) {
1132                         DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1133                         return -EINVAL;
1134                 }
1135
1136                 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
1137                                     GFP_KERNEL);
1138                 if (cliprects == NULL) {
1139                         ret = -ENOMEM;
1140                         goto pre_mutex_err;
1141                 }
1142
1143                 if (copy_from_user(cliprects,
1144                                      (struct drm_clip_rect __user *)(uintptr_t)
1145                                      args->cliprects_ptr,
1146                                      sizeof(*cliprects)*args->num_cliprects)) {
1147                         ret = -EFAULT;
1148                         goto pre_mutex_err;
1149                 }
1150         }
1151
1152         ret = i915_mutex_lock_interruptible(dev);
1153         if (ret)
1154                 goto pre_mutex_err;
1155
1156         if (dev_priv->mm.suspended) {
1157                 mutex_unlock(&dev->struct_mutex);
1158                 ret = -EBUSY;
1159                 goto pre_mutex_err;
1160         }
1161
1162         eb = eb_create(args->buffer_count);
1163         if (eb == NULL) {
1164                 mutex_unlock(&dev->struct_mutex);
1165                 ret = -ENOMEM;
1166                 goto pre_mutex_err;
1167         }
1168
1169         /* Look up object handles */
1170         INIT_LIST_HEAD(&objects);
1171         for (i = 0; i < args->buffer_count; i++) {
1172                 struct drm_i915_gem_object *obj;
1173
1174                 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
1175                                                         exec[i].handle));
1176                 if (&obj->base == NULL) {
1177                         DRM_DEBUG("Invalid object handle %d at index %d\n",
1178                                    exec[i].handle, i);
1179                         /* prevent error path from reading uninitialized data */
1180                         ret = -ENOENT;
1181                         goto err;
1182                 }
1183
1184                 if (!list_empty(&obj->exec_list)) {
1185                         DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
1186                                    obj, exec[i].handle, i);
1187                         ret = -EINVAL;
1188                         goto err;
1189                 }
1190
1191                 list_add_tail(&obj->exec_list, &objects);
1192                 obj->exec_handle = exec[i].handle;
1193                 obj->exec_entry = &exec[i];
1194                 eb_add_object(eb, obj);
1195         }
1196
1197         /* take note of the batch buffer before we might reorder the lists */
1198         batch_obj = list_entry(objects.prev,
1199                                struct drm_i915_gem_object,
1200                                exec_list);
1201
1202         /* Move the objects en-masse into the GTT, evicting if necessary. */
1203         ret = i915_gem_execbuffer_reserve(ring, file, &objects);
1204         if (ret)
1205                 goto err;
1206
1207         /* The objects are in their final locations, apply the relocations. */
1208         ret = i915_gem_execbuffer_relocate(dev, eb, &objects);
1209         if (ret) {
1210                 if (ret == -EFAULT) {
1211                         ret = i915_gem_execbuffer_relocate_slow(dev, file, ring,
1212                                                                 &objects, eb,
1213                                                                 exec,
1214                                                                 args->buffer_count);
1215                         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1216                 }
1217                 if (ret)
1218                         goto err;
1219         }
1220
1221         /* Set the pending read domains for the batch buffer to COMMAND */
1222         if (batch_obj->base.pending_write_domain) {
1223                 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1224                 ret = -EINVAL;
1225                 goto err;
1226         }
1227         batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1228
1229         ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
1230         if (ret)
1231                 goto err;
1232
1233         seqno = i915_gem_next_request_seqno(ring);
1234         for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) {
1235                 if (seqno < ring->sync_seqno[i]) {
1236                         /* The GPU can not handle its semaphore value wrapping,
1237                          * so every billion or so execbuffers, we need to stall
1238                          * the GPU in order to reset the counters.
1239                          */
1240                         ret = i915_gpu_idle(dev, true);
1241                         if (ret)
1242                                 goto err;
1243
1244                         BUG_ON(ring->sync_seqno[i]);
1245                 }
1246         }
1247
1248         if (ring == &dev_priv->ring[RCS] &&
1249             mode != dev_priv->relative_constants_mode) {
1250                 ret = intel_ring_begin(ring, 4);
1251                 if (ret)
1252                                 goto err;
1253
1254                 intel_ring_emit(ring, MI_NOOP);
1255                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1256                 intel_ring_emit(ring, INSTPM);
1257                 intel_ring_emit(ring, mask << 16 | mode);
1258                 intel_ring_advance(ring);
1259
1260                 dev_priv->relative_constants_mode = mode;
1261         }
1262
1263         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1264                 ret = i915_reset_gen7_sol_offsets(dev, ring);
1265                 if (ret)
1266                         goto err;
1267         }
1268
1269         trace_i915_gem_ring_dispatch(ring, seqno);
1270
1271         exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1272         exec_len = args->batch_len;
1273         if (cliprects) {
1274                 for (i = 0; i < args->num_cliprects; i++) {
1275                         ret = i915_emit_box(dev, &cliprects[i],
1276                                             args->DR1, args->DR4);
1277                         if (ret)
1278                                 goto err;
1279
1280                         ret = ring->dispatch_execbuffer(ring,
1281                                                         exec_start, exec_len);
1282                         if (ret)
1283                                 goto err;
1284                 }
1285         } else {
1286                 ret = ring->dispatch_execbuffer(ring, exec_start, exec_len);
1287                 if (ret)
1288                         goto err;
1289         }
1290
1291         i915_gem_execbuffer_move_to_active(&objects, ring, seqno);
1292         i915_gem_execbuffer_retire_commands(dev, file, ring);
1293
1294 err:
1295         eb_destroy(eb);
1296         while (!list_empty(&objects)) {
1297                 struct drm_i915_gem_object *obj;
1298
1299                 obj = list_first_entry(&objects,
1300                                        struct drm_i915_gem_object,
1301                                        exec_list);
1302                 list_del_init(&obj->exec_list);
1303                 drm_gem_object_unreference(&obj->base);
1304         }
1305
1306         mutex_unlock(&dev->struct_mutex);
1307
1308 pre_mutex_err:
1309         kfree(cliprects);
1310         return ret;
1311 }
1312
1313 /*
1314  * Legacy execbuffer just creates an exec2 list from the original exec object
1315  * list array and passes it to the real function.
1316  */
1317 int
1318 i915_gem_execbuffer(struct drm_device *dev, void *data,
1319                     struct drm_file *file)
1320 {
1321         struct drm_i915_gem_execbuffer *args = data;
1322         struct drm_i915_gem_execbuffer2 exec2;
1323         struct drm_i915_gem_exec_object *exec_list = NULL;
1324         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1325         int ret, i;
1326
1327         if (args->buffer_count < 1) {
1328                 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1329                 return -EINVAL;
1330         }
1331
1332         /* Copy in the exec list from userland */
1333         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1334         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1335         if (exec_list == NULL || exec2_list == NULL) {
1336                 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1337                           args->buffer_count);
1338                 drm_free_large(exec_list);
1339                 drm_free_large(exec2_list);
1340                 return -ENOMEM;
1341         }
1342         ret = copy_from_user(exec_list,
1343                              (struct drm_i915_relocation_entry __user *)
1344                              (uintptr_t) args->buffers_ptr,
1345                              sizeof(*exec_list) * args->buffer_count);
1346         if (ret != 0) {
1347                 DRM_DEBUG("copy %d exec entries failed %d\n",
1348                           args->buffer_count, ret);
1349                 drm_free_large(exec_list);
1350                 drm_free_large(exec2_list);
1351                 return -EFAULT;
1352         }
1353
1354         for (i = 0; i < args->buffer_count; i++) {
1355                 exec2_list[i].handle = exec_list[i].handle;
1356                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1357                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1358                 exec2_list[i].alignment = exec_list[i].alignment;
1359                 exec2_list[i].offset = exec_list[i].offset;
1360                 if (INTEL_INFO(dev)->gen < 4)
1361                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1362                 else
1363                         exec2_list[i].flags = 0;
1364         }
1365
1366         exec2.buffers_ptr = args->buffers_ptr;
1367         exec2.buffer_count = args->buffer_count;
1368         exec2.batch_start_offset = args->batch_start_offset;
1369         exec2.batch_len = args->batch_len;
1370         exec2.DR1 = args->DR1;
1371         exec2.DR4 = args->DR4;
1372         exec2.num_cliprects = args->num_cliprects;
1373         exec2.cliprects_ptr = args->cliprects_ptr;
1374         exec2.flags = I915_EXEC_RENDER;
1375
1376         ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1377         if (!ret) {
1378                 /* Copy the new buffer offsets back to the user's exec list. */
1379                 for (i = 0; i < args->buffer_count; i++)
1380                         exec_list[i].offset = exec2_list[i].offset;
1381                 /* ... and back out to userspace */
1382                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1383                                    (uintptr_t) args->buffers_ptr,
1384                                    exec_list,
1385                                    sizeof(*exec_list) * args->buffer_count);
1386                 if (ret) {
1387                         ret = -EFAULT;
1388                         DRM_DEBUG("failed to copy %d exec entries "
1389                                   "back to user (%d)\n",
1390                                   args->buffer_count, ret);
1391                 }
1392         }
1393
1394         drm_free_large(exec_list);
1395         drm_free_large(exec2_list);
1396         return ret;
1397 }
1398
1399 int
1400 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1401                      struct drm_file *file)
1402 {
1403         struct drm_i915_gem_execbuffer2 *args = data;
1404         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1405         int ret;
1406
1407         if (args->buffer_count < 1) {
1408                 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1409                 return -EINVAL;
1410         }
1411
1412         exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1413                              GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
1414         if (exec2_list == NULL)
1415                 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1416                                            args->buffer_count);
1417         if (exec2_list == NULL) {
1418                 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1419                           args->buffer_count);
1420                 return -ENOMEM;
1421         }
1422         ret = copy_from_user(exec2_list,
1423                              (struct drm_i915_relocation_entry __user *)
1424                              (uintptr_t) args->buffers_ptr,
1425                              sizeof(*exec2_list) * args->buffer_count);
1426         if (ret != 0) {
1427                 DRM_DEBUG("copy %d exec entries failed %d\n",
1428                           args->buffer_count, ret);
1429                 drm_free_large(exec2_list);
1430                 return -EFAULT;
1431         }
1432
1433         ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1434         if (!ret) {
1435                 /* Copy the new buffer offsets back to the user's exec list. */
1436                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1437                                    (uintptr_t) args->buffers_ptr,
1438                                    exec2_list,
1439                                    sizeof(*exec2_list) * args->buffer_count);
1440                 if (ret) {
1441                         ret = -EFAULT;
1442                         DRM_DEBUG("failed to copy %d exec entries "
1443                                   "back to user (%d)\n",
1444                                   args->buffer_count, ret);
1445                 }
1446         }
1447
1448         drm_free_large(exec2_list);
1449         return ret;
1450 }