arch/arm/mach-at91/at91sam9g45_devices.c

   1 /*
   2  *  On-Chip devices setup code for the AT91SAM9G45 family
   3  *
   4  *  Copyright (C) 2009 Atmel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12 #include <asm/mach/arch.h>
  13 #include <asm/mach/map.h>
  14
  15 #include <linux/dma-mapping.h>
  16 #include <linux/gpio.h>
  17 #include <linux/clk.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/i2c-gpio.h>
  20 #include <linux/atmel-mci.h>
  21
  22 #include <linux/fb.h>
  23 #include <video/atmel_lcdc.h>
  24
  25 #include <mach/board.h>
  26 #include <mach/at91sam9g45.h>
  27 #include <mach/at91sam9g45_matrix.h>
  28 #include <mach/at91_matrix.h>
  29 #include <mach/at91sam9_smc.h>
  30 #include <mach/at_hdmac.h>
  31 #include <mach/atmel-mci.h>
  32
  33 #include <media/atmel-isi.h>
  34
  35 #include "generic.h"
  36 #include "clock.h"
  37
  38
  39 /* --------------------------------------------------------------------
  40  *  HDMAC - AHB DMA Controller
  41  * -------------------------------------------------------------------- */
  42
  43 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
  44 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
  45
  46 static struct resource hdmac_resources[] = {
  47         [0] = {
  48                 .start  = AT91SAM9G45_BASE_DMA,
  49                 .end    = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
  50                 .flags  = IORESOURCE_MEM,
  51         },
  52         [1] = {
  53                 .start  = AT91SAM9G45_ID_DMA,
  54                 .end    = AT91SAM9G45_ID_DMA,
  55                 .flags  = IORESOURCE_IRQ,
  56         },
  57 };
  58
  59 static struct platform_device at_hdmac_device = {
  60         .name           = "at91sam9g45_dma",
  61         .id             = -1,
  62         .dev            = {
  63                                 .dma_mask               = &hdmac_dmamask,
  64                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
  65         },
  66         .resource       = hdmac_resources,
  67         .num_resources  = ARRAY_SIZE(hdmac_resources),
  68 };
  69
  70 void __init at91_add_device_hdmac(void)
  71 {
  72 #if defined(CONFIG_OF)
  73         struct device_node *of_node =
  74                 of_find_node_by_name(NULL, "dma-controller");
  75
  76         if (of_node)
  77                 of_node_put(of_node);
  78         else
  79 #endif
  80                 platform_device_register(&at_hdmac_device);
  81 }
  82 #else
  83 void __init at91_add_device_hdmac(void) {}
  84 #endif
  85
  86
  87 /* --------------------------------------------------------------------
  88  *  USB Host (OHCI)
  89  * -------------------------------------------------------------------- */
  90
  91 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  92 static u64 ohci_dmamask = DMA_BIT_MASK(32);
  93 static struct at91_usbh_data usbh_ohci_data;
  94
  95 static struct resource usbh_ohci_resources[] = {
  96         [0] = {
  97                 .start  = AT91SAM9G45_OHCI_BASE,
  98                 .end    = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
  99                 .flags  = IORESOURCE_MEM,
 100         },
 101         [1] = {
 102                 .start  = AT91SAM9G45_ID_UHPHS,
 103                 .end    = AT91SAM9G45_ID_UHPHS,
 104                 .flags  = IORESOURCE_IRQ,
 105         },
 106 };
 107
 108 static struct platform_device at91_usbh_ohci_device = {
 109         .name           = "at91_ohci",
 110         .id             = -1,
 111         .dev            = {
 112                                 .dma_mask               = &ohci_dmamask,
 113                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 114                                 .platform_data          = &usbh_ohci_data,
 115         },
 116         .resource       = usbh_ohci_resources,
 117         .num_resources  = ARRAY_SIZE(usbh_ohci_resources),
 118 };
 119
 120 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
 121 {
 122         int i;
 123
 124         if (!data)
 125                 return;
 126
 127         /* Enable VBus control for UHP ports */
 128         for (i = 0; i < data->ports; i++) {
 129                 if (gpio_is_valid(data->vbus_pin[i]))
 130                         at91_set_gpio_output(data->vbus_pin[i], 0);
 131         }
 132
 133         /* Enable overcurrent notification */
 134         for (i = 0; i < data->ports; i++) {
 135                 if (data->overcurrent_pin[i])
 136                         at91_set_gpio_input(data->overcurrent_pin[i], 1);
 137         }
 138
 139         usbh_ohci_data = *data;
 140         platform_device_register(&at91_usbh_ohci_device);
 141 }
 142 #else
 143 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
 144 #endif
 145
 146
 147 /* --------------------------------------------------------------------
 148  *  USB Host HS (EHCI)
 149  *  Needs an OHCI host for low and full speed management
 150  * -------------------------------------------------------------------- */
 151
 152 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
 153 static u64 ehci_dmamask = DMA_BIT_MASK(32);
 154 static struct at91_usbh_data usbh_ehci_data;
 155
 156 static struct resource usbh_ehci_resources[] = {
 157         [0] = {
 158                 .start  = AT91SAM9G45_EHCI_BASE,
 159                 .end    = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
 160                 .flags  = IORESOURCE_MEM,
 161         },
 162         [1] = {
 163                 .start  = AT91SAM9G45_ID_UHPHS,
 164                 .end    = AT91SAM9G45_ID_UHPHS,
 165                 .flags  = IORESOURCE_IRQ,
 166         },
 167 };
 168
 169 static struct platform_device at91_usbh_ehci_device = {
 170         .name           = "atmel-ehci",
 171         .id             = -1,
 172         .dev            = {
 173                                 .dma_mask               = &ehci_dmamask,
 174                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 175                                 .platform_data          = &usbh_ehci_data,
 176         },
 177         .resource       = usbh_ehci_resources,
 178         .num_resources  = ARRAY_SIZE(usbh_ehci_resources),
 179 };
 180
 181 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
 182 {
 183         int i;
 184
 185         if (!data)
 186                 return;
 187
 188         /* Enable VBus control for UHP ports */
 189         for (i = 0; i < data->ports; i++) {
 190                 if (gpio_is_valid(data->vbus_pin[i]))
 191                         at91_set_gpio_output(data->vbus_pin[i], 0);
 192         }
 193
 194         usbh_ehci_data = *data;
 195         platform_device_register(&at91_usbh_ehci_device);
 196 }
 197 #else
 198 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
 199 #endif
 200
 201
 202 /* --------------------------------------------------------------------
 203  *  USB HS Device (Gadget)
 204  * -------------------------------------------------------------------- */
 205
 206 #if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
 207 static struct resource usba_udc_resources[] = {
 208         [0] = {
 209                 .start  = AT91SAM9G45_UDPHS_FIFO,
 210                 .end    = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
 211                 .flags  = IORESOURCE_MEM,
 212         },
 213         [1] = {
 214                 .start  = AT91SAM9G45_BASE_UDPHS,
 215                 .end    = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
 216                 .flags  = IORESOURCE_MEM,
 217         },
 218         [2] = {
 219                 .start  = AT91SAM9G45_ID_UDPHS,
 220                 .end    = AT91SAM9G45_ID_UDPHS,
 221                 .flags  = IORESOURCE_IRQ,
 222         },
 223 };
 224
 225 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
 226         [idx] = {                                               \
 227                 .name           = nam,                          \
 228                 .index          = idx,                          \
 229                 .fifo_size      = maxpkt,                       \
 230                 .nr_banks       = maxbk,                        \
 231                 .can_dma        = dma,                          \
 232                 .can_isoc       = isoc,                         \
 233         }
 234
 235 static struct usba_ep_data usba_udc_ep[] __initdata = {
 236         EP("ep0", 0, 64, 1, 0, 0),
 237         EP("ep1", 1, 1024, 2, 1, 1),
 238         EP("ep2", 2, 1024, 2, 1, 1),
 239         EP("ep3", 3, 1024, 3, 1, 0),
 240         EP("ep4", 4, 1024, 3, 1, 0),
 241         EP("ep5", 5, 1024, 3, 1, 1),
 242         EP("ep6", 6, 1024, 3, 1, 1),
 243 };
 244
 245 #undef EP
 246
 247 /*
 248  * pdata doesn't have room for any endpoints, so we need to
 249  * append room for the ones we need right after it.
 250  */
 251 static struct {
 252         struct usba_platform_data pdata;
 253         struct usba_ep_data ep[7];
 254 } usba_udc_data;
 255
 256 static struct platform_device at91_usba_udc_device = {
 257         .name           = "atmel_usba_udc",
 258         .id             = -1,
 259         .dev            = {
 260                                 .platform_data  = &usba_udc_data.pdata,
 261         },
 262         .resource       = usba_udc_resources,
 263         .num_resources  = ARRAY_SIZE(usba_udc_resources),
 264 };
 265
 266 void __init at91_add_device_usba(struct usba_platform_data *data)
 267 {
 268         usba_udc_data.pdata.vbus_pin = -EINVAL;
 269         usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
 270         memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
 271
 272         if (data && gpio_is_valid(data->vbus_pin)) {
 273                 at91_set_gpio_input(data->vbus_pin, 0);
 274                 at91_set_deglitch(data->vbus_pin, 1);
 275                 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
 276         }
 277
 278         /* Pullup pin is handled internally by USB device peripheral */
 279
 280         platform_device_register(&at91_usba_udc_device);
 281 }
 282 #else
 283 void __init at91_add_device_usba(struct usba_platform_data *data) {}
 284 #endif
 285
 286
 287 /* --------------------------------------------------------------------
 288  *  Ethernet
 289  * -------------------------------------------------------------------- */
 290
 291 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
 292 static u64 eth_dmamask = DMA_BIT_MASK(32);
 293 static struct macb_platform_data eth_data;
 294
 295 static struct resource eth_resources[] = {
 296         [0] = {
 297                 .start  = AT91SAM9G45_BASE_EMAC,
 298                 .end    = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
 299                 .flags  = IORESOURCE_MEM,
 300         },
 301         [1] = {
 302                 .start  = AT91SAM9G45_ID_EMAC,
 303                 .end    = AT91SAM9G45_ID_EMAC,
 304                 .flags  = IORESOURCE_IRQ,
 305         },
 306 };
 307
 308 static struct platform_device at91sam9g45_eth_device = {
 309         .name           = "macb",
 310         .id             = -1,
 311         .dev            = {
 312                                 .dma_mask               = &eth_dmamask,
 313                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 314                                 .platform_data          = &eth_data,
 315         },
 316         .resource       = eth_resources,
 317         .num_resources  = ARRAY_SIZE(eth_resources),
 318 };
 319
 320 void __init at91_add_device_eth(struct macb_platform_data *data)
 321 {
 322         if (!data)
 323                 return;
 324
 325         if (gpio_is_valid(data->phy_irq_pin)) {
 326                 at91_set_gpio_input(data->phy_irq_pin, 0);
 327                 at91_set_deglitch(data->phy_irq_pin, 1);
 328         }
 329
 330         /* Pins used for MII and RMII */
 331         at91_set_A_periph(AT91_PIN_PA17, 0);    /* ETXCK_EREFCK */
 332         at91_set_A_periph(AT91_PIN_PA15, 0);    /* ERXDV */
 333         at91_set_A_periph(AT91_PIN_PA12, 0);    /* ERX0 */
 334         at91_set_A_periph(AT91_PIN_PA13, 0);    /* ERX1 */
 335         at91_set_A_periph(AT91_PIN_PA16, 0);    /* ERXER */
 336         at91_set_A_periph(AT91_PIN_PA14, 0);    /* ETXEN */
 337         at91_set_A_periph(AT91_PIN_PA10, 0);    /* ETX0 */
 338         at91_set_A_periph(AT91_PIN_PA11, 0);    /* ETX1 */
 339         at91_set_A_periph(AT91_PIN_PA19, 0);    /* EMDIO */
 340         at91_set_A_periph(AT91_PIN_PA18, 0);    /* EMDC */
 341
 342         if (!data->is_rmii) {
 343                 at91_set_B_periph(AT91_PIN_PA29, 0);    /* ECRS */
 344                 at91_set_B_periph(AT91_PIN_PA30, 0);    /* ECOL */
 345                 at91_set_B_periph(AT91_PIN_PA8,  0);    /* ERX2 */
 346                 at91_set_B_periph(AT91_PIN_PA9,  0);    /* ERX3 */
 347                 at91_set_B_periph(AT91_PIN_PA28, 0);    /* ERXCK */
 348                 at91_set_B_periph(AT91_PIN_PA6,  0);    /* ETX2 */
 349                 at91_set_B_periph(AT91_PIN_PA7,  0);    /* ETX3 */
 350                 at91_set_B_periph(AT91_PIN_PA27, 0);    /* ETXER */
 351         }
 352
 353         eth_data = *data;
 354         platform_device_register(&at91sam9g45_eth_device);
 355 }
 356 #else
 357 void __init at91_add_device_eth(struct macb_platform_data *data) {}
 358 #endif
 359
 360
 361 /* --------------------------------------------------------------------
 362  *  MMC / SD
 363  * -------------------------------------------------------------------- */
 364
 365 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
 366 static u64 mmc_dmamask = DMA_BIT_MASK(32);
 367 static struct mci_platform_data mmc0_data, mmc1_data;
 368
 369 static struct resource mmc0_resources[] = {
 370         [0] = {
 371                 .start  = AT91SAM9G45_BASE_MCI0,
 372                 .end    = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
 373                 .flags  = IORESOURCE_MEM,
 374         },
 375         [1] = {
 376                 .start  = AT91SAM9G45_ID_MCI0,
 377                 .end    = AT91SAM9G45_ID_MCI0,
 378                 .flags  = IORESOURCE_IRQ,
 379         },
 380 };
 381
 382 static struct platform_device at91sam9g45_mmc0_device = {
 383         .name           = "atmel_mci",
 384         .id             = 0,
 385         .dev            = {
 386                                 .dma_mask               = &mmc_dmamask,
 387                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 388                                 .platform_data          = &mmc0_data,
 389         },
 390         .resource       = mmc0_resources,
 391         .num_resources  = ARRAY_SIZE(mmc0_resources),
 392 };
 393
 394 static struct resource mmc1_resources[] = {
 395         [0] = {
 396                 .start  = AT91SAM9G45_BASE_MCI1,
 397                 .end    = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
 398                 .flags  = IORESOURCE_MEM,
 399         },
 400         [1] = {
 401                 .start  = AT91SAM9G45_ID_MCI1,
 402                 .end    = AT91SAM9G45_ID_MCI1,
 403                 .flags  = IORESOURCE_IRQ,
 404         },
 405 };
 406
 407 static struct platform_device at91sam9g45_mmc1_device = {
 408         .name           = "atmel_mci",
 409         .id             = 1,
 410         .dev            = {
 411                                 .dma_mask               = &mmc_dmamask,
 412                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 413                                 .platform_data          = &mmc1_data,
 414         },
 415         .resource       = mmc1_resources,
 416         .num_resources  = ARRAY_SIZE(mmc1_resources),
 417 };
 418
 419 /* Consider only one slot : slot 0 */
 420 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 421 {
 422
 423         if (!data)
 424                 return;
 425
 426         /* Must have at least one usable slot */
 427         if (!data->slot[0].bus_width)
 428                 return;
 429
 430 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
 431         {
 432         struct at_dma_slave     *atslave;
 433         struct mci_dma_data     *alt_atslave;
 434
 435         alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
 436         atslave = &alt_atslave->sdata;
 437
 438         /* DMA slave channel configuration */
 439         atslave->dma_dev = &at_hdmac_device.dev;
 440         atslave->cfg = ATC_FIFOCFG_HALFFIFO
 441                         | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
 442         atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
 443         if (mmc_id == 0)        /* MCI0 */
 444                 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
 445                               | ATC_DST_PER(AT_DMA_ID_MCI0);
 446
 447         else                    /* MCI1 */
 448                 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
 449                               | ATC_DST_PER(AT_DMA_ID_MCI1);
 450
 451         data->dma_slave = alt_atslave;
 452         }
 453 #endif
 454
 455
 456         /* input/irq */
 457         if (gpio_is_valid(data->slot[0].detect_pin)) {
 458                 at91_set_gpio_input(data->slot[0].detect_pin, 1);
 459                 at91_set_deglitch(data->slot[0].detect_pin, 1);
 460         }
 461         if (gpio_is_valid(data->slot[0].wp_pin))
 462                 at91_set_gpio_input(data->slot[0].wp_pin, 1);
 463
 464         if (mmc_id == 0) {              /* MCI0 */
 465
 466                 /* CLK */
 467                 at91_set_A_periph(AT91_PIN_PA0, 0);
 468
 469                 /* CMD */
 470                 at91_set_A_periph(AT91_PIN_PA1, 1);
 471
 472                 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
 473                 at91_set_A_periph(AT91_PIN_PA2, 1);
 474                 if (data->slot[0].bus_width == 4) {
 475                         at91_set_A_periph(AT91_PIN_PA3, 1);
 476                         at91_set_A_periph(AT91_PIN_PA4, 1);
 477                         at91_set_A_periph(AT91_PIN_PA5, 1);
 478                         if (data->slot[0].bus_width == 8) {
 479                                 at91_set_A_periph(AT91_PIN_PA6, 1);
 480                                 at91_set_A_periph(AT91_PIN_PA7, 1);
 481                                 at91_set_A_periph(AT91_PIN_PA8, 1);
 482                                 at91_set_A_periph(AT91_PIN_PA9, 1);
 483                         }
 484                 }
 485
 486                 mmc0_data = *data;
 487                 platform_device_register(&at91sam9g45_mmc0_device);
 488
 489         } else {                        /* MCI1 */
 490
 491                 /* CLK */
 492                 at91_set_A_periph(AT91_PIN_PA31, 0);
 493
 494                 /* CMD */
 495                 at91_set_A_periph(AT91_PIN_PA22, 1);
 496
 497                 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
 498                 at91_set_A_periph(AT91_PIN_PA23, 1);
 499                 if (data->slot[0].bus_width == 4) {
 500                         at91_set_A_periph(AT91_PIN_PA24, 1);
 501                         at91_set_A_periph(AT91_PIN_PA25, 1);
 502                         at91_set_A_periph(AT91_PIN_PA26, 1);
 503                         if (data->slot[0].bus_width == 8) {
 504                                 at91_set_A_periph(AT91_PIN_PA27, 1);
 505                                 at91_set_A_periph(AT91_PIN_PA28, 1);
 506                                 at91_set_A_periph(AT91_PIN_PA29, 1);
 507                                 at91_set_A_periph(AT91_PIN_PA30, 1);
 508                         }
 509                 }
 510
 511                 mmc1_data = *data;
 512                 platform_device_register(&at91sam9g45_mmc1_device);
 513
 514         }
 515 }
 516 #else
 517 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
 518 #endif
 519
 520
 521 /* --------------------------------------------------------------------
 522  *  NAND / SmartMedia
 523  * -------------------------------------------------------------------- */
 524
 525 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
 526 static struct atmel_nand_data nand_data;
 527
 528 #define NAND_BASE       AT91_CHIPSELECT_3
 529
 530 static struct resource nand_resources[] = {
 531         [0] = {
 532                 .start  = NAND_BASE,
 533                 .end    = NAND_BASE + SZ_256M - 1,
 534                 .flags  = IORESOURCE_MEM,
 535         },
 536         [1] = {
 537                 .start  = AT91SAM9G45_BASE_ECC,
 538                 .end    = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
 539                 .flags  = IORESOURCE_MEM,
 540         }
 541 };
 542
 543 static struct platform_device at91sam9g45_nand_device = {
 544         .name           = "atmel_nand",
 545         .id             = -1,
 546         .dev            = {
 547                                 .platform_data  = &nand_data,
 548         },
 549         .resource       = nand_resources,
 550         .num_resources  = ARRAY_SIZE(nand_resources),
 551 };
 552
 553 void __init at91_add_device_nand(struct atmel_nand_data *data)
 554 {
 555         unsigned long csa;
 556
 557         if (!data)
 558                 return;
 559
 560         csa = at91_matrix_read(AT91_MATRIX_EBICSA);
 561         at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
 562
 563         /* enable pin */
 564         if (gpio_is_valid(data->enable_pin))
 565                 at91_set_gpio_output(data->enable_pin, 1);
 566
 567         /* ready/busy pin */
 568         if (gpio_is_valid(data->rdy_pin))
 569                 at91_set_gpio_input(data->rdy_pin, 1);
 570
 571         /* card detect pin */
 572         if (gpio_is_valid(data->det_pin))
 573                 at91_set_gpio_input(data->det_pin, 1);
 574
 575         nand_data = *data;
 576         platform_device_register(&at91sam9g45_nand_device);
 577 }
 578 #else
 579 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
 580 #endif
 581
 582
 583 /* --------------------------------------------------------------------
 584  *  TWI (i2c)
 585  * -------------------------------------------------------------------- */
 586
 587 /*
 588  * Prefer the GPIO code since the TWI controller isn't robust
 589  * (gets overruns and underruns under load) and can only issue
 590  * repeated STARTs in one scenario (the driver doesn't yet handle them).
 591  */
 592 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
 593 static struct i2c_gpio_platform_data pdata_i2c0 = {
 594         .sda_pin                = AT91_PIN_PA20,
 595         .sda_is_open_drain      = 1,
 596         .scl_pin                = AT91_PIN_PA21,
 597         .scl_is_open_drain      = 1,
 598         .udelay                 = 5,            /* ~100 kHz */
 599 };
 600
 601 static struct platform_device at91sam9g45_twi0_device = {
 602         .name                   = "i2c-gpio",
 603         .id                     = 0,
 604         .dev.platform_data      = &pdata_i2c0,
 605 };
 606
 607 static struct i2c_gpio_platform_data pdata_i2c1 = {
 608         .sda_pin                = AT91_PIN_PB10,
 609         .sda_is_open_drain      = 1,
 610         .scl_pin                = AT91_PIN_PB11,
 611         .scl_is_open_drain      = 1,
 612         .udelay                 = 5,            /* ~100 kHz */
 613 };
 614
 615 static struct platform_device at91sam9g45_twi1_device = {
 616         .name                   = "i2c-gpio",
 617         .id                     = 1,
 618         .dev.platform_data      = &pdata_i2c1,
 619 };
 620
 621 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
 622 {
 623         i2c_register_board_info(i2c_id, devices, nr_devices);
 624
 625         if (i2c_id == 0) {
 626                 at91_set_GPIO_periph(AT91_PIN_PA20, 1);         /* TWD (SDA) */
 627                 at91_set_multi_drive(AT91_PIN_PA20, 1);
 628
 629                 at91_set_GPIO_periph(AT91_PIN_PA21, 1);         /* TWCK (SCL) */
 630                 at91_set_multi_drive(AT91_PIN_PA21, 1);
 631
 632                 platform_device_register(&at91sam9g45_twi0_device);
 633         } else {
 634                 at91_set_GPIO_periph(AT91_PIN_PB10, 1);         /* TWD (SDA) */
 635                 at91_set_multi_drive(AT91_PIN_PB10, 1);
 636
 637                 at91_set_GPIO_periph(AT91_PIN_PB11, 1);         /* TWCK (SCL) */
 638                 at91_set_multi_drive(AT91_PIN_PB11, 1);
 639
 640                 platform_device_register(&at91sam9g45_twi1_device);
 641         }
 642 }
 643
 644 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
 645 static struct resource twi0_resources[] = {
 646         [0] = {
 647                 .start  = AT91SAM9G45_BASE_TWI0,
 648                 .end    = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
 649                 .flags  = IORESOURCE_MEM,
 650         },
 651         [1] = {
 652                 .start  = AT91SAM9G45_ID_TWI0,
 653                 .end    = AT91SAM9G45_ID_TWI0,
 654                 .flags  = IORESOURCE_IRQ,
 655         },
 656 };
 657
 658 static struct platform_device at91sam9g45_twi0_device = {
 659         .name           = "at91_i2c",
 660         .id             = 0,
 661         .resource       = twi0_resources,
 662         .num_resources  = ARRAY_SIZE(twi0_resources),
 663 };
 664
 665 static struct resource twi1_resources[] = {
 666         [0] = {
 667                 .start  = AT91SAM9G45_BASE_TWI1,
 668                 .end    = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
 669                 .flags  = IORESOURCE_MEM,
 670         },
 671         [1] = {
 672                 .start  = AT91SAM9G45_ID_TWI1,
 673                 .end    = AT91SAM9G45_ID_TWI1,
 674                 .flags  = IORESOURCE_IRQ,
 675         },
 676 };
 677
 678 static struct platform_device at91sam9g45_twi1_device = {
 679         .name           = "at91_i2c",
 680         .id             = 1,
 681         .resource       = twi1_resources,
 682         .num_resources  = ARRAY_SIZE(twi1_resources),
 683 };
 684
 685 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
 686 {
 687         i2c_register_board_info(i2c_id, devices, nr_devices);
 688
 689         /* pins used for TWI interface */
 690         if (i2c_id == 0) {
 691                 at91_set_A_periph(AT91_PIN_PA20, 0);            /* TWD */
 692                 at91_set_multi_drive(AT91_PIN_PA20, 1);
 693
 694                 at91_set_A_periph(AT91_PIN_PA21, 0);            /* TWCK */
 695                 at91_set_multi_drive(AT91_PIN_PA21, 1);
 696
 697                 platform_device_register(&at91sam9g45_twi0_device);
 698         } else {
 699                 at91_set_A_periph(AT91_PIN_PB10, 0);            /* TWD */
 700                 at91_set_multi_drive(AT91_PIN_PB10, 1);
 701
 702                 at91_set_A_periph(AT91_PIN_PB11, 0);            /* TWCK */
 703                 at91_set_multi_drive(AT91_PIN_PB11, 1);
 704
 705                 platform_device_register(&at91sam9g45_twi1_device);
 706         }
 707 }
 708 #else
 709 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
 710 #endif
 711
 712
 713 /* --------------------------------------------------------------------
 714  *  SPI
 715  * -------------------------------------------------------------------- */
 716
 717 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 718 static u64 spi_dmamask = DMA_BIT_MASK(32);
 719
 720 static struct resource spi0_resources[] = {
 721         [0] = {
 722                 .start  = AT91SAM9G45_BASE_SPI0,
 723                 .end    = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
 724                 .flags  = IORESOURCE_MEM,
 725         },
 726         [1] = {
 727                 .start  = AT91SAM9G45_ID_SPI0,
 728                 .end    = AT91SAM9G45_ID_SPI0,
 729                 .flags  = IORESOURCE_IRQ,
 730         },
 731 };
 732
 733 static struct platform_device at91sam9g45_spi0_device = {
 734         .name           = "atmel_spi",
 735         .id             = 0,
 736         .dev            = {
 737                                 .dma_mask               = &spi_dmamask,
 738                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 739         },
 740         .resource       = spi0_resources,
 741         .num_resources  = ARRAY_SIZE(spi0_resources),
 742 };
 743
 744 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
 745
 746 static struct resource spi1_resources[] = {
 747         [0] = {
 748                 .start  = AT91SAM9G45_BASE_SPI1,
 749                 .end    = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
 750                 .flags  = IORESOURCE_MEM,
 751         },
 752         [1] = {
 753                 .start  = AT91SAM9G45_ID_SPI1,
 754                 .end    = AT91SAM9G45_ID_SPI1,
 755                 .flags  = IORESOURCE_IRQ,
 756         },
 757 };
 758
 759 static struct platform_device at91sam9g45_spi1_device = {
 760         .name           = "atmel_spi",
 761         .id             = 1,
 762         .dev            = {
 763                                 .dma_mask               = &spi_dmamask,
 764                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 765         },
 766         .resource       = spi1_resources,
 767         .num_resources  = ARRAY_SIZE(spi1_resources),
 768 };
 769
 770 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
 771
 772 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 773 {
 774         int i;
 775         unsigned long cs_pin;
 776         short enable_spi0 = 0;
 777         short enable_spi1 = 0;
 778
 779         /* Choose SPI chip-selects */
 780         for (i = 0; i < nr_devices; i++) {
 781                 if (devices[i].controller_data)
 782                         cs_pin = (unsigned long) devices[i].controller_data;
 783                 else if (devices[i].bus_num == 0)
 784                         cs_pin = spi0_standard_cs[devices[i].chip_select];
 785                 else
 786                         cs_pin = spi1_standard_cs[devices[i].chip_select];
 787
 788                 if (devices[i].bus_num == 0)
 789                         enable_spi0 = 1;
 790                 else
 791                         enable_spi1 = 1;
 792
 793                 /* enable chip-select pin */
 794                 at91_set_gpio_output(cs_pin, 1);
 795
 796                 /* pass chip-select pin to driver */
 797                 devices[i].controller_data = (void *) cs_pin;
 798         }
 799
 800         spi_register_board_info(devices, nr_devices);
 801
 802         /* Configure SPI bus(es) */
 803         if (enable_spi0) {
 804                 at91_set_A_periph(AT91_PIN_PB0, 0);     /* SPI0_MISO */
 805                 at91_set_A_periph(AT91_PIN_PB1, 0);     /* SPI0_MOSI */
 806                 at91_set_A_periph(AT91_PIN_PB2, 0);     /* SPI0_SPCK */
 807
 808                 platform_device_register(&at91sam9g45_spi0_device);
 809         }
 810         if (enable_spi1) {
 811                 at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_MISO */
 812                 at91_set_A_periph(AT91_PIN_PB15, 0);    /* SPI1_MOSI */
 813                 at91_set_A_periph(AT91_PIN_PB16, 0);    /* SPI1_SPCK */
 814
 815                 platform_device_register(&at91sam9g45_spi1_device);
 816         }
 817 }
 818 #else
 819 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
 820 #endif
 821
 822
 823 /* --------------------------------------------------------------------
 824  *  AC97
 825  * -------------------------------------------------------------------- */
 826
 827 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
 828 static u64 ac97_dmamask = DMA_BIT_MASK(32);
 829 static struct ac97c_platform_data ac97_data;
 830
 831 static struct resource ac97_resources[] = {
 832         [0] = {
 833                 .start  = AT91SAM9G45_BASE_AC97C,
 834                 .end    = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
 835                 .flags  = IORESOURCE_MEM,
 836         },
 837         [1] = {
 838                 .start  = AT91SAM9G45_ID_AC97C,
 839                 .end    = AT91SAM9G45_ID_AC97C,
 840                 .flags  = IORESOURCE_IRQ,
 841         },
 842 };
 843
 844 static struct platform_device at91sam9g45_ac97_device = {
 845         .name           = "atmel_ac97c",
 846         .id             = 0,
 847         .dev            = {
 848                                 .dma_mask               = &ac97_dmamask,
 849                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 850                                 .platform_data          = &ac97_data,
 851         },
 852         .resource       = ac97_resources,
 853         .num_resources  = ARRAY_SIZE(ac97_resources),
 854 };
 855
 856 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
 857 {
 858         if (!data)
 859                 return;
 860
 861         at91_set_A_periph(AT91_PIN_PD8, 0);     /* AC97FS */
 862         at91_set_A_periph(AT91_PIN_PD9, 0);     /* AC97CK */
 863         at91_set_A_periph(AT91_PIN_PD7, 0);     /* AC97TX */
 864         at91_set_A_periph(AT91_PIN_PD6, 0);     /* AC97RX */
 865
 866         /* reset */
 867         if (gpio_is_valid(data->reset_pin))
 868                 at91_set_gpio_output(data->reset_pin, 0);
 869
 870         ac97_data = *data;
 871         platform_device_register(&at91sam9g45_ac97_device);
 872 }
 873 #else
 874 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
 875 #endif
 876
 877 /* --------------------------------------------------------------------
 878  *  Image Sensor Interface
 879  * -------------------------------------------------------------------- */
 880 #if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
 881 static u64 isi_dmamask = DMA_BIT_MASK(32);
 882 static struct isi_platform_data isi_data;
 883
 884 struct resource isi_resources[] = {
 885         [0] = {
 886                 .start  = AT91SAM9G45_BASE_ISI,
 887                 .end    = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
 888                 .flags  = IORESOURCE_MEM,
 889         },
 890         [1] = {
 891                 .start  = AT91SAM9G45_ID_ISI,
 892                 .end    = AT91SAM9G45_ID_ISI,
 893                 .flags  = IORESOURCE_IRQ,
 894         },
 895 };
 896
 897 static struct platform_device at91sam9g45_isi_device = {
 898         .name           = "atmel_isi",
 899         .id             = 0,
 900         .dev            = {
 901                         .dma_mask               = &isi_dmamask,
 902                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 903                         .platform_data          = &isi_data,
 904         },
 905         .resource       = isi_resources,
 906         .num_resources  = ARRAY_SIZE(isi_resources),
 907 };
 908
 909 static struct clk_lookup isi_mck_lookups[] = {
 910         CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
 911 };
 912
 913 void __init at91_add_device_isi(struct isi_platform_data *data,
 914                 bool use_pck_as_mck)
 915 {
 916         struct clk *pck;
 917         struct clk *parent;
 918
 919         if (!data)
 920                 return;
 921         isi_data = *data;
 922
 923         at91_set_A_periph(AT91_PIN_PB20, 0);    /* ISI_D0 */
 924         at91_set_A_periph(AT91_PIN_PB21, 0);    /* ISI_D1 */
 925         at91_set_A_periph(AT91_PIN_PB22, 0);    /* ISI_D2 */
 926         at91_set_A_periph(AT91_PIN_PB23, 0);    /* ISI_D3 */
 927         at91_set_A_periph(AT91_PIN_PB24, 0);    /* ISI_D4 */
 928         at91_set_A_periph(AT91_PIN_PB25, 0);    /* ISI_D5 */
 929         at91_set_A_periph(AT91_PIN_PB26, 0);    /* ISI_D6 */
 930         at91_set_A_periph(AT91_PIN_PB27, 0);    /* ISI_D7 */
 931         at91_set_A_periph(AT91_PIN_PB28, 0);    /* ISI_PCK */
 932         at91_set_A_periph(AT91_PIN_PB30, 0);    /* ISI_HSYNC */
 933         at91_set_A_periph(AT91_PIN_PB29, 0);    /* ISI_VSYNC */
 934         at91_set_B_periph(AT91_PIN_PB8, 0);     /* ISI_PD8 */
 935         at91_set_B_periph(AT91_PIN_PB9, 0);     /* ISI_PD9 */
 936         at91_set_B_periph(AT91_PIN_PB10, 0);    /* ISI_PD10 */
 937         at91_set_B_periph(AT91_PIN_PB11, 0);    /* ISI_PD11 */
 938
 939         platform_device_register(&at91sam9g45_isi_device);
 940
 941         if (use_pck_as_mck) {
 942                 at91_set_B_periph(AT91_PIN_PB31, 0);    /* ISI_MCK (PCK1) */
 943
 944                 pck = clk_get(NULL, "pck1");
 945                 parent = clk_get(NULL, "plla");
 946
 947                 BUG_ON(IS_ERR(pck) || IS_ERR(parent));
 948
 949                 if (clk_set_parent(pck, parent)) {
 950                         pr_err("Failed to set PCK's parent\n");
 951                 } else {
 952                         /* Register PCK as ISI_MCK */
 953                         isi_mck_lookups[0].clk = pck;
 954                         clkdev_add_table(isi_mck_lookups,
 955                                         ARRAY_SIZE(isi_mck_lookups));
 956                 }
 957
 958                 clk_put(pck);
 959                 clk_put(parent);
 960         }
 961 }
 962 #else
 963 void __init at91_add_device_isi(struct isi_platform_data *data,
 964                 bool use_pck_as_mck) {}
 965 #endif
 966
 967
 968 /* --------------------------------------------------------------------
 969  *  LCD Controller
 970  * -------------------------------------------------------------------- */
 971
 972 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
 973 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
 974 static struct atmel_lcdfb_info lcdc_data;
 975
 976 static struct resource lcdc_resources[] = {
 977         [0] = {
 978                 .start  = AT91SAM9G45_LCDC_BASE,
 979                 .end    = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
 980                 .flags  = IORESOURCE_MEM,
 981         },
 982         [1] = {
 983                 .start  = AT91SAM9G45_ID_LCDC,
 984                 .end    = AT91SAM9G45_ID_LCDC,
 985                 .flags  = IORESOURCE_IRQ,
 986         },
 987 };
 988
 989 static struct platform_device at91_lcdc_device = {
 990         .name           = "atmel_lcdfb",
 991         .id             = 0,
 992         .dev            = {
 993                                 .dma_mask               = &lcdc_dmamask,
 994                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 995                                 .platform_data          = &lcdc_data,
 996         },
 997         .resource       = lcdc_resources,
 998         .num_resources  = ARRAY_SIZE(lcdc_resources),
 999 };
1000
1001 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
1002 {
1003         if (!data)
1004                 return;
1005
1006         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
1007
1008         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
1009         at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
1010         at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
1011         at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
1012         at91_set_A_periph(AT91_PIN_PE6, 0);     /* LCDDEN */
1013         at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
1014         at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
1015         at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
1016         at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
1017         at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
1018         at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
1019         at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
1020         at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
1021         at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
1022         at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
1023         at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
1024         at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
1025         at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
1026         at91_set_A_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
1027         at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
1028         at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
1029         at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
1030         at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
1031         at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
1032         at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
1033         at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
1034         at91_set_A_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
1035         at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
1036         at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
1037
1038         lcdc_data = *data;
1039         platform_device_register(&at91_lcdc_device);
1040 }
1041 #else
1042 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
1043 #endif
1044
1045
1046 /* --------------------------------------------------------------------
1047  *  Timer/Counter block
1048  * -------------------------------------------------------------------- */
1049
1050 #ifdef CONFIG_ATMEL_TCLIB
1051 static struct resource tcb0_resources[] = {
1052         [0] = {
1053                 .start  = AT91SAM9G45_BASE_TCB0,
1054                 .end    = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
1055                 .flags  = IORESOURCE_MEM,
1056         },
1057         [1] = {
1058                 .start  = AT91SAM9G45_ID_TCB,
1059                 .end    = AT91SAM9G45_ID_TCB,
1060                 .flags  = IORESOURCE_IRQ,
1061         },
1062 };
1063
1064 static struct platform_device at91sam9g45_tcb0_device = {
1065         .name           = "atmel_tcb",
1066         .id             = 0,
1067         .resource       = tcb0_resources,
1068         .num_resources  = ARRAY_SIZE(tcb0_resources),
1069 };
1070
1071 /* TCB1 begins with TC3 */
1072 static struct resource tcb1_resources[] = {
1073         [0] = {
1074                 .start  = AT91SAM9G45_BASE_TCB1,
1075                 .end    = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
1076                 .flags  = IORESOURCE_MEM,
1077         },
1078         [1] = {
1079                 .start  = AT91SAM9G45_ID_TCB,
1080                 .end    = AT91SAM9G45_ID_TCB,
1081                 .flags  = IORESOURCE_IRQ,
1082         },
1083 };
1084
1085 static struct platform_device at91sam9g45_tcb1_device = {
1086         .name           = "atmel_tcb",
1087         .id             = 1,
1088         .resource       = tcb1_resources,
1089         .num_resources  = ARRAY_SIZE(tcb1_resources),
1090 };
1091
1092 #if defined(CONFIG_OF)
1093 static struct of_device_id tcb_ids[] = {
1094         { .compatible = "atmel,at91rm9200-tcb" },
1095         { /*sentinel*/ }
1096 };
1097 #endif
1098
1099 static void __init at91_add_device_tc(void)
1100 {
1101 #if defined(CONFIG_OF)
1102         struct device_node *np;
1103
1104         np = of_find_matching_node(NULL, tcb_ids);
1105         if (np) {
1106                 of_node_put(np);
1107                 return;
1108         }
1109 #endif
1110
1111         platform_device_register(&at91sam9g45_tcb0_device);
1112         platform_device_register(&at91sam9g45_tcb1_device);
1113 }
1114 #else
1115 static void __init at91_add_device_tc(void) { }
1116 #endif
1117
1118
1119 /* --------------------------------------------------------------------
1120  *  RTC
1121  * -------------------------------------------------------------------- */
1122
1123 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1124 static struct resource rtc_resources[] = {
1125         [0] = {
1126                 .start  = AT91SAM9G45_BASE_RTC,
1127                 .end    = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
1128                 .flags  = IORESOURCE_MEM,
1129         },
1130         [1] = {
1131                 .start  = AT91_ID_SYS,
1132                 .end    = AT91_ID_SYS,
1133                 .flags  = IORESOURCE_IRQ,
1134         },
1135 };
1136
1137 static struct platform_device at91sam9g45_rtc_device = {
1138         .name           = "at91_rtc",
1139         .id             = -1,
1140         .resource       = rtc_resources,
1141         .num_resources  = ARRAY_SIZE(rtc_resources),
1142 };
1143
1144 static void __init at91_add_device_rtc(void)
1145 {
1146         platform_device_register(&at91sam9g45_rtc_device);
1147 }
1148 #else
1149 static void __init at91_add_device_rtc(void) {}
1150 #endif
1151
1152
1153 /* --------------------------------------------------------------------
1154  *  Touchscreen
1155  * -------------------------------------------------------------------- */
1156
1157 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1158 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1159 static struct at91_tsadcc_data tsadcc_data;
1160
1161 static struct resource tsadcc_resources[] = {
1162         [0] = {
1163                 .start  = AT91SAM9G45_BASE_TSC,
1164                 .end    = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1165                 .flags  = IORESOURCE_MEM,
1166         },
1167         [1] = {
1168                 .start  = AT91SAM9G45_ID_TSC,
1169                 .end    = AT91SAM9G45_ID_TSC,
1170                 .flags  = IORESOURCE_IRQ,
1171         }
1172 };
1173
1174 static struct platform_device at91sam9g45_tsadcc_device = {
1175         .name           = "atmel_tsadcc",
1176         .id             = -1,
1177         .dev            = {
1178                                 .dma_mask               = &tsadcc_dmamask,
1179                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1180                                 .platform_data          = &tsadcc_data,
1181         },
1182         .resource       = tsadcc_resources,
1183         .num_resources  = ARRAY_SIZE(tsadcc_resources),
1184 };
1185
1186 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
1187 {
1188         if (!data)
1189                 return;
1190
1191         at91_set_gpio_input(AT91_PIN_PD20, 0);  /* AD0_XR */
1192         at91_set_gpio_input(AT91_PIN_PD21, 0);  /* AD1_XL */
1193         at91_set_gpio_input(AT91_PIN_PD22, 0);  /* AD2_YT */
1194         at91_set_gpio_input(AT91_PIN_PD23, 0);  /* AD3_TB */
1195
1196         tsadcc_data = *data;
1197         platform_device_register(&at91sam9g45_tsadcc_device);
1198 }
1199 #else
1200 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
1201 #endif
1202
1203
1204 /* --------------------------------------------------------------------
1205  *  RTT
1206  * -------------------------------------------------------------------- */
1207
1208 static struct resource rtt_resources[] = {
1209         {
1210                 .start  = AT91SAM9G45_BASE_RTT,
1211                 .end    = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
1212                 .flags  = IORESOURCE_MEM,
1213         }, {
1214                 .flags  = IORESOURCE_MEM,
1215         }
1216 };
1217
1218 static struct platform_device at91sam9g45_rtt_device = {
1219         .name           = "at91_rtt",
1220         .id             = 0,
1221         .resource       = rtt_resources,
1222 };
1223
1224 #if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1225 static void __init at91_add_device_rtt_rtc(void)
1226 {
1227         at91sam9g45_rtt_device.name = "rtc-at91sam9";
1228         /*
1229          * The second resource is needed:
1230          * GPBR will serve as the storage for RTC time offset
1231          */
1232         at91sam9g45_rtt_device.num_resources = 2;
1233         rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
1234                                  4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1235         rtt_resources[1].end = rtt_resources[1].start + 3;
1236 }
1237 #else
1238 static void __init at91_add_device_rtt_rtc(void)
1239 {
1240         /* Only one resource is needed: RTT not used as RTC */
1241         at91sam9g45_rtt_device.num_resources = 1;
1242 }
1243 #endif
1244
1245 static void __init at91_add_device_rtt(void)
1246 {
1247         at91_add_device_rtt_rtc();
1248         platform_device_register(&at91sam9g45_rtt_device);
1249 }
1250
1251
1252 /* --------------------------------------------------------------------
1253  *  TRNG
1254  * -------------------------------------------------------------------- */
1255
1256 #if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
1257 static struct resource trng_resources[] = {
1258         {
1259                 .start  = AT91SAM9G45_BASE_TRNG,
1260                 .end    = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
1261                 .flags  = IORESOURCE_MEM,
1262         },
1263 };
1264
1265 static struct platform_device at91sam9g45_trng_device = {
1266         .name           = "atmel-trng",
1267         .id             = -1,
1268         .resource       = trng_resources,
1269         .num_resources  = ARRAY_SIZE(trng_resources),
1270 };
1271
1272 static void __init at91_add_device_trng(void)
1273 {
1274         platform_device_register(&at91sam9g45_trng_device);
1275 }
1276 #else
1277 static void __init at91_add_device_trng(void) {}
1278 #endif
1279
1280 /* --------------------------------------------------------------------
1281  *  Watchdog
1282  * -------------------------------------------------------------------- */
1283
1284 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1285 static struct resource wdt_resources[] = {
1286         {
1287                 .start  = AT91SAM9G45_BASE_WDT,
1288                 .end    = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
1289                 .flags  = IORESOURCE_MEM,
1290         }
1291 };
1292
1293 static struct platform_device at91sam9g45_wdt_device = {
1294         .name           = "at91_wdt",
1295         .id             = -1,
1296         .resource       = wdt_resources,
1297         .num_resources  = ARRAY_SIZE(wdt_resources),
1298 };
1299
1300 static void __init at91_add_device_watchdog(void)
1301 {
1302         platform_device_register(&at91sam9g45_wdt_device);
1303 }
1304 #else
1305 static void __init at91_add_device_watchdog(void) {}
1306 #endif
1307
1308
1309 /* --------------------------------------------------------------------
1310  *  PWM
1311  * --------------------------------------------------------------------*/
1312
1313 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
1314 static u32 pwm_mask;
1315
1316 static struct resource pwm_resources[] = {
1317         [0] = {
1318                 .start  = AT91SAM9G45_BASE_PWMC,
1319                 .end    = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1320                 .flags  = IORESOURCE_MEM,
1321         },
1322         [1] = {
1323                 .start  = AT91SAM9G45_ID_PWMC,
1324                 .end    = AT91SAM9G45_ID_PWMC,
1325                 .flags  = IORESOURCE_IRQ,
1326         },
1327 };
1328
1329 static struct platform_device at91sam9g45_pwm0_device = {
1330         .name   = "atmel_pwm",
1331         .id     = -1,
1332         .dev    = {
1333                 .platform_data          = &pwm_mask,
1334         },
1335         .resource       = pwm_resources,
1336         .num_resources  = ARRAY_SIZE(pwm_resources),
1337 };
1338
1339 void __init at91_add_device_pwm(u32 mask)
1340 {
1341         if (mask & (1 << AT91_PWM0))
1342                 at91_set_B_periph(AT91_PIN_PD24, 1);    /* enable PWM0 */
1343
1344         if (mask & (1 << AT91_PWM1))
1345                 at91_set_B_periph(AT91_PIN_PD31, 1);    /* enable PWM1 */
1346
1347         if (mask & (1 << AT91_PWM2))
1348                 at91_set_B_periph(AT91_PIN_PD26, 1);    /* enable PWM2 */
1349
1350         if (mask & (1 << AT91_PWM3))
1351                 at91_set_B_periph(AT91_PIN_PD0, 1);     /* enable PWM3 */
1352
1353         pwm_mask = mask;
1354
1355         platform_device_register(&at91sam9g45_pwm0_device);
1356 }
1357 #else
1358 void __init at91_add_device_pwm(u32 mask) {}
1359 #endif
1360
1361
1362 /* --------------------------------------------------------------------
1363  *  SSC -- Synchronous Serial Controller
1364  * -------------------------------------------------------------------- */
1365
1366 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1367 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1368
1369 static struct resource ssc0_resources[] = {
1370         [0] = {
1371                 .start  = AT91SAM9G45_BASE_SSC0,
1372                 .end    = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1373                 .flags  = IORESOURCE_MEM,
1374         },
1375         [1] = {
1376                 .start  = AT91SAM9G45_ID_SSC0,
1377                 .end    = AT91SAM9G45_ID_SSC0,
1378                 .flags  = IORESOURCE_IRQ,
1379         },
1380 };
1381
1382 static struct platform_device at91sam9g45_ssc0_device = {
1383         .name   = "ssc",
1384         .id     = 0,
1385         .dev    = {
1386                 .dma_mask               = &ssc0_dmamask,
1387                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1388         },
1389         .resource       = ssc0_resources,
1390         .num_resources  = ARRAY_SIZE(ssc0_resources),
1391 };
1392
1393 static inline void configure_ssc0_pins(unsigned pins)
1394 {
1395         if (pins & ATMEL_SSC_TF)
1396                 at91_set_A_periph(AT91_PIN_PD1, 1);
1397         if (pins & ATMEL_SSC_TK)
1398                 at91_set_A_periph(AT91_PIN_PD0, 1);
1399         if (pins & ATMEL_SSC_TD)
1400                 at91_set_A_periph(AT91_PIN_PD2, 1);
1401         if (pins & ATMEL_SSC_RD)
1402                 at91_set_A_periph(AT91_PIN_PD3, 1);
1403         if (pins & ATMEL_SSC_RK)
1404                 at91_set_A_periph(AT91_PIN_PD4, 1);
1405         if (pins & ATMEL_SSC_RF)
1406                 at91_set_A_periph(AT91_PIN_PD5, 1);
1407 }
1408
1409 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1410
1411 static struct resource ssc1_resources[] = {
1412         [0] = {
1413                 .start  = AT91SAM9G45_BASE_SSC1,
1414                 .end    = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1415                 .flags  = IORESOURCE_MEM,
1416         },
1417         [1] = {
1418                 .start  = AT91SAM9G45_ID_SSC1,
1419                 .end    = AT91SAM9G45_ID_SSC1,
1420                 .flags  = IORESOURCE_IRQ,
1421         },
1422 };
1423
1424 static struct platform_device at91sam9g45_ssc1_device = {
1425         .name   = "ssc",
1426         .id     = 1,
1427         .dev    = {
1428                 .dma_mask               = &ssc1_dmamask,
1429                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1430         },
1431         .resource       = ssc1_resources,
1432         .num_resources  = ARRAY_SIZE(ssc1_resources),
1433 };
1434
1435 static inline void configure_ssc1_pins(unsigned pins)
1436 {
1437         if (pins & ATMEL_SSC_TF)
1438                 at91_set_A_periph(AT91_PIN_PD14, 1);
1439         if (pins & ATMEL_SSC_TK)
1440                 at91_set_A_periph(AT91_PIN_PD12, 1);
1441         if (pins & ATMEL_SSC_TD)
1442                 at91_set_A_periph(AT91_PIN_PD10, 1);
1443         if (pins & ATMEL_SSC_RD)
1444                 at91_set_A_periph(AT91_PIN_PD11, 1);
1445         if (pins & ATMEL_SSC_RK)
1446                 at91_set_A_periph(AT91_PIN_PD13, 1);
1447         if (pins & ATMEL_SSC_RF)
1448                 at91_set_A_periph(AT91_PIN_PD15, 1);
1449 }
1450
1451 /*
1452  * SSC controllers are accessed through library code, instead of any
1453  * kind of all-singing/all-dancing driver.  For example one could be
1454  * used by a particular I2S audio codec's driver, while another one
1455  * on the same system might be used by a custom data capture driver.
1456  */
1457 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1458 {
1459         struct platform_device *pdev;
1460
1461         /*
1462          * NOTE: caller is responsible for passing information matching
1463          * "pins" to whatever will be using each particular controller.
1464          */
1465         switch (id) {
1466         case AT91SAM9G45_ID_SSC0:
1467                 pdev = &at91sam9g45_ssc0_device;
1468                 configure_ssc0_pins(pins);
1469                 break;
1470         case AT91SAM9G45_ID_SSC1:
1471                 pdev = &at91sam9g45_ssc1_device;
1472                 configure_ssc1_pins(pins);
1473                 break;
1474         default:
1475                 return;
1476         }
1477
1478         platform_device_register(pdev);
1479 }
1480
1481 #else
1482 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1483 #endif
1484
1485
1486 /* --------------------------------------------------------------------
1487  *  UART
1488  * -------------------------------------------------------------------- */
1489
1490 #if defined(CONFIG_SERIAL_ATMEL)
1491 static struct resource dbgu_resources[] = {
1492         [0] = {
1493                 .start  = AT91SAM9G45_BASE_DBGU,
1494                 .end    = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
1495                 .flags  = IORESOURCE_MEM,
1496         },
1497         [1] = {
1498                 .start  = AT91_ID_SYS,
1499                 .end    = AT91_ID_SYS,
1500                 .flags  = IORESOURCE_IRQ,
1501         },
1502 };
1503
1504 static struct atmel_uart_data dbgu_data = {
1505         .use_dma_tx     = 0,
1506         .use_dma_rx     = 0,
1507 };
1508
1509 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1510
1511 static struct platform_device at91sam9g45_dbgu_device = {
1512         .name           = "atmel_usart",
1513         .id             = 0,
1514         .dev            = {
1515                                 .dma_mask               = &dbgu_dmamask,
1516                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1517                                 .platform_data          = &dbgu_data,
1518         },
1519         .resource       = dbgu_resources,
1520         .num_resources  = ARRAY_SIZE(dbgu_resources),
1521 };
1522
1523 static inline void configure_dbgu_pins(void)
1524 {
1525         at91_set_A_periph(AT91_PIN_PB12, 0);            /* DRXD */
1526         at91_set_A_periph(AT91_PIN_PB13, 1);            /* DTXD */
1527 }
1528
1529 static struct resource uart0_resources[] = {
1530         [0] = {
1531                 .start  = AT91SAM9G45_BASE_US0,
1532                 .end    = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1533                 .flags  = IORESOURCE_MEM,
1534         },
1535         [1] = {
1536                 .start  = AT91SAM9G45_ID_US0,
1537                 .end    = AT91SAM9G45_ID_US0,
1538                 .flags  = IORESOURCE_IRQ,
1539         },
1540 };
1541
1542 static struct atmel_uart_data uart0_data = {
1543         .use_dma_tx     = 1,
1544         .use_dma_rx     = 1,
1545 };
1546
1547 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1548
1549 static struct platform_device at91sam9g45_uart0_device = {
1550         .name           = "atmel_usart",
1551         .id             = 1,
1552         .dev            = {
1553                                 .dma_mask               = &uart0_dmamask,
1554                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1555                                 .platform_data          = &uart0_data,
1556         },
1557         .resource       = uart0_resources,
1558         .num_resources  = ARRAY_SIZE(uart0_resources),
1559 };
1560
1561 static inline void configure_usart0_pins(unsigned pins)
1562 {
1563         at91_set_A_periph(AT91_PIN_PB19, 1);            /* TXD0 */
1564         at91_set_A_periph(AT91_PIN_PB18, 0);            /* RXD0 */
1565
1566         if (pins & ATMEL_UART_RTS)
1567                 at91_set_B_periph(AT91_PIN_PB17, 0);    /* RTS0 */
1568         if (pins & ATMEL_UART_CTS)
1569                 at91_set_B_periph(AT91_PIN_PB15, 0);    /* CTS0 */
1570 }
1571
1572 static struct resource uart1_resources[] = {
1573         [0] = {
1574                 .start  = AT91SAM9G45_BASE_US1,
1575                 .end    = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1576                 .flags  = IORESOURCE_MEM,
1577         },
1578         [1] = {
1579                 .start  = AT91SAM9G45_ID_US1,
1580                 .end    = AT91SAM9G45_ID_US1,
1581                 .flags  = IORESOURCE_IRQ,
1582         },
1583 };
1584
1585 static struct atmel_uart_data uart1_data = {
1586         .use_dma_tx     = 1,
1587         .use_dma_rx     = 1,
1588 };
1589
1590 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1591
1592 static struct platform_device at91sam9g45_uart1_device = {
1593         .name           = "atmel_usart",
1594         .id             = 2,
1595         .dev            = {
1596                                 .dma_mask               = &uart1_dmamask,
1597                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1598                                 .platform_data          = &uart1_data,
1599         },
1600         .resource       = uart1_resources,
1601         .num_resources  = ARRAY_SIZE(uart1_resources),
1602 };
1603
1604 static inline void configure_usart1_pins(unsigned pins)
1605 {
1606         at91_set_A_periph(AT91_PIN_PB4, 1);             /* TXD1 */
1607         at91_set_A_periph(AT91_PIN_PB5, 0);             /* RXD1 */
1608
1609         if (pins & ATMEL_UART_RTS)
1610                 at91_set_A_periph(AT91_PIN_PD16, 0);    /* RTS1 */
1611         if (pins & ATMEL_UART_CTS)
1612                 at91_set_A_periph(AT91_PIN_PD17, 0);    /* CTS1 */
1613 }
1614
1615 static struct resource uart2_resources[] = {
1616         [0] = {
1617                 .start  = AT91SAM9G45_BASE_US2,
1618                 .end    = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1619                 .flags  = IORESOURCE_MEM,
1620         },
1621         [1] = {
1622                 .start  = AT91SAM9G45_ID_US2,
1623                 .end    = AT91SAM9G45_ID_US2,
1624                 .flags  = IORESOURCE_IRQ,
1625         },
1626 };
1627
1628 static struct atmel_uart_data uart2_data = {
1629         .use_dma_tx     = 1,
1630         .use_dma_rx     = 1,
1631 };
1632
1633 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1634
1635 static struct platform_device at91sam9g45_uart2_device = {
1636         .name           = "atmel_usart",
1637         .id             = 3,
1638         .dev            = {
1639                                 .dma_mask               = &uart2_dmamask,
1640                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1641                                 .platform_data          = &uart2_data,
1642         },
1643         .resource       = uart2_resources,
1644         .num_resources  = ARRAY_SIZE(uart2_resources),
1645 };
1646
1647 static inline void configure_usart2_pins(unsigned pins)
1648 {
1649         at91_set_A_periph(AT91_PIN_PB6, 1);             /* TXD2 */
1650         at91_set_A_periph(AT91_PIN_PB7, 0);             /* RXD2 */
1651
1652         if (pins & ATMEL_UART_RTS)
1653                 at91_set_B_periph(AT91_PIN_PC9, 0);     /* RTS2 */
1654         if (pins & ATMEL_UART_CTS)
1655                 at91_set_B_periph(AT91_PIN_PC11, 0);    /* CTS2 */
1656 }
1657
1658 static struct resource uart3_resources[] = {
1659         [0] = {
1660                 .start  = AT91SAM9G45_BASE_US3,
1661                 .end    = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1662                 .flags  = IORESOURCE_MEM,
1663         },
1664         [1] = {
1665                 .start  = AT91SAM9G45_ID_US3,
1666                 .end    = AT91SAM9G45_ID_US3,
1667                 .flags  = IORESOURCE_IRQ,
1668         },
1669 };
1670
1671 static struct atmel_uart_data uart3_data = {
1672         .use_dma_tx     = 1,
1673         .use_dma_rx     = 1,
1674 };
1675
1676 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1677
1678 static struct platform_device at91sam9g45_uart3_device = {
1679         .name           = "atmel_usart",
1680         .id             = 4,
1681         .dev            = {
1682                                 .dma_mask               = &uart3_dmamask,
1683                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1684                                 .platform_data          = &uart3_data,
1685         },
1686         .resource       = uart3_resources,
1687         .num_resources  = ARRAY_SIZE(uart3_resources),
1688 };
1689
1690 static inline void configure_usart3_pins(unsigned pins)
1691 {
1692         at91_set_A_periph(AT91_PIN_PB8, 1);             /* TXD3 */
1693         at91_set_A_periph(AT91_PIN_PB9, 0);             /* RXD3 */
1694
1695         if (pins & ATMEL_UART_RTS)
1696                 at91_set_B_periph(AT91_PIN_PA23, 0);    /* RTS3 */
1697         if (pins & ATMEL_UART_CTS)
1698                 at91_set_B_periph(AT91_PIN_PA24, 0);    /* CTS3 */
1699 }
1700
1701 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
1702
1703 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1704 {
1705         struct platform_device *pdev;
1706         struct atmel_uart_data *pdata;
1707
1708         switch (id) {
1709                 case 0:         /* DBGU */
1710                         pdev = &at91sam9g45_dbgu_device;
1711                         configure_dbgu_pins();
1712                         break;
1713                 case AT91SAM9G45_ID_US0:
1714                         pdev = &at91sam9g45_uart0_device;
1715                         configure_usart0_pins(pins);
1716                         break;
1717                 case AT91SAM9G45_ID_US1:
1718                         pdev = &at91sam9g45_uart1_device;
1719                         configure_usart1_pins(pins);
1720                         break;
1721                 case AT91SAM9G45_ID_US2:
1722                         pdev = &at91sam9g45_uart2_device;
1723                         configure_usart2_pins(pins);
1724                         break;
1725                 case AT91SAM9G45_ID_US3:
1726                         pdev = &at91sam9g45_uart3_device;
1727                         configure_usart3_pins(pins);
1728                         break;
1729                 default:
1730                         return;
1731         }
1732         pdata = pdev->dev.platform_data;
1733         pdata->num = portnr;            /* update to mapped ID */
1734
1735         if (portnr < ATMEL_MAX_UART)
1736                 at91_uarts[portnr] = pdev;
1737 }
1738
1739 void __init at91_set_serial_console(unsigned portnr)
1740 {
1741         if (portnr < ATMEL_MAX_UART) {
1742                 atmel_default_console_device = at91_uarts[portnr];
1743                 at91sam9g45_set_console_clock(at91_uarts[portnr]->id);
1744         }
1745 }
1746
1747 void __init at91_add_device_serial(void)
1748 {
1749         int i;
1750
1751         for (i = 0; i < ATMEL_MAX_UART; i++) {
1752                 if (at91_uarts[i])
1753                         platform_device_register(at91_uarts[i]);
1754         }
1755
1756         if (!atmel_default_console_device)
1757                 printk(KERN_INFO "AT91: No default serial console defined.\n");
1758 }
1759 #else
1760 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1761 void __init at91_set_serial_console(unsigned portnr) {}
1762 void __init at91_add_device_serial(void) {}
1763 #endif
1764
1765
1766 /* -------------------------------------------------------------------- */
1767 /*
1768  * These devices are always present and don't need any board-specific
1769  * setup.
1770  */
1771 static int __init at91_add_standard_devices(void)
1772 {
1773         at91_add_device_hdmac();
1774         at91_add_device_rtc();
1775         at91_add_device_rtt();
1776         at91_add_device_trng();
1777         at91_add_device_watchdog();
1778         at91_add_device_tc();
1779         return 0;
1780 }
1781
1782 arch_initcall(at91_add_standard_devices);