sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #ifdef CONFIG_X86
  50 /* for snoop control */
  51 #include <asm/pgtable.h>
  52 #include <asm/cacheflush.h>
  53 #endif
  54 #include <sound/core.h>
  55 #include <sound/initval.h>
  56 #include "hda_codec.h"
  57
  58
  59 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  60 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  61 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  62 static char *model[SNDRV_CARDS];
  63 static int position_fix[SNDRV_CARDS];
  64 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  65 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  66 static int probe_only[SNDRV_CARDS];
  67 static bool single_cmd;
  68 static int enable_msi = -1;
  69 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  70 static char *patch[SNDRV_CARDS];
  71 #endif
  72 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  73 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  74                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  75 #endif
  76
  77 module_param_array(index, int, NULL, 0444);
  78 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  79 module_param_array(id, charp, NULL, 0444);
  80 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  81 module_param_array(enable, bool, NULL, 0444);
  82 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  83 module_param_array(model, charp, NULL, 0444);
  84 MODULE_PARM_DESC(model, "Use the given board model.");
  85 module_param_array(position_fix, int, NULL, 0444);
  86 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  87                  "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
  88 module_param_array(bdl_pos_adj, int, NULL, 0644);
  89 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  90 module_param_array(probe_mask, int, NULL, 0444);
  91 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  92 module_param_array(probe_only, int, NULL, 0444);
  93 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  94 module_param(single_cmd, bool, 0444);
  95 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  96                  "(for debugging only).");
  97 module_param(enable_msi, bint, 0444);
  98 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  99 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 100 module_param_array(patch, charp, NULL, 0444);
 101 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 102 #endif
 103 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 104 module_param_array(beep_mode, int, NULL, 0444);
 105 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 106                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
 107 #endif
 108
 109 #ifdef CONFIG_SND_HDA_POWER_SAVE
 110 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 111 module_param(power_save, int, 0644);
 112 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 113                  "(in second, 0 = disable).");
 114
 115 /* reset the HD-audio controller in power save mode.
 116  * this may give more power-saving, but will take longer time to
 117  * wake up.
 118  */
 119 static bool power_save_controller = 1;
 120 module_param(power_save_controller, bool, 0644);
 121 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 122 #endif
 123
 124 static int align_buffer_size = -1;
 125 module_param(align_buffer_size, bint, 0644);
 126 MODULE_PARM_DESC(align_buffer_size,
 127                 "Force buffer and period sizes to be multiple of 128 bytes.");
 128
 129 #ifdef CONFIG_X86
 130 static bool hda_snoop = true;
 131 module_param_named(snoop, hda_snoop, bool, 0444);
 132 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 133 #define azx_snoop(chip)         (chip)->snoop
 134 #else
 135 #define hda_snoop               true
 136 #define azx_snoop(chip)         true
 137 #endif
 138
 139
 140 MODULE_LICENSE("GPL");
 141 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 142                          "{Intel, ICH6M},"
 143                          "{Intel, ICH7},"
 144                          "{Intel, ESB2},"
 145                          "{Intel, ICH8},"
 146                          "{Intel, ICH9},"
 147                          "{Intel, ICH10},"
 148                          "{Intel, PCH},"
 149                          "{Intel, CPT},"
 150                          "{Intel, PPT},"
 151                          "{Intel, LPT},"
 152                          "{Intel, PBG},"
 153                          "{Intel, SCH},"
 154                          "{ATI, SB450},"
 155                          "{ATI, SB600},"
 156                          "{ATI, RS600},"
 157                          "{ATI, RS690},"
 158                          "{ATI, RS780},"
 159                          "{ATI, R600},"
 160                          "{ATI, RV630},"
 161                          "{ATI, RV610},"
 162                          "{ATI, RV670},"
 163                          "{ATI, RV635},"
 164                          "{ATI, RV620},"
 165                          "{ATI, RV770},"
 166                          "{VIA, VT8251},"
 167                          "{VIA, VT8237A},"
 168                          "{SiS, SIS966},"
 169                          "{ULI, M5461}}");
 170 MODULE_DESCRIPTION("Intel HDA driver");
 171
 172 #ifdef CONFIG_SND_VERBOSE_PRINTK
 173 #define SFX     /* nop */
 174 #else
 175 #define SFX     "hda-intel: "
 176 #endif
 177
 178 /*
 179  * registers
 180  */
 181 #define ICH6_REG_GCAP                   0x00
 182 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 183 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 184 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 185 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 186 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 187 #define ICH6_REG_VMIN                   0x02
 188 #define ICH6_REG_VMAJ                   0x03
 189 #define ICH6_REG_OUTPAY                 0x04
 190 #define ICH6_REG_INPAY                  0x06
 191 #define ICH6_REG_GCTL                   0x08
 192 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 193 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 194 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 195 #define ICH6_REG_WAKEEN                 0x0c
 196 #define ICH6_REG_STATESTS               0x0e
 197 #define ICH6_REG_GSTS                   0x10
 198 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 199 #define ICH6_REG_INTCTL                 0x20
 200 #define ICH6_REG_INTSTS                 0x24
 201 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 202 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 203 #define ICH6_REG_SSYNC                  0x38
 204 #define ICH6_REG_CORBLBASE              0x40
 205 #define ICH6_REG_CORBUBASE              0x44
 206 #define ICH6_REG_CORBWP                 0x48
 207 #define ICH6_REG_CORBRP                 0x4a
 208 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 209 #define ICH6_REG_CORBCTL                0x4c
 210 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 211 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 212 #define ICH6_REG_CORBSTS                0x4d
 213 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 214 #define ICH6_REG_CORBSIZE               0x4e
 215
 216 #define ICH6_REG_RIRBLBASE              0x50
 217 #define ICH6_REG_RIRBUBASE              0x54
 218 #define ICH6_REG_RIRBWP                 0x58
 219 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 220 #define ICH6_REG_RINTCNT                0x5a
 221 #define ICH6_REG_RIRBCTL                0x5c
 222 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 223 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 224 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 225 #define ICH6_REG_RIRBSTS                0x5d
 226 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 227 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 228 #define ICH6_REG_RIRBSIZE               0x5e
 229
 230 #define ICH6_REG_IC                     0x60
 231 #define ICH6_REG_IR                     0x64
 232 #define ICH6_REG_IRS                    0x68
 233 #define   ICH6_IRS_VALID        (1<<1)
 234 #define   ICH6_IRS_BUSY         (1<<0)
 235
 236 #define ICH6_REG_DPLBASE                0x70
 237 #define ICH6_REG_DPUBASE                0x74
 238 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 239
 240 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 241 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 242
 243 /* stream register offsets from stream base */
 244 #define ICH6_REG_SD_CTL                 0x00
 245 #define ICH6_REG_SD_STS                 0x03
 246 #define ICH6_REG_SD_LPIB                0x04
 247 #define ICH6_REG_SD_CBL                 0x08
 248 #define ICH6_REG_SD_LVI                 0x0c
 249 #define ICH6_REG_SD_FIFOW               0x0e
 250 #define ICH6_REG_SD_FIFOSIZE            0x10
 251 #define ICH6_REG_SD_FORMAT              0x12
 252 #define ICH6_REG_SD_BDLPL               0x18
 253 #define ICH6_REG_SD_BDLPU               0x1c
 254
 255 /* PCI space */
 256 #define ICH6_PCIREG_TCSEL       0x44
 257
 258 /*
 259  * other constants
 260  */
 261
 262 /* max number of SDs */
 263 /* ICH, ATI and VIA have 4 playback and 4 capture */
 264 #define ICH6_NUM_CAPTURE        4
 265 #define ICH6_NUM_PLAYBACK       4
 266
 267 /* ULI has 6 playback and 5 capture */
 268 #define ULI_NUM_CAPTURE         5
 269 #define ULI_NUM_PLAYBACK        6
 270
 271 /* ATI HDMI has 1 playback and 0 capture */
 272 #define ATIHDMI_NUM_CAPTURE     0
 273 #define ATIHDMI_NUM_PLAYBACK    1
 274
 275 /* TERA has 4 playback and 3 capture */
 276 #define TERA_NUM_CAPTURE        3
 277 #define TERA_NUM_PLAYBACK       4
 278
 279 /* this number is statically defined for simplicity */
 280 #define MAX_AZX_DEV             16
 281
 282 /* max number of fragments - we may use more if allocating more pages for BDL */
 283 #define BDL_SIZE                4096
 284 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 285 #define AZX_MAX_FRAG            32
 286 /* max buffer size - no h/w limit, you can increase as you like */
 287 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 288
 289 /* RIRB int mask: overrun[2], response[0] */
 290 #define RIRB_INT_RESPONSE       0x01
 291 #define RIRB_INT_OVERRUN        0x04
 292 #define RIRB_INT_MASK           0x05
 293
 294 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 295 #define AZX_MAX_CODECS          8
 296 #define AZX_DEFAULT_CODECS      4
 297 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 298
 299 /* SD_CTL bits */
 300 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 301 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 302 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 303 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 304 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 305 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 306 #define SD_CTL_STREAM_TAG_SHIFT 20
 307
 308 /* SD_CTL and SD_STS */
 309 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 310 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 311 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 312 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 313                                  SD_INT_COMPLETE)
 314
 315 /* SD_STS */
 316 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 317
 318 /* INTCTL and INTSTS */
 319 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 320 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 321 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 322
 323 /* below are so far hardcoded - should read registers in future */
 324 #define ICH6_MAX_CORB_ENTRIES   256
 325 #define ICH6_MAX_RIRB_ENTRIES   256
 326
 327 /* position fix mode */
 328 enum {
 329         POS_FIX_AUTO,
 330         POS_FIX_LPIB,
 331         POS_FIX_POSBUF,
 332         POS_FIX_VIACOMBO,
 333         POS_FIX_COMBO,
 334 };
 335
 336 /* Defines for ATI HD Audio support in SB450 south bridge */
 337 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 338 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 339
 340 /* Defines for Nvidia HDA support */
 341 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 342 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 343 #define NVIDIA_HDA_ISTRM_COH          0x4d
 344 #define NVIDIA_HDA_OSTRM_COH          0x4c
 345 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 346
 347 /* Defines for Intel SCH HDA snoop control */
 348 #define INTEL_SCH_HDA_DEVC      0x78
 349 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 350
 351 /* Define IN stream 0 FIFO size offset in VIA controller */
 352 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 353 /* Define VIA HD Audio Device ID*/
 354 #define VIA_HDAC_DEVICE_ID              0x3288
 355
 356 /* HD Audio class code */
 357 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 358
 359 /*
 360  */
 361
 362 struct azx_dev {
 363         struct snd_dma_buffer bdl; /* BDL buffer */
 364         u32 *posbuf;            /* position buffer pointer */
 365
 366         unsigned int bufsize;   /* size of the play buffer in bytes */
 367         unsigned int period_bytes; /* size of the period in bytes */
 368         unsigned int frags;     /* number for period in the play buffer */
 369         unsigned int fifo_size; /* FIFO size */
 370         unsigned long start_wallclk;    /* start + minimum wallclk */
 371         unsigned long period_wallclk;   /* wallclk for period */
 372
 373         void __iomem *sd_addr;  /* stream descriptor pointer */
 374
 375         u32 sd_int_sta_mask;    /* stream int status mask */
 376
 377         /* pcm support */
 378         struct snd_pcm_substream *substream;    /* assigned substream,
 379                                                  * set in PCM open
 380                                                  */
 381         unsigned int format_val;        /* format value to be set in the
 382                                          * controller and the codec
 383                                          */
 384         unsigned char stream_tag;       /* assigned stream */
 385         unsigned char index;            /* stream index */
 386         int assigned_key;               /* last device# key assigned to */
 387
 388         unsigned int opened :1;
 389         unsigned int running :1;
 390         unsigned int irq_pending :1;
 391         /*
 392          * For VIA:
 393          *  A flag to ensure DMA position is 0
 394          *  when link position is not greater than FIFO size
 395          */
 396         unsigned int insufficient :1;
 397         unsigned int wc_marked:1;
 398 };
 399
 400 /* CORB/RIRB */
 401 struct azx_rb {
 402         u32 *buf;               /* CORB/RIRB buffer
 403                                  * Each CORB entry is 4byte, RIRB is 8byte
 404                                  */
 405         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 406         /* for RIRB */
 407         unsigned short rp, wp;  /* read/write pointers */
 408         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 409         u32 res[AZX_MAX_CODECS];        /* last read value */
 410 };
 411
 412 struct azx_pcm {
 413         struct azx *chip;
 414         struct snd_pcm *pcm;
 415         struct hda_codec *codec;
 416         struct hda_pcm_stream *hinfo[2];
 417         struct list_head list;
 418 };
 419
 420 struct azx {
 421         struct snd_card *card;
 422         struct pci_dev *pci;
 423         int dev_index;
 424
 425         /* chip type specific */
 426         int driver_type;
 427         unsigned int driver_caps;
 428         int playback_streams;
 429         int playback_index_offset;
 430         int capture_streams;
 431         int capture_index_offset;
 432         int num_streams;
 433
 434         /* pci resources */
 435         unsigned long addr;
 436         void __iomem *remap_addr;
 437         int irq;
 438
 439         /* locks */
 440         spinlock_t reg_lock;
 441         struct mutex open_mutex;
 442
 443         /* streams (x num_streams) */
 444         struct azx_dev *azx_dev;
 445
 446         /* PCM */
 447         struct list_head pcm_list; /* azx_pcm list */
 448
 449         /* HD codec */
 450         unsigned short codec_mask;
 451         int  codec_probe_mask; /* copied from probe_mask option */
 452         struct hda_bus *bus;
 453         unsigned int beep_mode;
 454
 455         /* CORB/RIRB */
 456         struct azx_rb corb;
 457         struct azx_rb rirb;
 458
 459         /* CORB/RIRB and position buffers */
 460         struct snd_dma_buffer rb;
 461         struct snd_dma_buffer posbuf;
 462
 463         /* flags */
 464         int position_fix[2]; /* for both playback/capture streams */
 465         int poll_count;
 466         unsigned int running :1;
 467         unsigned int initialized :1;
 468         unsigned int single_cmd :1;
 469         unsigned int polling_mode :1;
 470         unsigned int msi :1;
 471         unsigned int irq_pending_warned :1;
 472         unsigned int probing :1; /* codec probing phase */
 473         unsigned int snoop:1;
 474         unsigned int align_buffer_size:1;
 475
 476         /* for debugging */
 477         unsigned int last_cmd[AZX_MAX_CODECS];
 478
 479         /* for pending irqs */
 480         struct work_struct irq_pending_work;
 481
 482         /* reboot notifier (for mysterious hangup problem at power-down) */
 483         struct notifier_block reboot_notifier;
 484 };
 485
 486 /* driver types */
 487 enum {
 488         AZX_DRIVER_ICH,
 489         AZX_DRIVER_PCH,
 490         AZX_DRIVER_SCH,
 491         AZX_DRIVER_ATI,
 492         AZX_DRIVER_ATIHDMI,
 493         AZX_DRIVER_ATIHDMI_NS,
 494         AZX_DRIVER_VIA,
 495         AZX_DRIVER_SIS,
 496         AZX_DRIVER_ULI,
 497         AZX_DRIVER_NVIDIA,
 498         AZX_DRIVER_TERA,
 499         AZX_DRIVER_CTX,
 500         AZX_DRIVER_GENERIC,
 501         AZX_NUM_DRIVERS, /* keep this as last entry */
 502 };
 503
 504 /* driver quirks (capabilities) */
 505 /* bits 0-7 are used for indicating driver type */
 506 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 507 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 508 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 509 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 510 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 511 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 512 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 513 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 514 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 515 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 516 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 517 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 518 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 519 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 520 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
 521
 522 /* quirks for ATI SB / AMD Hudson */
 523 #define AZX_DCAPS_PRESET_ATI_SB \
 524         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 525          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 526
 527 /* quirks for ATI/AMD HDMI */
 528 #define AZX_DCAPS_PRESET_ATI_HDMI \
 529         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 530
 531 /* quirks for Nvidia */
 532 #define AZX_DCAPS_PRESET_NVIDIA \
 533         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
 534          AZX_DCAPS_ALIGN_BUFSIZE)
 535
 536 static char *driver_short_names[] __devinitdata = {
 537         [AZX_DRIVER_ICH] = "HDA Intel",
 538         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 539         [AZX_DRIVER_SCH] = "HDA Intel MID",
 540         [AZX_DRIVER_ATI] = "HDA ATI SB",
 541         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 542         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 543         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 544         [AZX_DRIVER_SIS] = "HDA SIS966",
 545         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 546         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 547         [AZX_DRIVER_TERA] = "HDA Teradici",
 548         [AZX_DRIVER_CTX] = "HDA Creative",
 549         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 550 };
 551
 552 /*
 553  * macros for easy use
 554  */
 555 #define azx_writel(chip,reg,value) \
 556         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 557 #define azx_readl(chip,reg) \
 558         readl((chip)->remap_addr + ICH6_REG_##reg)
 559 #define azx_writew(chip,reg,value) \
 560         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 561 #define azx_readw(chip,reg) \
 562         readw((chip)->remap_addr + ICH6_REG_##reg)
 563 #define azx_writeb(chip,reg,value) \
 564         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 565 #define azx_readb(chip,reg) \
 566         readb((chip)->remap_addr + ICH6_REG_##reg)
 567
 568 #define azx_sd_writel(dev,reg,value) \
 569         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 570 #define azx_sd_readl(dev,reg) \
 571         readl((dev)->sd_addr + ICH6_REG_##reg)
 572 #define azx_sd_writew(dev,reg,value) \
 573         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 574 #define azx_sd_readw(dev,reg) \
 575         readw((dev)->sd_addr + ICH6_REG_##reg)
 576 #define azx_sd_writeb(dev,reg,value) \
 577         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 578 #define azx_sd_readb(dev,reg) \
 579         readb((dev)->sd_addr + ICH6_REG_##reg)
 580
 581 /* for pcm support */
 582 #define get_azx_dev(substream) (substream->runtime->private_data)
 583
 584 #ifdef CONFIG_X86
 585 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
 586 {
 587         if (azx_snoop(chip))
 588                 return;
 589         if (addr && size) {
 590                 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 591                 if (on)
 592                         set_memory_wc((unsigned long)addr, pages);
 593                 else
 594                         set_memory_wb((unsigned long)addr, pages);
 595         }
 596 }
 597
 598 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 599                                  bool on)
 600 {
 601         __mark_pages_wc(chip, buf->area, buf->bytes, on);
 602 }
 603 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 604                                    struct snd_pcm_runtime *runtime, bool on)
 605 {
 606         if (azx_dev->wc_marked != on) {
 607                 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
 608                 azx_dev->wc_marked = on;
 609         }
 610 }
 611 #else
 612 /* NOP for other archs */
 613 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 614                                  bool on)
 615 {
 616 }
 617 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 618                                    struct snd_pcm_runtime *runtime, bool on)
 619 {
 620 }
 621 #endif
 622
 623 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 624 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 625 /*
 626  * Interface for HD codec
 627  */
 628
 629 /*
 630  * CORB / RIRB interface
 631  */
 632 static int azx_alloc_cmd_io(struct azx *chip)
 633 {
 634         int err;
 635
 636         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 637         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 638                                   snd_dma_pci_data(chip->pci),
 639                                   PAGE_SIZE, &chip->rb);
 640         if (err < 0) {
 641                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 642                 return err;
 643         }
 644         mark_pages_wc(chip, &chip->rb, true);
 645         return 0;
 646 }
 647
 648 static void azx_init_cmd_io(struct azx *chip)
 649 {
 650         spin_lock_irq(&chip->reg_lock);
 651         /* CORB set up */
 652         chip->corb.addr = chip->rb.addr;
 653         chip->corb.buf = (u32 *)chip->rb.area;
 654         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 655         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 656
 657         /* set the corb size to 256 entries (ULI requires explicitly) */
 658         azx_writeb(chip, CORBSIZE, 0x02);
 659         /* set the corb write pointer to 0 */
 660         azx_writew(chip, CORBWP, 0);
 661         /* reset the corb hw read pointer */
 662         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 663         /* enable corb dma */
 664         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 665
 666         /* RIRB set up */
 667         chip->rirb.addr = chip->rb.addr + 2048;
 668         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 669         chip->rirb.wp = chip->rirb.rp = 0;
 670         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 671         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 672         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 673
 674         /* set the rirb size to 256 entries (ULI requires explicitly) */
 675         azx_writeb(chip, RIRBSIZE, 0x02);
 676         /* reset the rirb hw write pointer */
 677         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 678         /* set N=1, get RIRB response interrupt for new entry */
 679         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 680                 azx_writew(chip, RINTCNT, 0xc0);
 681         else
 682                 azx_writew(chip, RINTCNT, 1);
 683         /* enable rirb dma and response irq */
 684         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 685         spin_unlock_irq(&chip->reg_lock);
 686 }
 687
 688 static void azx_free_cmd_io(struct azx *chip)
 689 {
 690         spin_lock_irq(&chip->reg_lock);
 691         /* disable ringbuffer DMAs */
 692         azx_writeb(chip, RIRBCTL, 0);
 693         azx_writeb(chip, CORBCTL, 0);
 694         spin_unlock_irq(&chip->reg_lock);
 695 }
 696
 697 static unsigned int azx_command_addr(u32 cmd)
 698 {
 699         unsigned int addr = cmd >> 28;
 700
 701         if (addr >= AZX_MAX_CODECS) {
 702                 snd_BUG();
 703                 addr = 0;
 704         }
 705
 706         return addr;
 707 }
 708
 709 static unsigned int azx_response_addr(u32 res)
 710 {
 711         unsigned int addr = res & 0xf;
 712
 713         if (addr >= AZX_MAX_CODECS) {
 714                 snd_BUG();
 715                 addr = 0;
 716         }
 717
 718         return addr;
 719 }
 720
 721 /* send a command */
 722 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 723 {
 724         struct azx *chip = bus->private_data;
 725         unsigned int addr = azx_command_addr(val);
 726         unsigned int wp;
 727
 728         spin_lock_irq(&chip->reg_lock);
 729
 730         /* add command to corb */
 731         wp = azx_readb(chip, CORBWP);
 732         wp++;
 733         wp %= ICH6_MAX_CORB_ENTRIES;
 734
 735         chip->rirb.cmds[addr]++;
 736         chip->corb.buf[wp] = cpu_to_le32(val);
 737         azx_writel(chip, CORBWP, wp);
 738
 739         spin_unlock_irq(&chip->reg_lock);
 740
 741         return 0;
 742 }
 743
 744 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 745
 746 /* retrieve RIRB entry - called from interrupt handler */
 747 static void azx_update_rirb(struct azx *chip)
 748 {
 749         unsigned int rp, wp;
 750         unsigned int addr;
 751         u32 res, res_ex;
 752
 753         wp = azx_readb(chip, RIRBWP);
 754         if (wp == chip->rirb.wp)
 755                 return;
 756         chip->rirb.wp = wp;
 757
 758         while (chip->rirb.rp != wp) {
 759                 chip->rirb.rp++;
 760                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 761
 762                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 763                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 764                 res = le32_to_cpu(chip->rirb.buf[rp]);
 765                 addr = azx_response_addr(res_ex);
 766                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 767                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 768                 else if (chip->rirb.cmds[addr]) {
 769                         chip->rirb.res[addr] = res;
 770                         smp_wmb();
 771                         chip->rirb.cmds[addr]--;
 772                 } else
 773                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 774                                    "last cmd=%#08x\n",
 775                                    res, res_ex,
 776                                    chip->last_cmd[addr]);
 777         }
 778 }
 779
 780 /* receive a response */
 781 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 782                                           unsigned int addr)
 783 {
 784         struct azx *chip = bus->private_data;
 785         unsigned long timeout;
 786         unsigned long loopcounter;
 787         int do_poll = 0;
 788
 789  again:
 790         timeout = jiffies + msecs_to_jiffies(1000);
 791
 792         for (loopcounter = 0;; loopcounter++) {
 793                 if (chip->polling_mode || do_poll) {
 794                         spin_lock_irq(&chip->reg_lock);
 795                         azx_update_rirb(chip);
 796                         spin_unlock_irq(&chip->reg_lock);
 797                 }
 798                 if (!chip->rirb.cmds[addr]) {
 799                         smp_rmb();
 800                         bus->rirb_error = 0;
 801
 802                         if (!do_poll)
 803                                 chip->poll_count = 0;
 804                         return chip->rirb.res[addr]; /* the last value */
 805                 }
 806                 if (time_after(jiffies, timeout))
 807                         break;
 808                 if (bus->needs_damn_long_delay || loopcounter > 3000)
 809                         msleep(2); /* temporary workaround */
 810                 else {
 811                         udelay(10);
 812                         cond_resched();
 813                 }
 814         }
 815
 816         if (!chip->polling_mode && chip->poll_count < 2) {
 817                 snd_printdd(SFX "azx_get_response timeout, "
 818                            "polling the codec once: last cmd=0x%08x\n",
 819                            chip->last_cmd[addr]);
 820                 do_poll = 1;
 821                 chip->poll_count++;
 822                 goto again;
 823         }
 824
 825
 826         if (!chip->polling_mode) {
 827                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 828                            "switching to polling mode: last cmd=0x%08x\n",
 829                            chip->last_cmd[addr]);
 830                 chip->polling_mode = 1;
 831                 goto again;
 832         }
 833
 834         if (chip->msi) {
 835                 snd_printk(KERN_WARNING SFX "No response from codec, "
 836                            "disabling MSI: last cmd=0x%08x\n",
 837                            chip->last_cmd[addr]);
 838                 free_irq(chip->irq, chip);
 839                 chip->irq = -1;
 840                 pci_disable_msi(chip->pci);
 841                 chip->msi = 0;
 842                 if (azx_acquire_irq(chip, 1) < 0) {
 843                         bus->rirb_error = 1;
 844                         return -1;
 845                 }
 846                 goto again;
 847         }
 848
 849         if (chip->probing) {
 850                 /* If this critical timeout happens during the codec probing
 851                  * phase, this is likely an access to a non-existing codec
 852                  * slot.  Better to return an error and reset the system.
 853                  */
 854                 return -1;
 855         }
 856
 857         /* a fatal communication error; need either to reset or to fallback
 858          * to the single_cmd mode
 859          */
 860         bus->rirb_error = 1;
 861         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 862                 bus->response_reset = 1;
 863                 return -1; /* give a chance to retry */
 864         }
 865
 866         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 867                    "switching to single_cmd mode: last cmd=0x%08x\n",
 868                    chip->last_cmd[addr]);
 869         chip->single_cmd = 1;
 870         bus->response_reset = 0;
 871         /* release CORB/RIRB */
 872         azx_free_cmd_io(chip);
 873         /* disable unsolicited responses */
 874         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 875         return -1;
 876 }
 877
 878 /*
 879  * Use the single immediate command instead of CORB/RIRB for simplicity
 880  *
 881  * Note: according to Intel, this is not preferred use.  The command was
 882  *       intended for the BIOS only, and may get confused with unsolicited
 883  *       responses.  So, we shouldn't use it for normal operation from the
 884  *       driver.
 885  *       I left the codes, however, for debugging/testing purposes.
 886  */
 887
 888 /* receive a response */
 889 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 890 {
 891         int timeout = 50;
 892
 893         while (timeout--) {
 894                 /* check IRV busy bit */
 895                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 896                         /* reuse rirb.res as the response return value */
 897                         chip->rirb.res[addr] = azx_readl(chip, IR);
 898                         return 0;
 899                 }
 900                 udelay(1);
 901         }
 902         if (printk_ratelimit())
 903                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 904                            azx_readw(chip, IRS));
 905         chip->rirb.res[addr] = -1;
 906         return -EIO;
 907 }
 908
 909 /* send a command */
 910 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 911 {
 912         struct azx *chip = bus->private_data;
 913         unsigned int addr = azx_command_addr(val);
 914         int timeout = 50;
 915
 916         bus->rirb_error = 0;
 917         while (timeout--) {
 918                 /* check ICB busy bit */
 919                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 920                         /* Clear IRV valid bit */
 921                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 922                                    ICH6_IRS_VALID);
 923                         azx_writel(chip, IC, val);
 924                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 925                                    ICH6_IRS_BUSY);
 926                         return azx_single_wait_for_response(chip, addr);
 927                 }
 928                 udelay(1);
 929         }
 930         if (printk_ratelimit())
 931                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 932                            azx_readw(chip, IRS), val);
 933         return -EIO;
 934 }
 935
 936 /* receive a response */
 937 static unsigned int azx_single_get_response(struct hda_bus *bus,
 938                                             unsigned int addr)
 939 {
 940         struct azx *chip = bus->private_data;
 941         return chip->rirb.res[addr];
 942 }
 943
 944 /*
 945  * The below are the main callbacks from hda_codec.
 946  *
 947  * They are just the skeleton to call sub-callbacks according to the
 948  * current setting of chip->single_cmd.
 949  */
 950
 951 /* send a command */
 952 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 953 {
 954         struct azx *chip = bus->private_data;
 955
 956         chip->last_cmd[azx_command_addr(val)] = val;
 957         if (chip->single_cmd)
 958                 return azx_single_send_cmd(bus, val);
 959         else
 960                 return azx_corb_send_cmd(bus, val);
 961 }
 962
 963 /* get a response */
 964 static unsigned int azx_get_response(struct hda_bus *bus,
 965                                      unsigned int addr)
 966 {
 967         struct azx *chip = bus->private_data;
 968         if (chip->single_cmd)
 969                 return azx_single_get_response(bus, addr);
 970         else
 971                 return azx_rirb_get_response(bus, addr);
 972 }
 973
 974 #ifdef CONFIG_SND_HDA_POWER_SAVE
 975 static void azx_power_notify(struct hda_bus *bus);
 976 #endif
 977
 978 /* reset codec link */
 979 static int azx_reset(struct azx *chip, int full_reset)
 980 {
 981         int count;
 982
 983         if (!full_reset)
 984                 goto __skip;
 985
 986         /* clear STATESTS */
 987         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 988
 989         /* reset controller */
 990         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 991
 992         count = 50;
 993         while (azx_readb(chip, GCTL) && --count)
 994                 msleep(1);
 995
 996         /* delay for >= 100us for codec PLL to settle per spec
 997          * Rev 0.9 section 5.5.1
 998          */
 999         msleep(1);
1000
1001         /* Bring controller out of reset */
1002         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1003
1004         count = 50;
1005         while (!azx_readb(chip, GCTL) && --count)
1006                 msleep(1);
1007
1008         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1009         msleep(1);
1010
1011       __skip:
1012         /* check to see if controller is ready */
1013         if (!azx_readb(chip, GCTL)) {
1014                 snd_printd(SFX "azx_reset: controller not ready!\n");
1015                 return -EBUSY;
1016         }
1017
1018         /* Accept unsolicited responses */
1019         if (!chip->single_cmd)
1020                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1021                            ICH6_GCTL_UNSOL);
1022
1023         /* detect codecs */
1024         if (!chip->codec_mask) {
1025                 chip->codec_mask = azx_readw(chip, STATESTS);
1026                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1027         }
1028
1029         return 0;
1030 }
1031
1032
1033 /*
1034  * Lowlevel interface
1035  */
1036
1037 /* enable interrupts */
1038 static void azx_int_enable(struct azx *chip)
1039 {
1040         /* enable controller CIE and GIE */
1041         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1042                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1043 }
1044
1045 /* disable interrupts */
1046 static void azx_int_disable(struct azx *chip)
1047 {
1048         int i;
1049
1050         /* disable interrupts in stream descriptor */
1051         for (i = 0; i < chip->num_streams; i++) {
1052                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1053                 azx_sd_writeb(azx_dev, SD_CTL,
1054                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1055         }
1056
1057         /* disable SIE for all streams */
1058         azx_writeb(chip, INTCTL, 0);
1059
1060         /* disable controller CIE and GIE */
1061         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1062                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1063 }
1064
1065 /* clear interrupts */
1066 static void azx_int_clear(struct azx *chip)
1067 {
1068         int i;
1069
1070         /* clear stream status */
1071         for (i = 0; i < chip->num_streams; i++) {
1072                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1073                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1074         }
1075
1076         /* clear STATESTS */
1077         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1078
1079         /* clear rirb status */
1080         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1081
1082         /* clear int status */
1083         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1084 }
1085
1086 /* start a stream */
1087 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1088 {
1089         /*
1090          * Before stream start, initialize parameter
1091          */
1092         azx_dev->insufficient = 1;
1093
1094         /* enable SIE */
1095         azx_writel(chip, INTCTL,
1096                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1097         /* set DMA start and interrupt mask */
1098         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1099                       SD_CTL_DMA_START | SD_INT_MASK);
1100 }
1101
1102 /* stop DMA */
1103 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1104 {
1105         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1106                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1107         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1108 }
1109
1110 /* stop a stream */
1111 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1112 {
1113         azx_stream_clear(chip, azx_dev);
1114         /* disable SIE */
1115         azx_writel(chip, INTCTL,
1116                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1117 }
1118
1119
1120 /*
1121  * reset and start the controller registers
1122  */
1123 static void azx_init_chip(struct azx *chip, int full_reset)
1124 {
1125         if (chip->initialized)
1126                 return;
1127
1128         /* reset controller */
1129         azx_reset(chip, full_reset);
1130
1131         /* initialize interrupts */
1132         azx_int_clear(chip);
1133         azx_int_enable(chip);
1134
1135         /* initialize the codec command I/O */
1136         if (!chip->single_cmd)
1137                 azx_init_cmd_io(chip);
1138
1139         /* program the position buffer */
1140         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1141         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1142
1143         chip->initialized = 1;
1144 }
1145
1146 /*
1147  * initialize the PCI registers
1148  */
1149 /* update bits in a PCI register byte */
1150 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1151                             unsigned char mask, unsigned char val)
1152 {
1153         unsigned char data;
1154
1155         pci_read_config_byte(pci, reg, &data);
1156         data &= ~mask;
1157         data |= (val & mask);
1158         pci_write_config_byte(pci, reg, data);
1159 }
1160
1161 static void azx_init_pci(struct azx *chip)
1162 {
1163         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1164          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1165          * Ensuring these bits are 0 clears playback static on some HD Audio
1166          * codecs.
1167          * The PCI register TCSEL is defined in the Intel manuals.
1168          */
1169         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1170                 snd_printdd(SFX "Clearing TCSEL\n");
1171                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1172         }
1173
1174         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1175          * we need to enable snoop.
1176          */
1177         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1178                 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1179                 update_pci_byte(chip->pci,
1180                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1181                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1182         }
1183
1184         /* For NVIDIA HDA, enable snoop */
1185         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1186                 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1187                 update_pci_byte(chip->pci,
1188                                 NVIDIA_HDA_TRANSREG_ADDR,
1189                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1190                 update_pci_byte(chip->pci,
1191                                 NVIDIA_HDA_ISTRM_COH,
1192                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1193                 update_pci_byte(chip->pci,
1194                                 NVIDIA_HDA_OSTRM_COH,
1195                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1196         }
1197
1198         /* Enable SCH/PCH snoop if needed */
1199         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1200                 unsigned short snoop;
1201                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1202                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1203                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1204                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1205                         if (!azx_snoop(chip))
1206                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1207                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1208                         pci_read_config_word(chip->pci,
1209                                 INTEL_SCH_HDA_DEVC, &snoop);
1210                 }
1211                 snd_printdd(SFX "SCH snoop: %s\n",
1212                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1213                                 ? "Disabled" : "Enabled");
1214         }
1215 }
1216
1217
1218 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1219
1220 /*
1221  * interrupt handler
1222  */
1223 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1224 {
1225         struct azx *chip = dev_id;
1226         struct azx_dev *azx_dev;
1227         u32 status;
1228         u8 sd_status;
1229         int i, ok;
1230
1231         spin_lock(&chip->reg_lock);
1232
1233         status = azx_readl(chip, INTSTS);
1234         if (status == 0) {
1235                 spin_unlock(&chip->reg_lock);
1236                 return IRQ_NONE;
1237         }
1238
1239         for (i = 0; i < chip->num_streams; i++) {
1240                 azx_dev = &chip->azx_dev[i];
1241                 if (status & azx_dev->sd_int_sta_mask) {
1242                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1243                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1244                         if (!azx_dev->substream || !azx_dev->running ||
1245                             !(sd_status & SD_INT_COMPLETE))
1246                                 continue;
1247                         /* check whether this IRQ is really acceptable */
1248                         ok = azx_position_ok(chip, azx_dev);
1249                         if (ok == 1) {
1250                                 azx_dev->irq_pending = 0;
1251                                 spin_unlock(&chip->reg_lock);
1252                                 snd_pcm_period_elapsed(azx_dev->substream);
1253                                 spin_lock(&chip->reg_lock);
1254                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1255                                 /* bogus IRQ, process it later */
1256                                 azx_dev->irq_pending = 1;
1257                                 queue_work(chip->bus->workq,
1258                                            &chip->irq_pending_work);
1259                         }
1260                 }
1261         }
1262
1263         /* clear rirb int */
1264         status = azx_readb(chip, RIRBSTS);
1265         if (status & RIRB_INT_MASK) {
1266                 if (status & RIRB_INT_RESPONSE) {
1267                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1268                                 udelay(80);
1269                         azx_update_rirb(chip);
1270                 }
1271                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1272         }
1273
1274 #if 0
1275         /* clear state status int */
1276         if (azx_readb(chip, STATESTS) & 0x04)
1277                 azx_writeb(chip, STATESTS, 0x04);
1278 #endif
1279         spin_unlock(&chip->reg_lock);
1280
1281         return IRQ_HANDLED;
1282 }
1283
1284
1285 /*
1286  * set up a BDL entry
1287  */
1288 static int setup_bdle(struct snd_pcm_substream *substream,
1289                       struct azx_dev *azx_dev, u32 **bdlp,
1290                       int ofs, int size, int with_ioc)
1291 {
1292         u32 *bdl = *bdlp;
1293
1294         while (size > 0) {
1295                 dma_addr_t addr;
1296                 int chunk;
1297
1298                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1299                         return -EINVAL;
1300
1301                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1302                 /* program the address field of the BDL entry */
1303                 bdl[0] = cpu_to_le32((u32)addr);
1304                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1305                 /* program the size field of the BDL entry */
1306                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1307                 bdl[2] = cpu_to_le32(chunk);
1308                 /* program the IOC to enable interrupt
1309                  * only when the whole fragment is processed
1310                  */
1311                 size -= chunk;
1312                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1313                 bdl += 4;
1314                 azx_dev->frags++;
1315                 ofs += chunk;
1316         }
1317         *bdlp = bdl;
1318         return ofs;
1319 }
1320
1321 /*
1322  * set up BDL entries
1323  */
1324 static int azx_setup_periods(struct azx *chip,
1325                              struct snd_pcm_substream *substream,
1326                              struct azx_dev *azx_dev)
1327 {
1328         u32 *bdl;
1329         int i, ofs, periods, period_bytes;
1330         int pos_adj;
1331
1332         /* reset BDL address */
1333         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1334         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1335
1336         period_bytes = azx_dev->period_bytes;
1337         periods = azx_dev->bufsize / period_bytes;
1338
1339         /* program the initial BDL entries */
1340         bdl = (u32 *)azx_dev->bdl.area;
1341         ofs = 0;
1342         azx_dev->frags = 0;
1343         pos_adj = bdl_pos_adj[chip->dev_index];
1344         if (pos_adj > 0) {
1345                 struct snd_pcm_runtime *runtime = substream->runtime;
1346                 int pos_align = pos_adj;
1347                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1348                 if (!pos_adj)
1349                         pos_adj = pos_align;
1350                 else
1351                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1352                                 pos_align;
1353                 pos_adj = frames_to_bytes(runtime, pos_adj);
1354                 if (pos_adj >= period_bytes) {
1355                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1356                                    bdl_pos_adj[chip->dev_index]);
1357                         pos_adj = 0;
1358                 } else {
1359                         ofs = setup_bdle(substream, azx_dev,
1360                                          &bdl, ofs, pos_adj,
1361                                          !substream->runtime->no_period_wakeup);
1362                         if (ofs < 0)
1363                                 goto error;
1364                 }
1365         } else
1366                 pos_adj = 0;
1367         for (i = 0; i < periods; i++) {
1368                 if (i == periods - 1 && pos_adj)
1369                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1370                                          period_bytes - pos_adj, 0);
1371                 else
1372                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1373                                          period_bytes,
1374                                          !substream->runtime->no_period_wakeup);
1375                 if (ofs < 0)
1376                         goto error;
1377         }
1378         return 0;
1379
1380  error:
1381         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1382                    azx_dev->bufsize, period_bytes);
1383         return -EINVAL;
1384 }
1385
1386 /* reset stream */
1387 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1388 {
1389         unsigned char val;
1390         int timeout;
1391
1392         azx_stream_clear(chip, azx_dev);
1393
1394         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1395                       SD_CTL_STREAM_RESET);
1396         udelay(3);
1397         timeout = 300;
1398         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1399                --timeout)
1400                 ;
1401         val &= ~SD_CTL_STREAM_RESET;
1402         azx_sd_writeb(azx_dev, SD_CTL, val);
1403         udelay(3);
1404
1405         timeout = 300;
1406         /* waiting for hardware to report that the stream is out of reset */
1407         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1408                --timeout)
1409                 ;
1410
1411         /* reset first position - may not be synced with hw at this time */
1412         *azx_dev->posbuf = 0;
1413 }
1414
1415 /*
1416  * set up the SD for streaming
1417  */
1418 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1419 {
1420         unsigned int val;
1421         /* make sure the run bit is zero for SD */
1422         azx_stream_clear(chip, azx_dev);
1423         /* program the stream_tag */
1424         val = azx_sd_readl(azx_dev, SD_CTL);
1425         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1426                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1427         if (!azx_snoop(chip))
1428                 val |= SD_CTL_TRAFFIC_PRIO;
1429         azx_sd_writel(azx_dev, SD_CTL, val);
1430
1431         /* program the length of samples in cyclic buffer */
1432         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1433
1434         /* program the stream format */
1435         /* this value needs to be the same as the one programmed */
1436         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1437
1438         /* program the stream LVI (last valid index) of the BDL */
1439         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1440
1441         /* program the BDL address */
1442         /* lower BDL address */
1443         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1444         /* upper BDL address */
1445         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1446
1447         /* enable the position buffer */
1448         if (chip->position_fix[0] != POS_FIX_LPIB ||
1449             chip->position_fix[1] != POS_FIX_LPIB) {
1450                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1451                         azx_writel(chip, DPLBASE,
1452                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1453         }
1454
1455         /* set the interrupt enable bits in the descriptor control register */
1456         azx_sd_writel(azx_dev, SD_CTL,
1457                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1458
1459         return 0;
1460 }
1461
1462 /*
1463  * Probe the given codec address
1464  */
1465 static int probe_codec(struct azx *chip, int addr)
1466 {
1467         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1468                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1469         unsigned int res;
1470
1471         mutex_lock(&chip->bus->cmd_mutex);
1472         chip->probing = 1;
1473         azx_send_cmd(chip->bus, cmd);
1474         res = azx_get_response(chip->bus, addr);
1475         chip->probing = 0;
1476         mutex_unlock(&chip->bus->cmd_mutex);
1477         if (res == -1)
1478                 return -EIO;
1479         snd_printdd(SFX "codec #%d probed OK\n", addr);
1480         return 0;
1481 }
1482
1483 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1484                                  struct hda_pcm *cpcm);
1485 static void azx_stop_chip(struct azx *chip);
1486
1487 static void azx_bus_reset(struct hda_bus *bus)
1488 {
1489         struct azx *chip = bus->private_data;
1490
1491         bus->in_reset = 1;
1492         azx_stop_chip(chip);
1493         azx_init_chip(chip, 1);
1494 #ifdef CONFIG_PM
1495         if (chip->initialized) {
1496                 struct azx_pcm *p;
1497                 list_for_each_entry(p, &chip->pcm_list, list)
1498                         snd_pcm_suspend_all(p->pcm);
1499                 snd_hda_suspend(chip->bus);
1500                 snd_hda_resume(chip->bus);
1501         }
1502 #endif
1503         bus->in_reset = 0;
1504 }
1505
1506 /*
1507  * Codec initialization
1508  */
1509
1510 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1511 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1512         [AZX_DRIVER_NVIDIA] = 8,
1513         [AZX_DRIVER_TERA] = 1,
1514 };
1515
1516 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1517 {
1518         struct hda_bus_template bus_temp;
1519         int c, codecs, err;
1520         int max_slots;
1521
1522         memset(&bus_temp, 0, sizeof(bus_temp));
1523         bus_temp.private_data = chip;
1524         bus_temp.modelname = model;
1525         bus_temp.pci = chip->pci;
1526         bus_temp.ops.command = azx_send_cmd;
1527         bus_temp.ops.get_response = azx_get_response;
1528         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1529         bus_temp.ops.bus_reset = azx_bus_reset;
1530 #ifdef CONFIG_SND_HDA_POWER_SAVE
1531         bus_temp.power_save = &power_save;
1532         bus_temp.ops.pm_notify = azx_power_notify;
1533 #endif
1534
1535         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1536         if (err < 0)
1537                 return err;
1538
1539         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1540                 snd_printd(SFX "Enable delay in RIRB handling\n");
1541                 chip->bus->needs_damn_long_delay = 1;
1542         }
1543
1544         codecs = 0;
1545         max_slots = azx_max_codecs[chip->driver_type];
1546         if (!max_slots)
1547                 max_slots = AZX_DEFAULT_CODECS;
1548
1549         /* First try to probe all given codec slots */
1550         for (c = 0; c < max_slots; c++) {
1551                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1552                         if (probe_codec(chip, c) < 0) {
1553                                 /* Some BIOSen give you wrong codec addresses
1554                                  * that don't exist
1555                                  */
1556                                 snd_printk(KERN_WARNING SFX
1557                                            "Codec #%d probe error; "
1558                                            "disabling it...\n", c);
1559                                 chip->codec_mask &= ~(1 << c);
1560                                 /* More badly, accessing to a non-existing
1561                                  * codec often screws up the controller chip,
1562                                  * and disturbs the further communications.
1563                                  * Thus if an error occurs during probing,
1564                                  * better to reset the controller chip to
1565                                  * get back to the sanity state.
1566                                  */
1567                                 azx_stop_chip(chip);
1568                                 azx_init_chip(chip, 1);
1569                         }
1570                 }
1571         }
1572
1573         /* AMD chipsets often cause the communication stalls upon certain
1574          * sequence like the pin-detection.  It seems that forcing the synced
1575          * access works around the stall.  Grrr...
1576          */
1577         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1578                 snd_printd(SFX "Enable sync_write for stable communication\n");
1579                 chip->bus->sync_write = 1;
1580                 chip->bus->allow_bus_reset = 1;
1581         }
1582
1583         /* Then create codec instances */
1584         for (c = 0; c < max_slots; c++) {
1585                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1586                         struct hda_codec *codec;
1587                         err = snd_hda_codec_new(chip->bus, c, &codec);
1588                         if (err < 0)
1589                                 continue;
1590                         codec->beep_mode = chip->beep_mode;
1591                         codecs++;
1592                 }
1593         }
1594         if (!codecs) {
1595                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1596                 return -ENXIO;
1597         }
1598         return 0;
1599 }
1600
1601 /* configure each codec instance */
1602 static int __devinit azx_codec_configure(struct azx *chip)
1603 {
1604         struct hda_codec *codec;
1605         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1606                 snd_hda_codec_configure(codec);
1607         }
1608         return 0;
1609 }
1610
1611
1612 /*
1613  * PCM support
1614  */
1615
1616 /* assign a stream for the PCM */
1617 static inline struct azx_dev *
1618 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1619 {
1620         int dev, i, nums;
1621         struct azx_dev *res = NULL;
1622         /* make a non-zero unique key for the substream */
1623         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1624                 (substream->stream + 1);
1625
1626         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1627                 dev = chip->playback_index_offset;
1628                 nums = chip->playback_streams;
1629         } else {
1630                 dev = chip->capture_index_offset;
1631                 nums = chip->capture_streams;
1632         }
1633         for (i = 0; i < nums; i++, dev++)
1634                 if (!chip->azx_dev[dev].opened) {
1635                         res = &chip->azx_dev[dev];
1636                         if (res->assigned_key == key)
1637                                 break;
1638                 }
1639         if (res) {
1640                 res->opened = 1;
1641                 res->assigned_key = key;
1642         }
1643         return res;
1644 }
1645
1646 /* release the assigned stream */
1647 static inline void azx_release_device(struct azx_dev *azx_dev)
1648 {
1649         azx_dev->opened = 0;
1650 }
1651
1652 static struct snd_pcm_hardware azx_pcm_hw = {
1653         .info =                 (SNDRV_PCM_INFO_MMAP |
1654                                  SNDRV_PCM_INFO_INTERLEAVED |
1655                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1656                                  SNDRV_PCM_INFO_MMAP_VALID |
1657                                  /* No full-resume yet implemented */
1658                                  /* SNDRV_PCM_INFO_RESUME |*/
1659                                  SNDRV_PCM_INFO_PAUSE |
1660                                  SNDRV_PCM_INFO_SYNC_START |
1661                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1662         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1663         .rates =                SNDRV_PCM_RATE_48000,
1664         .rate_min =             48000,
1665         .rate_max =             48000,
1666         .channels_min =         2,
1667         .channels_max =         2,
1668         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1669         .period_bytes_min =     128,
1670         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1671         .periods_min =          2,
1672         .periods_max =          AZX_MAX_FRAG,
1673         .fifo_size =            0,
1674 };
1675
1676 static int azx_pcm_open(struct snd_pcm_substream *substream)
1677 {
1678         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1679         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1680         struct azx *chip = apcm->chip;
1681         struct azx_dev *azx_dev;
1682         struct snd_pcm_runtime *runtime = substream->runtime;
1683         unsigned long flags;
1684         int err;
1685         int buff_step;
1686
1687         mutex_lock(&chip->open_mutex);
1688         azx_dev = azx_assign_device(chip, substream);
1689         if (azx_dev == NULL) {
1690                 mutex_unlock(&chip->open_mutex);
1691                 return -EBUSY;
1692         }
1693         runtime->hw = azx_pcm_hw;
1694         runtime->hw.channels_min = hinfo->channels_min;
1695         runtime->hw.channels_max = hinfo->channels_max;
1696         runtime->hw.formats = hinfo->formats;
1697         runtime->hw.rates = hinfo->rates;
1698         snd_pcm_limit_hw_rates(runtime);
1699         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1700         if (chip->align_buffer_size)
1701                 /* constrain buffer sizes to be multiple of 128
1702                    bytes. This is more efficient in terms of memory
1703                    access but isn't required by the HDA spec and
1704                    prevents users from specifying exact period/buffer
1705                    sizes. For example for 44.1kHz, a period size set
1706                    to 20ms will be rounded to 19.59ms. */
1707                 buff_step = 128;
1708         else
1709                 /* Don't enforce steps on buffer sizes, still need to
1710                    be multiple of 4 bytes (HDA spec). Tested on Intel
1711                    HDA controllers, may not work on all devices where
1712                    option needs to be disabled */
1713                 buff_step = 4;
1714
1715         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1716                                    buff_step);
1717         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1718                                    buff_step);
1719         snd_hda_power_up(apcm->codec);
1720         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1721         if (err < 0) {
1722                 azx_release_device(azx_dev);
1723                 snd_hda_power_down(apcm->codec);
1724                 mutex_unlock(&chip->open_mutex);
1725                 return err;
1726         }
1727         snd_pcm_limit_hw_rates(runtime);
1728         /* sanity check */
1729         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1730             snd_BUG_ON(!runtime->hw.channels_max) ||
1731             snd_BUG_ON(!runtime->hw.formats) ||
1732             snd_BUG_ON(!runtime->hw.rates)) {
1733                 azx_release_device(azx_dev);
1734                 hinfo->ops.close(hinfo, apcm->codec, substream);
1735                 snd_hda_power_down(apcm->codec);
1736                 mutex_unlock(&chip->open_mutex);
1737                 return -EINVAL;
1738         }
1739         spin_lock_irqsave(&chip->reg_lock, flags);
1740         azx_dev->substream = substream;
1741         azx_dev->running = 0;
1742         spin_unlock_irqrestore(&chip->reg_lock, flags);
1743
1744         runtime->private_data = azx_dev;
1745         snd_pcm_set_sync(substream);
1746         mutex_unlock(&chip->open_mutex);
1747         return 0;
1748 }
1749
1750 static int azx_pcm_close(struct snd_pcm_substream *substream)
1751 {
1752         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1753         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1754         struct azx *chip = apcm->chip;
1755         struct azx_dev *azx_dev = get_azx_dev(substream);
1756         unsigned long flags;
1757
1758         mutex_lock(&chip->open_mutex);
1759         spin_lock_irqsave(&chip->reg_lock, flags);
1760         azx_dev->substream = NULL;
1761         azx_dev->running = 0;
1762         spin_unlock_irqrestore(&chip->reg_lock, flags);
1763         azx_release_device(azx_dev);
1764         hinfo->ops.close(hinfo, apcm->codec, substream);
1765         snd_hda_power_down(apcm->codec);
1766         mutex_unlock(&chip->open_mutex);
1767         return 0;
1768 }
1769
1770 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1771                              struct snd_pcm_hw_params *hw_params)
1772 {
1773         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1774         struct azx *chip = apcm->chip;
1775         struct snd_pcm_runtime *runtime = substream->runtime;
1776         struct azx_dev *azx_dev = get_azx_dev(substream);
1777         int ret;
1778
1779         mark_runtime_wc(chip, azx_dev, runtime, false);
1780         azx_dev->bufsize = 0;
1781         azx_dev->period_bytes = 0;
1782         azx_dev->format_val = 0;
1783         ret = snd_pcm_lib_malloc_pages(substream,
1784                                         params_buffer_bytes(hw_params));
1785         if (ret < 0)
1786                 return ret;
1787         mark_runtime_wc(chip, azx_dev, runtime, true);
1788         return ret;
1789 }
1790
1791 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1792 {
1793         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1794         struct azx_dev *azx_dev = get_azx_dev(substream);
1795         struct azx *chip = apcm->chip;
1796         struct snd_pcm_runtime *runtime = substream->runtime;
1797         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1798
1799         /* reset BDL address */
1800         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1801         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1802         azx_sd_writel(azx_dev, SD_CTL, 0);
1803         azx_dev->bufsize = 0;
1804         azx_dev->period_bytes = 0;
1805         azx_dev->format_val = 0;
1806
1807         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1808
1809         mark_runtime_wc(chip, azx_dev, runtime, false);
1810         return snd_pcm_lib_free_pages(substream);
1811 }
1812
1813 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1814 {
1815         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1816         struct azx *chip = apcm->chip;
1817         struct azx_dev *azx_dev = get_azx_dev(substream);
1818         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1819         struct snd_pcm_runtime *runtime = substream->runtime;
1820         unsigned int bufsize, period_bytes, format_val, stream_tag;
1821         int err;
1822         struct hda_spdif_out *spdif =
1823                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1824         unsigned short ctls = spdif ? spdif->ctls : 0;
1825
1826         azx_stream_reset(chip, azx_dev);
1827         format_val = snd_hda_calc_stream_format(runtime->rate,
1828                                                 runtime->channels,
1829                                                 runtime->format,
1830                                                 hinfo->maxbps,
1831                                                 ctls);
1832         if (!format_val) {
1833                 snd_printk(KERN_ERR SFX
1834                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1835                            runtime->rate, runtime->channels, runtime->format);
1836                 return -EINVAL;
1837         }
1838
1839         bufsize = snd_pcm_lib_buffer_bytes(substream);
1840         period_bytes = snd_pcm_lib_period_bytes(substream);
1841
1842         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1843                     bufsize, format_val);
1844
1845         if (bufsize != azx_dev->bufsize ||
1846             period_bytes != azx_dev->period_bytes ||
1847             format_val != azx_dev->format_val) {
1848                 azx_dev->bufsize = bufsize;
1849                 azx_dev->period_bytes = period_bytes;
1850                 azx_dev->format_val = format_val;
1851                 err = azx_setup_periods(chip, substream, azx_dev);
1852                 if (err < 0)
1853                         return err;
1854         }
1855
1856         /* wallclk has 24Mhz clock source */
1857         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1858                                                 runtime->rate) * 1000);
1859         azx_setup_controller(chip, azx_dev);
1860         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1861                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1862         else
1863                 azx_dev->fifo_size = 0;
1864
1865         stream_tag = azx_dev->stream_tag;
1866         /* CA-IBG chips need the playback stream starting from 1 */
1867         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1868             stream_tag > chip->capture_streams)
1869                 stream_tag -= chip->capture_streams;
1870         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1871                                      azx_dev->format_val, substream);
1872 }
1873
1874 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1875 {
1876         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1877         struct azx *chip = apcm->chip;
1878         struct azx_dev *azx_dev;
1879         struct snd_pcm_substream *s;
1880         int rstart = 0, start, nsync = 0, sbits = 0;
1881         int nwait, timeout;
1882
1883         switch (cmd) {
1884         case SNDRV_PCM_TRIGGER_START:
1885                 rstart = 1;
1886         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1887         case SNDRV_PCM_TRIGGER_RESUME:
1888                 start = 1;
1889                 break;
1890         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1891         case SNDRV_PCM_TRIGGER_SUSPEND:
1892         case SNDRV_PCM_TRIGGER_STOP:
1893                 start = 0;
1894                 break;
1895         default:
1896                 return -EINVAL;
1897         }
1898
1899         snd_pcm_group_for_each_entry(s, substream) {
1900                 if (s->pcm->card != substream->pcm->card)
1901                         continue;
1902                 azx_dev = get_azx_dev(s);
1903                 sbits |= 1 << azx_dev->index;
1904                 nsync++;
1905                 snd_pcm_trigger_done(s, substream);
1906         }
1907
1908         spin_lock(&chip->reg_lock);
1909         if (nsync > 1) {
1910                 /* first, set SYNC bits of corresponding streams */
1911                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1912                         azx_writel(chip, OLD_SSYNC,
1913                                    azx_readl(chip, OLD_SSYNC) | sbits);
1914                 else
1915                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1916         }
1917         snd_pcm_group_for_each_entry(s, substream) {
1918                 if (s->pcm->card != substream->pcm->card)
1919                         continue;
1920                 azx_dev = get_azx_dev(s);
1921                 if (start) {
1922                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1923                         if (!rstart)
1924                                 azx_dev->start_wallclk -=
1925                                                 azx_dev->period_wallclk;
1926                         azx_stream_start(chip, azx_dev);
1927                 } else {
1928                         azx_stream_stop(chip, azx_dev);
1929                 }
1930                 azx_dev->running = start;
1931         }
1932         spin_unlock(&chip->reg_lock);
1933         if (start) {
1934                 if (nsync == 1)
1935                         return 0;
1936                 /* wait until all FIFOs get ready */
1937                 for (timeout = 5000; timeout; timeout--) {
1938                         nwait = 0;
1939                         snd_pcm_group_for_each_entry(s, substream) {
1940                                 if (s->pcm->card != substream->pcm->card)
1941                                         continue;
1942                                 azx_dev = get_azx_dev(s);
1943                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1944                                       SD_STS_FIFO_READY))
1945                                         nwait++;
1946                         }
1947                         if (!nwait)
1948                                 break;
1949                         cpu_relax();
1950                 }
1951         } else {
1952                 /* wait until all RUN bits are cleared */
1953                 for (timeout = 5000; timeout; timeout--) {
1954                         nwait = 0;
1955                         snd_pcm_group_for_each_entry(s, substream) {
1956                                 if (s->pcm->card != substream->pcm->card)
1957                                         continue;
1958                                 azx_dev = get_azx_dev(s);
1959                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1960                                     SD_CTL_DMA_START)
1961                                         nwait++;
1962                         }
1963                         if (!nwait)
1964                                 break;
1965                         cpu_relax();
1966                 }
1967         }
1968         if (nsync > 1) {
1969                 spin_lock(&chip->reg_lock);
1970                 /* reset SYNC bits */
1971                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1972                         azx_writel(chip, OLD_SSYNC,
1973                                    azx_readl(chip, OLD_SSYNC) & ~sbits);
1974                 else
1975                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1976                 spin_unlock(&chip->reg_lock);
1977         }
1978         return 0;
1979 }
1980
1981 /* get the current DMA position with correction on VIA chips */
1982 static unsigned int azx_via_get_position(struct azx *chip,
1983                                          struct azx_dev *azx_dev)
1984 {
1985         unsigned int link_pos, mini_pos, bound_pos;
1986         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1987         unsigned int fifo_size;
1988
1989         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1990         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1991                 /* Playback, no problem using link position */
1992                 return link_pos;
1993         }
1994
1995         /* Capture */
1996         /* For new chipset,
1997          * use mod to get the DMA position just like old chipset
1998          */
1999         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2000         mod_dma_pos %= azx_dev->period_bytes;
2001
2002         /* azx_dev->fifo_size can't get FIFO size of in stream.
2003          * Get from base address + offset.
2004          */
2005         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2006
2007         if (azx_dev->insufficient) {
2008                 /* Link position never gather than FIFO size */
2009                 if (link_pos <= fifo_size)
2010                         return 0;
2011
2012                 azx_dev->insufficient = 0;
2013         }
2014
2015         if (link_pos <= fifo_size)
2016                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2017         else
2018                 mini_pos = link_pos - fifo_size;
2019
2020         /* Find nearest previous boudary */
2021         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2022         mod_link_pos = link_pos % azx_dev->period_bytes;
2023         if (mod_link_pos >= fifo_size)
2024                 bound_pos = link_pos - mod_link_pos;
2025         else if (mod_dma_pos >= mod_mini_pos)
2026                 bound_pos = mini_pos - mod_mini_pos;
2027         else {
2028                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2029                 if (bound_pos >= azx_dev->bufsize)
2030                         bound_pos = 0;
2031         }
2032
2033         /* Calculate real DMA position we want */
2034         return bound_pos + mod_dma_pos;
2035 }
2036
2037 static unsigned int azx_get_position(struct azx *chip,
2038                                      struct azx_dev *azx_dev,
2039                                      bool with_check)
2040 {
2041         unsigned int pos;
2042         int stream = azx_dev->substream->stream;
2043
2044         switch (chip->position_fix[stream]) {
2045         case POS_FIX_LPIB:
2046                 /* read LPIB */
2047                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2048                 break;
2049         case POS_FIX_VIACOMBO:
2050                 pos = azx_via_get_position(chip, azx_dev);
2051                 break;
2052         default:
2053                 /* use the position buffer */
2054                 pos = le32_to_cpu(*azx_dev->posbuf);
2055                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2056                         if (!pos || pos == (u32)-1) {
2057                                 printk(KERN_WARNING
2058                                        "hda-intel: Invalid position buffer, "
2059                                        "using LPIB read method instead.\n");
2060                                 chip->position_fix[stream] = POS_FIX_LPIB;
2061                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2062                         } else
2063                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2064                 }
2065                 break;
2066         }
2067
2068         if (pos >= azx_dev->bufsize)
2069                 pos = 0;
2070         return pos;
2071 }
2072
2073 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2074 {
2075         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2076         struct azx *chip = apcm->chip;
2077         struct azx_dev *azx_dev = get_azx_dev(substream);
2078         return bytes_to_frames(substream->runtime,
2079                                azx_get_position(chip, azx_dev, false));
2080 }
2081
2082 /*
2083  * Check whether the current DMA position is acceptable for updating
2084  * periods.  Returns non-zero if it's OK.
2085  *
2086  * Many HD-audio controllers appear pretty inaccurate about
2087  * the update-IRQ timing.  The IRQ is issued before actually the
2088  * data is processed.  So, we need to process it afterwords in a
2089  * workqueue.
2090  */
2091 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2092 {
2093         u32 wallclk;
2094         unsigned int pos;
2095         int stream;
2096
2097         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2098         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2099                 return -1;      /* bogus (too early) interrupt */
2100
2101         stream = azx_dev->substream->stream;
2102         pos = azx_get_position(chip, azx_dev, true);
2103
2104         if (WARN_ONCE(!azx_dev->period_bytes,
2105                       "hda-intel: zero azx_dev->period_bytes"))
2106                 return -1; /* this shouldn't happen! */
2107         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2108             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2109                 /* NG - it's below the first next period boundary */
2110                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2111         azx_dev->start_wallclk += wallclk;
2112         return 1; /* OK, it's fine */
2113 }
2114
2115 /*
2116  * The work for pending PCM period updates.
2117  */
2118 static void azx_irq_pending_work(struct work_struct *work)
2119 {
2120         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2121         int i, pending, ok;
2122
2123         if (!chip->irq_pending_warned) {
2124                 printk(KERN_WARNING
2125                        "hda-intel: IRQ timing workaround is activated "
2126                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2127                        chip->card->number);
2128                 chip->irq_pending_warned = 1;
2129         }
2130
2131         for (;;) {
2132                 pending = 0;
2133                 spin_lock_irq(&chip->reg_lock);
2134                 for (i = 0; i < chip->num_streams; i++) {
2135                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2136                         if (!azx_dev->irq_pending ||
2137                             !azx_dev->substream ||
2138                             !azx_dev->running)
2139                                 continue;
2140                         ok = azx_position_ok(chip, azx_dev);
2141                         if (ok > 0) {
2142                                 azx_dev->irq_pending = 0;
2143                                 spin_unlock(&chip->reg_lock);
2144                                 snd_pcm_period_elapsed(azx_dev->substream);
2145                                 spin_lock(&chip->reg_lock);
2146                         } else if (ok < 0) {
2147                                 pending = 0;    /* too early */
2148                         } else
2149                                 pending++;
2150                 }
2151                 spin_unlock_irq(&chip->reg_lock);
2152                 if (!pending)
2153                         return;
2154                 msleep(1);
2155         }
2156 }
2157
2158 /* clear irq_pending flags and assure no on-going workq */
2159 static void azx_clear_irq_pending(struct azx *chip)
2160 {
2161         int i;
2162
2163         spin_lock_irq(&chip->reg_lock);
2164         for (i = 0; i < chip->num_streams; i++)
2165                 chip->azx_dev[i].irq_pending = 0;
2166         spin_unlock_irq(&chip->reg_lock);
2167 }
2168
2169 #ifdef CONFIG_X86
2170 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2171                         struct vm_area_struct *area)
2172 {
2173         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2174         struct azx *chip = apcm->chip;
2175         if (!azx_snoop(chip))
2176                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2177         return snd_pcm_lib_default_mmap(substream, area);
2178 }
2179 #else
2180 #define azx_pcm_mmap    NULL
2181 #endif
2182
2183 static struct snd_pcm_ops azx_pcm_ops = {
2184         .open = azx_pcm_open,
2185         .close = azx_pcm_close,
2186         .ioctl = snd_pcm_lib_ioctl,
2187         .hw_params = azx_pcm_hw_params,
2188         .hw_free = azx_pcm_hw_free,
2189         .prepare = azx_pcm_prepare,
2190         .trigger = azx_pcm_trigger,
2191         .pointer = azx_pcm_pointer,
2192         .mmap = azx_pcm_mmap,
2193         .page = snd_pcm_sgbuf_ops_page,
2194 };
2195
2196 static void azx_pcm_free(struct snd_pcm *pcm)
2197 {
2198         struct azx_pcm *apcm = pcm->private_data;
2199         if (apcm) {
2200                 list_del(&apcm->list);
2201                 kfree(apcm);
2202         }
2203 }
2204
2205 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2206
2207 static int
2208 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2209                       struct hda_pcm *cpcm)
2210 {
2211         struct azx *chip = bus->private_data;
2212         struct snd_pcm *pcm;
2213         struct azx_pcm *apcm;
2214         int pcm_dev = cpcm->device;
2215         unsigned int size;
2216         int s, err;
2217
2218         list_for_each_entry(apcm, &chip->pcm_list, list) {
2219                 if (apcm->pcm->device == pcm_dev) {
2220                         snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2221                         return -EBUSY;
2222                 }
2223         }
2224         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2225                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2226                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2227                           &pcm);
2228         if (err < 0)
2229                 return err;
2230         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2231         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2232         if (apcm == NULL)
2233                 return -ENOMEM;
2234         apcm->chip = chip;
2235         apcm->pcm = pcm;
2236         apcm->codec = codec;
2237         pcm->private_data = apcm;
2238         pcm->private_free = azx_pcm_free;
2239         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2240                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2241         list_add_tail(&apcm->list, &chip->pcm_list);
2242         cpcm->pcm = pcm;
2243         for (s = 0; s < 2; s++) {
2244                 apcm->hinfo[s] = &cpcm->stream[s];
2245                 if (cpcm->stream[s].substreams)
2246                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2247         }
2248         /* buffer pre-allocation */
2249         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2250         if (size > MAX_PREALLOC_SIZE)
2251                 size = MAX_PREALLOC_SIZE;
2252         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2253                                               snd_dma_pci_data(chip->pci),
2254                                               size, MAX_PREALLOC_SIZE);
2255         return 0;
2256 }
2257
2258 /*
2259  * mixer creation - all stuff is implemented in hda module
2260  */
2261 static int __devinit azx_mixer_create(struct azx *chip)
2262 {
2263         return snd_hda_build_controls(chip->bus);
2264 }
2265
2266
2267 /*
2268  * initialize SD streams
2269  */
2270 static int __devinit azx_init_stream(struct azx *chip)
2271 {
2272         int i;
2273
2274         /* initialize each stream (aka device)
2275          * assign the starting bdl address to each stream (device)
2276          * and initialize
2277          */
2278         for (i = 0; i < chip->num_streams; i++) {
2279                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2280                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2281                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2282                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2283                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2284                 azx_dev->sd_int_sta_mask = 1 << i;
2285                 /* stream tag: must be non-zero and unique */
2286                 azx_dev->index = i;
2287                 azx_dev->stream_tag = i + 1;
2288         }
2289
2290         return 0;
2291 }
2292
2293 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2294 {
2295         if (request_irq(chip->pci->irq, azx_interrupt,
2296                         chip->msi ? 0 : IRQF_SHARED,
2297                         KBUILD_MODNAME, chip)) {
2298                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2299                        "disabling device\n", chip->pci->irq);
2300                 if (do_disconnect)
2301                         snd_card_disconnect(chip->card);
2302                 return -1;
2303         }
2304         chip->irq = chip->pci->irq;
2305         pci_intx(chip->pci, !chip->msi);
2306         return 0;
2307 }
2308
2309
2310 static void azx_stop_chip(struct azx *chip)
2311 {
2312         if (!chip->initialized)
2313                 return;
2314
2315         /* disable interrupts */
2316         azx_int_disable(chip);
2317         azx_int_clear(chip);
2318
2319         /* disable CORB/RIRB */
2320         azx_free_cmd_io(chip);
2321
2322         /* disable position buffer */
2323         azx_writel(chip, DPLBASE, 0);
2324         azx_writel(chip, DPUBASE, 0);
2325
2326         chip->initialized = 0;
2327 }
2328
2329 #ifdef CONFIG_SND_HDA_POWER_SAVE
2330 /* power-up/down the controller */
2331 static void azx_power_notify(struct hda_bus *bus)
2332 {
2333         struct azx *chip = bus->private_data;
2334         struct hda_codec *c;
2335         int power_on = 0;
2336
2337         list_for_each_entry(c, &bus->codec_list, list) {
2338                 if (c->power_on) {
2339                         power_on = 1;
2340                         break;
2341                 }
2342         }
2343         if (power_on)
2344                 azx_init_chip(chip, 1);
2345         else if (chip->running && power_save_controller &&
2346                  !bus->power_keep_link_on)
2347                 azx_stop_chip(chip);
2348 }
2349 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2350
2351 #ifdef CONFIG_PM
2352 /*
2353  * power management
2354  */
2355
2356 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2357 {
2358         struct hda_codec *codec;
2359
2360         list_for_each_entry(codec, &bus->codec_list, list) {
2361                 if (snd_hda_codec_needs_resume(codec))
2362                         return 1;
2363         }
2364         return 0;
2365 }
2366
2367 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2368 {
2369         struct snd_card *card = pci_get_drvdata(pci);
2370         struct azx *chip = card->private_data;
2371         struct azx_pcm *p;
2372
2373         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2374         azx_clear_irq_pending(chip);
2375         list_for_each_entry(p, &chip->pcm_list, list)
2376                 snd_pcm_suspend_all(p->pcm);
2377         if (chip->initialized)
2378                 snd_hda_suspend(chip->bus);
2379         azx_stop_chip(chip);
2380         if (chip->irq >= 0) {
2381                 free_irq(chip->irq, chip);
2382                 chip->irq = -1;
2383         }
2384         if (chip->msi)
2385                 pci_disable_msi(chip->pci);
2386         pci_disable_device(pci);
2387         pci_save_state(pci);
2388         pci_set_power_state(pci, pci_choose_state(pci, state));
2389         return 0;
2390 }
2391
2392 static int azx_resume(struct pci_dev *pci)
2393 {
2394         struct snd_card *card = pci_get_drvdata(pci);
2395         struct azx *chip = card->private_data;
2396
2397         pci_set_power_state(pci, PCI_D0);
2398         pci_restore_state(pci);
2399         if (pci_enable_device(pci) < 0) {
2400                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2401                        "disabling device\n");
2402                 snd_card_disconnect(card);
2403                 return -EIO;
2404         }
2405         pci_set_master(pci);
2406         if (chip->msi)
2407                 if (pci_enable_msi(pci) < 0)
2408                         chip->msi = 0;
2409         if (azx_acquire_irq(chip, 1) < 0)
2410                 return -EIO;
2411         azx_init_pci(chip);
2412
2413         if (snd_hda_codecs_inuse(chip->bus))
2414                 azx_init_chip(chip, 1);
2415
2416         snd_hda_resume(chip->bus);
2417         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2418         return 0;
2419 }
2420 #endif /* CONFIG_PM */
2421
2422
2423 /*
2424  * reboot notifier for hang-up problem at power-down
2425  */
2426 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2427 {
2428         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2429         snd_hda_bus_reboot_notify(chip->bus);
2430         azx_stop_chip(chip);
2431         return NOTIFY_OK;
2432 }
2433
2434 static void azx_notifier_register(struct azx *chip)
2435 {
2436         chip->reboot_notifier.notifier_call = azx_halt;
2437         register_reboot_notifier(&chip->reboot_notifier);
2438 }
2439
2440 static void azx_notifier_unregister(struct azx *chip)
2441 {
2442         if (chip->reboot_notifier.notifier_call)
2443                 unregister_reboot_notifier(&chip->reboot_notifier);
2444 }
2445
2446 /*
2447  * destructor
2448  */
2449 static int azx_free(struct azx *chip)
2450 {
2451         int i;
2452
2453         azx_notifier_unregister(chip);
2454
2455         if (chip->initialized) {
2456                 azx_clear_irq_pending(chip);
2457                 for (i = 0; i < chip->num_streams; i++)
2458                         azx_stream_stop(chip, &chip->azx_dev[i]);
2459                 azx_stop_chip(chip);
2460         }
2461
2462         if (chip->irq >= 0)
2463                 free_irq(chip->irq, (void*)chip);
2464         if (chip->msi)
2465                 pci_disable_msi(chip->pci);
2466         if (chip->remap_addr)
2467                 iounmap(chip->remap_addr);
2468
2469         if (chip->azx_dev) {
2470                 for (i = 0; i < chip->num_streams; i++)
2471                         if (chip->azx_dev[i].bdl.area) {
2472                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2473                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2474                         }
2475         }
2476         if (chip->rb.area) {
2477                 mark_pages_wc(chip, &chip->rb, false);
2478                 snd_dma_free_pages(&chip->rb);
2479         }
2480         if (chip->posbuf.area) {
2481                 mark_pages_wc(chip, &chip->posbuf, false);
2482                 snd_dma_free_pages(&chip->posbuf);
2483         }
2484         pci_release_regions(chip->pci);
2485         pci_disable_device(chip->pci);
2486         kfree(chip->azx_dev);
2487         kfree(chip);
2488
2489         return 0;
2490 }
2491
2492 static int azx_dev_free(struct snd_device *device)
2493 {
2494         return azx_free(device->device_data);
2495 }
2496
2497 /*
2498  * white/black-listing for position_fix
2499  */
2500 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2501         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2502         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2503         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2504         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2505         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2506         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2507         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2508         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2509         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2510         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2511         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2512         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2513         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2514         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2515         {}
2516 };
2517
2518 static int __devinit check_position_fix(struct azx *chip, int fix)
2519 {
2520         const struct snd_pci_quirk *q;
2521
2522         switch (fix) {
2523         case POS_FIX_LPIB:
2524         case POS_FIX_POSBUF:
2525         case POS_FIX_VIACOMBO:
2526         case POS_FIX_COMBO:
2527                 return fix;
2528         }
2529
2530         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2531         if (q) {
2532                 printk(KERN_INFO
2533                        "hda_intel: position_fix set to %d "
2534                        "for device %04x:%04x\n",
2535                        q->value, q->subvendor, q->subdevice);
2536                 return q->value;
2537         }
2538
2539         /* Check VIA/ATI HD Audio Controller exist */
2540         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2541                 snd_printd(SFX "Using VIACOMBO position fix\n");
2542                 return POS_FIX_VIACOMBO;
2543         }
2544         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2545                 snd_printd(SFX "Using LPIB position fix\n");
2546                 return POS_FIX_LPIB;
2547         }
2548         return POS_FIX_AUTO;
2549 }
2550
2551 /*
2552  * black-lists for probe_mask
2553  */
2554 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2555         /* Thinkpad often breaks the controller communication when accessing
2556          * to the non-working (or non-existing) modem codec slot.
2557          */
2558         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2559         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2560         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2561         /* broken BIOS */
2562         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2563         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2564         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2565         /* forced codec slots */
2566         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2567         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2568         {}
2569 };
2570
2571 #define AZX_FORCE_CODEC_MASK    0x100
2572
2573 static void __devinit check_probe_mask(struct azx *chip, int dev)
2574 {
2575         const struct snd_pci_quirk *q;
2576
2577         chip->codec_probe_mask = probe_mask[dev];
2578         if (chip->codec_probe_mask == -1) {
2579                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2580                 if (q) {
2581                         printk(KERN_INFO
2582                                "hda_intel: probe_mask set to 0x%x "
2583                                "for device %04x:%04x\n",
2584                                q->value, q->subvendor, q->subdevice);
2585                         chip->codec_probe_mask = q->value;
2586                 }
2587         }
2588
2589         /* check forced option */
2590         if (chip->codec_probe_mask != -1 &&
2591             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2592                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2593                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2594                        chip->codec_mask);
2595         }
2596 }
2597
2598 /*
2599  * white/black-list for enable_msi
2600  */
2601 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2602         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2603         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2604         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2605         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2606         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2607         {}
2608 };
2609
2610 static void __devinit check_msi(struct azx *chip)
2611 {
2612         const struct snd_pci_quirk *q;
2613
2614         if (enable_msi >= 0) {
2615                 chip->msi = !!enable_msi;
2616                 return;
2617         }
2618         chip->msi = 1;  /* enable MSI as default */
2619         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2620         if (q) {
2621                 printk(KERN_INFO
2622                        "hda_intel: msi for device %04x:%04x set to %d\n",
2623                        q->subvendor, q->subdevice, q->value);
2624                 chip->msi = q->value;
2625                 return;
2626         }
2627
2628         /* NVidia chipsets seem to cause troubles with MSI */
2629         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2630                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2631                 chip->msi = 0;
2632         }
2633 }
2634
2635 /* check the snoop mode availability */
2636 static void __devinit azx_check_snoop_available(struct azx *chip)
2637 {
2638         bool snoop = chip->snoop;
2639
2640         switch (chip->driver_type) {
2641         case AZX_DRIVER_VIA:
2642                 /* force to non-snoop mode for a new VIA controller
2643                  * when BIOS is set
2644                  */
2645                 if (snoop) {
2646                         u8 val;
2647                         pci_read_config_byte(chip->pci, 0x42, &val);
2648                         if (!(val & 0x80) && chip->pci->revision == 0x30)
2649                                 snoop = false;
2650                 }
2651                 break;
2652         case AZX_DRIVER_ATIHDMI_NS:
2653                 /* new ATI HDMI requires non-snoop */
2654                 snoop = false;
2655                 break;
2656         }
2657
2658         if (snoop != chip->snoop) {
2659                 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2660                            snoop ? "snoop" : "non-snoop");
2661                 chip->snoop = snoop;
2662         }
2663 }
2664
2665 /*
2666  * constructor
2667  */
2668 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2669                                 int dev, unsigned int driver_caps,
2670                                 struct azx **rchip)
2671 {
2672         struct azx *chip;
2673         int i, err;
2674         unsigned short gcap;
2675         static struct snd_device_ops ops = {
2676                 .dev_free = azx_dev_free,
2677         };
2678
2679         *rchip = NULL;
2680
2681         err = pci_enable_device(pci);
2682         if (err < 0)
2683                 return err;
2684
2685         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2686         if (!chip) {
2687                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2688                 pci_disable_device(pci);
2689                 return -ENOMEM;
2690         }
2691
2692         spin_lock_init(&chip->reg_lock);
2693         mutex_init(&chip->open_mutex);
2694         chip->card = card;
2695         chip->pci = pci;
2696         chip->irq = -1;
2697         chip->driver_caps = driver_caps;
2698         chip->driver_type = driver_caps & 0xff;
2699         check_msi(chip);
2700         chip->dev_index = dev;
2701         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2702         INIT_LIST_HEAD(&chip->pcm_list);
2703
2704         chip->position_fix[0] = chip->position_fix[1] =
2705                 check_position_fix(chip, position_fix[dev]);
2706         /* combo mode uses LPIB for playback */
2707         if (chip->position_fix[0] == POS_FIX_COMBO) {
2708                 chip->position_fix[0] = POS_FIX_LPIB;
2709                 chip->position_fix[1] = POS_FIX_AUTO;
2710         }
2711
2712         check_probe_mask(chip, dev);
2713
2714         chip->single_cmd = single_cmd;
2715         chip->snoop = hda_snoop;
2716         azx_check_snoop_available(chip);
2717
2718         if (bdl_pos_adj[dev] < 0) {
2719                 switch (chip->driver_type) {
2720                 case AZX_DRIVER_ICH:
2721                 case AZX_DRIVER_PCH:
2722                         bdl_pos_adj[dev] = 1;
2723                         break;
2724                 default:
2725                         bdl_pos_adj[dev] = 32;
2726                         break;
2727                 }
2728         }
2729
2730 #if BITS_PER_LONG != 64
2731         /* Fix up base address on ULI M5461 */
2732         if (chip->driver_type == AZX_DRIVER_ULI) {
2733                 u16 tmp3;
2734                 pci_read_config_word(pci, 0x40, &tmp3);
2735                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2736                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2737         }
2738 #endif
2739
2740         err = pci_request_regions(pci, "ICH HD audio");
2741         if (err < 0) {
2742                 kfree(chip);
2743                 pci_disable_device(pci);
2744                 return err;
2745         }
2746
2747         chip->addr = pci_resource_start(pci, 0);
2748         chip->remap_addr = pci_ioremap_bar(pci, 0);
2749         if (chip->remap_addr == NULL) {
2750                 snd_printk(KERN_ERR SFX "ioremap error\n");
2751                 err = -ENXIO;
2752                 goto errout;
2753         }
2754
2755         if (chip->msi)
2756                 if (pci_enable_msi(pci) < 0)
2757                         chip->msi = 0;
2758
2759         if (azx_acquire_irq(chip, 0) < 0) {
2760                 err = -EBUSY;
2761                 goto errout;
2762         }
2763
2764         pci_set_master(pci);
2765         synchronize_irq(chip->irq);
2766
2767         gcap = azx_readw(chip, GCAP);
2768         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2769
2770         /* disable SB600 64bit support for safety */
2771         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2772                 struct pci_dev *p_smbus;
2773                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2774                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2775                                          NULL);
2776                 if (p_smbus) {
2777                         if (p_smbus->revision < 0x30)
2778                                 gcap &= ~ICH6_GCAP_64OK;
2779                         pci_dev_put(p_smbus);
2780                 }
2781         }
2782
2783         /* disable 64bit DMA address on some devices */
2784         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2785                 snd_printd(SFX "Disabling 64bit DMA\n");
2786                 gcap &= ~ICH6_GCAP_64OK;
2787         }
2788
2789         /* disable buffer size rounding to 128-byte multiples if supported */
2790         if (align_buffer_size >= 0)
2791                 chip->align_buffer_size = !!align_buffer_size;
2792         else {
2793                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2794                         chip->align_buffer_size = 0;
2795                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
2796                         chip->align_buffer_size = 1;
2797                 else
2798                         chip->align_buffer_size = 1;
2799         }
2800
2801         /* allow 64bit DMA address if supported by H/W */
2802         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2803                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2804         else {
2805                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2806                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2807         }
2808
2809         /* read number of streams from GCAP register instead of using
2810          * hardcoded value
2811          */
2812         chip->capture_streams = (gcap >> 8) & 0x0f;
2813         chip->playback_streams = (gcap >> 12) & 0x0f;
2814         if (!chip->playback_streams && !chip->capture_streams) {
2815                 /* gcap didn't give any info, switching to old method */
2816
2817                 switch (chip->driver_type) {
2818                 case AZX_DRIVER_ULI:
2819                         chip->playback_streams = ULI_NUM_PLAYBACK;
2820                         chip->capture_streams = ULI_NUM_CAPTURE;
2821                         break;
2822                 case AZX_DRIVER_ATIHDMI:
2823                 case AZX_DRIVER_ATIHDMI_NS:
2824                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2825                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2826                         break;
2827                 case AZX_DRIVER_GENERIC:
2828                 default:
2829                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2830                         chip->capture_streams = ICH6_NUM_CAPTURE;
2831                         break;
2832                 }
2833         }
2834         chip->capture_index_offset = 0;
2835         chip->playback_index_offset = chip->capture_streams;
2836         chip->num_streams = chip->playback_streams + chip->capture_streams;
2837         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2838                                 GFP_KERNEL);
2839         if (!chip->azx_dev) {
2840                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2841                 goto errout;
2842         }
2843
2844         for (i = 0; i < chip->num_streams; i++) {
2845                 /* allocate memory for the BDL for each stream */
2846                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2847                                           snd_dma_pci_data(chip->pci),
2848                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2849                 if (err < 0) {
2850                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2851                         goto errout;
2852                 }
2853                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
2854         }
2855         /* allocate memory for the position buffer */
2856         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2857                                   snd_dma_pci_data(chip->pci),
2858                                   chip->num_streams * 8, &chip->posbuf);
2859         if (err < 0) {
2860                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2861                 goto errout;
2862         }
2863         mark_pages_wc(chip, &chip->posbuf, true);
2864         /* allocate CORB/RIRB */
2865         err = azx_alloc_cmd_io(chip);
2866         if (err < 0)
2867                 goto errout;
2868
2869         /* initialize streams */
2870         azx_init_stream(chip);
2871
2872         /* initialize chip */
2873         azx_init_pci(chip);
2874         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2875
2876         /* codec detection */
2877         if (!chip->codec_mask) {
2878                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2879                 err = -ENODEV;
2880                 goto errout;
2881         }
2882
2883         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2884         if (err <0) {
2885                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2886                 goto errout;
2887         }
2888
2889         strcpy(card->driver, "HDA-Intel");
2890         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2891                 sizeof(card->shortname));
2892         snprintf(card->longname, sizeof(card->longname),
2893                  "%s at 0x%lx irq %i",
2894                  card->shortname, chip->addr, chip->irq);
2895
2896         *rchip = chip;
2897         return 0;
2898
2899  errout:
2900         azx_free(chip);
2901         return err;
2902 }
2903
2904 static void power_down_all_codecs(struct azx *chip)
2905 {
2906 #ifdef CONFIG_SND_HDA_POWER_SAVE
2907         /* The codecs were powered up in snd_hda_codec_new().
2908          * Now all initialization done, so turn them down if possible
2909          */
2910         struct hda_codec *codec;
2911         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2912                 snd_hda_power_down(codec);
2913         }
2914 #endif
2915 }
2916
2917 static int __devinit azx_probe(struct pci_dev *pci,
2918                                const struct pci_device_id *pci_id)
2919 {
2920         static int dev;
2921         struct snd_card *card;
2922         struct azx *chip;
2923         int err;
2924
2925         if (dev >= SNDRV_CARDS)
2926                 return -ENODEV;
2927         if (!enable[dev]) {
2928                 dev++;
2929                 return -ENOENT;
2930         }
2931
2932         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2933         if (err < 0) {
2934                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2935                 return err;
2936         }
2937
2938         /* set this here since it's referred in snd_hda_load_patch() */
2939         snd_card_set_dev(card, &pci->dev);
2940
2941         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2942         if (err < 0)
2943                 goto out_free;
2944         card->private_data = chip;
2945
2946 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2947         chip->beep_mode = beep_mode[dev];
2948 #endif
2949
2950         /* create codec instances */
2951         err = azx_codec_create(chip, model[dev]);
2952         if (err < 0)
2953                 goto out_free;
2954 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2955         if (patch[dev] && *patch[dev]) {
2956                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2957                            patch[dev]);
2958                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2959                 if (err < 0)
2960                         goto out_free;
2961         }
2962 #endif
2963         if ((probe_only[dev] & 1) == 0) {
2964                 err = azx_codec_configure(chip);
2965                 if (err < 0)
2966                         goto out_free;
2967         }
2968
2969         /* create PCM streams */
2970         err = snd_hda_build_pcms(chip->bus);
2971         if (err < 0)
2972                 goto out_free;
2973
2974         /* create mixer controls */
2975         err = azx_mixer_create(chip);
2976         if (err < 0)
2977                 goto out_free;
2978
2979         err = snd_card_register(card);
2980         if (err < 0)
2981                 goto out_free;
2982
2983         pci_set_drvdata(pci, card);
2984         chip->running = 1;
2985         power_down_all_codecs(chip);
2986         azx_notifier_register(chip);
2987
2988         dev++;
2989         return err;
2990 out_free:
2991         snd_card_free(card);
2992         return err;
2993 }
2994
2995 static void __devexit azx_remove(struct pci_dev *pci)
2996 {
2997         snd_card_free(pci_get_drvdata(pci));
2998         pci_set_drvdata(pci, NULL);
2999 }
3000
3001 /* PCI IDs */
3002 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3003         /* CPT */
3004         { PCI_DEVICE(0x8086, 0x1c20),
3005           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3006           AZX_DCAPS_BUFSIZE },
3007         /* PBG */
3008         { PCI_DEVICE(0x8086, 0x1d20),
3009           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3010           AZX_DCAPS_BUFSIZE},
3011         /* Panther Point */
3012         { PCI_DEVICE(0x8086, 0x1e20),
3013           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3014           AZX_DCAPS_BUFSIZE},
3015         /* Lynx Point */
3016         { PCI_DEVICE(0x8086, 0x8c20),
3017           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3018           AZX_DCAPS_BUFSIZE},
3019         /* SCH */
3020         { PCI_DEVICE(0x8086, 0x811b),
3021           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3022           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3023         { PCI_DEVICE(0x8086, 0x080a),
3024           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3025           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3026         /* ICH */
3027         { PCI_DEVICE(0x8086, 0x2668),
3028           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3029           AZX_DCAPS_BUFSIZE },  /* ICH6 */
3030         { PCI_DEVICE(0x8086, 0x27d8),
3031           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3032           AZX_DCAPS_BUFSIZE },  /* ICH7 */
3033         { PCI_DEVICE(0x8086, 0x269a),
3034           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3035           AZX_DCAPS_BUFSIZE },  /* ESB2 */
3036         { PCI_DEVICE(0x8086, 0x284b),
3037           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3038           AZX_DCAPS_BUFSIZE },  /* ICH8 */
3039         { PCI_DEVICE(0x8086, 0x293e),
3040           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3041           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3042         { PCI_DEVICE(0x8086, 0x293f),
3043           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3044           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3045         { PCI_DEVICE(0x8086, 0x3a3e),
3046           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3047           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3048         { PCI_DEVICE(0x8086, 0x3a6e),
3049           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3050           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3051         /* Generic Intel */
3052         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3053           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3054           .class_mask = 0xffffff,
3055           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3056         /* ATI SB 450/600/700/800/900 */
3057         { PCI_DEVICE(0x1002, 0x437b),
3058           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3059         { PCI_DEVICE(0x1002, 0x4383),
3060           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3061         /* AMD Hudson */
3062         { PCI_DEVICE(0x1022, 0x780d),
3063           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3064         /* ATI HDMI */
3065         { PCI_DEVICE(0x1002, 0x793b),
3066           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3067         { PCI_DEVICE(0x1002, 0x7919),
3068           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3069         { PCI_DEVICE(0x1002, 0x960f),
3070           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3071         { PCI_DEVICE(0x1002, 0x970f),
3072           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3073         { PCI_DEVICE(0x1002, 0xaa00),
3074           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3075         { PCI_DEVICE(0x1002, 0xaa08),
3076           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3077         { PCI_DEVICE(0x1002, 0xaa10),
3078           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3079         { PCI_DEVICE(0x1002, 0xaa18),
3080           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3081         { PCI_DEVICE(0x1002, 0xaa20),
3082           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3083         { PCI_DEVICE(0x1002, 0xaa28),
3084           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3085         { PCI_DEVICE(0x1002, 0xaa30),
3086           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3087         { PCI_DEVICE(0x1002, 0xaa38),
3088           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3089         { PCI_DEVICE(0x1002, 0xaa40),
3090           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3091         { PCI_DEVICE(0x1002, 0xaa48),
3092           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3093         { PCI_DEVICE(0x1002, 0x9902),
3094           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3095         { PCI_DEVICE(0x1002, 0xaaa0),
3096           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3097         { PCI_DEVICE(0x1002, 0xaaa8),
3098           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3099         { PCI_DEVICE(0x1002, 0xaab0),
3100           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3101         /* VIA VT8251/VT8237A */
3102         { PCI_DEVICE(0x1106, 0x3288),
3103           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3104         /* SIS966 */
3105         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3106         /* ULI M5461 */
3107         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3108         /* NVIDIA MCP */
3109         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3110           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3111           .class_mask = 0xffffff,
3112           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3113         /* Teradici */
3114         { PCI_DEVICE(0x6549, 0x1200),
3115           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3116         /* Creative X-Fi (CA0110-IBG) */
3117 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3118         /* the following entry conflicts with snd-ctxfi driver,
3119          * as ctxfi driver mutates from HD-audio to native mode with
3120          * a special command sequence.
3121          */
3122         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3123           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3124           .class_mask = 0xffffff,
3125           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3126           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3127 #else
3128         /* this entry seems still valid -- i.e. without emu20kx chip */
3129         { PCI_DEVICE(0x1102, 0x0009),
3130           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3131           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3132 #endif
3133         /* Vortex86MX */
3134         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3135         /* VMware HDAudio */
3136         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3137         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3138         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3139           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3140           .class_mask = 0xffffff,
3141           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3142         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3143           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3144           .class_mask = 0xffffff,
3145           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3146         { 0, }
3147 };
3148 MODULE_DEVICE_TABLE(pci, azx_ids);
3149
3150 /* pci_driver definition */
3151 static struct pci_driver driver = {
3152         .name = KBUILD_MODNAME,
3153         .id_table = azx_ids,
3154         .probe = azx_probe,
3155         .remove = __devexit_p(azx_remove),
3156 #ifdef CONFIG_PM
3157         .suspend = azx_suspend,
3158         .resume = azx_resume,
3159 #endif
3160 };
3161
3162 static int __init alsa_card_azx_init(void)
3163 {
3164         return pci_register_driver(&driver);
3165 }
3166
3167 static void __exit alsa_card_azx_exit(void)
3168 {
3169         pci_unregister_driver(&driver);
3170 }
3171
3172 module_init(alsa_card_azx_init)
3173 module_exit(alsa_card_azx_exit)