drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 /*
  38  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  39  * over cache flushing.
  40  */
  41 struct pipe_control {
  42         struct drm_i915_gem_object *obj;
  43         volatile u32 *cpu_page;
  44         u32 gtt_offset;
  45 };
  46
  47 static inline int ring_space(struct intel_ring_buffer *ring)
  48 {
  49         int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
  50         if (space < 0)
  51                 space += ring->size;
  52         return space;
  53 }
  54
  55 static int
  56 render_ring_flush(struct intel_ring_buffer *ring,
  57                   u32   invalidate_domains,
  58                   u32   flush_domains)
  59 {
  60         struct drm_device *dev = ring->dev;
  61         u32 cmd;
  62         int ret;
  63
  64         /*
  65          * read/write caches:
  66          *
  67          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  68          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  69          * also flushed at 2d versus 3d pipeline switches.
  70          *
  71          * read-only caches:
  72          *
  73          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  74          * MI_READ_FLUSH is set, and is always flushed on 965.
  75          *
  76          * I915_GEM_DOMAIN_COMMAND may not exist?
  77          *
  78          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
  79          * invalidated when MI_EXE_FLUSH is set.
  80          *
  81          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
  82          * invalidated with every MI_FLUSH.
  83          *
  84          * TLBs:
  85          *
  86          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
  87          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
  88          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
  89          * are flushed at any MI_FLUSH.
  90          */
  91
  92         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
  93         if ((invalidate_domains|flush_domains) &
  94             I915_GEM_DOMAIN_RENDER)
  95                 cmd &= ~MI_NO_WRITE_FLUSH;
  96         if (INTEL_INFO(dev)->gen < 4) {
  97                 /*
  98                  * On the 965, the sampler cache always gets flushed
  99                  * and this bit is reserved.
 100                  */
 101                 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 102                         cmd |= MI_READ_FLUSH;
 103         }
 104         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 105                 cmd |= MI_EXE_FLUSH;
 106
 107         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 108             (IS_G4X(dev) || IS_GEN5(dev)))
 109                 cmd |= MI_INVALIDATE_ISP;
 110
 111         ret = intel_ring_begin(ring, 2);
 112         if (ret)
 113                 return ret;
 114
 115         intel_ring_emit(ring, cmd);
 116         intel_ring_emit(ring, MI_NOOP);
 117         intel_ring_advance(ring);
 118
 119         return 0;
 120 }
 121
 122 /**
 123  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 124  * implementing two workarounds on gen6.  From section 1.4.7.1
 125  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 126  *
 127  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 128  * produced by non-pipelined state commands), software needs to first
 129  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 130  * 0.
 131  *
 132  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 133  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 134  *
 135  * And the workaround for these two requires this workaround first:
 136  *
 137  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 138  * BEFORE the pipe-control with a post-sync op and no write-cache
 139  * flushes.
 140  *
 141  * And this last workaround is tricky because of the requirements on
 142  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 143  * volume 2 part 1:
 144  *
 145  *     "1 of the following must also be set:
 146  *      - Render Target Cache Flush Enable ([12] of DW1)
 147  *      - Depth Cache Flush Enable ([0] of DW1)
 148  *      - Stall at Pixel Scoreboard ([1] of DW1)
 149  *      - Depth Stall ([13] of DW1)
 150  *      - Post-Sync Operation ([13] of DW1)
 151  *      - Notify Enable ([8] of DW1)"
 152  *
 153  * The cache flushes require the workaround flush that triggered this
 154  * one, so we can't use it.  Depth stall would trigger the same.
 155  * Post-sync nonzero is what triggered this second workaround, so we
 156  * can't use that one either.  Notify enable is IRQs, which aren't
 157  * really our business.  That leaves only stall at scoreboard.
 158  */
 159 static int
 160 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 161 {
 162         struct pipe_control *pc = ring->private;
 163         u32 scratch_addr = pc->gtt_offset + 128;
 164         int ret;
 165
 166
 167         ret = intel_ring_begin(ring, 6);
 168         if (ret)
 169                 return ret;
 170
 171         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 172         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 173                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 174         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 175         intel_ring_emit(ring, 0); /* low dword */
 176         intel_ring_emit(ring, 0); /* high dword */
 177         intel_ring_emit(ring, MI_NOOP);
 178         intel_ring_advance(ring);
 179
 180         ret = intel_ring_begin(ring, 6);
 181         if (ret)
 182                 return ret;
 183
 184         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 185         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 186         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 187         intel_ring_emit(ring, 0);
 188         intel_ring_emit(ring, 0);
 189         intel_ring_emit(ring, MI_NOOP);
 190         intel_ring_advance(ring);
 191
 192         return 0;
 193 }
 194
 195 static int
 196 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 197                          u32 invalidate_domains, u32 flush_domains)
 198 {
 199         u32 flags = 0;
 200         struct pipe_control *pc = ring->private;
 201         u32 scratch_addr = pc->gtt_offset + 128;
 202         int ret;
 203
 204         /* Force SNB workarounds for PIPE_CONTROL flushes */
 205         intel_emit_post_sync_nonzero_flush(ring);
 206
 207         /* Just flush everything.  Experiments have shown that reducing the
 208          * number of bits based on the write domains has little performance
 209          * impact.
 210          */
 211         flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 212         flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 213         flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 214         flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 215         flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 216         flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 217         flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 218
 219         ret = intel_ring_begin(ring, 6);
 220         if (ret)
 221                 return ret;
 222
 223         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 224         intel_ring_emit(ring, flags);
 225         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 226         intel_ring_emit(ring, 0); /* lower dword */
 227         intel_ring_emit(ring, 0); /* uppwer dword */
 228         intel_ring_emit(ring, MI_NOOP);
 229         intel_ring_advance(ring);
 230
 231         return 0;
 232 }
 233
 234 static void ring_write_tail(struct intel_ring_buffer *ring,
 235                             u32 value)
 236 {
 237         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 238         I915_WRITE_TAIL(ring, value);
 239 }
 240
 241 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 242 {
 243         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 244         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 245                         RING_ACTHD(ring->mmio_base) : ACTHD;
 246
 247         return I915_READ(acthd_reg);
 248 }
 249
 250 static int init_ring_common(struct intel_ring_buffer *ring)
 251 {
 252         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 253         struct drm_i915_gem_object *obj = ring->obj;
 254         u32 head;
 255
 256         /* Stop the ring if it's running. */
 257         I915_WRITE_CTL(ring, 0);
 258         I915_WRITE_HEAD(ring, 0);
 259         ring->write_tail(ring, 0);
 260
 261         /* Initialize the ring. */
 262         I915_WRITE_START(ring, obj->gtt_offset);
 263         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 264
 265         /* G45 ring initialization fails to reset head to zero */
 266         if (head != 0) {
 267                 DRM_DEBUG_KMS("%s head not reset to zero "
 268                               "ctl %08x head %08x tail %08x start %08x\n",
 269                               ring->name,
 270                               I915_READ_CTL(ring),
 271                               I915_READ_HEAD(ring),
 272                               I915_READ_TAIL(ring),
 273                               I915_READ_START(ring));
 274
 275                 I915_WRITE_HEAD(ring, 0);
 276
 277                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 278                         DRM_ERROR("failed to set %s head to zero "
 279                                   "ctl %08x head %08x tail %08x start %08x\n",
 280                                   ring->name,
 281                                   I915_READ_CTL(ring),
 282                                   I915_READ_HEAD(ring),
 283                                   I915_READ_TAIL(ring),
 284                                   I915_READ_START(ring));
 285                 }
 286         }
 287
 288         I915_WRITE_CTL(ring,
 289                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 290                         | RING_VALID);
 291
 292         /* If the head is still not zero, the ring is dead */
 293         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
 294             I915_READ_START(ring) != obj->gtt_offset ||
 295             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
 296                 DRM_ERROR("%s initialization failed "
 297                                 "ctl %08x head %08x tail %08x start %08x\n",
 298                                 ring->name,
 299                                 I915_READ_CTL(ring),
 300                                 I915_READ_HEAD(ring),
 301                                 I915_READ_TAIL(ring),
 302                                 I915_READ_START(ring));
 303                 return -EIO;
 304         }
 305
 306         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 307                 i915_kernel_lost_context(ring->dev);
 308         else {
 309                 ring->head = I915_READ_HEAD(ring);
 310                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 311                 ring->space = ring_space(ring);
 312         }
 313
 314         return 0;
 315 }
 316
 317 static int
 318 init_pipe_control(struct intel_ring_buffer *ring)
 319 {
 320         struct pipe_control *pc;
 321         struct drm_i915_gem_object *obj;
 322         int ret;
 323
 324         if (ring->private)
 325                 return 0;
 326
 327         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 328         if (!pc)
 329                 return -ENOMEM;
 330
 331         obj = i915_gem_alloc_object(ring->dev, 4096);
 332         if (obj == NULL) {
 333                 DRM_ERROR("Failed to allocate seqno page\n");
 334                 ret = -ENOMEM;
 335                 goto err;
 336         }
 337
 338         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 339
 340         ret = i915_gem_object_pin(obj, 4096, true);
 341         if (ret)
 342                 goto err_unref;
 343
 344         pc->gtt_offset = obj->gtt_offset;
 345         pc->cpu_page =  kmap(obj->pages[0]);
 346         if (pc->cpu_page == NULL)
 347                 goto err_unpin;
 348
 349         pc->obj = obj;
 350         ring->private = pc;
 351         return 0;
 352
 353 err_unpin:
 354         i915_gem_object_unpin(obj);
 355 err_unref:
 356         drm_gem_object_unreference(&obj->base);
 357 err:
 358         kfree(pc);
 359         return ret;
 360 }
 361
 362 static void
 363 cleanup_pipe_control(struct intel_ring_buffer *ring)
 364 {
 365         struct pipe_control *pc = ring->private;
 366         struct drm_i915_gem_object *obj;
 367
 368         if (!ring->private)
 369                 return;
 370
 371         obj = pc->obj;
 372         kunmap(obj->pages[0]);
 373         i915_gem_object_unpin(obj);
 374         drm_gem_object_unreference(&obj->base);
 375
 376         kfree(pc);
 377         ring->private = NULL;
 378 }
 379
 380 static int init_render_ring(struct intel_ring_buffer *ring)
 381 {
 382         struct drm_device *dev = ring->dev;
 383         struct drm_i915_private *dev_priv = dev->dev_private;
 384         int ret = init_ring_common(ring);
 385
 386         if (INTEL_INFO(dev)->gen > 3) {
 387                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
 388                 I915_WRITE(MI_MODE, mode);
 389                 if (IS_GEN7(dev))
 390                         I915_WRITE(GFX_MODE_GEN7,
 391                                    GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 392                                    GFX_MODE_ENABLE(GFX_REPLAY_MODE));
 393         }
 394
 395         if (INTEL_INFO(dev)->gen >= 5) {
 396                 ret = init_pipe_control(ring);
 397                 if (ret)
 398                         return ret;
 399         }
 400
 401
 402         if (IS_GEN6(dev)) {
 403                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 404                  * "If this bit is set, STCunit will have LRA as replacement
 405                  *  policy. [...] This bit must be reset.  LRA replacement
 406                  *  policy is not supported."
 407                  */
 408                 I915_WRITE(CACHE_MODE_0,
 409                            CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
 410         }
 411
 412         if (INTEL_INFO(dev)->gen >= 6) {
 413                 I915_WRITE(INSTPM,
 414                            INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
 415         }
 416
 417         return ret;
 418 }
 419
 420 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 421 {
 422         if (!ring->private)
 423                 return;
 424
 425         cleanup_pipe_control(ring);
 426 }
 427
 428 static void
 429 update_mboxes(struct intel_ring_buffer *ring,
 430             u32 seqno,
 431             u32 mmio_offset)
 432 {
 433         intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
 434                               MI_SEMAPHORE_GLOBAL_GTT |
 435                               MI_SEMAPHORE_REGISTER |
 436                               MI_SEMAPHORE_UPDATE);
 437         intel_ring_emit(ring, seqno);
 438         intel_ring_emit(ring, mmio_offset);
 439 }
 440
 441 /**
 442  * gen6_add_request - Update the semaphore mailbox registers
 443  *
 444  * @ring - ring that is adding a request
 445  * @seqno - return seqno stuck into the ring
 446  *
 447  * Update the mailbox registers in the *other* rings with the current seqno.
 448  * This acts like a signal in the canonical semaphore.
 449  */
 450 static int
 451 gen6_add_request(struct intel_ring_buffer *ring,
 452                  u32 *seqno)
 453 {
 454         u32 mbox1_reg;
 455         u32 mbox2_reg;
 456         int ret;
 457
 458         ret = intel_ring_begin(ring, 10);
 459         if (ret)
 460                 return ret;
 461
 462         mbox1_reg = ring->signal_mbox[0];
 463         mbox2_reg = ring->signal_mbox[1];
 464
 465         *seqno = i915_gem_next_request_seqno(ring);
 466
 467         update_mboxes(ring, *seqno, mbox1_reg);
 468         update_mboxes(ring, *seqno, mbox2_reg);
 469         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 470         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 471         intel_ring_emit(ring, *seqno);
 472         intel_ring_emit(ring, MI_USER_INTERRUPT);
 473         intel_ring_advance(ring);
 474
 475         return 0;
 476 }
 477
 478 /**
 479  * intel_ring_sync - sync the waiter to the signaller on seqno
 480  *
 481  * @waiter - ring that is waiting
 482  * @signaller - ring which has, or will signal
 483  * @seqno - seqno which the waiter will block on
 484  */
 485 static int
 486 intel_ring_sync(struct intel_ring_buffer *waiter,
 487                 struct intel_ring_buffer *signaller,
 488                 int ring,
 489                 u32 seqno)
 490 {
 491         int ret;
 492         u32 dw1 = MI_SEMAPHORE_MBOX |
 493                   MI_SEMAPHORE_COMPARE |
 494                   MI_SEMAPHORE_REGISTER;
 495
 496         ret = intel_ring_begin(waiter, 4);
 497         if (ret)
 498                 return ret;
 499
 500         intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
 501         intel_ring_emit(waiter, seqno);
 502         intel_ring_emit(waiter, 0);
 503         intel_ring_emit(waiter, MI_NOOP);
 504         intel_ring_advance(waiter);
 505
 506         return 0;
 507 }
 508
 509 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
 510 int
 511 render_ring_sync_to(struct intel_ring_buffer *waiter,
 512                     struct intel_ring_buffer *signaller,
 513                     u32 seqno)
 514 {
 515         WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
 516         return intel_ring_sync(waiter,
 517                                signaller,
 518                                RCS,
 519                                seqno);
 520 }
 521
 522 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
 523 int
 524 gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
 525                       struct intel_ring_buffer *signaller,
 526                       u32 seqno)
 527 {
 528         WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
 529         return intel_ring_sync(waiter,
 530                                signaller,
 531                                VCS,
 532                                seqno);
 533 }
 534
 535 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
 536 int
 537 gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
 538                       struct intel_ring_buffer *signaller,
 539                       u32 seqno)
 540 {
 541         WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
 542         return intel_ring_sync(waiter,
 543                                signaller,
 544                                BCS,
 545                                seqno);
 546 }
 547
 548
 549
 550 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 551 do {                                                                    \
 552         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 553                  PIPE_CONTROL_DEPTH_STALL);                             \
 554         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 555         intel_ring_emit(ring__, 0);                                                     \
 556         intel_ring_emit(ring__, 0);                                                     \
 557 } while (0)
 558
 559 static int
 560 pc_render_add_request(struct intel_ring_buffer *ring,
 561                       u32 *result)
 562 {
 563         u32 seqno = i915_gem_next_request_seqno(ring);
 564         struct pipe_control *pc = ring->private;
 565         u32 scratch_addr = pc->gtt_offset + 128;
 566         int ret;
 567
 568         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 569          * incoherent with writes to memory, i.e. completely fubar,
 570          * so we need to use PIPE_NOTIFY instead.
 571          *
 572          * However, we also need to workaround the qword write
 573          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 574          * memory before requesting an interrupt.
 575          */
 576         ret = intel_ring_begin(ring, 32);
 577         if (ret)
 578                 return ret;
 579
 580         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 581                         PIPE_CONTROL_WRITE_FLUSH |
 582                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 583         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 584         intel_ring_emit(ring, seqno);
 585         intel_ring_emit(ring, 0);
 586         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 587         scratch_addr += 128; /* write to separate cachelines */
 588         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 589         scratch_addr += 128;
 590         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 591         scratch_addr += 128;
 592         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 593         scratch_addr += 128;
 594         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 595         scratch_addr += 128;
 596         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 597
 598         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 599                         PIPE_CONTROL_WRITE_FLUSH |
 600                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 601                         PIPE_CONTROL_NOTIFY);
 602         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 603         intel_ring_emit(ring, seqno);
 604         intel_ring_emit(ring, 0);
 605         intel_ring_advance(ring);
 606
 607         *result = seqno;
 608         return 0;
 609 }
 610
 611 static int
 612 render_ring_add_request(struct intel_ring_buffer *ring,
 613                         u32 *result)
 614 {
 615         u32 seqno = i915_gem_next_request_seqno(ring);
 616         int ret;
 617
 618         ret = intel_ring_begin(ring, 4);
 619         if (ret)
 620                 return ret;
 621
 622         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 623         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 624         intel_ring_emit(ring, seqno);
 625         intel_ring_emit(ring, MI_USER_INTERRUPT);
 626         intel_ring_advance(ring);
 627
 628         *result = seqno;
 629         return 0;
 630 }
 631
 632 static u32
 633 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
 634 {
 635         struct drm_device *dev = ring->dev;
 636
 637         /* Workaround to force correct ordering between irq and seqno writes on
 638          * ivb (and maybe also on snb) by reading from a CS register (like
 639          * ACTHD) before reading the status page. */
 640         if (IS_GEN6(dev) || IS_GEN7(dev))
 641                 intel_ring_get_active_head(ring);
 642         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 643 }
 644
 645 static u32
 646 ring_get_seqno(struct intel_ring_buffer *ring)
 647 {
 648         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 649 }
 650
 651 static u32
 652 pc_render_get_seqno(struct intel_ring_buffer *ring)
 653 {
 654         struct pipe_control *pc = ring->private;
 655         return pc->cpu_page[0];
 656 }
 657
 658 static void
 659 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 660 {
 661         dev_priv->gt_irq_mask &= ~mask;
 662         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 663         POSTING_READ(GTIMR);
 664 }
 665
 666 static void
 667 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 668 {
 669         dev_priv->gt_irq_mask |= mask;
 670         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 671         POSTING_READ(GTIMR);
 672 }
 673
 674 static void
 675 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 676 {
 677         dev_priv->irq_mask &= ~mask;
 678         I915_WRITE(IMR, dev_priv->irq_mask);
 679         POSTING_READ(IMR);
 680 }
 681
 682 static void
 683 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 684 {
 685         dev_priv->irq_mask |= mask;
 686         I915_WRITE(IMR, dev_priv->irq_mask);
 687         POSTING_READ(IMR);
 688 }
 689
 690 static bool
 691 render_ring_get_irq(struct intel_ring_buffer *ring)
 692 {
 693         struct drm_device *dev = ring->dev;
 694         drm_i915_private_t *dev_priv = dev->dev_private;
 695
 696         if (!dev->irq_enabled)
 697                 return false;
 698
 699         spin_lock(&ring->irq_lock);
 700         if (ring->irq_refcount++ == 0) {
 701                 if (HAS_PCH_SPLIT(dev))
 702                         ironlake_enable_irq(dev_priv,
 703                                             GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
 704                 else
 705                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 706         }
 707         spin_unlock(&ring->irq_lock);
 708
 709         return true;
 710 }
 711
 712 static void
 713 render_ring_put_irq(struct intel_ring_buffer *ring)
 714 {
 715         struct drm_device *dev = ring->dev;
 716         drm_i915_private_t *dev_priv = dev->dev_private;
 717
 718         spin_lock(&ring->irq_lock);
 719         if (--ring->irq_refcount == 0) {
 720                 if (HAS_PCH_SPLIT(dev))
 721                         ironlake_disable_irq(dev_priv,
 722                                              GT_USER_INTERRUPT |
 723                                              GT_PIPE_NOTIFY);
 724                 else
 725                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 726         }
 727         spin_unlock(&ring->irq_lock);
 728 }
 729
 730 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 731 {
 732         struct drm_device *dev = ring->dev;
 733         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 734         u32 mmio = 0;
 735
 736         /* The ring status page addresses are no longer next to the rest of
 737          * the ring registers as of gen7.
 738          */
 739         if (IS_GEN7(dev)) {
 740                 switch (ring->id) {
 741                 case RCS:
 742                         mmio = RENDER_HWS_PGA_GEN7;
 743                         break;
 744                 case BCS:
 745                         mmio = BLT_HWS_PGA_GEN7;
 746                         break;
 747                 case VCS:
 748                         mmio = BSD_HWS_PGA_GEN7;
 749                         break;
 750                 }
 751         } else if (IS_GEN6(ring->dev)) {
 752                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 753         } else {
 754                 mmio = RING_HWS_PGA(ring->mmio_base);
 755         }
 756
 757         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 758         POSTING_READ(mmio);
 759 }
 760
 761 static int
 762 bsd_ring_flush(struct intel_ring_buffer *ring,
 763                u32     invalidate_domains,
 764                u32     flush_domains)
 765 {
 766         int ret;
 767
 768         ret = intel_ring_begin(ring, 2);
 769         if (ret)
 770                 return ret;
 771
 772         intel_ring_emit(ring, MI_FLUSH);
 773         intel_ring_emit(ring, MI_NOOP);
 774         intel_ring_advance(ring);
 775         return 0;
 776 }
 777
 778 static int
 779 ring_add_request(struct intel_ring_buffer *ring,
 780                  u32 *result)
 781 {
 782         u32 seqno;
 783         int ret;
 784
 785         ret = intel_ring_begin(ring, 4);
 786         if (ret)
 787                 return ret;
 788
 789         seqno = i915_gem_next_request_seqno(ring);
 790
 791         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 792         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 793         intel_ring_emit(ring, seqno);
 794         intel_ring_emit(ring, MI_USER_INTERRUPT);
 795         intel_ring_advance(ring);
 796
 797         *result = seqno;
 798         return 0;
 799 }
 800
 801 static bool
 802 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 803 {
 804         struct drm_device *dev = ring->dev;
 805         drm_i915_private_t *dev_priv = dev->dev_private;
 806
 807         if (!dev->irq_enabled)
 808                return false;
 809
 810         /* It looks like we need to prevent the gt from suspending while waiting
 811          * for an notifiy irq, otherwise irqs seem to get lost on at least the
 812          * blt/bsd rings on ivb. */
 813         gen6_gt_force_wake_get(dev_priv);
 814
 815         spin_lock(&ring->irq_lock);
 816         if (ring->irq_refcount++ == 0) {
 817                 ring->irq_mask &= ~rflag;
 818                 I915_WRITE_IMR(ring, ring->irq_mask);
 819                 ironlake_enable_irq(dev_priv, gflag);
 820         }
 821         spin_unlock(&ring->irq_lock);
 822
 823         return true;
 824 }
 825
 826 static void
 827 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 828 {
 829         struct drm_device *dev = ring->dev;
 830         drm_i915_private_t *dev_priv = dev->dev_private;
 831
 832         spin_lock(&ring->irq_lock);
 833         if (--ring->irq_refcount == 0) {
 834                 ring->irq_mask |= rflag;
 835                 I915_WRITE_IMR(ring, ring->irq_mask);
 836                 ironlake_disable_irq(dev_priv, gflag);
 837         }
 838         spin_unlock(&ring->irq_lock);
 839
 840         gen6_gt_force_wake_put(dev_priv);
 841 }
 842
 843 static bool
 844 bsd_ring_get_irq(struct intel_ring_buffer *ring)
 845 {
 846         struct drm_device *dev = ring->dev;
 847         drm_i915_private_t *dev_priv = dev->dev_private;
 848
 849         if (!dev->irq_enabled)
 850                 return false;
 851
 852         spin_lock(&ring->irq_lock);
 853         if (ring->irq_refcount++ == 0) {
 854                 if (IS_G4X(dev))
 855                         i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
 856                 else
 857                         ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
 858         }
 859         spin_unlock(&ring->irq_lock);
 860
 861         return true;
 862 }
 863 static void
 864 bsd_ring_put_irq(struct intel_ring_buffer *ring)
 865 {
 866         struct drm_device *dev = ring->dev;
 867         drm_i915_private_t *dev_priv = dev->dev_private;
 868
 869         spin_lock(&ring->irq_lock);
 870         if (--ring->irq_refcount == 0) {
 871                 if (IS_G4X(dev))
 872                         i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
 873                 else
 874                         ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
 875         }
 876         spin_unlock(&ring->irq_lock);
 877 }
 878
 879 static int
 880 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
 881 {
 882         int ret;
 883
 884         ret = intel_ring_begin(ring, 2);
 885         if (ret)
 886                 return ret;
 887
 888         intel_ring_emit(ring,
 889                         MI_BATCH_BUFFER_START | (2 << 6) |
 890                         MI_BATCH_NON_SECURE_I965);
 891         intel_ring_emit(ring, offset);
 892         intel_ring_advance(ring);
 893
 894         return 0;
 895 }
 896
 897 static int
 898 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 899                                 u32 offset, u32 len)
 900 {
 901         struct drm_device *dev = ring->dev;
 902         int ret;
 903
 904         if (IS_I830(dev) || IS_845G(dev)) {
 905                 ret = intel_ring_begin(ring, 4);
 906                 if (ret)
 907                         return ret;
 908
 909                 intel_ring_emit(ring, MI_BATCH_BUFFER);
 910                 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 911                 intel_ring_emit(ring, offset + len - 8);
 912                 intel_ring_emit(ring, 0);
 913         } else {
 914                 ret = intel_ring_begin(ring, 2);
 915                 if (ret)
 916                         return ret;
 917
 918                 if (INTEL_INFO(dev)->gen >= 4) {
 919                         intel_ring_emit(ring,
 920                                         MI_BATCH_BUFFER_START | (2 << 6) |
 921                                         MI_BATCH_NON_SECURE_I965);
 922                         intel_ring_emit(ring, offset);
 923                 } else {
 924                         intel_ring_emit(ring,
 925                                         MI_BATCH_BUFFER_START | (2 << 6));
 926                         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 927                 }
 928         }
 929         intel_ring_advance(ring);
 930
 931         return 0;
 932 }
 933
 934 static void cleanup_status_page(struct intel_ring_buffer *ring)
 935 {
 936         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 937         struct drm_i915_gem_object *obj;
 938
 939         obj = ring->status_page.obj;
 940         if (obj == NULL)
 941                 return;
 942
 943         kunmap(obj->pages[0]);
 944         i915_gem_object_unpin(obj);
 945         drm_gem_object_unreference(&obj->base);
 946         ring->status_page.obj = NULL;
 947
 948         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 949 }
 950
 951 static int init_status_page(struct intel_ring_buffer *ring)
 952 {
 953         struct drm_device *dev = ring->dev;
 954         drm_i915_private_t *dev_priv = dev->dev_private;
 955         struct drm_i915_gem_object *obj;
 956         int ret;
 957
 958         obj = i915_gem_alloc_object(dev, 4096);
 959         if (obj == NULL) {
 960                 DRM_ERROR("Failed to allocate status page\n");
 961                 ret = -ENOMEM;
 962                 goto err;
 963         }
 964
 965         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 966
 967         ret = i915_gem_object_pin(obj, 4096, true);
 968         if (ret != 0) {
 969                 goto err_unref;
 970         }
 971
 972         ring->status_page.gfx_addr = obj->gtt_offset;
 973         ring->status_page.page_addr = kmap(obj->pages[0]);
 974         if (ring->status_page.page_addr == NULL) {
 975                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 976                 goto err_unpin;
 977         }
 978         ring->status_page.obj = obj;
 979         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 980
 981         intel_ring_setup_status_page(ring);
 982         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 983                         ring->name, ring->status_page.gfx_addr);
 984
 985         return 0;
 986
 987 err_unpin:
 988         i915_gem_object_unpin(obj);
 989 err_unref:
 990         drm_gem_object_unreference(&obj->base);
 991 err:
 992         return ret;
 993 }
 994
 995 int intel_init_ring_buffer(struct drm_device *dev,
 996                            struct intel_ring_buffer *ring)
 997 {
 998         struct drm_i915_gem_object *obj;
 999         int ret;
1000
1001         ring->dev = dev;
1002         INIT_LIST_HEAD(&ring->active_list);
1003         INIT_LIST_HEAD(&ring->request_list);
1004         INIT_LIST_HEAD(&ring->gpu_write_list);
1005
1006         init_waitqueue_head(&ring->irq_queue);
1007         spin_lock_init(&ring->irq_lock);
1008         ring->irq_mask = ~0;
1009
1010         if (I915_NEED_GFX_HWS(dev)) {
1011                 ret = init_status_page(ring);
1012                 if (ret)
1013                         return ret;
1014         }
1015
1016         obj = i915_gem_alloc_object(dev, ring->size);
1017         if (obj == NULL) {
1018                 DRM_ERROR("Failed to allocate ringbuffer\n");
1019                 ret = -ENOMEM;
1020                 goto err_hws;
1021         }
1022
1023         ring->obj = obj;
1024
1025         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1026         if (ret)
1027                 goto err_unref;
1028
1029         ring->map.size = ring->size;
1030         ring->map.offset = dev->agp->base + obj->gtt_offset;
1031         ring->map.type = 0;
1032         ring->map.flags = 0;
1033         ring->map.mtrr = 0;
1034
1035         drm_core_ioremap_wc(&ring->map, dev);
1036         if (ring->map.handle == NULL) {
1037                 DRM_ERROR("Failed to map ringbuffer.\n");
1038                 ret = -EINVAL;
1039                 goto err_unpin;
1040         }
1041
1042         ring->virtual_start = ring->map.handle;
1043         ret = ring->init(ring);
1044         if (ret)
1045                 goto err_unmap;
1046
1047         /* Workaround an erratum on the i830 which causes a hang if
1048          * the TAIL pointer points to within the last 2 cachelines
1049          * of the buffer.
1050          */
1051         ring->effective_size = ring->size;
1052         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1053                 ring->effective_size -= 128;
1054
1055         return 0;
1056
1057 err_unmap:
1058         drm_core_ioremapfree(&ring->map, dev);
1059 err_unpin:
1060         i915_gem_object_unpin(obj);
1061 err_unref:
1062         drm_gem_object_unreference(&obj->base);
1063         ring->obj = NULL;
1064 err_hws:
1065         cleanup_status_page(ring);
1066         return ret;
1067 }
1068
1069 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1070 {
1071         struct drm_i915_private *dev_priv;
1072         int ret;
1073
1074         if (ring->obj == NULL)
1075                 return;
1076
1077         /* Disable the ring buffer. The ring must be idle at this point */
1078         dev_priv = ring->dev->dev_private;
1079         ret = intel_wait_ring_idle(ring);
1080         if (ret)
1081                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1082                           ring->name, ret);
1083
1084         I915_WRITE_CTL(ring, 0);
1085
1086         drm_core_ioremapfree(&ring->map, ring->dev);
1087
1088         i915_gem_object_unpin(ring->obj);
1089         drm_gem_object_unreference(&ring->obj->base);
1090         ring->obj = NULL;
1091
1092         if (ring->cleanup)
1093                 ring->cleanup(ring);
1094
1095         cleanup_status_page(ring);
1096 }
1097
1098 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1099 {
1100         unsigned int *virt;
1101         int rem = ring->size - ring->tail;
1102
1103         if (ring->space < rem) {
1104                 int ret = intel_wait_ring_buffer(ring, rem);
1105                 if (ret)
1106                         return ret;
1107         }
1108
1109         virt = (unsigned int *)(ring->virtual_start + ring->tail);
1110         rem /= 8;
1111         while (rem--) {
1112                 *virt++ = MI_NOOP;
1113                 *virt++ = MI_NOOP;
1114         }
1115
1116         ring->tail = 0;
1117         ring->space = ring_space(ring);
1118
1119         return 0;
1120 }
1121
1122 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1123 {
1124         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1125         bool was_interruptible;
1126         int ret;
1127
1128         /* XXX As we have not yet audited all the paths to check that
1129          * they are ready for ERESTARTSYS from intel_ring_begin, do not
1130          * allow us to be interruptible by a signal.
1131          */
1132         was_interruptible = dev_priv->mm.interruptible;
1133         dev_priv->mm.interruptible = false;
1134
1135         ret = i915_wait_request(ring, seqno, true);
1136
1137         dev_priv->mm.interruptible = was_interruptible;
1138
1139         return ret;
1140 }
1141
1142 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1143 {
1144         struct drm_i915_gem_request *request;
1145         u32 seqno = 0;
1146         int ret;
1147
1148         i915_gem_retire_requests_ring(ring);
1149
1150         if (ring->last_retired_head != -1) {
1151                 ring->head = ring->last_retired_head;
1152                 ring->last_retired_head = -1;
1153                 ring->space = ring_space(ring);
1154                 if (ring->space >= n)
1155                         return 0;
1156         }
1157
1158         list_for_each_entry(request, &ring->request_list, list) {
1159                 int space;
1160
1161                 if (request->tail == -1)
1162                         continue;
1163
1164                 space = request->tail - (ring->tail + 8);
1165                 if (space < 0)
1166                         space += ring->size;
1167                 if (space >= n) {
1168                         seqno = request->seqno;
1169                         break;
1170                 }
1171
1172                 /* Consume this request in case we need more space than
1173                  * is available and so need to prevent a race between
1174                  * updating last_retired_head and direct reads of
1175                  * I915_RING_HEAD. It also provides a nice sanity check.
1176                  */
1177                 request->tail = -1;
1178         }
1179
1180         if (seqno == 0)
1181                 return -ENOSPC;
1182
1183         ret = intel_ring_wait_seqno(ring, seqno);
1184         if (ret)
1185                 return ret;
1186
1187         if (WARN_ON(ring->last_retired_head == -1))
1188                 return -ENOSPC;
1189
1190         ring->head = ring->last_retired_head;
1191         ring->last_retired_head = -1;
1192         ring->space = ring_space(ring);
1193         if (WARN_ON(ring->space < n))
1194                 return -ENOSPC;
1195
1196         return 0;
1197 }
1198
1199 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1200 {
1201         struct drm_device *dev = ring->dev;
1202         struct drm_i915_private *dev_priv = dev->dev_private;
1203         unsigned long end;
1204         int ret;
1205
1206         ret = intel_ring_wait_request(ring, n);
1207         if (ret != -ENOSPC)
1208                 return ret;
1209
1210         trace_i915_ring_wait_begin(ring);
1211         if (drm_core_check_feature(dev, DRIVER_GEM))
1212                 /* With GEM the hangcheck timer should kick us out of the loop,
1213                  * leaving it early runs the risk of corrupting GEM state (due
1214                  * to running on almost untested codepaths). But on resume
1215                  * timers don't work yet, so prevent a complete hang in that
1216                  * case by choosing an insanely large timeout. */
1217                 end = jiffies + 60 * HZ;
1218         else
1219                 end = jiffies + 3 * HZ;
1220
1221         do {
1222                 ring->head = I915_READ_HEAD(ring);
1223                 ring->space = ring_space(ring);
1224                 if (ring->space >= n) {
1225                         trace_i915_ring_wait_end(ring);
1226                         return 0;
1227                 }
1228
1229                 if (dev->primary->master) {
1230                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1231                         if (master_priv->sarea_priv)
1232                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1233                 }
1234
1235                 msleep(1);
1236                 if (atomic_read(&dev_priv->mm.wedged))
1237                         return -EAGAIN;
1238         } while (!time_after(jiffies, end));
1239         trace_i915_ring_wait_end(ring);
1240         return -EBUSY;
1241 }
1242
1243 int intel_ring_begin(struct intel_ring_buffer *ring,
1244                      int num_dwords)
1245 {
1246         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1247         int n = 4*num_dwords;
1248         int ret;
1249
1250         if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1251                 return -EIO;
1252
1253         if (unlikely(ring->tail + n > ring->effective_size)) {
1254                 ret = intel_wrap_ring_buffer(ring);
1255                 if (unlikely(ret))
1256                         return ret;
1257         }
1258
1259         if (unlikely(ring->space < n)) {
1260                 ret = intel_wait_ring_buffer(ring, n);
1261                 if (unlikely(ret))
1262                         return ret;
1263         }
1264
1265         ring->space -= n;
1266         return 0;
1267 }
1268
1269 void intel_ring_advance(struct intel_ring_buffer *ring)
1270 {
1271         ring->tail &= ring->size - 1;
1272         ring->write_tail(ring, ring->tail);
1273 }
1274
1275 static const struct intel_ring_buffer render_ring = {
1276         .name                   = "render ring",
1277         .id                     = RCS,
1278         .mmio_base              = RENDER_RING_BASE,
1279         .size                   = 32 * PAGE_SIZE,
1280         .init                   = init_render_ring,
1281         .write_tail             = ring_write_tail,
1282         .flush                  = render_ring_flush,
1283         .add_request            = render_ring_add_request,
1284         .get_seqno              = ring_get_seqno,
1285         .irq_get                = render_ring_get_irq,
1286         .irq_put                = render_ring_put_irq,
1287         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
1288         .cleanup                = render_ring_cleanup,
1289         .sync_to                = render_ring_sync_to,
1290         .semaphore_register     = {MI_SEMAPHORE_SYNC_INVALID,
1291                                    MI_SEMAPHORE_SYNC_RV,
1292                                    MI_SEMAPHORE_SYNC_RB},
1293         .signal_mbox            = {GEN6_VRSYNC, GEN6_BRSYNC},
1294 };
1295
1296 /* ring buffer for bit-stream decoder */
1297
1298 static const struct intel_ring_buffer bsd_ring = {
1299         .name                   = "bsd ring",
1300         .id                     = VCS,
1301         .mmio_base              = BSD_RING_BASE,
1302         .size                   = 32 * PAGE_SIZE,
1303         .init                   = init_ring_common,
1304         .write_tail             = ring_write_tail,
1305         .flush                  = bsd_ring_flush,
1306         .add_request            = ring_add_request,
1307         .get_seqno              = ring_get_seqno,
1308         .irq_get                = bsd_ring_get_irq,
1309         .irq_put                = bsd_ring_put_irq,
1310         .dispatch_execbuffer    = ring_dispatch_execbuffer,
1311 };
1312
1313
1314 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1315                                      u32 value)
1316 {
1317         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1318
1319        /* Every tail move must follow the sequence below */
1320         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1321                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1322                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1323         I915_WRITE(GEN6_BSD_RNCID, 0x0);
1324
1325         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1326                 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1327                 50))
1328         DRM_ERROR("timed out waiting for IDLE Indicator\n");
1329
1330         I915_WRITE_TAIL(ring, value);
1331         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1332                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1333                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1334 }
1335
1336 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1337                            u32 invalidate, u32 flush)
1338 {
1339         uint32_t cmd;
1340         int ret;
1341
1342         ret = intel_ring_begin(ring, 4);
1343         if (ret)
1344                 return ret;
1345
1346         cmd = MI_FLUSH_DW;
1347         if (invalidate & I915_GEM_GPU_DOMAINS)
1348                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1349         intel_ring_emit(ring, cmd);
1350         intel_ring_emit(ring, 0);
1351         intel_ring_emit(ring, 0);
1352         intel_ring_emit(ring, MI_NOOP);
1353         intel_ring_advance(ring);
1354         return 0;
1355 }
1356
1357 static int
1358 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1359                               u32 offset, u32 len)
1360 {
1361         int ret;
1362
1363         ret = intel_ring_begin(ring, 2);
1364         if (ret)
1365                 return ret;
1366
1367         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1368         /* bit0-7 is the length on GEN6+ */
1369         intel_ring_emit(ring, offset);
1370         intel_ring_advance(ring);
1371
1372         return 0;
1373 }
1374
1375 static bool
1376 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1377 {
1378         return gen6_ring_get_irq(ring,
1379                                  GT_USER_INTERRUPT,
1380                                  GEN6_RENDER_USER_INTERRUPT);
1381 }
1382
1383 static void
1384 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1385 {
1386         return gen6_ring_put_irq(ring,
1387                                  GT_USER_INTERRUPT,
1388                                  GEN6_RENDER_USER_INTERRUPT);
1389 }
1390
1391 static bool
1392 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1393 {
1394         return gen6_ring_get_irq(ring,
1395                                  GT_GEN6_BSD_USER_INTERRUPT,
1396                                  GEN6_BSD_USER_INTERRUPT);
1397 }
1398
1399 static void
1400 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1401 {
1402         return gen6_ring_put_irq(ring,
1403                                  GT_GEN6_BSD_USER_INTERRUPT,
1404                                  GEN6_BSD_USER_INTERRUPT);
1405 }
1406
1407 /* ring buffer for Video Codec for Gen6+ */
1408 static const struct intel_ring_buffer gen6_bsd_ring = {
1409         .name                   = "gen6 bsd ring",
1410         .id                     = VCS,
1411         .mmio_base              = GEN6_BSD_RING_BASE,
1412         .size                   = 32 * PAGE_SIZE,
1413         .init                   = init_ring_common,
1414         .write_tail             = gen6_bsd_ring_write_tail,
1415         .flush                  = gen6_ring_flush,
1416         .add_request            = gen6_add_request,
1417         .get_seqno              = gen6_ring_get_seqno,
1418         .irq_get                = gen6_bsd_ring_get_irq,
1419         .irq_put                = gen6_bsd_ring_put_irq,
1420         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1421         .sync_to                = gen6_bsd_ring_sync_to,
1422         .semaphore_register     = {MI_SEMAPHORE_SYNC_VR,
1423                                    MI_SEMAPHORE_SYNC_INVALID,
1424                                    MI_SEMAPHORE_SYNC_VB},
1425         .signal_mbox            = {GEN6_RVSYNC, GEN6_BVSYNC},
1426 };
1427
1428 /* Blitter support (SandyBridge+) */
1429
1430 static bool
1431 blt_ring_get_irq(struct intel_ring_buffer *ring)
1432 {
1433         return gen6_ring_get_irq(ring,
1434                                  GT_BLT_USER_INTERRUPT,
1435                                  GEN6_BLITTER_USER_INTERRUPT);
1436 }
1437
1438 static void
1439 blt_ring_put_irq(struct intel_ring_buffer *ring)
1440 {
1441         gen6_ring_put_irq(ring,
1442                           GT_BLT_USER_INTERRUPT,
1443                           GEN6_BLITTER_USER_INTERRUPT);
1444 }
1445
1446 static int blt_ring_flush(struct intel_ring_buffer *ring,
1447                           u32 invalidate, u32 flush)
1448 {
1449         uint32_t cmd;
1450         int ret;
1451
1452         ret = intel_ring_begin(ring, 4);
1453         if (ret)
1454                 return ret;
1455
1456         cmd = MI_FLUSH_DW;
1457         if (invalidate & I915_GEM_DOMAIN_RENDER)
1458                 cmd |= MI_INVALIDATE_TLB;
1459         intel_ring_emit(ring, cmd);
1460         intel_ring_emit(ring, 0);
1461         intel_ring_emit(ring, 0);
1462         intel_ring_emit(ring, MI_NOOP);
1463         intel_ring_advance(ring);
1464         return 0;
1465 }
1466
1467 static const struct intel_ring_buffer gen6_blt_ring = {
1468         .name                   = "blt ring",
1469         .id                     = BCS,
1470         .mmio_base              = BLT_RING_BASE,
1471         .size                   = 32 * PAGE_SIZE,
1472         .init                   = init_ring_common,
1473         .write_tail             = ring_write_tail,
1474         .flush                  = blt_ring_flush,
1475         .add_request            = gen6_add_request,
1476         .get_seqno              = gen6_ring_get_seqno,
1477         .irq_get                = blt_ring_get_irq,
1478         .irq_put                = blt_ring_put_irq,
1479         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1480         .sync_to                = gen6_blt_ring_sync_to,
1481         .semaphore_register     = {MI_SEMAPHORE_SYNC_BR,
1482                                    MI_SEMAPHORE_SYNC_BV,
1483                                    MI_SEMAPHORE_SYNC_INVALID},
1484         .signal_mbox            = {GEN6_RBSYNC, GEN6_VBSYNC},
1485 };
1486
1487 int intel_init_render_ring_buffer(struct drm_device *dev)
1488 {
1489         drm_i915_private_t *dev_priv = dev->dev_private;
1490         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1491
1492         *ring = render_ring;
1493         if (INTEL_INFO(dev)->gen >= 6) {
1494                 ring->add_request = gen6_add_request;
1495                 ring->flush = gen6_render_ring_flush;
1496                 ring->irq_get = gen6_render_ring_get_irq;
1497                 ring->irq_put = gen6_render_ring_put_irq;
1498                 ring->get_seqno = gen6_ring_get_seqno;
1499         } else if (IS_GEN5(dev)) {
1500                 ring->add_request = pc_render_add_request;
1501                 ring->get_seqno = pc_render_get_seqno;
1502         }
1503
1504         if (!I915_NEED_GFX_HWS(dev)) {
1505                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1506                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1507         }
1508
1509         return intel_init_ring_buffer(dev, ring);
1510 }
1511
1512 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1513 {
1514         drm_i915_private_t *dev_priv = dev->dev_private;
1515         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1516
1517         *ring = render_ring;
1518         if (INTEL_INFO(dev)->gen >= 6) {
1519                 ring->add_request = gen6_add_request;
1520                 ring->irq_get = gen6_render_ring_get_irq;
1521                 ring->irq_put = gen6_render_ring_put_irq;
1522         } else if (IS_GEN5(dev)) {
1523                 ring->add_request = pc_render_add_request;
1524                 ring->get_seqno = pc_render_get_seqno;
1525         }
1526
1527         if (!I915_NEED_GFX_HWS(dev))
1528                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1529
1530         ring->dev = dev;
1531         INIT_LIST_HEAD(&ring->active_list);
1532         INIT_LIST_HEAD(&ring->request_list);
1533         INIT_LIST_HEAD(&ring->gpu_write_list);
1534
1535         ring->size = size;
1536         ring->effective_size = ring->size;
1537         if (IS_I830(ring->dev))
1538                 ring->effective_size -= 128;
1539
1540         ring->map.offset = start;
1541         ring->map.size = size;
1542         ring->map.type = 0;
1543         ring->map.flags = 0;
1544         ring->map.mtrr = 0;
1545
1546         drm_core_ioremap_wc(&ring->map, dev);
1547         if (ring->map.handle == NULL) {
1548                 DRM_ERROR("can not ioremap virtual address for"
1549                           " ring buffer\n");
1550                 return -ENOMEM;
1551         }
1552
1553         ring->virtual_start = (void __force __iomem *)ring->map.handle;
1554         return 0;
1555 }
1556
1557 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1558 {
1559         drm_i915_private_t *dev_priv = dev->dev_private;
1560         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1561
1562         if (IS_GEN6(dev) || IS_GEN7(dev))
1563                 *ring = gen6_bsd_ring;
1564         else
1565                 *ring = bsd_ring;
1566
1567         return intel_init_ring_buffer(dev, ring);
1568 }
1569
1570 int intel_init_blt_ring_buffer(struct drm_device *dev)
1571 {
1572         drm_i915_private_t *dev_priv = dev->dev_private;
1573         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1574
1575         *ring = gen6_blt_ring;
1576
1577         return intel_init_ring_buffer(dev, ring);
1578 }