3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
9 #ifndef _ASM_IA64_SN_SN1_HUBPI_H
10 #define _ASM_IA64_SN_SN1_HUBPI_H
12 /************************************************************************
14 * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! *
16 * This file is created by an automated script. Any (minimal) changes *
17 * made manually to this file should be made with care. *
19 * MAKE ALL ADDITIONS TO THE END OF THIS FILE *
21 ************************************************************************/
24 #define PI_CPU_PROTECT 0x00000000 /* CPU Protection */
28 #define PI_PROT_OVRRD 0x00000008 /*
36 #define PI_IO_PROTECT 0x00000010 /*
44 #define PI_REGION_PRESENT 0x00000018 /* Region present */
48 #define PI_CPU_NUM 0x00000020 /* CPU Number ID */
52 #define PI_CALIAS_SIZE 0x00000028 /* Cached Alias Size */
56 #define PI_MAX_CRB_TIMEOUT 0x00000030 /*
63 #define PI_CRB_SFACTOR 0x00000038 /*
70 #define PI_CPU_PRESENT_A 0x00000040 /*
77 #define PI_CPU_PRESENT_B 0x00000048 /*
84 #define PI_CPU_ENABLE_A 0x00000050 /*
91 #define PI_CPU_ENABLE_B 0x00000058 /*
98 #define PI_REPLY_LEVEL 0x00010060 /*
105 #define PI_GFX_CREDIT_MODE 0x00020068 /*
112 #define PI_NMI_A 0x00000070 /*
119 #define PI_NMI_B 0x00000078 /*
126 #define PI_INT_PEND_MOD 0x00000090 /*
133 #define PI_INT_PEND0 0x00000098 /* Interrupt Pending 0 */
137 #define PI_INT_PEND1 0x000000A0 /* Interrupt Pending 1 */
141 #define PI_INT_MASK0_A 0x000000A8 /*
148 #define PI_INT_MASK1_A 0x000000B0 /*
155 #define PI_INT_MASK0_B 0x000000B8 /*
162 #define PI_INT_MASK1_B 0x000000C0 /*
169 #define PI_CC_PEND_SET_A 0x000000C8 /*
176 #define PI_CC_PEND_SET_B 0x000000D0 /*
183 #define PI_CC_PEND_CLR_A 0x000000D8 /*
191 #define PI_CC_PEND_CLR_B 0x000000E0 /*
199 #define PI_CC_MASK 0x000000E8 /*
206 #define PI_INT_PEND1_REMAP 0x000000F0 /*
213 #define PI_RT_COUNTER 0x00030100 /* Real Time Counter */
217 #define PI_RT_COMPARE_A 0x00000108 /* Real Time Compare A */
221 #define PI_RT_COMPARE_B 0x00000110 /* Real Time Compare B */
225 #define PI_PROFILE_COMPARE 0x00000118 /* Profiling Compare */
229 #define PI_RT_INT_PEND_A 0x00000120 /*
236 #define PI_RT_INT_PEND_B 0x00000128 /*
243 #define PI_PROF_INT_PEND_A 0x00000130 /*
244 * Profiling interrupt
250 #define PI_PROF_INT_PEND_B 0x00000138 /*
251 * Profiling interrupt
257 #define PI_RT_INT_EN_A 0x00000140 /* RT Interrupt Enable */
261 #define PI_RT_INT_EN_B 0x00000148 /* RT Interrupt Enable */
265 #define PI_PROF_INT_EN_A 0x00000150 /*
266 * Profiling Interrupt
272 #define PI_PROF_INT_EN_B 0x00000158 /*
273 * Profiling Interrupt
279 #define PI_DEBUG_SEL 0x00000160 /* PI Debug Select */
283 #define PI_INT_PEND_MOD_ALIAS 0x00000180 /*
290 #define PI_PERF_CNTL_A 0x00040200 /*
291 * Performance Counter
297 #define PI_PERF_CNTR0_A 0x00040208 /*
298 * Performance Counter
304 #define PI_PERF_CNTR1_A 0x00040210 /*
305 * Performance Counter
311 #define PI_PERF_CNTL_B 0x00050200 /*
312 * Performance Counter
318 #define PI_PERF_CNTR0_B 0x00050208 /*
319 * Performance Counter
325 #define PI_PERF_CNTR1_B 0x00050210 /*
326 * Performance Counter
332 #define PI_GFX_PAGE_A 0x00000300 /* Graphics Page */
336 #define PI_GFX_CREDIT_CNTR_A 0x00000308 /*
343 #define PI_GFX_BIAS_A 0x00000310 /* TRex+ BIAS */
347 #define PI_GFX_INT_CNTR_A 0x00000318 /*
354 #define PI_GFX_INT_CMP_A 0x00000320 /*
361 #define PI_GFX_PAGE_B 0x00000328 /* Graphics Page */
365 #define PI_GFX_CREDIT_CNTR_B 0x00000330 /*
372 #define PI_GFX_BIAS_B 0x00000338 /* TRex+ BIAS */
376 #define PI_GFX_INT_CNTR_B 0x00000340 /*
383 #define PI_GFX_INT_CMP_B 0x00000348 /*
390 #define PI_ERR_INT_PEND_WR 0x000003F8 /*
397 #define PI_ERR_INT_PEND 0x00000400 /*
404 #define PI_ERR_INT_MASK_A 0x00000408 /*
411 #define PI_ERR_INT_MASK_B 0x00000410 /*
418 #define PI_ERR_STACK_ADDR_A 0x00000418 /*
419 * Error Stack Address
425 #define PI_ERR_STACK_ADDR_B 0x00000420 /*
426 * Error Stack Address
432 #define PI_ERR_STACK_SIZE 0x00000428 /* Error Stack Size */
436 #define PI_ERR_STATUS0_A 0x00000430 /* Error Status 0 */
440 #define PI_ERR_STATUS0_A_CLR 0x00000438 /* Error Status 0 */
444 #define PI_ERR_STATUS1_A 0x00000440 /* Error Status 1 */
448 #define PI_ERR_STATUS1_A_CLR 0x00000448 /* Error Status 1 */
452 #define PI_ERR_STATUS0_B 0x00000450 /* Error Status 0 */
456 #define PI_ERR_STATUS0_B_CLR 0x00000458 /* Error Status 0 */
460 #define PI_ERR_STATUS1_B 0x00000460 /* Error Status 1 */
464 #define PI_ERR_STATUS1_B_CLR 0x00000468 /* Error Status 1 */
468 #define PI_SPOOL_CMP_A 0x00000470 /* Spool Compare */
472 #define PI_SPOOL_CMP_B 0x00000478 /* Spool Compare */
476 #define PI_CRB_TIMEOUT_A 0x00000480 /*
484 #define PI_CRB_TIMEOUT_B 0x00000488 /*
492 #define PI_SYSAD_ERRCHK_EN 0x00000490 /*
500 #define PI_FORCE_BAD_CHECK_BIT_A 0x00000498 /*
507 #define PI_FORCE_BAD_CHECK_BIT_B 0x000004A0 /*
514 #define PI_NACK_CNT_A 0x000004A8 /*
521 #define PI_NACK_CNT_B 0x000004B0 /*
528 #define PI_NACK_CMP 0x000004B8 /* NACK count compare */
532 #define PI_SPOOL_MASK 0x000004C0 /* Spool error mask */
536 #define PI_SPURIOUS_HDR_0 0x000004C8 /* Spurious Error 0 */
540 #define PI_SPURIOUS_HDR_1 0x000004D0 /* Spurious Error 1 */
544 #define PI_ERR_INJECT 0x000004D8 /*
555 /************************************************************************
557 * Description: This read/write register determines on a *
558 * bit-per-region basis whether incoming CPU-initiated PIO Read and *
559 * Write to local PI registers are allowed. If access is allowed, the *
560 * PI's response to a partial read is a PRPLY message, and the *
561 * response to a partial write is a PACK message. If access is not *
562 * allowed, the PI's response to a partial read is a PRERR message, *
563 * and the response to a partial write is a PWERR message. *
564 * This register is not reset by a soft reset. *
566 ************************************************************************/
571 typedef union pi_cpu_protect_u {
572 bdrkreg_t pi_cpu_protect_regval;
574 bdrkreg_t cp_cpu_protect : 64;
575 } pi_cpu_protect_fld_s;
576 } pi_cpu_protect_u_t;
581 /************************************************************************
583 * A write with a special data pattern allows any CPU to set its *
584 * region's bit in CPU_PROTECT. This register has data pattern *
587 ************************************************************************/
592 typedef union pi_prot_ovrrd_u {
593 bdrkreg_t pi_prot_ovrrd_regval;
595 bdrkreg_t po_prot_ovrrd : 64;
596 } pi_prot_ovrrd_fld_s;
602 /************************************************************************
604 * Description: This read/write register determines on a *
605 * bit-per-region basis whether incoming IO-initiated interrupts are *
606 * allowed to set bits in INT_PEND0 and INT_PEND1. If access is *
607 * allowed, the PI's response to a partial read is a PRPLY message, *
608 * and the response to a partial write is a PACK message. If access *
609 * is not allowed, the PI's response to a partial read is a PRERR *
610 * message, and the response to a partial write is a PWERR message. *
611 * This register is not reset by a soft reset. *
613 ************************************************************************/
618 typedef union pi_io_protect_u {
619 bdrkreg_t pi_io_protect_regval;
621 bdrkreg_t ip_io_protect : 64;
622 } pi_io_protect_fld_s;
628 /************************************************************************
630 * Description: This read/write register determines on a *
631 * bit-per-region basis whether read access from a local processor to *
632 * the region is permissible. For example, setting a bit to 0 *
633 * prevents speculative reads to that non-existent node. If a read *
634 * request to a non-present region occurs, an ERR response is issued *
635 * to the TRex+ (no PI error registers are modified). It is up to *
636 * software to load this register with the proper contents. *
637 * Region-present checking is only done for coherent read requests - *
638 * partial reads/writes will be issued to a non-present region. The *
639 * setting of these bits does not affect a node's access to its *
641 * This register is not reset by a soft reset. *
643 ************************************************************************/
648 typedef union pi_region_present_u {
649 bdrkreg_t pi_region_present_regval;
651 bdrkreg_t rp_region_present : 64;
652 } pi_region_present_fld_s;
653 } pi_region_present_u_t;
658 /************************************************************************
660 * A read to the location will allow a CPU to identify itself as *
661 * either CPU_A or CPU_B, and will indicate whether the CPU is *
662 * connected to PI 0 or PI 1. *
664 ************************************************************************/
671 typedef union pi_cpu_num_u {
672 bdrkreg_t pi_cpu_num_regval;
674 bdrkreg_t cn_cpu_num : 1;
675 bdrkreg_t cn_pi_id : 1;
676 bdrkreg_t cn_rsvd : 62;
682 typedef union pi_cpu_num_u {
683 bdrkreg_t pi_cpu_num_regval;
685 bdrkreg_t cn_rsvd : 62;
686 bdrkreg_t cn_pi_id : 1;
687 bdrkreg_t cn_cpu_num : 1;
696 /************************************************************************
698 * Description: This read/write location determines the size of the *
700 * This register is not reset by a soft reset. *
701 * NOTE: For predictable behavior, all Calias spaces in a system must *
702 * be set to the same size. *
704 ************************************************************************/
711 typedef union pi_calias_size_u {
712 bdrkreg_t pi_calias_size_regval;
714 bdrkreg_t cs_calias_size : 4;
715 bdrkreg_t cs_rsvd : 60;
716 } pi_calias_size_fld_s;
717 } pi_calias_size_u_t;
721 typedef union pi_calias_size_u {
722 bdrkreg_t pi_calias_size_regval;
724 bdrkreg_t cs_rsvd : 60;
725 bdrkreg_t cs_calias_size : 4;
726 } pi_calias_size_fld_s;
727 } pi_calias_size_u_t;
734 /************************************************************************
736 * This Read/Write location determines at which value (increment) *
737 * the CRB Timeout Counters cause a timeout error to occur. See *
738 * Section 3.4.2.2, "Time-outs in RRB and WRB" in the *
739 * Processor Interface chapter, volume 1 of this document for more *
742 ************************************************************************/
749 typedef union pi_max_crb_timeout_u {
750 bdrkreg_t pi_max_crb_timeout_regval;
752 bdrkreg_t mct_max_timeout : 8;
753 bdrkreg_t mct_rsvd : 56;
754 } pi_max_crb_timeout_fld_s;
755 } pi_max_crb_timeout_u_t;
759 typedef union pi_max_crb_timeout_u {
760 bdrkreg_t pi_max_crb_timeout_regval;
762 bdrkreg_t mct_rsvd : 56;
763 bdrkreg_t mct_max_timeout : 8;
764 } pi_max_crb_timeout_fld_s;
765 } pi_max_crb_timeout_u_t;
772 /************************************************************************
774 * This Read/Write location determines how often a valid CRB's *
775 * Timeout Counter is incremented. See Section 3.4.2.2, *
776 * "Time-outs in RRB and WRB" in the Processor Interface *
777 * chapter, volume 1 of this document for more details. *
779 ************************************************************************/
786 typedef union pi_crb_sfactor_u {
787 bdrkreg_t pi_crb_sfactor_regval;
789 bdrkreg_t cs_sfactor : 24;
790 bdrkreg_t cs_rsvd : 40;
791 } pi_crb_sfactor_fld_s;
792 } pi_crb_sfactor_u_t;
796 typedef union pi_crb_sfactor_u {
797 bdrkreg_t pi_crb_sfactor_regval;
799 bdrkreg_t cs_rsvd : 40;
800 bdrkreg_t cs_sfactor : 24;
801 } pi_crb_sfactor_fld_s;
802 } pi_crb_sfactor_u_t;
809 /************************************************************************
811 * There is one of these registers for each CPU. The PI sets this *
812 * bit when it sees the first transaction initiated by the associated *
815 ************************************************************************/
822 typedef union pi_cpu_present_a_u {
823 bdrkreg_t pi_cpu_present_a_regval;
825 bdrkreg_t cpa_cpu_present : 1;
826 bdrkreg_t cpa_rsvd : 63;
827 } pi_cpu_present_a_fld_s;
828 } pi_cpu_present_a_u_t;
832 typedef union pi_cpu_present_a_u {
833 bdrkreg_t pi_cpu_present_a_regval;
835 bdrkreg_t cpa_rsvd : 63;
836 bdrkreg_t cpa_cpu_present : 1;
837 } pi_cpu_present_a_fld_s;
838 } pi_cpu_present_a_u_t;
845 /************************************************************************
847 * There is one of these registers for each CPU. The PI sets this *
848 * bit when it sees the first transaction initiated by the associated *
851 ************************************************************************/
858 typedef union pi_cpu_present_b_u {
859 bdrkreg_t pi_cpu_present_b_regval;
861 bdrkreg_t cpb_cpu_present : 1;
862 bdrkreg_t cpb_rsvd : 63;
863 } pi_cpu_present_b_fld_s;
864 } pi_cpu_present_b_u_t;
868 typedef union pi_cpu_present_b_u {
869 bdrkreg_t pi_cpu_present_b_regval;
871 bdrkreg_t cpb_rsvd : 63;
872 bdrkreg_t cpb_cpu_present : 1;
873 } pi_cpu_present_b_fld_s;
874 } pi_cpu_present_b_u_t;
881 /************************************************************************
883 * Description: There is one of these registers for each CPU. This *
884 * Read/Write location determines whether the associated CPU is *
885 * enabled to issue external requests. When this bit is zero for a *
886 * processor, the PI ignores SysReq_L from that processor, and so *
887 * never grants it the bus. *
888 * This register is not reset by a soft reset. *
890 ************************************************************************/
897 typedef union pi_cpu_enable_a_u {
898 bdrkreg_t pi_cpu_enable_a_regval;
900 bdrkreg_t cea_cpu_enable : 1;
901 bdrkreg_t cea_rsvd : 63;
902 } pi_cpu_enable_a_fld_s;
903 } pi_cpu_enable_a_u_t;
907 typedef union pi_cpu_enable_a_u {
908 bdrkreg_t pi_cpu_enable_a_regval;
910 bdrkreg_t cea_rsvd : 63;
911 bdrkreg_t cea_cpu_enable : 1;
912 } pi_cpu_enable_a_fld_s;
913 } pi_cpu_enable_a_u_t;
920 /************************************************************************
922 * Description: There is one of these registers for each CPU. This *
923 * Read/Write location determines whether the associated CPU is *
924 * enabled to issue external requests. When this bit is zero for a *
925 * processor, the PI ignores SysReq_L from that processor, and so *
926 * never grants it the bus. *
927 * This register is not reset by a soft reset. *
929 ************************************************************************/
936 typedef union pi_cpu_enable_b_u {
937 bdrkreg_t pi_cpu_enable_b_regval;
939 bdrkreg_t ceb_cpu_enable : 1;
940 bdrkreg_t ceb_rsvd : 63;
941 } pi_cpu_enable_b_fld_s;
942 } pi_cpu_enable_b_u_t;
946 typedef union pi_cpu_enable_b_u {
947 bdrkreg_t pi_cpu_enable_b_regval;
949 bdrkreg_t ceb_rsvd : 63;
950 bdrkreg_t ceb_cpu_enable : 1;
951 } pi_cpu_enable_b_fld_s;
952 } pi_cpu_enable_b_u_t;
959 /************************************************************************
961 * There is one of these registers for each CPU. A write to this *
962 * location will cause an NMI to be issued to the CPU. *
964 ************************************************************************/
969 typedef union pi_nmi_a_u {
970 bdrkreg_t pi_nmi_a_regval;
972 bdrkreg_t na_nmi_cpu : 64;
979 /************************************************************************
981 * There is one of these registers for each CPU. A write to this *
982 * location will cause an NMI to be issued to the CPU. *
984 ************************************************************************/
989 typedef union pi_nmi_b_u {
990 bdrkreg_t pi_nmi_b_regval;
992 bdrkreg_t nb_nmi_cpu : 64;
999 /************************************************************************
1001 * A write to this register allows a single bit in the INT_PEND0 or *
1002 * INT_PEND1 registers to be set or cleared. If 6 is clear, a bit is *
1003 * modified in INT_PEND0, while if 6 is set, a bit is modified in *
1004 * INT_PEND1. The value in 5:0 (ranging from 63 to 0) will determine *
1005 * which bit in the register is effected. The value of 8 will *
1006 * determine whether the desired bit is set (8=1) or cleared (8=0). *
1007 * This is the only register which is accessible by IO issued PWRI *
1008 * command and is protected through the IO_PROTECT register. If the *
1009 * region bit in the IO_PROTECT is not set then a WERR reply is *
1010 * issued. CPU access is controlled through CPU_PROTECT. The contents *
1011 * of this register are masked with the contents of INT_MASK_A *
1012 * (INT_MASK_B) to determine whether an L2 interrupt is issued to *
1015 ************************************************************************/
1020 #ifdef LITTLE_ENDIAN
1022 typedef union pi_int_pend_mod_u {
1023 bdrkreg_t pi_int_pend_mod_regval;
1025 bdrkreg_t ipm_bit_select : 6;
1026 bdrkreg_t ipm_reg_select : 1;
1027 bdrkreg_t ipm_rsvd_1 : 1;
1028 bdrkreg_t ipm_value : 1;
1029 bdrkreg_t ipm_rsvd : 55;
1030 } pi_int_pend_mod_fld_s;
1031 } pi_int_pend_mod_u_t;
1035 typedef union pi_int_pend_mod_u {
1036 bdrkreg_t pi_int_pend_mod_regval;
1038 bdrkreg_t ipm_rsvd : 55;
1039 bdrkreg_t ipm_value : 1;
1040 bdrkreg_t ipm_rsvd_1 : 1;
1041 bdrkreg_t ipm_reg_select : 1;
1042 bdrkreg_t ipm_bit_select : 6;
1043 } pi_int_pend_mod_fld_s;
1044 } pi_int_pend_mod_u_t;
1051 /************************************************************************
1053 * This read-only register provides information about interrupts *
1054 * that are currently pending. The interrupts in this register map to *
1055 * interrupt level 2 (L2). The GFX_INT_A/B bits are set by hardware *
1056 * but must be cleared by software. *
1058 ************************************************************************/
1063 #ifdef LITTLE_ENDIAN
1065 typedef union pi_int_pend0_u {
1066 bdrkreg_t pi_int_pend0_regval;
1068 bdrkreg_t ip_int_pend0_lo : 1;
1069 bdrkreg_t ip_gfx_int_a : 1;
1070 bdrkreg_t ip_gfx_int_b : 1;
1071 bdrkreg_t ip_page_migration : 1;
1072 bdrkreg_t ip_uart_ucntrl : 1;
1073 bdrkreg_t ip_or_cc_pend_a : 1;
1074 bdrkreg_t ip_or_cc_pend_b : 1;
1075 bdrkreg_t ip_int_pend0_hi : 57;
1076 } pi_int_pend0_fld_s;
1081 typedef union pi_int_pend0_u {
1082 bdrkreg_t pi_int_pend0_regval;
1084 bdrkreg_t ip_int_pend0_hi : 57;
1085 bdrkreg_t ip_or_cc_pend_b : 1;
1086 bdrkreg_t ip_or_cc_pend_a : 1;
1087 bdrkreg_t ip_uart_ucntrl : 1;
1088 bdrkreg_t ip_page_migration : 1;
1089 bdrkreg_t ip_gfx_int_b : 1;
1090 bdrkreg_t ip_gfx_int_a : 1;
1091 bdrkreg_t ip_int_pend0_lo : 1;
1092 } pi_int_pend0_fld_s;
1100 /************************************************************************
1102 * This read-only register provides information about interrupts *
1103 * that are currently pending. The interrupts in this register map to *
1104 * interrupt level 3 (L3), unless remapped by the INT_PEND1_REMAP *
1105 * register. The SYS_COR_ERR_A/B, RTC_DROP_OUT, and NACK_INT_A/B bits *
1106 * are set by hardware but must be cleared by software. The *
1107 * SYSTEM_SHUTDOWN, NI_ERROR, LB_ERROR and XB_ERROR bits just reflect *
1108 * the value of other logic, and cannot be changed by PI register *
1111 ************************************************************************/
1116 #ifdef LITTLE_ENDIAN
1118 typedef union pi_int_pend1_u {
1119 bdrkreg_t pi_int_pend1_regval;
1121 bdrkreg_t ip_int_pend1 : 54;
1122 bdrkreg_t ip_xb_error : 1;
1123 bdrkreg_t ip_lb_error : 1;
1124 bdrkreg_t ip_nack_int_a : 1;
1125 bdrkreg_t ip_nack_int_b : 1;
1126 bdrkreg_t ip_perf_cntr_oflow : 1;
1127 bdrkreg_t ip_sys_cor_err_b : 1;
1128 bdrkreg_t ip_sys_cor_err_a : 1;
1129 bdrkreg_t ip_md_corr_error : 1;
1130 bdrkreg_t ip_ni_error : 1;
1131 bdrkreg_t ip_system_shutdown : 1;
1132 } pi_int_pend1_fld_s;
1137 typedef union pi_int_pend1_u {
1138 bdrkreg_t pi_int_pend1_regval;
1140 bdrkreg_t ip_system_shutdown : 1;
1141 bdrkreg_t ip_ni_error : 1;
1142 bdrkreg_t ip_md_corr_error : 1;
1143 bdrkreg_t ip_sys_cor_err_a : 1;
1144 bdrkreg_t ip_sys_cor_err_b : 1;
1145 bdrkreg_t ip_perf_cntr_oflow : 1;
1146 bdrkreg_t ip_nack_int_b : 1;
1147 bdrkreg_t ip_nack_int_a : 1;
1148 bdrkreg_t ip_lb_error : 1;
1149 bdrkreg_t ip_xb_error : 1;
1150 bdrkreg_t ip_int_pend1 : 54;
1151 } pi_int_pend1_fld_s;
1159 /************************************************************************
1161 * This read/write register masks the contents of INT_PEND0 to *
1162 * determine whether an L2 interrupt (bit 10 of the processor's Cause *
1163 * register) is sent to CPU_A if the same bit in the INT_PEND0 *
1164 * register is also set. Only one processor in a Bedrock should *
1165 * enable the PAGE_MIGRATION bit/interrupt. *
1167 ************************************************************************/
1172 #ifdef LITTLE_ENDIAN
1174 typedef union pi_int_mask0_a_u {
1175 bdrkreg_t pi_int_mask0_a_regval;
1177 bdrkreg_t ima_int_mask0_lo : 1;
1178 bdrkreg_t ima_gfx_int_a : 1;
1179 bdrkreg_t ima_gfx_int_b : 1;
1180 bdrkreg_t ima_page_migration : 1;
1181 bdrkreg_t ima_uart_ucntrl : 1;
1182 bdrkreg_t ima_or_ccp_mask_a : 1;
1183 bdrkreg_t ima_or_ccp_mask_b : 1;
1184 bdrkreg_t ima_int_mask0_hi : 57;
1185 } pi_int_mask0_a_fld_s;
1186 } pi_int_mask0_a_u_t;
1190 typedef union pi_int_mask0_a_u {
1191 bdrkreg_t pi_int_mask0_a_regval;
1193 bdrkreg_t ima_int_mask0_hi : 57;
1194 bdrkreg_t ima_or_ccp_mask_b : 1;
1195 bdrkreg_t ima_or_ccp_mask_a : 1;
1196 bdrkreg_t ima_uart_ucntrl : 1;
1197 bdrkreg_t ima_page_migration : 1;
1198 bdrkreg_t ima_gfx_int_b : 1;
1199 bdrkreg_t ima_gfx_int_a : 1;
1200 bdrkreg_t ima_int_mask0_lo : 1;
1201 } pi_int_mask0_a_fld_s;
1202 } pi_int_mask0_a_u_t;
1209 /************************************************************************
1211 * This read/write register masks the contents of INT_PEND1 to *
1212 * determine whether an interrupt should be sent. Bits 63:32 always *
1213 * generate an L3 interrupt (bit 11 of the processor's Cause *
1214 * register) is sent to CPU_A if the same bit in the INT_PEND1 *
1215 * register is set. Bits 31:0 can generate either an L3 or L2 *
1216 * interrupt, depending on the value of INT_PEND1_REMAP[3:0]. Only *
1217 * one processor in a Bedrock should enable the NI_ERROR, LB_ERROR, *
1218 * XB_ERROR and MD_CORR_ERROR bits. *
1220 ************************************************************************/
1225 typedef union pi_int_mask1_a_u {
1226 bdrkreg_t pi_int_mask1_a_regval;
1228 bdrkreg_t ima_int_mask1 : 64;
1229 } pi_int_mask1_a_fld_s;
1230 } pi_int_mask1_a_u_t;
1235 /************************************************************************
1237 * This read/write register masks the contents of INT_PEND0 to *
1238 * determine whether an L2 interrupt (bit 10 of the processor's Cause *
1239 * register) is sent to CPU_B if the same bit in the INT_PEND0 *
1240 * register is also set. Only one processor in a Bedrock should *
1241 * enable the PAGE_MIGRATION bit/interrupt. *
1243 ************************************************************************/
1248 #ifdef LITTLE_ENDIAN
1250 typedef union pi_int_mask0_b_u {
1251 bdrkreg_t pi_int_mask0_b_regval;
1253 bdrkreg_t imb_int_mask0_lo : 1;
1254 bdrkreg_t imb_gfx_int_a : 1;
1255 bdrkreg_t imb_gfx_int_b : 1;
1256 bdrkreg_t imb_page_migration : 1;
1257 bdrkreg_t imb_uart_ucntrl : 1;
1258 bdrkreg_t imb_or_ccp_mask_a : 1;
1259 bdrkreg_t imb_or_ccp_mask_b : 1;
1260 bdrkreg_t imb_int_mask0_hi : 57;
1261 } pi_int_mask0_b_fld_s;
1262 } pi_int_mask0_b_u_t;
1266 typedef union pi_int_mask0_b_u {
1267 bdrkreg_t pi_int_mask0_b_regval;
1269 bdrkreg_t imb_int_mask0_hi : 57;
1270 bdrkreg_t imb_or_ccp_mask_b : 1;
1271 bdrkreg_t imb_or_ccp_mask_a : 1;
1272 bdrkreg_t imb_uart_ucntrl : 1;
1273 bdrkreg_t imb_page_migration : 1;
1274 bdrkreg_t imb_gfx_int_b : 1;
1275 bdrkreg_t imb_gfx_int_a : 1;
1276 bdrkreg_t imb_int_mask0_lo : 1;
1277 } pi_int_mask0_b_fld_s;
1278 } pi_int_mask0_b_u_t;
1285 /************************************************************************
1287 * This read/write register masks the contents of INT_PEND1 to *
1288 * determine whether an interrupt should be sent. Bits 63:32 always *
1289 * generate an L3 interrupt (bit 11 of the processor's Cause *
1290 * register) is sent to CPU_B if the same bit in the INT_PEND1 *
1291 * register is set. Bits 31:0 can generate either an L3 or L2 *
1292 * interrupt, depending on the value of INT_PEND1_REMAP[3:0]. Only *
1293 * one processor in a Bedrock should enable the NI_ERROR, LB_ERROR, *
1294 * XB_ERROR and MD_CORR_ERROR bits. *
1296 ************************************************************************/
1301 typedef union pi_int_mask1_b_u {
1302 bdrkreg_t pi_int_mask1_b_regval;
1304 bdrkreg_t imb_int_mask1 : 64;
1305 } pi_int_mask1_b_fld_s;
1306 } pi_int_mask1_b_u_t;
1311 /************************************************************************
1313 * There is one of these registers for each CPU. These registers do *
1314 * not have access protection. A store to this location by a CPU will *
1315 * cause the bit corresponding to the source's region to be set in *
1316 * CC_PEND_A (or CC_PEND_B). The contents of CC_PEND_A (or CC_PEND_B) *
1317 * determines on a bit-per-region basis whether a CPU-to-CPU *
1318 * interrupt is pending CPU_A (or CPU_B). *
1320 ************************************************************************/
1325 typedef union pi_cc_pend_set_a_u {
1326 bdrkreg_t pi_cc_pend_set_a_regval;
1328 bdrkreg_t cpsa_cc_pend : 64;
1329 } pi_cc_pend_set_a_fld_s;
1330 } pi_cc_pend_set_a_u_t;
1335 /************************************************************************
1337 * There is one of these registers for each CPU. These registers do *
1338 * not have access protection. A store to this location by a CPU will *
1339 * cause the bit corresponding to the source's region to be set in *
1340 * CC_PEND_A (or CC_PEND_B). The contents of CC_PEND_A (or CC_PEND_B) *
1341 * determines on a bit-per-region basis whether a CPU-to-CPU *
1342 * interrupt is pending CPU_A (or CPU_B). *
1344 ************************************************************************/
1349 typedef union pi_cc_pend_set_b_u {
1350 bdrkreg_t pi_cc_pend_set_b_regval;
1352 bdrkreg_t cpsb_cc_pend : 64;
1353 } pi_cc_pend_set_b_fld_s;
1354 } pi_cc_pend_set_b_u_t;
1359 /************************************************************************
1361 * There is one of these registers for each CPU. Reading this *
1362 * location will return the contents of CC_PEND_A (or CC_PEND_B). *
1363 * Writing this location will clear the bits corresponding to which *
1364 * data bits are driven high during the store; therefore, storing all *
1365 * ones would clear all bits. *
1367 ************************************************************************/
1372 typedef union pi_cc_pend_clr_a_u {
1373 bdrkreg_t pi_cc_pend_clr_a_regval;
1375 bdrkreg_t cpca_cc_pend : 64;
1376 } pi_cc_pend_clr_a_fld_s;
1377 } pi_cc_pend_clr_a_u_t;
1382 /************************************************************************
1384 * There is one of these registers for each CPU. Reading this *
1385 * location will return the contents of CC_PEND_A (or CC_PEND_B). *
1386 * Writing this location will clear the bits corresponding to which *
1387 * data bits are driven high during the store; therefore, storing all *
1388 * ones would clear all bits. *
1390 ************************************************************************/
1395 typedef union pi_cc_pend_clr_b_u {
1396 bdrkreg_t pi_cc_pend_clr_b_regval;
1398 bdrkreg_t cpcb_cc_pend : 64;
1399 } pi_cc_pend_clr_b_fld_s;
1400 } pi_cc_pend_clr_b_u_t;
1405 /************************************************************************
1407 * This read/write register masks the contents of both CC_PEND_A and *
1410 ************************************************************************/
1415 typedef union pi_cc_mask_u {
1416 bdrkreg_t pi_cc_mask_regval;
1418 bdrkreg_t cm_cc_mask : 64;
1425 /************************************************************************
1427 * This read/write register redirects INT_PEND1[31:0] from L3 to L2 *
1428 * interrupt level.Bit 4 in this register is used to enable error *
1429 * interrupt forwarding to the II. When this bit is set, if any of *
1430 * the three memory interrupts (correctable error, uncorrectable *
1431 * error, or page migration), or the NI, LB or XB error interrupts *
1432 * are set, the PI_II_ERROR_INT wire will be asserted. When this wire *
1433 * is asserted, the II will send an interrupt to the node specified *
1434 * in its IIDSR (Interrupt Destination Register). This allows these *
1435 * interrupts to be forwarded to another node. *
1437 ************************************************************************/
1442 #ifdef LITTLE_ENDIAN
1444 typedef union pi_int_pend1_remap_u {
1445 bdrkreg_t pi_int_pend1_remap_regval;
1447 bdrkreg_t ipr_remap_0 : 1;
1448 bdrkreg_t ipr_remap_1 : 1;
1449 bdrkreg_t ipr_remap_2 : 1;
1450 bdrkreg_t ipr_remap_3 : 1;
1451 bdrkreg_t ipr_error_forward : 1;
1452 bdrkreg_t ipr_reserved : 59;
1453 } pi_int_pend1_remap_fld_s;
1454 } pi_int_pend1_remap_u_t;
1458 typedef union pi_int_pend1_remap_u {
1459 bdrkreg_t pi_int_pend1_remap_regval;
1461 bdrkreg_t ipr_reserved : 59;
1462 bdrkreg_t ipr_error_forward : 1;
1463 bdrkreg_t ipr_remap_3 : 1;
1464 bdrkreg_t ipr_remap_2 : 1;
1465 bdrkreg_t ipr_remap_1 : 1;
1466 bdrkreg_t ipr_remap_0 : 1;
1467 } pi_int_pend1_remap_fld_s;
1468 } pi_int_pend1_remap_u_t;
1475 /************************************************************************
1477 * There is one of these registers for each CPU. When the real time *
1478 * counter (RT_Counter) is equal to the value in this register, the *
1479 * RT_INT_PEND register is set, which causes a Level-4 interrupt to *
1480 * be sent to the processor. *
1482 ************************************************************************/
1487 #ifdef LITTLE_ENDIAN
1489 typedef union pi_rt_compare_a_u {
1490 bdrkreg_t pi_rt_compare_a_regval;
1492 bdrkreg_t rca_rt_compare : 55;
1493 bdrkreg_t rca_rsvd : 9;
1494 } pi_rt_compare_a_fld_s;
1495 } pi_rt_compare_a_u_t;
1499 typedef union pi_rt_compare_a_u {
1500 bdrkreg_t pi_rt_compare_a_regval;
1502 bdrkreg_t rca_rsvd : 9;
1503 bdrkreg_t rca_rt_compare : 55;
1504 } pi_rt_compare_a_fld_s;
1505 } pi_rt_compare_a_u_t;
1512 /************************************************************************
1514 * There is one of these registers for each CPU. When the real time *
1515 * counter (RT_Counter) is equal to the value in this register, the *
1516 * RT_INT_PEND register is set, which causes a Level-4 interrupt to *
1517 * be sent to the processor. *
1519 ************************************************************************/
1524 #ifdef LITTLE_ENDIAN
1526 typedef union pi_rt_compare_b_u {
1527 bdrkreg_t pi_rt_compare_b_regval;
1529 bdrkreg_t rcb_rt_compare : 55;
1530 bdrkreg_t rcb_rsvd : 9;
1531 } pi_rt_compare_b_fld_s;
1532 } pi_rt_compare_b_u_t;
1536 typedef union pi_rt_compare_b_u {
1537 bdrkreg_t pi_rt_compare_b_regval;
1539 bdrkreg_t rcb_rsvd : 9;
1540 bdrkreg_t rcb_rt_compare : 55;
1541 } pi_rt_compare_b_fld_s;
1542 } pi_rt_compare_b_u_t;
1549 /************************************************************************
1551 * When the least significant 32 bits of the real time counter *
1552 * (RT_Counter) are equal to the value in this register, the *
1553 * PROF_INT_PEND_A and PROF_INT_PEND_B registers are set to 0x1. *
1555 ************************************************************************/
1560 #ifdef LITTLE_ENDIAN
1562 typedef union pi_profile_compare_u {
1563 bdrkreg_t pi_profile_compare_regval;
1565 bdrkreg_t pc_profile_compare : 32;
1566 bdrkreg_t pc_rsvd : 32;
1567 } pi_profile_compare_fld_s;
1568 } pi_profile_compare_u_t;
1572 typedef union pi_profile_compare_u {
1573 bdrkreg_t pi_profile_compare_regval;
1575 bdrkreg_t pc_rsvd : 32;
1576 bdrkreg_t pc_profile_compare : 32;
1577 } pi_profile_compare_fld_s;
1578 } pi_profile_compare_u_t;
1585 /************************************************************************
1587 * There is one of these registers for each CPU. If the bit in the *
1588 * corresponding RT_INT_EN_A/B register is set, the processor's level *
1589 * 5 interrupt is set to the value of the RTC_INT_PEND bit in this *
1590 * register. Storing any value to this location will clear the *
1591 * RTC_INT_PEND bit in the register. *
1593 ************************************************************************/
1598 #ifdef LITTLE_ENDIAN
1600 typedef union pi_rt_int_pend_a_u {
1601 bdrkreg_t pi_rt_int_pend_a_regval;
1603 bdrkreg_t ripa_rtc_int_pend : 1;
1604 bdrkreg_t ripa_rsvd : 63;
1605 } pi_rt_int_pend_a_fld_s;
1606 } pi_rt_int_pend_a_u_t;
1610 typedef union pi_rt_int_pend_a_u {
1611 bdrkreg_t pi_rt_int_pend_a_regval;
1613 bdrkreg_t ripa_rsvd : 63;
1614 bdrkreg_t ripa_rtc_int_pend : 1;
1615 } pi_rt_int_pend_a_fld_s;
1616 } pi_rt_int_pend_a_u_t;
1623 /************************************************************************
1625 * There is one of these registers for each CPU. If the bit in the *
1626 * corresponding RT_INT_EN_A/B register is set, the processor's level *
1627 * 5 interrupt is set to the value of the RTC_INT_PEND bit in this *
1628 * register. Storing any value to this location will clear the *
1629 * RTC_INT_PEND bit in the register. *
1631 ************************************************************************/
1636 #ifdef LITTLE_ENDIAN
1638 typedef union pi_rt_int_pend_b_u {
1639 bdrkreg_t pi_rt_int_pend_b_regval;
1641 bdrkreg_t ripb_rtc_int_pend : 1;
1642 bdrkreg_t ripb_rsvd : 63;
1643 } pi_rt_int_pend_b_fld_s;
1644 } pi_rt_int_pend_b_u_t;
1648 typedef union pi_rt_int_pend_b_u {
1649 bdrkreg_t pi_rt_int_pend_b_regval;
1651 bdrkreg_t ripb_rsvd : 63;
1652 bdrkreg_t ripb_rtc_int_pend : 1;
1653 } pi_rt_int_pend_b_fld_s;
1654 } pi_rt_int_pend_b_u_t;
1661 /************************************************************************
1663 * There is one of these registers for each CPU. Both registers are *
1664 * set when the PROFILE_COMPARE register is equal to bits [31:0] of *
1665 * the RT_Counter. If the bit in the corresponding PROF_INT_EN_A/B *
1666 * register is set, the processor's level 5 interrupt is set to the *
1667 * value of the PROF_INT_PEND bit in this register. Storing any value *
1668 * to this location will clear the PROF_INT_PEND bit in the register. *
1669 * The reason for having A and B versions of this register is that *
1670 * they need to be cleared independently. *
1672 ************************************************************************/
1677 #ifdef LITTLE_ENDIAN
1679 typedef union pi_prof_int_pend_a_u {
1680 bdrkreg_t pi_prof_int_pend_a_regval;
1682 bdrkreg_t pipa_prof_int_pend : 1;
1683 bdrkreg_t pipa_rsvd : 63;
1684 } pi_prof_int_pend_a_fld_s;
1685 } pi_prof_int_pend_a_u_t;
1689 typedef union pi_prof_int_pend_a_u {
1690 bdrkreg_t pi_prof_int_pend_a_regval;
1692 bdrkreg_t pipa_rsvd : 63;
1693 bdrkreg_t pipa_prof_int_pend : 1;
1694 } pi_prof_int_pend_a_fld_s;
1695 } pi_prof_int_pend_a_u_t;
1702 /************************************************************************
1704 * There is one of these registers for each CPU. Both registers are *
1705 * set when the PROFILE_COMPARE register is equal to bits [31:0] of *
1706 * the RT_Counter. If the bit in the corresponding PROF_INT_EN_A/B *
1707 * register is set, the processor's level 5 interrupt is set to the *
1708 * value of the PROF_INT_PEND bit in this register. Storing any value *
1709 * to this location will clear the PROF_INT_PEND bit in the register. *
1710 * The reason for having A and B versions of this register is that *
1711 * they need to be cleared independently. *
1713 ************************************************************************/
1718 #ifdef LITTLE_ENDIAN
1720 typedef union pi_prof_int_pend_b_u {
1721 bdrkreg_t pi_prof_int_pend_b_regval;
1723 bdrkreg_t pipb_prof_int_pend : 1;
1724 bdrkreg_t pipb_rsvd : 63;
1725 } pi_prof_int_pend_b_fld_s;
1726 } pi_prof_int_pend_b_u_t;
1730 typedef union pi_prof_int_pend_b_u {
1731 bdrkreg_t pi_prof_int_pend_b_regval;
1733 bdrkreg_t pipb_rsvd : 63;
1734 bdrkreg_t pipb_prof_int_pend : 1;
1735 } pi_prof_int_pend_b_fld_s;
1736 } pi_prof_int_pend_b_u_t;
1743 /************************************************************************
1745 * There is one of these registers for each CPU. Enables RTC *
1746 * interrupt to the associated CPU. *
1748 ************************************************************************/
1753 #ifdef LITTLE_ENDIAN
1755 typedef union pi_rt_int_en_a_u {
1756 bdrkreg_t pi_rt_int_en_a_regval;
1758 bdrkreg_t riea_rtc_int_en : 1;
1759 bdrkreg_t riea_rsvd : 63;
1760 } pi_rt_int_en_a_fld_s;
1761 } pi_rt_int_en_a_u_t;
1765 typedef union pi_rt_int_en_a_u {
1766 bdrkreg_t pi_rt_int_en_a_regval;
1768 bdrkreg_t riea_rsvd : 63;
1769 bdrkreg_t riea_rtc_int_en : 1;
1770 } pi_rt_int_en_a_fld_s;
1771 } pi_rt_int_en_a_u_t;
1778 /************************************************************************
1780 * There is one of these registers for each CPU. Enables RTC *
1781 * interrupt to the associated CPU. *
1783 ************************************************************************/
1788 #ifdef LITTLE_ENDIAN
1790 typedef union pi_rt_int_en_b_u {
1791 bdrkreg_t pi_rt_int_en_b_regval;
1793 bdrkreg_t rieb_rtc_int_en : 1;
1794 bdrkreg_t rieb_rsvd : 63;
1795 } pi_rt_int_en_b_fld_s;
1796 } pi_rt_int_en_b_u_t;
1800 typedef union pi_rt_int_en_b_u {
1801 bdrkreg_t pi_rt_int_en_b_regval;
1803 bdrkreg_t rieb_rsvd : 63;
1804 bdrkreg_t rieb_rtc_int_en : 1;
1805 } pi_rt_int_en_b_fld_s;
1806 } pi_rt_int_en_b_u_t;
1813 /************************************************************************
1815 * There is one of these registers for each CPU. Enables profiling *
1816 * interrupt to the associated CPU. *
1818 ************************************************************************/
1823 #ifdef LITTLE_ENDIAN
1825 typedef union pi_prof_int_en_a_u {
1826 bdrkreg_t pi_prof_int_en_a_regval;
1828 bdrkreg_t piea_prof_int_en : 1;
1829 bdrkreg_t piea_rsvd : 63;
1830 } pi_prof_int_en_a_fld_s;
1831 } pi_prof_int_en_a_u_t;
1835 typedef union pi_prof_int_en_a_u {
1836 bdrkreg_t pi_prof_int_en_a_regval;
1838 bdrkreg_t piea_rsvd : 63;
1839 bdrkreg_t piea_prof_int_en : 1;
1840 } pi_prof_int_en_a_fld_s;
1841 } pi_prof_int_en_a_u_t;
1848 /************************************************************************
1850 * There is one of these registers for each CPU. Enables profiling *
1851 * interrupt to the associated CPU. *
1853 ************************************************************************/
1858 #ifdef LITTLE_ENDIAN
1860 typedef union pi_prof_int_en_b_u {
1861 bdrkreg_t pi_prof_int_en_b_regval;
1863 bdrkreg_t pieb_prof_int_en : 1;
1864 bdrkreg_t pieb_rsvd : 63;
1865 } pi_prof_int_en_b_fld_s;
1866 } pi_prof_int_en_b_u_t;
1870 typedef union pi_prof_int_en_b_u {
1871 bdrkreg_t pi_prof_int_en_b_regval;
1873 bdrkreg_t pieb_rsvd : 63;
1874 bdrkreg_t pieb_prof_int_en : 1;
1875 } pi_prof_int_en_b_fld_s;
1876 } pi_prof_int_en_b_u_t;
1883 /************************************************************************
1885 * This register controls operation of the debug data from the PI, *
1886 * along with Debug_Sel[2:0] from the Debug module. For some values *
1887 * of Debug_Sel[2:0], the B_SEL bit selects whether the debug bits *
1888 * are looking at the processor A or processor B logic. The remaining *
1889 * bits select which signal(s) are ORed to create DebugData bits 31 *
1890 * and 30 for all of the PI debug selections. *
1892 ************************************************************************/
1897 #ifdef LITTLE_ENDIAN
1899 typedef union pi_debug_sel_u {
1900 bdrkreg_t pi_debug_sel_regval;
1902 bdrkreg_t ds_low_t5cc_a : 1;
1903 bdrkreg_t ds_low_t5cc_b : 1;
1904 bdrkreg_t ds_low_totcc_a : 1;
1905 bdrkreg_t ds_low_totcc_b : 1;
1906 bdrkreg_t ds_low_reqcc_a : 1;
1907 bdrkreg_t ds_low_reqcc_b : 1;
1908 bdrkreg_t ds_low_rplcc_a : 1;
1909 bdrkreg_t ds_low_rplcc_b : 1;
1910 bdrkreg_t ds_low_intcc : 1;
1911 bdrkreg_t ds_low_perf_inc_a_0 : 1;
1912 bdrkreg_t ds_low_perf_inc_a_1 : 1;
1913 bdrkreg_t ds_low_perf_inc_b_0 : 1;
1914 bdrkreg_t ds_low_perf_inc_b_1 : 1;
1915 bdrkreg_t ds_high_t5cc_a : 1;
1916 bdrkreg_t ds_high_t5cc_b : 1;
1917 bdrkreg_t ds_high_totcc_a : 1;
1918 bdrkreg_t ds_high_totcc_b : 1;
1919 bdrkreg_t ds_high_reqcc_a : 1;
1920 bdrkreg_t ds_high_reqcc_b : 1;
1921 bdrkreg_t ds_high_rplcc_a : 1;
1922 bdrkreg_t ds_high_rplcc_b : 1;
1923 bdrkreg_t ds_high_intcc : 1;
1924 bdrkreg_t ds_high_perf_inc_a_0 : 1;
1925 bdrkreg_t ds_high_perf_inc_a_1 : 1;
1926 bdrkreg_t ds_high_perf_inc_b_0 : 1;
1927 bdrkreg_t ds_high_perf_inc_b_1 : 1;
1928 bdrkreg_t ds_b_sel : 1;
1929 bdrkreg_t ds_rsvd : 37;
1930 } pi_debug_sel_fld_s;
1935 typedef union pi_debug_sel_u {
1936 bdrkreg_t pi_debug_sel_regval;
1938 bdrkreg_t ds_rsvd : 37;
1939 bdrkreg_t ds_b_sel : 1;
1940 bdrkreg_t ds_high_perf_inc_b_1 : 1;
1941 bdrkreg_t ds_high_perf_inc_b_0 : 1;
1942 bdrkreg_t ds_high_perf_inc_a_1 : 1;
1943 bdrkreg_t ds_high_perf_inc_a_0 : 1;
1944 bdrkreg_t ds_high_intcc : 1;
1945 bdrkreg_t ds_high_rplcc_b : 1;
1946 bdrkreg_t ds_high_rplcc_a : 1;
1947 bdrkreg_t ds_high_reqcc_b : 1;
1948 bdrkreg_t ds_high_reqcc_a : 1;
1949 bdrkreg_t ds_high_totcc_b : 1;
1950 bdrkreg_t ds_high_totcc_a : 1;
1951 bdrkreg_t ds_high_t5cc_b : 1;
1952 bdrkreg_t ds_high_t5cc_a : 1;
1953 bdrkreg_t ds_low_perf_inc_b_1 : 1;
1954 bdrkreg_t ds_low_perf_inc_b_0 : 1;
1955 bdrkreg_t ds_low_perf_inc_a_1 : 1;
1956 bdrkreg_t ds_low_perf_inc_a_0 : 1;
1957 bdrkreg_t ds_low_intcc : 1;
1958 bdrkreg_t ds_low_rplcc_b : 1;
1959 bdrkreg_t ds_low_rplcc_a : 1;
1960 bdrkreg_t ds_low_reqcc_b : 1;
1961 bdrkreg_t ds_low_reqcc_a : 1;
1962 bdrkreg_t ds_low_totcc_b : 1;
1963 bdrkreg_t ds_low_totcc_a : 1;
1964 bdrkreg_t ds_low_t5cc_b : 1;
1965 bdrkreg_t ds_low_t5cc_a : 1;
1966 } pi_debug_sel_fld_s;
1972 /************************************************************************
1974 * A write to this register allows a single bit in the INT_PEND0 or *
1975 * INT_PEND1 registers to be set or cleared. If 6 is clear, a bit is *
1976 * modified in INT_PEND0, while if 6 is set, a bit is modified in *
1977 * INT_PEND1. The value in 5:0 (ranging from 63 to 0) will determine *
1978 * which bit in the register is effected. The value of 8 will *
1979 * determine whether the desired bit is set (8=1) or cleared (8=0). *
1980 * This is the only register which is accessible by IO issued PWRI *
1981 * command and is protected through the IO_PROTECT register. If the *
1982 * region bit in the IO_PROTECT is not set then a WERR reply is *
1983 * issued. CPU access is controlled through CPU_PROTECT. The contents *
1984 * of this register are masked with the contents of INT_MASK_A *
1985 * (INT_MASK_B) to determine whether an L2 interrupt is issued to *
1988 ************************************************************************/
1993 #ifdef LITTLE_ENDIAN
1995 typedef union pi_int_pend_mod_alias_u {
1996 bdrkreg_t pi_int_pend_mod_alias_regval;
1998 bdrkreg_t ipma_bit_select : 6;
1999 bdrkreg_t ipma_reg_select : 1;
2000 bdrkreg_t ipma_rsvd_1 : 1;
2001 bdrkreg_t ipma_value : 1;
2002 bdrkreg_t ipma_rsvd : 55;
2003 } pi_int_pend_mod_alias_fld_s;
2004 } pi_int_pend_mod_alias_u_t;
2008 typedef union pi_int_pend_mod_alias_u {
2009 bdrkreg_t pi_int_pend_mod_alias_regval;
2011 bdrkreg_t ipma_rsvd : 55;
2012 bdrkreg_t ipma_value : 1;
2013 bdrkreg_t ipma_rsvd_1 : 1;
2014 bdrkreg_t ipma_reg_select : 1;
2015 bdrkreg_t ipma_bit_select : 6;
2016 } pi_int_pend_mod_alias_fld_s;
2017 } pi_int_pend_mod_alias_u_t;
2024 /************************************************************************
2026 * There is one of these registers for each CPU. This register *
2027 * specifies the value of the Graphics Page. Uncached writes into the *
2028 * Graphics Page (with uncached attribute of IO) are done with GFXWS *
2029 * commands rather than the normal PWRI commands. GFXWS commands are *
2030 * tracked with the graphics credit counters. *
2032 ************************************************************************/
2037 #ifdef LITTLE_ENDIAN
2039 typedef union pi_gfx_page_a_u {
2040 bdrkreg_t pi_gfx_page_a_regval;
2042 bdrkreg_t gpa_rsvd_1 : 17;
2043 bdrkreg_t gpa_gfx_page_addr : 23;
2044 bdrkreg_t gpa_en_gfx_page : 1;
2045 bdrkreg_t gpa_rsvd : 23;
2046 } pi_gfx_page_a_fld_s;
2047 } pi_gfx_page_a_u_t;
2051 typedef union pi_gfx_page_a_u {
2052 bdrkreg_t pi_gfx_page_a_regval;
2054 bdrkreg_t gpa_rsvd : 23;
2055 bdrkreg_t gpa_en_gfx_page : 1;
2056 bdrkreg_t gpa_gfx_page_addr : 23;
2057 bdrkreg_t gpa_rsvd_1 : 17;
2058 } pi_gfx_page_a_fld_s;
2059 } pi_gfx_page_a_u_t;
2066 /************************************************************************
2068 * There is one of these registers for each CPU. This register *
2069 * counts graphics credits. This counter is decremented for each *
2070 * doubleword sent to graphics with GFXWS or GFXWL commands. It is *
2071 * incremented for each doubleword acknowledge from graphics. When *
2072 * this counter has a smaller value than the GFX_BIAS register, *
2073 * SysWrRdy_L is deasserted, an interrupt is sent to the processor, *
2074 * and SysWrRdy_L is allowed to be asserted again. This is the basic *
2075 * mechanism for flow-controlling graphics writes. *
2077 ************************************************************************/
2082 #ifdef LITTLE_ENDIAN
2084 typedef union pi_gfx_credit_cntr_a_u {
2085 bdrkreg_t pi_gfx_credit_cntr_a_regval;
2087 bdrkreg_t gcca_gfx_credit_cntr : 12;
2088 bdrkreg_t gcca_rsvd : 52;
2089 } pi_gfx_credit_cntr_a_fld_s;
2090 } pi_gfx_credit_cntr_a_u_t;
2094 typedef union pi_gfx_credit_cntr_a_u {
2095 bdrkreg_t pi_gfx_credit_cntr_a_regval;
2097 bdrkreg_t gcca_rsvd : 52;
2098 bdrkreg_t gcca_gfx_credit_cntr : 12;
2099 } pi_gfx_credit_cntr_a_fld_s;
2100 } pi_gfx_credit_cntr_a_u_t;
2107 /************************************************************************
2109 * There is one of these registers for each CPU. When the graphics *
2110 * credit counter is less than or equal to this value, a flow control *
2111 * interrupt is sent. *
2113 ************************************************************************/
2118 #ifdef LITTLE_ENDIAN
2120 typedef union pi_gfx_bias_a_u {
2121 bdrkreg_t pi_gfx_bias_a_regval;
2123 bdrkreg_t gba_gfx_bias : 12;
2124 bdrkreg_t gba_rsvd : 52;
2125 } pi_gfx_bias_a_fld_s;
2126 } pi_gfx_bias_a_u_t;
2130 typedef union pi_gfx_bias_a_u {
2131 bdrkreg_t pi_gfx_bias_a_regval;
2133 bdrkreg_t gba_rsvd : 52;
2134 bdrkreg_t gba_gfx_bias : 12;
2135 } pi_gfx_bias_a_fld_s;
2136 } pi_gfx_bias_a_u_t;
2143 /************************************************************************
2145 * Description: There is one of these registers for each CPU. When *
2146 * this counter reaches the value of the GFX_INT_CMP register, an *
2147 * interrupt is sent to the associated processor. At each clock *
2148 * cycle, the value in this register can be changed by any one of the *
2149 * following actions: *
2150 * - Written by software. *
2151 * - Loaded with the value of GFX_INT_CMP, when an interrupt, NMI, or *
2152 * soft reset occurs, thus preventing an additional interrupt. *
2153 * - Zeroed, when the GFX_CREDIT_CNTR rises above the bias value. *
2154 * - Incremented (by one at each clock) for each clock that the *
2155 * GFX_CREDIT_CNTR is less than or equal to zero. *
2157 ************************************************************************/
2162 #ifdef LITTLE_ENDIAN
2164 typedef union pi_gfx_int_cntr_a_u {
2165 bdrkreg_t pi_gfx_int_cntr_a_regval;
2167 bdrkreg_t gica_gfx_int_cntr : 26;
2168 bdrkreg_t gica_rsvd : 38;
2169 } pi_gfx_int_cntr_a_fld_s;
2170 } pi_gfx_int_cntr_a_u_t;
2174 typedef union pi_gfx_int_cntr_a_u {
2175 bdrkreg_t pi_gfx_int_cntr_a_regval;
2177 bdrkreg_t gica_rsvd : 38;
2178 bdrkreg_t gica_gfx_int_cntr : 26;
2179 } pi_gfx_int_cntr_a_fld_s;
2180 } pi_gfx_int_cntr_a_u_t;
2187 /************************************************************************
2189 * There is one of these registers for each CPU. The value in this *
2190 * register is loaded into the GFX_INT_CNTR register when an *
2191 * interrupt, NMI, or soft reset is sent to the processor. The value *
2192 * in this register is compared to the value of GFX_INT_CNTR and an *
2193 * interrupt is sent when they become equal. *
2195 ************************************************************************/
2202 typedef union pi_gfx_int_cmp_a_u {
2203 bdrkreg_t pi_gfx_int_cmp_a_regval;
2205 bdrkreg_t gica_gfx_int_cmp : 26;
2206 bdrkreg_t gica_rsvd : 38;
2207 } pi_gfx_int_cmp_a_fld_s;
2208 } pi_gfx_int_cmp_a_u_t;
2212 typedef union pi_gfx_int_cmp_a_u {
2213 bdrkreg_t pi_gfx_int_cmp_a_regval;
2215 bdrkreg_t gica_rsvd : 38;
2216 bdrkreg_t gica_gfx_int_cmp : 26;
2217 } pi_gfx_int_cmp_a_fld_s;
2218 } pi_gfx_int_cmp_a_u_t;
2225 /************************************************************************
2227 * There is one of these registers for each CPU. This register *
2228 * specifies the value of the Graphics Page. Uncached writes into the *
2229 * Graphics Page (with uncached attribute of IO) are done with GFXWS *
2230 * commands rather than the normal PWRI commands. GFXWS commands are *
2231 * tracked with the graphics credit counters. *
2233 ************************************************************************/
2238 #ifdef LITTLE_ENDIAN
2240 typedef union pi_gfx_page_b_u {
2241 bdrkreg_t pi_gfx_page_b_regval;
2243 bdrkreg_t gpb_rsvd_1 : 17;
2244 bdrkreg_t gpb_gfx_page_addr : 23;
2245 bdrkreg_t gpb_en_gfx_page : 1;
2246 bdrkreg_t gpb_rsvd : 23;
2247 } pi_gfx_page_b_fld_s;
2248 } pi_gfx_page_b_u_t;
2252 typedef union pi_gfx_page_b_u {
2253 bdrkreg_t pi_gfx_page_b_regval;
2255 bdrkreg_t gpb_rsvd : 23;
2256 bdrkreg_t gpb_en_gfx_page : 1;
2257 bdrkreg_t gpb_gfx_page_addr : 23;
2258 bdrkreg_t gpb_rsvd_1 : 17;
2259 } pi_gfx_page_b_fld_s;
2260 } pi_gfx_page_b_u_t;
2267 /************************************************************************
2269 * There is one of these registers for each CPU. This register *
2270 * counts graphics credits. This counter is decremented for each *
2271 * doubleword sent to graphics with GFXWS or GFXWL commands. It is *
2272 * incremented for each doubleword acknowledge from graphics. When *
2273 * this counter has a smaller value than the GFX_BIAS register, *
2274 * SysWrRdy_L is deasserted, an interrupt is sent to the processor, *
2275 * and SysWrRdy_L is allowed to be asserted again. This is the basic *
2276 * mechanism for flow-controlling graphics writes. *
2278 ************************************************************************/
2283 #ifdef LITTLE_ENDIAN
2285 typedef union pi_gfx_credit_cntr_b_u {
2286 bdrkreg_t pi_gfx_credit_cntr_b_regval;
2288 bdrkreg_t gccb_gfx_credit_cntr : 12;
2289 bdrkreg_t gccb_rsvd : 52;
2290 } pi_gfx_credit_cntr_b_fld_s;
2291 } pi_gfx_credit_cntr_b_u_t;
2295 typedef union pi_gfx_credit_cntr_b_u {
2296 bdrkreg_t pi_gfx_credit_cntr_b_regval;
2298 bdrkreg_t gccb_rsvd : 52;
2299 bdrkreg_t gccb_gfx_credit_cntr : 12;
2300 } pi_gfx_credit_cntr_b_fld_s;
2301 } pi_gfx_credit_cntr_b_u_t;
2308 /************************************************************************
2310 * There is one of these registers for each CPU. When the graphics *
2311 * credit counter is less than or equal to this value, a flow control *
2312 * interrupt is sent. *
2314 ************************************************************************/
2319 #ifdef LITTLE_ENDIAN
2321 typedef union pi_gfx_bias_b_u {
2322 bdrkreg_t pi_gfx_bias_b_regval;
2324 bdrkreg_t gbb_gfx_bias : 12;
2325 bdrkreg_t gbb_rsvd : 52;
2326 } pi_gfx_bias_b_fld_s;
2327 } pi_gfx_bias_b_u_t;
2331 typedef union pi_gfx_bias_b_u {
2332 bdrkreg_t pi_gfx_bias_b_regval;
2334 bdrkreg_t gbb_rsvd : 52;
2335 bdrkreg_t gbb_gfx_bias : 12;
2336 } pi_gfx_bias_b_fld_s;
2337 } pi_gfx_bias_b_u_t;
2344 /************************************************************************
2346 * Description: There is one of these registers for each CPU. When *
2347 * this counter reaches the value of the GFX_INT_CMP register, an *
2348 * interrupt is sent to the associated processor. At each clock *
2349 * cycle, the value in this register can be changed by any one of the *
2350 * following actions: *
2351 * - Written by software. *
2352 * - Loaded with the value of GFX_INT_CMP, when an interrupt, NMI, or *
2353 * soft reset occurs, thus preventing an additional interrupt. *
2354 * - Zeroed, when the GFX_CREDIT_CNTR rises above the bias value. *
2355 * - Incremented (by one at each clock) for each clock that the *
2356 * GFX_CREDIT_CNTR is less than or equal to zero. *
2358 ************************************************************************/
2363 #ifdef LITTLE_ENDIAN
2365 typedef union pi_gfx_int_cntr_b_u {
2366 bdrkreg_t pi_gfx_int_cntr_b_regval;
2368 bdrkreg_t gicb_gfx_int_cntr : 26;
2369 bdrkreg_t gicb_rsvd : 38;
2370 } pi_gfx_int_cntr_b_fld_s;
2371 } pi_gfx_int_cntr_b_u_t;
2375 typedef union pi_gfx_int_cntr_b_u {
2376 bdrkreg_t pi_gfx_int_cntr_b_regval;
2378 bdrkreg_t gicb_rsvd : 38;
2379 bdrkreg_t gicb_gfx_int_cntr : 26;
2380 } pi_gfx_int_cntr_b_fld_s;
2381 } pi_gfx_int_cntr_b_u_t;
2388 /************************************************************************
2390 * There is one of these registers for each CPU. The value in this *
2391 * register is loaded into the GFX_INT_CNTR register when an *
2392 * interrupt, NMI, or soft reset is sent to the processor. The value *
2393 * in this register is compared to the value of GFX_INT_CNTR and an *
2394 * interrupt is sent when they become equal. *
2396 ************************************************************************/
2401 #ifdef LITTLE_ENDIAN
2403 typedef union pi_gfx_int_cmp_b_u {
2404 bdrkreg_t pi_gfx_int_cmp_b_regval;
2406 bdrkreg_t gicb_gfx_int_cmp : 26;
2407 bdrkreg_t gicb_rsvd : 38;
2408 } pi_gfx_int_cmp_b_fld_s;
2409 } pi_gfx_int_cmp_b_u_t;
2413 typedef union pi_gfx_int_cmp_b_u {
2414 bdrkreg_t pi_gfx_int_cmp_b_regval;
2416 bdrkreg_t gicb_rsvd : 38;
2417 bdrkreg_t gicb_gfx_int_cmp : 26;
2418 } pi_gfx_int_cmp_b_fld_s;
2419 } pi_gfx_int_cmp_b_u_t;
2426 /************************************************************************
2428 * Description: A read of this register returns all sources of *
2429 * Bedrock Error Interrupts. Storing to the write-with-clear location *
2430 * clears any bit for which a one appears on the data bus. Storing to *
2431 * the writable location does a direct write to all unreserved bits *
2432 * (except for MEM_UNC). *
2433 * In Synergy mode, the processor that is the source of the command *
2434 * that got an error is independent of the A or B SysAD bus. So in *
2435 * Synergy mode, Synergy provides the source processor number in bit *
2436 * 52 of the SysAD bus in all commands. The PI saves this in the RRB *
2437 * or WRB entry, and uses that value to determine which error bit (A *
2438 * or B) to set, as well as which ERR_STATUS and spool registers to *
2439 * use, for all error types in this register that are specified as an *
2440 * error to CPU_A or CPU_B. *
2441 * This register is not cleared at reset. *
2443 ************************************************************************/
2448 #ifdef LITTLE_ENDIAN
2450 typedef union pi_err_int_pend_wr_u {
2451 bdrkreg_t pi_err_int_pend_wr_regval;
2453 bdrkreg_t eipw_spool_comp_b : 1;
2454 bdrkreg_t eipw_spool_comp_a : 1;
2455 bdrkreg_t eipw_spurious_b : 1;
2456 bdrkreg_t eipw_spurious_a : 1;
2457 bdrkreg_t eipw_wrb_terr_b : 1;
2458 bdrkreg_t eipw_wrb_terr_a : 1;
2459 bdrkreg_t eipw_wrb_werr_b : 1;
2460 bdrkreg_t eipw_wrb_werr_a : 1;
2461 bdrkreg_t eipw_sysstate_par_b : 1;
2462 bdrkreg_t eipw_sysstate_par_a : 1;
2463 bdrkreg_t eipw_sysad_data_ecc_b : 1;
2464 bdrkreg_t eipw_sysad_data_ecc_a : 1;
2465 bdrkreg_t eipw_sysad_addr_ecc_b : 1;
2466 bdrkreg_t eipw_sysad_addr_ecc_a : 1;
2467 bdrkreg_t eipw_syscmd_data_par_b : 1;
2468 bdrkreg_t eipw_syscmd_data_par_a : 1;
2469 bdrkreg_t eipw_syscmd_addr_par_b : 1;
2470 bdrkreg_t eipw_syscmd_addr_par_a : 1;
2471 bdrkreg_t eipw_spool_err_b : 1;
2472 bdrkreg_t eipw_spool_err_a : 1;
2473 bdrkreg_t eipw_ue_uncached_b : 1;
2474 bdrkreg_t eipw_ue_uncached_a : 1;
2475 bdrkreg_t eipw_sysstate_tag_b : 1;
2476 bdrkreg_t eipw_sysstate_tag_a : 1;
2477 bdrkreg_t eipw_mem_unc : 1;
2478 bdrkreg_t eipw_sysad_bad_data_b : 1;
2479 bdrkreg_t eipw_sysad_bad_data_a : 1;
2480 bdrkreg_t eipw_ue_cached_b : 1;
2481 bdrkreg_t eipw_ue_cached_a : 1;
2482 bdrkreg_t eipw_pkt_len_err_b : 1;
2483 bdrkreg_t eipw_pkt_len_err_a : 1;
2484 bdrkreg_t eipw_irb_err_b : 1;
2485 bdrkreg_t eipw_irb_err_a : 1;
2486 bdrkreg_t eipw_irb_timeout_b : 1;
2487 bdrkreg_t eipw_irb_timeout_a : 1;
2488 bdrkreg_t eipw_rsvd : 29;
2489 } pi_err_int_pend_wr_fld_s;
2490 } pi_err_int_pend_wr_u_t;
2494 typedef union pi_err_int_pend_wr_u {
2495 bdrkreg_t pi_err_int_pend_wr_regval;
2497 bdrkreg_t eipw_rsvd : 29;
2498 bdrkreg_t eipw_irb_timeout_a : 1;
2499 bdrkreg_t eipw_irb_timeout_b : 1;
2500 bdrkreg_t eipw_irb_err_a : 1;
2501 bdrkreg_t eipw_irb_err_b : 1;
2502 bdrkreg_t eipw_pkt_len_err_a : 1;
2503 bdrkreg_t eipw_pkt_len_err_b : 1;
2504 bdrkreg_t eipw_ue_cached_a : 1;
2505 bdrkreg_t eipw_ue_cached_b : 1;
2506 bdrkreg_t eipw_sysad_bad_data_a : 1;
2507 bdrkreg_t eipw_sysad_bad_data_b : 1;
2508 bdrkreg_t eipw_mem_unc : 1;
2509 bdrkreg_t eipw_sysstate_tag_a : 1;
2510 bdrkreg_t eipw_sysstate_tag_b : 1;
2511 bdrkreg_t eipw_ue_uncached_a : 1;
2512 bdrkreg_t eipw_ue_uncached_b : 1;
2513 bdrkreg_t eipw_spool_err_a : 1;
2514 bdrkreg_t eipw_spool_err_b : 1;
2515 bdrkreg_t eipw_syscmd_addr_par_a : 1;
2516 bdrkreg_t eipw_syscmd_addr_par_b : 1;
2517 bdrkreg_t eipw_syscmd_data_par_a : 1;
2518 bdrkreg_t eipw_syscmd_data_par_b : 1;
2519 bdrkreg_t eipw_sysad_addr_ecc_a : 1;
2520 bdrkreg_t eipw_sysad_addr_ecc_b : 1;
2521 bdrkreg_t eipw_sysad_data_ecc_a : 1;
2522 bdrkreg_t eipw_sysad_data_ecc_b : 1;
2523 bdrkreg_t eipw_sysstate_par_a : 1;
2524 bdrkreg_t eipw_sysstate_par_b : 1;
2525 bdrkreg_t eipw_wrb_werr_a : 1;
2526 bdrkreg_t eipw_wrb_werr_b : 1;
2527 bdrkreg_t eipw_wrb_terr_a : 1;
2528 bdrkreg_t eipw_wrb_terr_b : 1;
2529 bdrkreg_t eipw_spurious_a : 1;
2530 bdrkreg_t eipw_spurious_b : 1;
2531 bdrkreg_t eipw_spool_comp_a : 1;
2532 bdrkreg_t eipw_spool_comp_b : 1;
2533 } pi_err_int_pend_wr_fld_s;
2534 } pi_err_int_pend_wr_u_t;
2541 /************************************************************************
2543 * Description: A read of this register returns all sources of *
2544 * Bedrock Error Interrupts. Storing to the write-with-clear location *
2545 * clears any bit for which a one appears on the data bus. Storing to *
2546 * the writable location does a direct write to all unreserved bits *
2547 * (except for MEM_UNC). *
2548 * In Synergy mode, the processor that is the source of the command *
2549 * that got an error is independent of the A or B SysAD bus. So in *
2550 * Synergy mode, Synergy provides the source processor number in bit *
2551 * 52 of the SysAD bus in all commands. The PI saves this in the RRB *
2552 * or WRB entry, and uses that value to determine which error bit (A *
2553 * or B) to set, as well as which ERR_STATUS and spool registers to *
2554 * use, for all error types in this register that are specified as an *
2555 * error to CPU_A or CPU_B. *
2556 * This register is not cleared at reset. *
2558 ************************************************************************/
2563 #ifdef LITTLE_ENDIAN
2565 typedef union pi_err_int_pend_u {
2566 bdrkreg_t pi_err_int_pend_regval;
2568 bdrkreg_t eip_spool_comp_b : 1;
2569 bdrkreg_t eip_spool_comp_a : 1;
2570 bdrkreg_t eip_spurious_b : 1;
2571 bdrkreg_t eip_spurious_a : 1;
2572 bdrkreg_t eip_wrb_terr_b : 1;
2573 bdrkreg_t eip_wrb_terr_a : 1;
2574 bdrkreg_t eip_wrb_werr_b : 1;
2575 bdrkreg_t eip_wrb_werr_a : 1;
2576 bdrkreg_t eip_sysstate_par_b : 1;
2577 bdrkreg_t eip_sysstate_par_a : 1;
2578 bdrkreg_t eip_sysad_data_ecc_b : 1;
2579 bdrkreg_t eip_sysad_data_ecc_a : 1;
2580 bdrkreg_t eip_sysad_addr_ecc_b : 1;
2581 bdrkreg_t eip_sysad_addr_ecc_a : 1;
2582 bdrkreg_t eip_syscmd_data_par_b : 1;
2583 bdrkreg_t eip_syscmd_data_par_a : 1;
2584 bdrkreg_t eip_syscmd_addr_par_b : 1;
2585 bdrkreg_t eip_syscmd_addr_par_a : 1;
2586 bdrkreg_t eip_spool_err_b : 1;
2587 bdrkreg_t eip_spool_err_a : 1;
2588 bdrkreg_t eip_ue_uncached_b : 1;
2589 bdrkreg_t eip_ue_uncached_a : 1;
2590 bdrkreg_t eip_sysstate_tag_b : 1;
2591 bdrkreg_t eip_sysstate_tag_a : 1;
2592 bdrkreg_t eip_mem_unc : 1;
2593 bdrkreg_t eip_sysad_bad_data_b : 1;
2594 bdrkreg_t eip_sysad_bad_data_a : 1;
2595 bdrkreg_t eip_ue_cached_b : 1;
2596 bdrkreg_t eip_ue_cached_a : 1;
2597 bdrkreg_t eip_pkt_len_err_b : 1;
2598 bdrkreg_t eip_pkt_len_err_a : 1;
2599 bdrkreg_t eip_irb_err_b : 1;
2600 bdrkreg_t eip_irb_err_a : 1;
2601 bdrkreg_t eip_irb_timeout_b : 1;
2602 bdrkreg_t eip_irb_timeout_a : 1;
2603 bdrkreg_t eip_rsvd : 29;
2604 } pi_err_int_pend_fld_s;
2605 } pi_err_int_pend_u_t;
2609 typedef union pi_err_int_pend_u {
2610 bdrkreg_t pi_err_int_pend_regval;
2612 bdrkreg_t eip_rsvd : 29;
2613 bdrkreg_t eip_irb_timeout_a : 1;
2614 bdrkreg_t eip_irb_timeout_b : 1;
2615 bdrkreg_t eip_irb_err_a : 1;
2616 bdrkreg_t eip_irb_err_b : 1;
2617 bdrkreg_t eip_pkt_len_err_a : 1;
2618 bdrkreg_t eip_pkt_len_err_b : 1;
2619 bdrkreg_t eip_ue_cached_a : 1;
2620 bdrkreg_t eip_ue_cached_b : 1;
2621 bdrkreg_t eip_sysad_bad_data_a : 1;
2622 bdrkreg_t eip_sysad_bad_data_b : 1;
2623 bdrkreg_t eip_mem_unc : 1;
2624 bdrkreg_t eip_sysstate_tag_a : 1;
2625 bdrkreg_t eip_sysstate_tag_b : 1;
2626 bdrkreg_t eip_ue_uncached_a : 1;
2627 bdrkreg_t eip_ue_uncached_b : 1;
2628 bdrkreg_t eip_spool_err_a : 1;
2629 bdrkreg_t eip_spool_err_b : 1;
2630 bdrkreg_t eip_syscmd_addr_par_a : 1;
2631 bdrkreg_t eip_syscmd_addr_par_b : 1;
2632 bdrkreg_t eip_syscmd_data_par_a : 1;
2633 bdrkreg_t eip_syscmd_data_par_b : 1;
2634 bdrkreg_t eip_sysad_addr_ecc_a : 1;
2635 bdrkreg_t eip_sysad_addr_ecc_b : 1;
2636 bdrkreg_t eip_sysad_data_ecc_a : 1;
2637 bdrkreg_t eip_sysad_data_ecc_b : 1;
2638 bdrkreg_t eip_sysstate_par_a : 1;
2639 bdrkreg_t eip_sysstate_par_b : 1;
2640 bdrkreg_t eip_wrb_werr_a : 1;
2641 bdrkreg_t eip_wrb_werr_b : 1;
2642 bdrkreg_t eip_wrb_terr_a : 1;
2643 bdrkreg_t eip_wrb_terr_b : 1;
2644 bdrkreg_t eip_spurious_a : 1;
2645 bdrkreg_t eip_spurious_b : 1;
2646 bdrkreg_t eip_spool_comp_a : 1;
2647 bdrkreg_t eip_spool_comp_b : 1;
2648 } pi_err_int_pend_fld_s;
2649 } pi_err_int_pend_u_t;
2657 /************************************************************************
2659 * There is one of these registers for each CPU. This read/write *
2660 * register masks the contents of ERR_INT_PEND to determine which *
2661 * conditions cause a Level-6 interrupt to CPU_A or CPU_B. A bit set *
2662 * allows the interrupt. Only one processor in a Bedrock should *
2663 * enable the Memory/Directory Uncorrectable Error bit. *
2665 ************************************************************************/
2670 #ifdef LITTLE_ENDIAN
2672 typedef union pi_err_int_mask_a_u {
2673 bdrkreg_t pi_err_int_mask_a_regval;
2675 bdrkreg_t eima_mask : 35;
2676 bdrkreg_t eima_rsvd : 29;
2677 } pi_err_int_mask_a_fld_s;
2678 } pi_err_int_mask_a_u_t;
2682 typedef union pi_err_int_mask_a_u {
2683 bdrkreg_t pi_err_int_mask_a_regval;
2685 bdrkreg_t eima_rsvd : 29;
2686 bdrkreg_t eima_mask : 35;
2687 } pi_err_int_mask_a_fld_s;
2688 } pi_err_int_mask_a_u_t;
2695 /************************************************************************
2697 * There is one of these registers for each CPU. This read/write *
2698 * register masks the contents of ERR_INT_PEND to determine which *
2699 * conditions cause a Level-6 interrupt to CPU_A or CPU_B. A bit set *
2700 * allows the interrupt. Only one processor in a Bedrock should *
2701 * enable the Memory/Directory Uncorrectable Error bit. *
2703 ************************************************************************/
2708 #ifdef LITTLE_ENDIAN
2710 typedef union pi_err_int_mask_b_u {
2711 bdrkreg_t pi_err_int_mask_b_regval;
2713 bdrkreg_t eimb_mask : 35;
2714 bdrkreg_t eimb_rsvd : 29;
2715 } pi_err_int_mask_b_fld_s;
2716 } pi_err_int_mask_b_u_t;
2720 typedef union pi_err_int_mask_b_u {
2721 bdrkreg_t pi_err_int_mask_b_regval;
2723 bdrkreg_t eimb_rsvd : 29;
2724 bdrkreg_t eimb_mask : 35;
2725 } pi_err_int_mask_b_fld_s;
2726 } pi_err_int_mask_b_u_t;
2733 /************************************************************************
2735 * Description: There is one of these registers for each CPU. This *
2736 * register is the address of the next write to the error stack. This *
2737 * register is incremented after each such write. Only the low N bits *
2738 * are incremented, where N is defined by the size of the error stack *
2739 * specified in the ERR_STACK_SIZE register. *
2740 * This register is not reset by a soft reset. *
2742 ************************************************************************/
2747 #ifdef LITTLE_ENDIAN
2749 typedef union pi_err_stack_addr_a_u {
2750 bdrkreg_t pi_err_stack_addr_a_regval;
2752 bdrkreg_t esaa_rsvd_1 : 3;
2753 bdrkreg_t esaa_addr : 30;
2754 bdrkreg_t esaa_rsvd : 31;
2755 } pi_err_stack_addr_a_fld_s;
2756 } pi_err_stack_addr_a_u_t;
2760 typedef union pi_err_stack_addr_a_u {
2761 bdrkreg_t pi_err_stack_addr_a_regval;
2763 bdrkreg_t esaa_rsvd : 31;
2764 bdrkreg_t esaa_addr : 30;
2765 bdrkreg_t esaa_rsvd_1 : 3;
2766 } pi_err_stack_addr_a_fld_s;
2767 } pi_err_stack_addr_a_u_t;
2774 /************************************************************************
2776 * Description: There is one of these registers for each CPU. This *
2777 * register is the address of the next write to the error stack. This *
2778 * register is incremented after each such write. Only the low N bits *
2779 * are incremented, where N is defined by the size of the error stack *
2780 * specified in the ERR_STACK_SIZE register. *
2781 * This register is not reset by a soft reset. *
2783 ************************************************************************/
2788 #ifdef LITTLE_ENDIAN
2790 typedef union pi_err_stack_addr_b_u {
2791 bdrkreg_t pi_err_stack_addr_b_regval;
2793 bdrkreg_t esab_rsvd_1 : 3;
2794 bdrkreg_t esab_addr : 30;
2795 bdrkreg_t esab_rsvd : 31;
2796 } pi_err_stack_addr_b_fld_s;
2797 } pi_err_stack_addr_b_u_t;
2801 typedef union pi_err_stack_addr_b_u {
2802 bdrkreg_t pi_err_stack_addr_b_regval;
2804 bdrkreg_t esab_rsvd : 31;
2805 bdrkreg_t esab_addr : 30;
2806 bdrkreg_t esab_rsvd_1 : 3;
2807 } pi_err_stack_addr_b_fld_s;
2808 } pi_err_stack_addr_b_u_t;
2815 /************************************************************************
2817 * Description: Sets the size (number of 64-bit entries) in the *
2818 * error stack that is spooled to local memory when an error occurs. *
2819 * Table16 defines the format of each entry in the spooled error *
2821 * This register is not reset by a soft reset. *
2823 ************************************************************************/
2828 #ifdef LITTLE_ENDIAN
2830 typedef union pi_err_stack_size_u {
2831 bdrkreg_t pi_err_stack_size_regval;
2833 bdrkreg_t ess_size : 4;
2834 bdrkreg_t ess_rsvd : 60;
2835 } pi_err_stack_size_fld_s;
2836 } pi_err_stack_size_u_t;
2840 typedef union pi_err_stack_size_u {
2841 bdrkreg_t pi_err_stack_size_regval;
2843 bdrkreg_t ess_rsvd : 60;
2844 bdrkreg_t ess_size : 4;
2845 } pi_err_stack_size_fld_s;
2846 } pi_err_stack_size_u_t;
2853 /************************************************************************
2855 * This register is not cleared at reset. Writing this register with *
2856 * the Write-clear address (with any data) clears both the *
2857 * ERR_STATUS0_A and ERR_STATUS1_A registers. *
2859 ************************************************************************/
2864 #ifdef LITTLE_ENDIAN
2866 typedef union pi_err_status0_a_u {
2867 bdrkreg_t pi_err_status0_a_regval;
2869 bdrkreg_t esa_error_type : 3;
2870 bdrkreg_t esa_proc_req_num : 3;
2871 bdrkreg_t esa_supplemental : 11;
2872 bdrkreg_t esa_cmd : 8;
2873 bdrkreg_t esa_addr : 37;
2874 bdrkreg_t esa_over_run : 1;
2875 bdrkreg_t esa_valid : 1;
2876 } pi_err_status0_a_fld_s;
2877 } pi_err_status0_a_u_t;
2881 typedef union pi_err_status0_a_u {
2882 bdrkreg_t pi_err_status0_a_regval;
2884 bdrkreg_t esa_valid : 1;
2885 bdrkreg_t esa_over_run : 1;
2886 bdrkreg_t esa_addr : 37;
2887 bdrkreg_t esa_cmd : 8;
2888 bdrkreg_t esa_supplemental : 11;
2889 bdrkreg_t esa_proc_req_num : 3;
2890 bdrkreg_t esa_error_type : 3;
2891 } pi_err_status0_a_fld_s;
2892 } pi_err_status0_a_u_t;
2899 /************************************************************************
2901 * This register is not cleared at reset. Writing this register with *
2902 * the Write-clear address (with any data) clears both the *
2903 * ERR_STATUS0_A and ERR_STATUS1_A registers. *
2905 ************************************************************************/
2910 #ifdef LITTLE_ENDIAN
2912 typedef union pi_err_status0_a_clr_u {
2913 bdrkreg_t pi_err_status0_a_clr_regval;
2915 bdrkreg_t esac_error_type : 3;
2916 bdrkreg_t esac_proc_req_num : 3;
2917 bdrkreg_t esac_supplemental : 11;
2918 bdrkreg_t esac_cmd : 8;
2919 bdrkreg_t esac_addr : 37;
2920 bdrkreg_t esac_over_run : 1;
2921 bdrkreg_t esac_valid : 1;
2922 } pi_err_status0_a_clr_fld_s;
2923 } pi_err_status0_a_clr_u_t;
2927 typedef union pi_err_status0_a_clr_u {
2928 bdrkreg_t pi_err_status0_a_clr_regval;
2930 bdrkreg_t esac_valid : 1;
2931 bdrkreg_t esac_over_run : 1;
2932 bdrkreg_t esac_addr : 37;
2933 bdrkreg_t esac_cmd : 8;
2934 bdrkreg_t esac_supplemental : 11;
2935 bdrkreg_t esac_proc_req_num : 3;
2936 bdrkreg_t esac_error_type : 3;
2937 } pi_err_status0_a_clr_fld_s;
2938 } pi_err_status0_a_clr_u_t;
2945 /************************************************************************
2947 * This register is not cleared at reset. Writing this register with *
2948 * the Write-clear address (with any data) clears both the *
2949 * ERR_STATUS0_A and ERR_STATUS1_A registers. *
2951 ************************************************************************/
2956 #ifdef LITTLE_ENDIAN
2958 typedef union pi_err_status1_a_u {
2959 bdrkreg_t pi_err_status1_a_regval;
2961 bdrkreg_t esa_spool_count : 21;
2962 bdrkreg_t esa_time_out_count : 8;
2963 bdrkreg_t esa_inval_count : 10;
2964 bdrkreg_t esa_crb_num : 3;
2965 bdrkreg_t esa_wrb : 1;
2966 bdrkreg_t esa_e_bits : 2;
2967 bdrkreg_t esa_t_bit : 1;
2968 bdrkreg_t esa_i_bit : 1;
2969 bdrkreg_t esa_h_bit : 1;
2970 bdrkreg_t esa_w_bit : 1;
2971 bdrkreg_t esa_a_bit : 1;
2972 bdrkreg_t esa_r_bit : 1;
2973 bdrkreg_t esa_v_bit : 1;
2974 bdrkreg_t esa_p_bit : 1;
2975 bdrkreg_t esa_source : 11;
2976 } pi_err_status1_a_fld_s;
2977 } pi_err_status1_a_u_t;
2981 typedef union pi_err_status1_a_u {
2982 bdrkreg_t pi_err_status1_a_regval;
2984 bdrkreg_t esa_source : 11;
2985 bdrkreg_t esa_p_bit : 1;
2986 bdrkreg_t esa_v_bit : 1;
2987 bdrkreg_t esa_r_bit : 1;
2988 bdrkreg_t esa_a_bit : 1;
2989 bdrkreg_t esa_w_bit : 1;
2990 bdrkreg_t esa_h_bit : 1;
2991 bdrkreg_t esa_i_bit : 1;
2992 bdrkreg_t esa_t_bit : 1;
2993 bdrkreg_t esa_e_bits : 2;
2994 bdrkreg_t esa_wrb : 1;
2995 bdrkreg_t esa_crb_num : 3;
2996 bdrkreg_t esa_inval_count : 10;
2997 bdrkreg_t esa_time_out_count : 8;
2998 bdrkreg_t esa_spool_count : 21;
2999 } pi_err_status1_a_fld_s;
3000 } pi_err_status1_a_u_t;
3007 /************************************************************************
3009 * This register is not cleared at reset. Writing this register with *
3010 * the Write-clear address (with any data) clears both the *
3011 * ERR_STATUS0_A and ERR_STATUS1_A registers. *
3013 ************************************************************************/
3018 #ifdef LITTLE_ENDIAN
3020 typedef union pi_err_status1_a_clr_u {
3021 bdrkreg_t pi_err_status1_a_clr_regval;
3023 bdrkreg_t esac_spool_count : 21;
3024 bdrkreg_t esac_time_out_count : 8;
3025 bdrkreg_t esac_inval_count : 10;
3026 bdrkreg_t esac_crb_num : 3;
3027 bdrkreg_t esac_wrb : 1;
3028 bdrkreg_t esac_e_bits : 2;
3029 bdrkreg_t esac_t_bit : 1;
3030 bdrkreg_t esac_i_bit : 1;
3031 bdrkreg_t esac_h_bit : 1;
3032 bdrkreg_t esac_w_bit : 1;
3033 bdrkreg_t esac_a_bit : 1;
3034 bdrkreg_t esac_r_bit : 1;
3035 bdrkreg_t esac_v_bit : 1;
3036 bdrkreg_t esac_p_bit : 1;
3037 bdrkreg_t esac_source : 11;
3038 } pi_err_status1_a_clr_fld_s;
3039 } pi_err_status1_a_clr_u_t;
3043 typedef union pi_err_status1_a_clr_u {
3044 bdrkreg_t pi_err_status1_a_clr_regval;
3046 bdrkreg_t esac_source : 11;
3047 bdrkreg_t esac_p_bit : 1;
3048 bdrkreg_t esac_v_bit : 1;
3049 bdrkreg_t esac_r_bit : 1;
3050 bdrkreg_t esac_a_bit : 1;
3051 bdrkreg_t esac_w_bit : 1;
3052 bdrkreg_t esac_h_bit : 1;
3053 bdrkreg_t esac_i_bit : 1;
3054 bdrkreg_t esac_t_bit : 1;
3055 bdrkreg_t esac_e_bits : 2;
3056 bdrkreg_t esac_wrb : 1;
3057 bdrkreg_t esac_crb_num : 3;
3058 bdrkreg_t esac_inval_count : 10;
3059 bdrkreg_t esac_time_out_count : 8;
3060 bdrkreg_t esac_spool_count : 21;
3061 } pi_err_status1_a_clr_fld_s;
3062 } pi_err_status1_a_clr_u_t;
3069 /************************************************************************
3071 * This register is not cleared at reset. Writing this register with *
3072 * the Write-clear address (with any data) clears both the *
3073 * ERR_STATUS0_B and ERR_STATUS1_B registers. *
3075 ************************************************************************/
3080 #ifdef LITTLE_ENDIAN
3082 typedef union pi_err_status0_b_u {
3083 bdrkreg_t pi_err_status0_b_regval;
3085 bdrkreg_t esb_error_type : 3;
3086 bdrkreg_t esb_proc_request_number : 3;
3087 bdrkreg_t esb_supplemental : 11;
3088 bdrkreg_t esb_cmd : 8;
3089 bdrkreg_t esb_addr : 37;
3090 bdrkreg_t esb_over_run : 1;
3091 bdrkreg_t esb_valid : 1;
3092 } pi_err_status0_b_fld_s;
3093 } pi_err_status0_b_u_t;
3097 typedef union pi_err_status0_b_u {
3098 bdrkreg_t pi_err_status0_b_regval;
3100 bdrkreg_t esb_valid : 1;
3101 bdrkreg_t esb_over_run : 1;
3102 bdrkreg_t esb_addr : 37;
3103 bdrkreg_t esb_cmd : 8;
3104 bdrkreg_t esb_supplemental : 11;
3105 bdrkreg_t esb_proc_request_number : 3;
3106 bdrkreg_t esb_error_type : 3;
3107 } pi_err_status0_b_fld_s;
3108 } pi_err_status0_b_u_t;
3115 /************************************************************************
3117 * This register is not cleared at reset. Writing this register with *
3118 * the Write-clear address (with any data) clears both the *
3119 * ERR_STATUS0_B and ERR_STATUS1_B registers. *
3121 ************************************************************************/
3126 #ifdef LITTLE_ENDIAN
3128 typedef union pi_err_status0_b_clr_u {
3129 bdrkreg_t pi_err_status0_b_clr_regval;
3131 bdrkreg_t esbc_error_type : 3;
3132 bdrkreg_t esbc_proc_request_number : 3;
3133 bdrkreg_t esbc_supplemental : 11;
3134 bdrkreg_t esbc_cmd : 8;
3135 bdrkreg_t esbc_addr : 37;
3136 bdrkreg_t esbc_over_run : 1;
3137 bdrkreg_t esbc_valid : 1;
3138 } pi_err_status0_b_clr_fld_s;
3139 } pi_err_status0_b_clr_u_t;
3143 typedef union pi_err_status0_b_clr_u {
3144 bdrkreg_t pi_err_status0_b_clr_regval;
3146 bdrkreg_t esbc_valid : 1;
3147 bdrkreg_t esbc_over_run : 1;
3148 bdrkreg_t esbc_addr : 37;
3149 bdrkreg_t esbc_cmd : 8;
3150 bdrkreg_t esbc_supplemental : 11;
3151 bdrkreg_t esbc_proc_request_number : 3;
3152 bdrkreg_t esbc_error_type : 3;
3153 } pi_err_status0_b_clr_fld_s;
3154 } pi_err_status0_b_clr_u_t;
3161 /************************************************************************
3163 * This register is not cleared at reset. Writing this register with *
3164 * the Write-clear address (with any data) clears both the *
3165 * ERR_STATUS0_B and ERR_STATUS1_B registers. *
3167 ************************************************************************/
3172 #ifdef LITTLE_ENDIAN
3174 typedef union pi_err_status1_b_u {
3175 bdrkreg_t pi_err_status1_b_regval;
3177 bdrkreg_t esb_spool_count : 21;
3178 bdrkreg_t esb_time_out_count : 8;
3179 bdrkreg_t esb_inval_count : 10;
3180 bdrkreg_t esb_crb_num : 3;
3181 bdrkreg_t esb_wrb : 1;
3182 bdrkreg_t esb_e_bits : 2;
3183 bdrkreg_t esb_t_bit : 1;
3184 bdrkreg_t esb_i_bit : 1;
3185 bdrkreg_t esb_h_bit : 1;
3186 bdrkreg_t esb_w_bit : 1;
3187 bdrkreg_t esb_a_bit : 1;
3188 bdrkreg_t esb_r_bit : 1;
3189 bdrkreg_t esb_v_bit : 1;
3190 bdrkreg_t esb_p_bit : 1;
3191 bdrkreg_t esb_source : 11;
3192 } pi_err_status1_b_fld_s;
3193 } pi_err_status1_b_u_t;
3197 typedef union pi_err_status1_b_u {
3198 bdrkreg_t pi_err_status1_b_regval;
3200 bdrkreg_t esb_source : 11;
3201 bdrkreg_t esb_p_bit : 1;
3202 bdrkreg_t esb_v_bit : 1;
3203 bdrkreg_t esb_r_bit : 1;
3204 bdrkreg_t esb_a_bit : 1;
3205 bdrkreg_t esb_w_bit : 1;
3206 bdrkreg_t esb_h_bit : 1;
3207 bdrkreg_t esb_i_bit : 1;
3208 bdrkreg_t esb_t_bit : 1;
3209 bdrkreg_t esb_e_bits : 2;
3210 bdrkreg_t esb_wrb : 1;
3211 bdrkreg_t esb_crb_num : 3;
3212 bdrkreg_t esb_inval_count : 10;
3213 bdrkreg_t esb_time_out_count : 8;
3214 bdrkreg_t esb_spool_count : 21;
3215 } pi_err_status1_b_fld_s;
3216 } pi_err_status1_b_u_t;
3223 /************************************************************************
3225 * This register is not cleared at reset. Writing this register with *
3226 * the Write-clear address (with any data) clears both the *
3227 * ERR_STATUS0_B and ERR_STATUS1_B registers. *
3229 ************************************************************************/
3234 #ifdef LITTLE_ENDIAN
3236 typedef union pi_err_status1_b_clr_u {
3237 bdrkreg_t pi_err_status1_b_clr_regval;
3239 bdrkreg_t esbc_spool_count : 21;
3240 bdrkreg_t esbc_time_out_count : 8;
3241 bdrkreg_t esbc_inval_count : 10;
3242 bdrkreg_t esbc_crb_num : 3;
3243 bdrkreg_t esbc_wrb : 1;
3244 bdrkreg_t esbc_e_bits : 2;
3245 bdrkreg_t esbc_t_bit : 1;
3246 bdrkreg_t esbc_i_bit : 1;
3247 bdrkreg_t esbc_h_bit : 1;
3248 bdrkreg_t esbc_w_bit : 1;
3249 bdrkreg_t esbc_a_bit : 1;
3250 bdrkreg_t esbc_r_bit : 1;
3251 bdrkreg_t esbc_v_bit : 1;
3252 bdrkreg_t esbc_p_bit : 1;
3253 bdrkreg_t esbc_source : 11;
3254 } pi_err_status1_b_clr_fld_s;
3255 } pi_err_status1_b_clr_u_t;
3259 typedef union pi_err_status1_b_clr_u {
3260 bdrkreg_t pi_err_status1_b_clr_regval;
3262 bdrkreg_t esbc_source : 11;
3263 bdrkreg_t esbc_p_bit : 1;
3264 bdrkreg_t esbc_v_bit : 1;
3265 bdrkreg_t esbc_r_bit : 1;
3266 bdrkreg_t esbc_a_bit : 1;
3267 bdrkreg_t esbc_w_bit : 1;
3268 bdrkreg_t esbc_h_bit : 1;
3269 bdrkreg_t esbc_i_bit : 1;
3270 bdrkreg_t esbc_t_bit : 1;
3271 bdrkreg_t esbc_e_bits : 2;
3272 bdrkreg_t esbc_wrb : 1;
3273 bdrkreg_t esbc_crb_num : 3;
3274 bdrkreg_t esbc_inval_count : 10;
3275 bdrkreg_t esbc_time_out_count : 8;
3276 bdrkreg_t esbc_spool_count : 21;
3277 } pi_err_status1_b_clr_fld_s;
3278 } pi_err_status1_b_clr_u_t;
3285 /************************************************************************
3287 * There is one of these registers for each CPU. *
3289 ************************************************************************/
3294 #ifdef LITTLE_ENDIAN
3296 typedef union pi_spool_cmp_a_u {
3297 bdrkreg_t pi_spool_cmp_a_regval;
3299 bdrkreg_t sca_compare : 20;
3300 bdrkreg_t sca_rsvd : 44;
3301 } pi_spool_cmp_a_fld_s;
3302 } pi_spool_cmp_a_u_t;
3306 typedef union pi_spool_cmp_a_u {
3307 bdrkreg_t pi_spool_cmp_a_regval;
3309 bdrkreg_t sca_rsvd : 44;
3310 bdrkreg_t sca_compare : 20;
3311 } pi_spool_cmp_a_fld_s;
3312 } pi_spool_cmp_a_u_t;
3319 /************************************************************************
3321 * There is one of these registers for each CPU. *
3323 ************************************************************************/
3328 #ifdef LITTLE_ENDIAN
3330 typedef union pi_spool_cmp_b_u {
3331 bdrkreg_t pi_spool_cmp_b_regval;
3333 bdrkreg_t scb_compare : 20;
3334 bdrkreg_t scb_rsvd : 44;
3335 } pi_spool_cmp_b_fld_s;
3336 } pi_spool_cmp_b_u_t;
3340 typedef union pi_spool_cmp_b_u {
3341 bdrkreg_t pi_spool_cmp_b_regval;
3343 bdrkreg_t scb_rsvd : 44;
3344 bdrkreg_t scb_compare : 20;
3345 } pi_spool_cmp_b_fld_s;
3346 } pi_spool_cmp_b_u_t;
3353 /************************************************************************
3355 * There is one of these registers for each CPU. A timeout can be *
3356 * forced by writing one(s). *
3358 ************************************************************************/
3363 #ifdef LITTLE_ENDIAN
3365 typedef union pi_crb_timeout_a_u {
3366 bdrkreg_t pi_crb_timeout_a_regval;
3368 bdrkreg_t cta_rrb : 4;
3369 bdrkreg_t cta_wrb : 8;
3370 bdrkreg_t cta_rsvd : 52;
3371 } pi_crb_timeout_a_fld_s;
3372 } pi_crb_timeout_a_u_t;
3376 typedef union pi_crb_timeout_a_u {
3377 bdrkreg_t pi_crb_timeout_a_regval;
3379 bdrkreg_t cta_rsvd : 52;
3380 bdrkreg_t cta_wrb : 8;
3381 bdrkreg_t cta_rrb : 4;
3382 } pi_crb_timeout_a_fld_s;
3383 } pi_crb_timeout_a_u_t;
3390 /************************************************************************
3392 * There is one of these registers for each CPU. A timeout can be *
3393 * forced by writing one(s). *
3395 ************************************************************************/
3400 #ifdef LITTLE_ENDIAN
3402 typedef union pi_crb_timeout_b_u {
3403 bdrkreg_t pi_crb_timeout_b_regval;
3405 bdrkreg_t ctb_rrb : 4;
3406 bdrkreg_t ctb_wrb : 8;
3407 bdrkreg_t ctb_rsvd : 52;
3408 } pi_crb_timeout_b_fld_s;
3409 } pi_crb_timeout_b_u_t;
3413 typedef union pi_crb_timeout_b_u {
3414 bdrkreg_t pi_crb_timeout_b_regval;
3416 bdrkreg_t ctb_rsvd : 52;
3417 bdrkreg_t ctb_wrb : 8;
3418 bdrkreg_t ctb_rrb : 4;
3419 } pi_crb_timeout_b_fld_s;
3420 } pi_crb_timeout_b_u_t;
3427 /************************************************************************
3429 * This register controls error checking and forwarding of SysAD *
3432 ************************************************************************/
3437 #ifdef LITTLE_ENDIAN
3439 typedef union pi_sysad_errchk_en_u {
3440 bdrkreg_t pi_sysad_errchk_en_regval;
3442 bdrkreg_t see_ecc_gen_en : 1;
3443 bdrkreg_t see_qual_gen_en : 1;
3444 bdrkreg_t see_sadp_chk_en : 1;
3445 bdrkreg_t see_cmdp_chk_en : 1;
3446 bdrkreg_t see_state_chk_en : 1;
3447 bdrkreg_t see_qual_chk_en : 1;
3448 bdrkreg_t see_rsvd : 58;
3449 } pi_sysad_errchk_en_fld_s;
3450 } pi_sysad_errchk_en_u_t;
3454 typedef union pi_sysad_errchk_en_u {
3455 bdrkreg_t pi_sysad_errchk_en_regval;
3457 bdrkreg_t see_rsvd : 58;
3458 bdrkreg_t see_qual_chk_en : 1;
3459 bdrkreg_t see_state_chk_en : 1;
3460 bdrkreg_t see_cmdp_chk_en : 1;
3461 bdrkreg_t see_sadp_chk_en : 1;
3462 bdrkreg_t see_qual_gen_en : 1;
3463 bdrkreg_t see_ecc_gen_en : 1;
3464 } pi_sysad_errchk_en_fld_s;
3465 } pi_sysad_errchk_en_u_t;
3472 /************************************************************************
3474 * There is one of these registers for each CPU. If any bit in this *
3475 * register is set, then whenever reply data arrives with the UE *
3476 * (uncorrectable error) indication set, the check-bits that are *
3477 * generated and sent to the SysAD will be inverted corresponding to *
3478 * the bits set in the register. This will also prevent the assertion *
3479 * of the data quality indicator. *
3481 ************************************************************************/
3486 #ifdef LITTLE_ENDIAN
3488 typedef union pi_force_bad_check_bit_a_u {
3489 bdrkreg_t pi_force_bad_check_bit_a_regval;
3491 bdrkreg_t fbcba_bad_check_bit : 8;
3492 bdrkreg_t fbcba_rsvd : 56;
3493 } pi_force_bad_check_bit_a_fld_s;
3494 } pi_force_bad_check_bit_a_u_t;
3498 typedef union pi_force_bad_check_bit_a_u {
3499 bdrkreg_t pi_force_bad_check_bit_a_regval;
3501 bdrkreg_t fbcba_rsvd : 56;
3502 bdrkreg_t fbcba_bad_check_bit : 8;
3503 } pi_force_bad_check_bit_a_fld_s;
3504 } pi_force_bad_check_bit_a_u_t;
3511 /************************************************************************
3513 * There is one of these registers for each CPU. If any bit in this *
3514 * register is set, then whenever reply data arrives with the UE *
3515 * (uncorrectable error) indication set, the check-bits that are *
3516 * generated and sent to the SysAD will be inverted corresponding to *
3517 * the bits set in the register. This will also prevent the assertion *
3518 * of the data quality indicator. *
3520 ************************************************************************/
3525 #ifdef LITTLE_ENDIAN
3527 typedef union pi_force_bad_check_bit_b_u {
3528 bdrkreg_t pi_force_bad_check_bit_b_regval;
3530 bdrkreg_t fbcbb_bad_check_bit : 8;
3531 bdrkreg_t fbcbb_rsvd : 56;
3532 } pi_force_bad_check_bit_b_fld_s;
3533 } pi_force_bad_check_bit_b_u_t;
3537 typedef union pi_force_bad_check_bit_b_u {
3538 bdrkreg_t pi_force_bad_check_bit_b_regval;
3540 bdrkreg_t fbcbb_rsvd : 56;
3541 bdrkreg_t fbcbb_bad_check_bit : 8;
3542 } pi_force_bad_check_bit_b_fld_s;
3543 } pi_force_bad_check_bit_b_u_t;
3550 /************************************************************************
3552 * There is one of these registers for each CPU. When a counter is *
3553 * enabled, it increments each time a DNACK reply is received. The *
3554 * counter is cleared when any other reply is received. The register *
3555 * is cleared when the CNT_EN bit is zero. If a DNACK reply is *
3556 * received when the counter equals the value in the NACK_CMP *
3557 * register, the counter is cleared, an error response is sent to the *
3558 * CPU instead of a nack response, and the NACK_INT_A/B bit is set in *
3561 ************************************************************************/
3566 #ifdef LITTLE_ENDIAN
3568 typedef union pi_nack_cnt_a_u {
3569 bdrkreg_t pi_nack_cnt_a_regval;
3571 bdrkreg_t nca_nack_cnt : 20;
3572 bdrkreg_t nca_cnt_en : 1;
3573 bdrkreg_t nca_rsvd : 43;
3574 } pi_nack_cnt_a_fld_s;
3575 } pi_nack_cnt_a_u_t;
3579 typedef union pi_nack_cnt_a_u {
3580 bdrkreg_t pi_nack_cnt_a_regval;
3582 bdrkreg_t nca_rsvd : 43;
3583 bdrkreg_t nca_cnt_en : 1;
3584 bdrkreg_t nca_nack_cnt : 20;
3585 } pi_nack_cnt_a_fld_s;
3586 } pi_nack_cnt_a_u_t;
3593 /************************************************************************
3595 * There is one of these registers for each CPU. When a counter is *
3596 * enabled, it increments each time a DNACK reply is received. The *
3597 * counter is cleared when any other reply is received. The register *
3598 * is cleared when the CNT_EN bit is zero. If a DNACK reply is *
3599 * received when the counter equals the value in the NACK_CMP *
3600 * register, the counter is cleared, an error response is sent to the *
3601 * CPU instead of a nack response, and the NACK_INT_A/B bit is set in *
3604 ************************************************************************/
3609 #ifdef LITTLE_ENDIAN
3611 typedef union pi_nack_cnt_b_u {
3612 bdrkreg_t pi_nack_cnt_b_regval;
3614 bdrkreg_t ncb_nack_cnt : 20;
3615 bdrkreg_t ncb_cnt_en : 1;
3616 bdrkreg_t ncb_rsvd : 43;
3617 } pi_nack_cnt_b_fld_s;
3618 } pi_nack_cnt_b_u_t;
3622 typedef union pi_nack_cnt_b_u {
3623 bdrkreg_t pi_nack_cnt_b_regval;
3625 bdrkreg_t ncb_rsvd : 43;
3626 bdrkreg_t ncb_cnt_en : 1;
3627 bdrkreg_t ncb_nack_cnt : 20;
3628 } pi_nack_cnt_b_fld_s;
3629 } pi_nack_cnt_b_u_t;
3636 /************************************************************************
3638 * The setting of this register affects both CPUs on this PI. *
3640 ************************************************************************/
3645 #ifdef LITTLE_ENDIAN
3647 typedef union pi_nack_cmp_u {
3648 bdrkreg_t pi_nack_cmp_regval;
3650 bdrkreg_t nc_nack_cmp : 20;
3651 bdrkreg_t nc_rsvd : 44;
3652 } pi_nack_cmp_fld_s;
3657 typedef union pi_nack_cmp_u {
3658 bdrkreg_t pi_nack_cmp_regval;
3660 bdrkreg_t nc_rsvd : 44;
3661 bdrkreg_t nc_nack_cmp : 20;
3662 } pi_nack_cmp_fld_s;
3670 /************************************************************************
3672 * This register controls which errors are spooled. When a bit in *
3673 * this register is set, the corresponding error is spooled. The *
3674 * setting of this register affects both CPUs on this PI. *
3676 ************************************************************************/
3681 #ifdef LITTLE_ENDIAN
3683 typedef union pi_spool_mask_u {
3684 bdrkreg_t pi_spool_mask_regval;
3686 bdrkreg_t sm_access_err : 1;
3687 bdrkreg_t sm_uncached_err : 1;
3688 bdrkreg_t sm_dir_err : 1;
3689 bdrkreg_t sm_timeout_err : 1;
3690 bdrkreg_t sm_poison_err : 1;
3691 bdrkreg_t sm_nack_oflow_err : 1;
3692 bdrkreg_t sm_rsvd : 58;
3693 } pi_spool_mask_fld_s;
3694 } pi_spool_mask_u_t;
3698 typedef union pi_spool_mask_u {
3699 bdrkreg_t pi_spool_mask_regval;
3701 bdrkreg_t sm_rsvd : 58;
3702 bdrkreg_t sm_nack_oflow_err : 1;
3703 bdrkreg_t sm_poison_err : 1;
3704 bdrkreg_t sm_timeout_err : 1;
3705 bdrkreg_t sm_dir_err : 1;
3706 bdrkreg_t sm_uncached_err : 1;
3707 bdrkreg_t sm_access_err : 1;
3708 } pi_spool_mask_fld_s;
3709 } pi_spool_mask_u_t;
3716 /************************************************************************
3718 * This register is not cleared at reset. When the VALID bit is *
3719 * zero, this register (along with SPURIOUS_HDR_1) will capture the *
3720 * header of an incoming spurious message received from the XBar. A *
3721 * spurious message is a message that does not match up with any of *
3722 * the CRB entries. This is a read/write register, so it is cleared *
3723 * by writing of all zeros. *
3725 ************************************************************************/
3730 #ifdef LITTLE_ENDIAN
3732 typedef union pi_spurious_hdr_0_u {
3733 bdrkreg_t pi_spurious_hdr_0_regval;
3735 bdrkreg_t sh0_prev_valid_b : 1;
3736 bdrkreg_t sh0_prev_valid_a : 1;
3737 bdrkreg_t sh0_rsvd : 4;
3738 bdrkreg_t sh0_supplemental : 11;
3739 bdrkreg_t sh0_cmd : 8;
3740 bdrkreg_t sh0_addr : 37;
3741 bdrkreg_t sh0_tail : 1;
3742 bdrkreg_t sh0_valid : 1;
3743 } pi_spurious_hdr_0_fld_s;
3744 } pi_spurious_hdr_0_u_t;
3748 typedef union pi_spurious_hdr_0_u {
3749 bdrkreg_t pi_spurious_hdr_0_regval;
3751 bdrkreg_t sh0_valid : 1;
3752 bdrkreg_t sh0_tail : 1;
3753 bdrkreg_t sh0_addr : 37;
3754 bdrkreg_t sh0_cmd : 8;
3755 bdrkreg_t sh0_supplemental : 11;
3756 bdrkreg_t sh0_rsvd : 4;
3757 bdrkreg_t sh0_prev_valid_a : 1;
3758 bdrkreg_t sh0_prev_valid_b : 1;
3759 } pi_spurious_hdr_0_fld_s;
3760 } pi_spurious_hdr_0_u_t;
3767 /************************************************************************
3769 * This register is not cleared at reset. When the VALID bit in *
3770 * SPURIOUS_HDR_0 is zero, this register (along with SPURIOUS_HDR_0) *
3771 * will capture the header of an incoming spurious message received *
3772 * from the XBar. A spurious message is a message that does not match *
3773 * up with any of the CRB entries. This is a read/write register, so *
3774 * it is cleared by writing of all zeros. *
3776 ************************************************************************/
3781 #ifdef LITTLE_ENDIAN
3783 typedef union pi_spurious_hdr_1_u {
3784 bdrkreg_t pi_spurious_hdr_1_regval;
3786 bdrkreg_t sh1_rsvd : 53;
3787 bdrkreg_t sh1_source : 11;
3788 } pi_spurious_hdr_1_fld_s;
3789 } pi_spurious_hdr_1_u_t;
3793 typedef union pi_spurious_hdr_1_u {
3794 bdrkreg_t pi_spurious_hdr_1_regval;
3796 bdrkreg_t sh1_source : 11;
3797 bdrkreg_t sh1_rsvd : 53;
3798 } pi_spurious_hdr_1_fld_s;
3799 } pi_spurious_hdr_1_u_t;
3806 /************************************************************************
3808 * Description: This register controls the injection of errors in *
3809 * outbound SysAD transfers. When a write sets a bit in this *
3810 * register, the PI logic is "armed" to inject that error. At the *
3811 * first transfer of the specified type, the error is injected and *
3812 * the bit in this register is cleared. Writing to this register does *
3813 * not cause a transaction to occur. A bit in this register will *
3814 * remain set until a transaction of the specified type occurs as a *
3815 * result of normal system activity. This register can be polled to *
3816 * determine if an error has been injected or is still "armed". *
3817 * This register does not control injection of data quality bad *
3818 * indicator on a data cycle. This type of error can be created by *
3819 * reading from a memory location that has an uncorrectable ECC *
3822 ************************************************************************/
3827 #ifdef LITTLE_ENDIAN
3829 typedef union pi_err_inject_u {
3830 bdrkreg_t pi_err_inject_regval;
3832 bdrkreg_t ei_cmd_syscmd_par_a : 1;
3833 bdrkreg_t ei_data_syscmd_par_a : 1;
3834 bdrkreg_t ei_cmd_sysad_corecc_a : 1;
3835 bdrkreg_t ei_data_sysad_corecc_a : 1;
3836 bdrkreg_t ei_cmd_sysad_uncecc_a : 1;
3837 bdrkreg_t ei_data_sysad_uncecc_a : 1;
3838 bdrkreg_t ei_sysresp_par_a : 1;
3839 bdrkreg_t ei_reserved_1 : 25;
3840 bdrkreg_t ei_cmd_syscmd_par_b : 1;
3841 bdrkreg_t ei_data_syscmd_par_b : 1;
3842 bdrkreg_t ei_cmd_sysad_corecc_b : 1;
3843 bdrkreg_t ei_data_sysad_corecc_b : 1;
3844 bdrkreg_t ei_cmd_sysad_uncecc_b : 1;
3845 bdrkreg_t ei_data_sysad_uncecc_b : 1;
3846 bdrkreg_t ei_sysresp_par_b : 1;
3847 bdrkreg_t ei_reserved : 25;
3848 } pi_err_inject_fld_s;
3849 } pi_err_inject_u_t;
3853 typedef union pi_err_inject_u {
3854 bdrkreg_t pi_err_inject_regval;
3856 bdrkreg_t ei_reserved : 25;
3857 bdrkreg_t ei_sysresp_par_b : 1;
3858 bdrkreg_t ei_data_sysad_uncecc_b : 1;
3859 bdrkreg_t ei_cmd_sysad_uncecc_b : 1;
3860 bdrkreg_t ei_data_sysad_corecc_b : 1;
3861 bdrkreg_t ei_cmd_sysad_corecc_b : 1;
3862 bdrkreg_t ei_data_syscmd_par_b : 1;
3863 bdrkreg_t ei_cmd_syscmd_par_b : 1;
3864 bdrkreg_t ei_reserved_1 : 25;
3865 bdrkreg_t ei_sysresp_par_a : 1;
3866 bdrkreg_t ei_data_sysad_uncecc_a : 1;
3867 bdrkreg_t ei_cmd_sysad_uncecc_a : 1;
3868 bdrkreg_t ei_data_sysad_corecc_a : 1;
3869 bdrkreg_t ei_cmd_sysad_corecc_a : 1;
3870 bdrkreg_t ei_data_syscmd_par_a : 1;
3871 bdrkreg_t ei_cmd_syscmd_par_a : 1;
3872 } pi_err_inject_fld_s;
3873 } pi_err_inject_u_t;
3880 /************************************************************************
3882 * This Read/Write location determines at what point the TRex+ is *
3883 * stopped from issuing requests, based on the number of entries in *
3884 * the incoming reply FIFO. When the number of entries in the Reply *
3885 * FIFO is greater than the value of this register, the PI will *
3886 * deassert both SysWrRdy and SysRdRdy to both processors. The Reply *
3887 * FIFO has a depth of 0x3F entries, so setting this register to 0x3F *
3888 * effectively disables this feature, allowing requests to be issued *
3889 * always. Setting this register to 0x00 effectively lowers the *
3890 * TRex+'s priority below the reply FIFO, disabling TRex+ requests *
3891 * any time there is an entry waiting in the incoming FIFO.This *
3892 * register is in its own 64KB page so that it can be mapped to user *
3895 ************************************************************************/
3900 #ifdef LITTLE_ENDIAN
3902 typedef union pi_reply_level_u {
3903 bdrkreg_t pi_reply_level_regval;
3905 bdrkreg_t rl_reply_level : 6;
3906 bdrkreg_t rl_rsvd : 58;
3907 } pi_reply_level_fld_s;
3908 } pi_reply_level_u_t;
3912 typedef union pi_reply_level_u {
3913 bdrkreg_t pi_reply_level_regval;
3915 bdrkreg_t rl_rsvd : 58;
3916 bdrkreg_t rl_reply_level : 6;
3917 } pi_reply_level_fld_s;
3918 } pi_reply_level_u_t;
3925 /************************************************************************
3927 * This register is used to change the graphics credit counter *
3928 * operation from "Doubleword" mode to "Transaction" mode. This *
3929 * register is in its own 64KB page so that it can be mapped to user *
3932 ************************************************************************/
3937 #ifdef LITTLE_ENDIAN
3939 typedef union pi_gfx_credit_mode_u {
3940 bdrkreg_t pi_gfx_credit_mode_regval;
3942 bdrkreg_t gcm_trans_mode : 1;
3943 bdrkreg_t gcm_rsvd : 63;
3944 } pi_gfx_credit_mode_fld_s;
3945 } pi_gfx_credit_mode_u_t;
3949 typedef union pi_gfx_credit_mode_u {
3950 bdrkreg_t pi_gfx_credit_mode_regval;
3952 bdrkreg_t gcm_rsvd : 63;
3953 bdrkreg_t gcm_trans_mode : 1;
3954 } pi_gfx_credit_mode_fld_s;
3955 } pi_gfx_credit_mode_u_t;
3961 /************************************************************************
3963 * This location contains a 55-bit read/write counter that wraps to *
3964 * zero when the maximum value is reached. This counter is *
3965 * incremented at each rising edge of the global clock (GCLK). This *
3966 * register is in its own 64KB page so that it can be mapped to user *
3969 ************************************************************************/
3974 #ifdef LITTLE_ENDIAN
3976 typedef union pi_rt_counter_u {
3977 bdrkreg_t pi_rt_counter_regval;
3979 bdrkreg_t rc_count : 55;
3980 bdrkreg_t rc_rsvd : 9;
3981 } pi_rt_counter_fld_s;
3982 } pi_rt_counter_u_t;
3986 typedef union pi_rt_counter_u {
3987 bdrkreg_t pi_rt_counter_regval;
3989 bdrkreg_t rc_rsvd : 9;
3990 bdrkreg_t rc_count : 55;
3991 } pi_rt_counter_fld_s;
3992 } pi_rt_counter_u_t;
3999 /************************************************************************
4001 * This register controls the performance counters for one CPU. *
4002 * There are two counters for each CPU. Each counter can be *
4003 * configured to count a variety of events. The performance counter *
4004 * registers for each processor are in their own 64KB page so that *
4005 * they can be mapped to user space. *
4007 ************************************************************************/
4012 #ifdef LITTLE_ENDIAN
4014 typedef union pi_perf_cntl_a_u {
4015 bdrkreg_t pi_perf_cntl_a_regval;
4017 bdrkreg_t pca_cntr_0_select : 28;
4018 bdrkreg_t pca_cntr_0_mode : 3;
4019 bdrkreg_t pca_cntr_0_enable : 1;
4020 bdrkreg_t pca_cntr_1_select : 28;
4021 bdrkreg_t pca_cntr_1_mode : 3;
4022 bdrkreg_t pca_cntr_1_enable : 1;
4023 } pi_perf_cntl_a_fld_s;
4024 } pi_perf_cntl_a_u_t;
4028 typedef union pi_perf_cntl_a_u {
4029 bdrkreg_t pi_perf_cntl_a_regval;
4031 bdrkreg_t pca_cntr_1_enable : 1;
4032 bdrkreg_t pca_cntr_1_mode : 3;
4033 bdrkreg_t pca_cntr_1_select : 28;
4034 bdrkreg_t pca_cntr_0_enable : 1;
4035 bdrkreg_t pca_cntr_0_mode : 3;
4036 bdrkreg_t pca_cntr_0_select : 28;
4037 } pi_perf_cntl_a_fld_s;
4038 } pi_perf_cntl_a_u_t;
4045 /************************************************************************
4047 * This register accesses the performance counter 0 for each CPU. *
4048 * Each performance counter is 40-bits wide. On overflow, It wraps to *
4049 * zero, sets the overflow bit in this register, and sets the *
4050 * PERF_CNTR_OFLOW bit in the INT_PEND1 register. *
4052 ************************************************************************/
4057 #ifdef LITTLE_ENDIAN
4059 typedef union pi_perf_cntr0_a_u {
4060 bdrkreg_t pi_perf_cntr0_a_regval;
4062 bdrkreg_t pca_count_value : 40;
4063 bdrkreg_t pca_overflow : 1;
4064 bdrkreg_t pca_rsvd : 23;
4065 } pi_perf_cntr0_a_fld_s;
4066 } pi_perf_cntr0_a_u_t;
4070 typedef union pi_perf_cntr0_a_u {
4071 bdrkreg_t pi_perf_cntr0_a_regval;
4073 bdrkreg_t pca_rsvd : 23;
4074 bdrkreg_t pca_overflow : 1;
4075 bdrkreg_t pca_count_value : 40;
4076 } pi_perf_cntr0_a_fld_s;
4077 } pi_perf_cntr0_a_u_t;
4084 /************************************************************************
4086 * This register accesses the performance counter 1for each CPU. *
4087 * Each performance counter is 40-bits wide. On overflow, It wraps to *
4088 * zero, sets the overflow bit in this register, and sets the *
4089 * PERF_CNTR_OFLOW bit in the INT_PEND1 register. *
4091 ************************************************************************/
4096 #ifdef LITTLE_ENDIAN
4098 typedef union pi_perf_cntr1_a_u {
4099 bdrkreg_t pi_perf_cntr1_a_regval;
4101 bdrkreg_t pca_count_value : 40;
4102 bdrkreg_t pca_overflow : 1;
4103 bdrkreg_t pca_rsvd : 23;
4104 } pi_perf_cntr1_a_fld_s;
4105 } pi_perf_cntr1_a_u_t;
4109 typedef union pi_perf_cntr1_a_u {
4110 bdrkreg_t pi_perf_cntr1_a_regval;
4112 bdrkreg_t pca_rsvd : 23;
4113 bdrkreg_t pca_overflow : 1;
4114 bdrkreg_t pca_count_value : 40;
4115 } pi_perf_cntr1_a_fld_s;
4116 } pi_perf_cntr1_a_u_t;
4124 /************************************************************************
4126 * This register controls the performance counters for one CPU. *
4127 * There are two counters for each CPU. Each counter can be *
4128 * configured to count a variety of events. The performance counter *
4129 * registers for each processor are in their own 64KB page so that *
4130 * they can be mapped to user space. *
4132 ************************************************************************/
4137 #ifdef LITTLE_ENDIAN
4139 typedef union pi_perf_cntl_b_u {
4140 bdrkreg_t pi_perf_cntl_b_regval;
4142 bdrkreg_t pcb_cntr_0_select : 28;
4143 bdrkreg_t pcb_cntr_0_mode : 3;
4144 bdrkreg_t pcb_cntr_0_enable : 1;
4145 bdrkreg_t pcb_cntr_1_select : 28;
4146 bdrkreg_t pcb_cntr_1_mode : 3;
4147 bdrkreg_t pcb_cntr_1_enable : 1;
4148 } pi_perf_cntl_b_fld_s;
4149 } pi_perf_cntl_b_u_t;
4153 typedef union pi_perf_cntl_b_u {
4154 bdrkreg_t pi_perf_cntl_b_regval;
4156 bdrkreg_t pcb_cntr_1_enable : 1;
4157 bdrkreg_t pcb_cntr_1_mode : 3;
4158 bdrkreg_t pcb_cntr_1_select : 28;
4159 bdrkreg_t pcb_cntr_0_enable : 1;
4160 bdrkreg_t pcb_cntr_0_mode : 3;
4161 bdrkreg_t pcb_cntr_0_select : 28;
4162 } pi_perf_cntl_b_fld_s;
4163 } pi_perf_cntl_b_u_t;
4170 /************************************************************************
4172 * This register accesses the performance counter 0 for each CPU. *
4173 * Each performance counter is 40-bits wide. On overflow, It wraps to *
4174 * zero, sets the overflow bit in this register, and sets the *
4175 * PERF_CNTR_OFLOW bit in the INT_PEND1 register. *
4177 ************************************************************************/
4182 #ifdef LITTLE_ENDIAN
4184 typedef union pi_perf_cntr0_b_u {
4185 bdrkreg_t pi_perf_cntr0_b_regval;
4187 bdrkreg_t pcb_count_value : 40;
4188 bdrkreg_t pcb_overflow : 1;
4189 bdrkreg_t pcb_rsvd : 23;
4190 } pi_perf_cntr0_b_fld_s;
4191 } pi_perf_cntr0_b_u_t;
4195 typedef union pi_perf_cntr0_b_u {
4196 bdrkreg_t pi_perf_cntr0_b_regval;
4198 bdrkreg_t pcb_rsvd : 23;
4199 bdrkreg_t pcb_overflow : 1;
4200 bdrkreg_t pcb_count_value : 40;
4201 } pi_perf_cntr0_b_fld_s;
4202 } pi_perf_cntr0_b_u_t;
4209 /************************************************************************
4211 * This register accesses the performance counter 1for each CPU. *
4212 * Each performance counter is 40-bits wide. On overflow, It wraps to *
4213 * zero, sets the overflow bit in this register, and sets the *
4214 * PERF_CNTR_OFLOW bit in the INT_PEND1 register. *
4216 ************************************************************************/
4221 #ifdef LITTLE_ENDIAN
4223 typedef union pi_perf_cntr1_b_u {
4224 bdrkreg_t pi_perf_cntr1_b_regval;
4226 bdrkreg_t pcb_count_value : 40;
4227 bdrkreg_t pcb_overflow : 1;
4228 bdrkreg_t pcb_rsvd : 23;
4229 } pi_perf_cntr1_b_fld_s;
4230 } pi_perf_cntr1_b_u_t;
4234 typedef union pi_perf_cntr1_b_u {
4235 bdrkreg_t pi_perf_cntr1_b_regval;
4237 bdrkreg_t pcb_rsvd : 23;
4238 bdrkreg_t pcb_overflow : 1;
4239 bdrkreg_t pcb_count_value : 40;
4240 } pi_perf_cntr1_b_fld_s;
4241 } pi_perf_cntr1_b_u_t;
4250 #endif /* __ASSEMBLY__ */
4252 /************************************************************************
4254 * MAKE ALL ADDITIONS AFTER THIS LINE *
4256 ************************************************************************/
4259 #define PI_GFX_OFFSET (PI_GFX_PAGE_B - PI_GFX_PAGE_A)
4260 #define PI_GFX_PAGE_ENABLE 0x0000010000000000LL
4263 #endif /* _ASM_IA64_SN_SN1_HUBPI_H */
projects / linux-flexiantxendom0-3.2.10.git / blob