3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
9 #ifndef _ASM_IA64_SN_SN1_HUBNI_H
10 #define _ASM_IA64_SN_SN1_HUBNI_H
13 /************************************************************************
15 * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! *
17 * This file is created by an automated script. Any (minimal) changes *
18 * made manually to this file should be made with care. *
20 * MAKE ALL ADDITIONS TO THE END OF THIS FILE *
22 ************************************************************************/
24 #define NI_PORT_STATUS 0x00680000 /* LLP Status */
28 #define NI_PORT_RESET 0x00680008 /*
35 #define NI_RESET_ENABLE 0x00680010 /* Warm Reset Enable */
39 #define NI_DIAG_PARMS 0x00680018 /*
46 #define NI_CHANNEL_CONTROL 0x00680020 /*
53 #define NI_CHANNEL_TEST 0x00680028 /* LLP Test Control. */
57 #define NI_PORT_PARMS 0x00680030 /* LLP Parameters */
61 #define NI_CHANNEL_AGE 0x00680038 /*
68 #define NI_PORT_ERRORS 0x00680100 /* Errors */
72 #define NI_PORT_HEADER_A 0x00680108 /*
79 #define NI_PORT_HEADER_B 0x00680110 /*
86 #define NI_PORT_SIDEBAND 0x00680118 /* Error Sideband */
90 #define NI_PORT_ERROR_CLEAR 0x00680120 /*
97 #define NI_LOCAL_TABLE_0 0x00681000 /*
104 #define NI_LOCAL_TABLE_1 0x00681008 /*
106 * Mapping Table 0-127
111 #define NI_LOCAL_TABLE_2 0x00681010 /*
113 * Mapping Table 0-127
118 #define NI_LOCAL_TABLE_3 0x00681018 /*
120 * Mapping Table 0-127
125 #define NI_LOCAL_TABLE_4 0x00681020 /*
127 * Mapping Table 0-127
132 #define NI_LOCAL_TABLE_5 0x00681028 /*
134 * Mapping Table 0-127
139 #define NI_LOCAL_TABLE_6 0x00681030 /*
141 * Mapping Table 0-127
146 #define NI_LOCAL_TABLE_7 0x00681038 /*
148 * Mapping Table 0-127
153 #define NI_LOCAL_TABLE_8 0x00681040 /*
155 * Mapping Table 0-127
160 #define NI_LOCAL_TABLE_9 0x00681048 /*
162 * Mapping Table 0-127
167 #define NI_LOCAL_TABLE_10 0x00681050 /*
169 * Mapping Table 0-127
174 #define NI_LOCAL_TABLE_11 0x00681058 /*
176 * Mapping Table 0-127
181 #define NI_LOCAL_TABLE_12 0x00681060 /*
183 * Mapping Table 0-127
188 #define NI_LOCAL_TABLE_13 0x00681068 /*
190 * Mapping Table 0-127
195 #define NI_LOCAL_TABLE_14 0x00681070 /*
197 * Mapping Table 0-127
202 #define NI_LOCAL_TABLE_15 0x00681078 /*
204 * Mapping Table 0-127
209 #define NI_LOCAL_TABLE_16 0x00681080 /*
211 * Mapping Table 0-127
216 #define NI_LOCAL_TABLE_17 0x00681088 /*
218 * Mapping Table 0-127
223 #define NI_LOCAL_TABLE_18 0x00681090 /*
225 * Mapping Table 0-127
230 #define NI_LOCAL_TABLE_19 0x00681098 /*
232 * Mapping Table 0-127
237 #define NI_LOCAL_TABLE_20 0x006810A0 /*
239 * Mapping Table 0-127
244 #define NI_LOCAL_TABLE_21 0x006810A8 /*
246 * Mapping Table 0-127
251 #define NI_LOCAL_TABLE_22 0x006810B0 /*
253 * Mapping Table 0-127
258 #define NI_LOCAL_TABLE_23 0x006810B8 /*
260 * Mapping Table 0-127
265 #define NI_LOCAL_TABLE_24 0x006810C0 /*
267 * Mapping Table 0-127
272 #define NI_LOCAL_TABLE_25 0x006810C8 /*
274 * Mapping Table 0-127
279 #define NI_LOCAL_TABLE_26 0x006810D0 /*
281 * Mapping Table 0-127
286 #define NI_LOCAL_TABLE_27 0x006810D8 /*
288 * Mapping Table 0-127
293 #define NI_LOCAL_TABLE_28 0x006810E0 /*
295 * Mapping Table 0-127
300 #define NI_LOCAL_TABLE_29 0x006810E8 /*
302 * Mapping Table 0-127
307 #define NI_LOCAL_TABLE_30 0x006810F0 /*
309 * Mapping Table 0-127
314 #define NI_LOCAL_TABLE_31 0x006810F8 /*
316 * Mapping Table 0-127
321 #define NI_LOCAL_TABLE_32 0x00681100 /*
323 * Mapping Table 0-127
328 #define NI_LOCAL_TABLE_33 0x00681108 /*
330 * Mapping Table 0-127
335 #define NI_LOCAL_TABLE_34 0x00681110 /*
337 * Mapping Table 0-127
342 #define NI_LOCAL_TABLE_35 0x00681118 /*
344 * Mapping Table 0-127
349 #define NI_LOCAL_TABLE_36 0x00681120 /*
351 * Mapping Table 0-127
356 #define NI_LOCAL_TABLE_37 0x00681128 /*
358 * Mapping Table 0-127
363 #define NI_LOCAL_TABLE_38 0x00681130 /*
365 * Mapping Table 0-127
370 #define NI_LOCAL_TABLE_39 0x00681138 /*
372 * Mapping Table 0-127
377 #define NI_LOCAL_TABLE_40 0x00681140 /*
379 * Mapping Table 0-127
384 #define NI_LOCAL_TABLE_41 0x00681148 /*
386 * Mapping Table 0-127
391 #define NI_LOCAL_TABLE_42 0x00681150 /*
393 * Mapping Table 0-127
398 #define NI_LOCAL_TABLE_43 0x00681158 /*
400 * Mapping Table 0-127
405 #define NI_LOCAL_TABLE_44 0x00681160 /*
407 * Mapping Table 0-127
412 #define NI_LOCAL_TABLE_45 0x00681168 /*
414 * Mapping Table 0-127
419 #define NI_LOCAL_TABLE_46 0x00681170 /*
421 * Mapping Table 0-127
426 #define NI_LOCAL_TABLE_47 0x00681178 /*
428 * Mapping Table 0-127
433 #define NI_LOCAL_TABLE_48 0x00681180 /*
435 * Mapping Table 0-127
440 #define NI_LOCAL_TABLE_49 0x00681188 /*
442 * Mapping Table 0-127
447 #define NI_LOCAL_TABLE_50 0x00681190 /*
449 * Mapping Table 0-127
454 #define NI_LOCAL_TABLE_51 0x00681198 /*
456 * Mapping Table 0-127
461 #define NI_LOCAL_TABLE_52 0x006811A0 /*
463 * Mapping Table 0-127
468 #define NI_LOCAL_TABLE_53 0x006811A8 /*
470 * Mapping Table 0-127
475 #define NI_LOCAL_TABLE_54 0x006811B0 /*
477 * Mapping Table 0-127
482 #define NI_LOCAL_TABLE_55 0x006811B8 /*
484 * Mapping Table 0-127
489 #define NI_LOCAL_TABLE_56 0x006811C0 /*
491 * Mapping Table 0-127
496 #define NI_LOCAL_TABLE_57 0x006811C8 /*
498 * Mapping Table 0-127
503 #define NI_LOCAL_TABLE_58 0x006811D0 /*
505 * Mapping Table 0-127
510 #define NI_LOCAL_TABLE_59 0x006811D8 /*
512 * Mapping Table 0-127
517 #define NI_LOCAL_TABLE_60 0x006811E0 /*
519 * Mapping Table 0-127
524 #define NI_LOCAL_TABLE_61 0x006811E8 /*
526 * Mapping Table 0-127
531 #define NI_LOCAL_TABLE_62 0x006811F0 /*
533 * Mapping Table 0-127
538 #define NI_LOCAL_TABLE_63 0x006811F8 /*
540 * Mapping Table 0-127
545 #define NI_LOCAL_TABLE_64 0x00681200 /*
547 * Mapping Table 0-127
552 #define NI_LOCAL_TABLE_65 0x00681208 /*
554 * Mapping Table 0-127
559 #define NI_LOCAL_TABLE_66 0x00681210 /*
561 * Mapping Table 0-127
566 #define NI_LOCAL_TABLE_67 0x00681218 /*
568 * Mapping Table 0-127
573 #define NI_LOCAL_TABLE_68 0x00681220 /*
575 * Mapping Table 0-127
580 #define NI_LOCAL_TABLE_69 0x00681228 /*
582 * Mapping Table 0-127
587 #define NI_LOCAL_TABLE_70 0x00681230 /*
589 * Mapping Table 0-127
594 #define NI_LOCAL_TABLE_71 0x00681238 /*
596 * Mapping Table 0-127
601 #define NI_LOCAL_TABLE_72 0x00681240 /*
603 * Mapping Table 0-127
608 #define NI_LOCAL_TABLE_73 0x00681248 /*
610 * Mapping Table 0-127
615 #define NI_LOCAL_TABLE_74 0x00681250 /*
617 * Mapping Table 0-127
622 #define NI_LOCAL_TABLE_75 0x00681258 /*
624 * Mapping Table 0-127
629 #define NI_LOCAL_TABLE_76 0x00681260 /*
631 * Mapping Table 0-127
636 #define NI_LOCAL_TABLE_77 0x00681268 /*
638 * Mapping Table 0-127
643 #define NI_LOCAL_TABLE_78 0x00681270 /*
645 * Mapping Table 0-127
650 #define NI_LOCAL_TABLE_79 0x00681278 /*
652 * Mapping Table 0-127
657 #define NI_LOCAL_TABLE_80 0x00681280 /*
659 * Mapping Table 0-127
664 #define NI_LOCAL_TABLE_81 0x00681288 /*
666 * Mapping Table 0-127
671 #define NI_LOCAL_TABLE_82 0x00681290 /*
673 * Mapping Table 0-127
678 #define NI_LOCAL_TABLE_83 0x00681298 /*
680 * Mapping Table 0-127
685 #define NI_LOCAL_TABLE_84 0x006812A0 /*
687 * Mapping Table 0-127
692 #define NI_LOCAL_TABLE_85 0x006812A8 /*
694 * Mapping Table 0-127
699 #define NI_LOCAL_TABLE_86 0x006812B0 /*
701 * Mapping Table 0-127
706 #define NI_LOCAL_TABLE_87 0x006812B8 /*
708 * Mapping Table 0-127
713 #define NI_LOCAL_TABLE_88 0x006812C0 /*
715 * Mapping Table 0-127
720 #define NI_LOCAL_TABLE_89 0x006812C8 /*
722 * Mapping Table 0-127
727 #define NI_LOCAL_TABLE_90 0x006812D0 /*
729 * Mapping Table 0-127
734 #define NI_LOCAL_TABLE_91 0x006812D8 /*
736 * Mapping Table 0-127
741 #define NI_LOCAL_TABLE_92 0x006812E0 /*
743 * Mapping Table 0-127
748 #define NI_LOCAL_TABLE_93 0x006812E8 /*
750 * Mapping Table 0-127
755 #define NI_LOCAL_TABLE_94 0x006812F0 /*
757 * Mapping Table 0-127
762 #define NI_LOCAL_TABLE_95 0x006812F8 /*
764 * Mapping Table 0-127
769 #define NI_LOCAL_TABLE_96 0x00681300 /*
771 * Mapping Table 0-127
776 #define NI_LOCAL_TABLE_97 0x00681308 /*
778 * Mapping Table 0-127
783 #define NI_LOCAL_TABLE_98 0x00681310 /*
785 * Mapping Table 0-127
790 #define NI_LOCAL_TABLE_99 0x00681318 /*
792 * Mapping Table 0-127
797 #define NI_LOCAL_TABLE_100 0x00681320 /*
799 * Mapping Table 0-127
804 #define NI_LOCAL_TABLE_101 0x00681328 /*
806 * Mapping Table 0-127
811 #define NI_LOCAL_TABLE_102 0x00681330 /*
813 * Mapping Table 0-127
818 #define NI_LOCAL_TABLE_103 0x00681338 /*
820 * Mapping Table 0-127
825 #define NI_LOCAL_TABLE_104 0x00681340 /*
827 * Mapping Table 0-127
832 #define NI_LOCAL_TABLE_105 0x00681348 /*
834 * Mapping Table 0-127
839 #define NI_LOCAL_TABLE_106 0x00681350 /*
841 * Mapping Table 0-127
846 #define NI_LOCAL_TABLE_107 0x00681358 /*
848 * Mapping Table 0-127
853 #define NI_LOCAL_TABLE_108 0x00681360 /*
855 * Mapping Table 0-127
860 #define NI_LOCAL_TABLE_109 0x00681368 /*
862 * Mapping Table 0-127
867 #define NI_LOCAL_TABLE_110 0x00681370 /*
869 * Mapping Table 0-127
874 #define NI_LOCAL_TABLE_111 0x00681378 /*
876 * Mapping Table 0-127
881 #define NI_LOCAL_TABLE_112 0x00681380 /*
883 * Mapping Table 0-127
888 #define NI_LOCAL_TABLE_113 0x00681388 /*
890 * Mapping Table 0-127
895 #define NI_LOCAL_TABLE_114 0x00681390 /*
897 * Mapping Table 0-127
902 #define NI_LOCAL_TABLE_115 0x00681398 /*
904 * Mapping Table 0-127
909 #define NI_LOCAL_TABLE_116 0x006813A0 /*
911 * Mapping Table 0-127
916 #define NI_LOCAL_TABLE_117 0x006813A8 /*
918 * Mapping Table 0-127
923 #define NI_LOCAL_TABLE_118 0x006813B0 /*
925 * Mapping Table 0-127
930 #define NI_LOCAL_TABLE_119 0x006813B8 /*
932 * Mapping Table 0-127
937 #define NI_LOCAL_TABLE_120 0x006813C0 /*
939 * Mapping Table 0-127
944 #define NI_LOCAL_TABLE_121 0x006813C8 /*
946 * Mapping Table 0-127
951 #define NI_LOCAL_TABLE_122 0x006813D0 /*
953 * Mapping Table 0-127
958 #define NI_LOCAL_TABLE_123 0x006813D8 /*
960 * Mapping Table 0-127
965 #define NI_LOCAL_TABLE_124 0x006813E0 /*
967 * Mapping Table 0-127
972 #define NI_LOCAL_TABLE_125 0x006813E8 /*
974 * Mapping Table 0-127
979 #define NI_LOCAL_TABLE_126 0x006813F0 /*
981 * Mapping Table 0-127
986 #define NI_LOCAL_TABLE_127 0x006813F8 /*
988 * Mapping Table 0-127
993 #define NI_GLOBAL_TABLE 0x00682000 /*
1002 #ifndef __ASSEMBLY__
1004 /************************************************************************
1006 * This register describes the LLP status. *
1008 ************************************************************************/
1013 #ifdef LITTLE_ENDIAN
1015 typedef union ni_port_status_u {
1016 bdrkreg_t ni_port_status_regval;
1018 bdrkreg_t ps_port_status : 2;
1019 bdrkreg_t ps_remote_power : 1;
1020 bdrkreg_t ps_rsvd : 61;
1021 } ni_port_status_fld_s;
1022 } ni_port_status_u_t;
1026 typedef union ni_port_status_u {
1027 bdrkreg_t ni_port_status_regval;
1029 bdrkreg_t ps_rsvd : 61;
1030 bdrkreg_t ps_remote_power : 1;
1031 bdrkreg_t ps_port_status : 2;
1032 } ni_port_status_fld_s;
1033 } ni_port_status_u_t;
1040 /************************************************************************
1042 * Writing this register issues a reset to the network interface. *
1044 ************************************************************************/
1049 #ifdef LITTLE_ENDIAN
1051 typedef union ni_port_reset_u {
1052 bdrkreg_t ni_port_reset_regval;
1054 bdrkreg_t pr_link_reset_out : 1;
1055 bdrkreg_t pr_port_reset : 1;
1056 bdrkreg_t pr_local_reset : 1;
1057 bdrkreg_t pr_rsvd : 61;
1058 } ni_port_reset_fld_s;
1059 } ni_port_reset_u_t;
1063 typedef union ni_port_reset_u {
1064 bdrkreg_t ni_port_reset_regval;
1066 bdrkreg_t pr_rsvd : 61;
1067 bdrkreg_t pr_local_reset : 1;
1068 bdrkreg_t pr_port_reset : 1;
1069 bdrkreg_t pr_link_reset_out : 1;
1070 } ni_port_reset_fld_s;
1071 } ni_port_reset_u_t;
1077 /************************************************************************
1079 * This register contains the warm reset enable bit. *
1081 ************************************************************************/
1086 #ifdef LITTLE_ENDIAN
1088 typedef union ni_reset_enable_u {
1089 bdrkreg_t ni_reset_enable_regval;
1091 bdrkreg_t re_reset_ok : 1;
1092 bdrkreg_t re_rsvd : 63;
1093 } ni_reset_enable_fld_s;
1094 } ni_reset_enable_u_t;
1098 typedef union ni_reset_enable_u {
1099 bdrkreg_t ni_reset_enable_regval;
1101 bdrkreg_t re_rsvd : 63;
1102 bdrkreg_t re_reset_ok : 1;
1103 } ni_reset_enable_fld_s;
1104 } ni_reset_enable_u_t;
1111 /************************************************************************
1113 * This register contains parameters for diagnostics. *
1115 ************************************************************************/
1120 #ifdef LITTLE_ENDIAN
1122 typedef union ni_diag_parms_u {
1123 bdrkreg_t ni_diag_parms_regval;
1125 bdrkreg_t dp_send_data_error : 1;
1126 bdrkreg_t dp_port_disable : 1;
1127 bdrkreg_t dp_send_err_off : 1;
1128 bdrkreg_t dp_rsvd : 61;
1129 } ni_diag_parms_fld_s;
1130 } ni_diag_parms_u_t;
1134 typedef union ni_diag_parms_u {
1135 bdrkreg_t ni_diag_parms_regval;
1137 bdrkreg_t dp_rsvd : 61;
1138 bdrkreg_t dp_send_err_off : 1;
1139 bdrkreg_t dp_port_disable : 1;
1140 bdrkreg_t dp_send_data_error : 1;
1141 } ni_diag_parms_fld_s;
1142 } ni_diag_parms_u_t;
1149 /************************************************************************
1151 * This register contains the virtual channel selection control for *
1152 * outgoing messages from the Bedrock. *
1154 ************************************************************************/
1159 #ifdef LITTLE_ENDIAN
1161 typedef union ni_channel_control_u {
1162 bdrkreg_t ni_channel_control_regval;
1164 bdrkreg_t cc_vch_one_request : 1;
1165 bdrkreg_t cc_vch_two_request : 1;
1166 bdrkreg_t cc_vch_nine_request : 1;
1167 bdrkreg_t cc_vch_vector_request : 1;
1168 bdrkreg_t cc_vch_one_reply : 1;
1169 bdrkreg_t cc_vch_two_reply : 1;
1170 bdrkreg_t cc_vch_nine_reply : 1;
1171 bdrkreg_t cc_vch_vector_reply : 1;
1172 bdrkreg_t cc_send_vch_sel : 1;
1173 bdrkreg_t cc_rsvd : 55;
1174 } ni_channel_control_fld_s;
1175 } ni_channel_control_u_t;
1179 typedef union ni_channel_control_u {
1180 bdrkreg_t ni_channel_control_regval;
1182 bdrkreg_t cc_rsvd : 55;
1183 bdrkreg_t cc_send_vch_sel : 1;
1184 bdrkreg_t cc_vch_vector_reply : 1;
1185 bdrkreg_t cc_vch_nine_reply : 1;
1186 bdrkreg_t cc_vch_two_reply : 1;
1187 bdrkreg_t cc_vch_one_reply : 1;
1188 bdrkreg_t cc_vch_vector_request : 1;
1189 bdrkreg_t cc_vch_nine_request : 1;
1190 bdrkreg_t cc_vch_two_request : 1;
1191 bdrkreg_t cc_vch_one_request : 1;
1192 } ni_channel_control_fld_s;
1193 } ni_channel_control_u_t;
1200 /************************************************************************
1202 * This register allows access to the LLP test logic. *
1204 ************************************************************************/
1209 #ifdef LITTLE_ENDIAN
1211 typedef union ni_channel_test_u {
1212 bdrkreg_t ni_channel_test_regval;
1214 bdrkreg_t ct_testseed : 20;
1215 bdrkreg_t ct_testmask : 8;
1216 bdrkreg_t ct_testdata : 20;
1217 bdrkreg_t ct_testvalid : 1;
1218 bdrkreg_t ct_testcberr : 1;
1219 bdrkreg_t ct_testflit : 3;
1220 bdrkreg_t ct_testclear : 1;
1221 bdrkreg_t ct_testerrcapture : 1;
1222 bdrkreg_t ct_rsvd : 9;
1223 } ni_channel_test_fld_s;
1224 } ni_channel_test_u_t;
1228 typedef union ni_channel_test_u {
1229 bdrkreg_t ni_channel_test_regval;
1231 bdrkreg_t ct_rsvd : 9;
1232 bdrkreg_t ct_testerrcapture : 1;
1233 bdrkreg_t ct_testclear : 1;
1234 bdrkreg_t ct_testflit : 3;
1235 bdrkreg_t ct_testcberr : 1;
1236 bdrkreg_t ct_testvalid : 1;
1237 bdrkreg_t ct_testdata : 20;
1238 bdrkreg_t ct_testmask : 8;
1239 bdrkreg_t ct_testseed : 20;
1240 } ni_channel_test_fld_s;
1241 } ni_channel_test_u_t;
1248 /************************************************************************
1250 * This register contains LLP port parameters and enables for the *
1251 * capture of header data. *
1253 ************************************************************************/
1258 #ifdef LITTLE_ENDIAN
1260 typedef union ni_port_parms_u {
1261 bdrkreg_t ni_port_parms_regval;
1263 bdrkreg_t pp_max_burst : 10;
1264 bdrkreg_t pp_null_timeout : 6;
1265 bdrkreg_t pp_max_retry : 10;
1266 bdrkreg_t pp_d_avail_sel : 2;
1267 bdrkreg_t pp_rsvd_1 : 1;
1268 bdrkreg_t pp_first_err_enable : 1;
1269 bdrkreg_t pp_squash_err_enable : 1;
1270 bdrkreg_t pp_vch_err_enable : 4;
1271 bdrkreg_t pp_rsvd : 29;
1272 } ni_port_parms_fld_s;
1273 } ni_port_parms_u_t;
1277 typedef union ni_port_parms_u {
1278 bdrkreg_t ni_port_parms_regval;
1280 bdrkreg_t pp_rsvd : 29;
1281 bdrkreg_t pp_vch_err_enable : 4;
1282 bdrkreg_t pp_squash_err_enable : 1;
1283 bdrkreg_t pp_first_err_enable : 1;
1284 bdrkreg_t pp_rsvd_1 : 1;
1285 bdrkreg_t pp_d_avail_sel : 2;
1286 bdrkreg_t pp_max_retry : 10;
1287 bdrkreg_t pp_null_timeout : 6;
1288 bdrkreg_t pp_max_burst : 10;
1289 } ni_port_parms_fld_s;
1290 } ni_port_parms_u_t;
1297 /************************************************************************
1299 * This register contains the age at which request and reply packets *
1300 * are injected into the network. This feature allows replies to be *
1301 * given a higher fixed priority than requests, which can be *
1302 * important in some network saturation situations. *
1304 ************************************************************************/
1309 #ifdef LITTLE_ENDIAN
1311 typedef union ni_channel_age_u {
1312 bdrkreg_t ni_channel_age_regval;
1314 bdrkreg_t ca_request_inject_age : 8;
1315 bdrkreg_t ca_reply_inject_age : 8;
1316 bdrkreg_t ca_rsvd : 48;
1317 } ni_channel_age_fld_s;
1318 } ni_channel_age_u_t;
1322 typedef union ni_channel_age_u {
1323 bdrkreg_t ni_channel_age_regval;
1325 bdrkreg_t ca_rsvd : 48;
1326 bdrkreg_t ca_reply_inject_age : 8;
1327 bdrkreg_t ca_request_inject_age : 8;
1328 } ni_channel_age_fld_s;
1329 } ni_channel_age_u_t;
1336 /************************************************************************
1338 * This register contains latched LLP port and problematic message *
1339 * errors. The contents are the same information as the *
1340 * NI_PORT_ERROR_CLEAR register, but, in this register read accesses *
1341 * are non-destructive. Bits [52:24] assert the NI interrupt. *
1343 ************************************************************************/
1348 #ifdef LITTLE_ENDIAN
1350 typedef union ni_port_errors_u {
1351 bdrkreg_t ni_port_errors_regval;
1353 bdrkreg_t pe_sn_error_count : 8;
1354 bdrkreg_t pe_cb_error_count : 8;
1355 bdrkreg_t pe_retry_count : 8;
1356 bdrkreg_t pe_tail_timeout : 4;
1357 bdrkreg_t pe_fifo_overflow : 4;
1358 bdrkreg_t pe_external_short : 4;
1359 bdrkreg_t pe_external_long : 4;
1360 bdrkreg_t pe_external_bad_header : 4;
1361 bdrkreg_t pe_internal_short : 4;
1362 bdrkreg_t pe_internal_long : 4;
1363 bdrkreg_t pe_link_reset_in : 1;
1364 bdrkreg_t pe_rsvd : 11;
1365 } ni_port_errors_fld_s;
1366 } ni_port_errors_u_t;
1370 typedef union ni_port_errors_u {
1371 bdrkreg_t ni_port_errors_regval;
1373 bdrkreg_t pe_rsvd : 11;
1374 bdrkreg_t pe_link_reset_in : 1;
1375 bdrkreg_t pe_internal_long : 4;
1376 bdrkreg_t pe_internal_short : 4;
1377 bdrkreg_t pe_external_bad_header : 4;
1378 bdrkreg_t pe_external_long : 4;
1379 bdrkreg_t pe_external_short : 4;
1380 bdrkreg_t pe_fifo_overflow : 4;
1381 bdrkreg_t pe_tail_timeout : 4;
1382 bdrkreg_t pe_retry_count : 8;
1383 bdrkreg_t pe_cb_error_count : 8;
1384 bdrkreg_t pe_sn_error_count : 8;
1385 } ni_port_errors_fld_s;
1386 } ni_port_errors_u_t;
1393 /************************************************************************
1395 * This register provides the sideband data associated with the *
1396 * NI_PORT_HEADER registers and also additional data for error *
1397 * processing. This register is not cleared on reset. *
1399 ************************************************************************/
1404 #ifdef LITTLE_ENDIAN
1406 typedef union ni_port_sideband_u {
1407 bdrkreg_t ni_port_sideband_regval;
1409 bdrkreg_t ps_sideband : 8;
1410 bdrkreg_t ps_bad_dest : 1;
1411 bdrkreg_t ps_bad_prexsel : 1;
1412 bdrkreg_t ps_rcv_error : 1;
1413 bdrkreg_t ps_bad_message : 1;
1414 bdrkreg_t ps_squash : 1;
1415 bdrkreg_t ps_sn_status : 1;
1416 bdrkreg_t ps_cb_status : 1;
1417 bdrkreg_t ps_send_error : 1;
1418 bdrkreg_t ps_vch_active : 4;
1419 bdrkreg_t ps_rsvd : 44;
1420 } ni_port_sideband_fld_s;
1421 } ni_port_sideband_u_t;
1425 typedef union ni_port_sideband_u {
1426 bdrkreg_t ni_port_sideband_regval;
1428 bdrkreg_t ps_rsvd : 44;
1429 bdrkreg_t ps_vch_active : 4;
1430 bdrkreg_t ps_send_error : 1;
1431 bdrkreg_t ps_cb_status : 1;
1432 bdrkreg_t ps_sn_status : 1;
1433 bdrkreg_t ps_squash : 1;
1434 bdrkreg_t ps_bad_message : 1;
1435 bdrkreg_t ps_rcv_error : 1;
1436 bdrkreg_t ps_bad_prexsel : 1;
1437 bdrkreg_t ps_bad_dest : 1;
1438 bdrkreg_t ps_sideband : 8;
1439 } ni_port_sideband_fld_s;
1440 } ni_port_sideband_u_t;
1447 /************************************************************************
1449 * This register contains latched LLP port and problematic message *
1450 * errors. The contents are the same information as the *
1451 * NI_PORT_ERROR_CLEAR register, but, in this register read accesses *
1452 * are non-destructive. Bits [52:24] assert the NI interrupt. *
1454 ************************************************************************/
1459 #ifdef LITTLE_ENDIAN
1461 typedef union ni_port_error_clear_u {
1462 bdrkreg_t ni_port_error_clear_regval;
1464 bdrkreg_t pec_sn_error_count : 8;
1465 bdrkreg_t pec_cb_error_count : 8;
1466 bdrkreg_t pec_retry_count : 8;
1467 bdrkreg_t pec_tail_timeout : 4;
1468 bdrkreg_t pec_fifo_overflow : 4;
1469 bdrkreg_t pec_external_short : 4;
1470 bdrkreg_t pec_external_long : 4;
1471 bdrkreg_t pec_external_bad_header : 4;
1472 bdrkreg_t pec_internal_short : 4;
1473 bdrkreg_t pec_internal_long : 4;
1474 bdrkreg_t pec_link_reset_in : 1;
1475 bdrkreg_t pec_rsvd : 11;
1476 } ni_port_error_clear_fld_s;
1477 } ni_port_error_clear_u_t;
1481 typedef union ni_port_error_clear_u {
1482 bdrkreg_t ni_port_error_clear_regval;
1484 bdrkreg_t pec_rsvd : 11;
1485 bdrkreg_t pec_link_reset_in : 1;
1486 bdrkreg_t pec_internal_long : 4;
1487 bdrkreg_t pec_internal_short : 4;
1488 bdrkreg_t pec_external_bad_header : 4;
1489 bdrkreg_t pec_external_long : 4;
1490 bdrkreg_t pec_external_short : 4;
1491 bdrkreg_t pec_fifo_overflow : 4;
1492 bdrkreg_t pec_tail_timeout : 4;
1493 bdrkreg_t pec_retry_count : 8;
1494 bdrkreg_t pec_cb_error_count : 8;
1495 bdrkreg_t pec_sn_error_count : 8;
1496 } ni_port_error_clear_fld_s;
1497 } ni_port_error_clear_u_t;
1504 /************************************************************************
1506 * Lookup table for the next hop's exit port. The table entry *
1507 * selection is based on the 7-bit LocalCube routing destination. *
1509 ************************************************************************/
1514 #ifdef LITTLE_ENDIAN
1516 typedef union ni_local_table_0_u {
1517 bdrkreg_t ni_local_table_0_regval;
1519 bdrkreg_t lt0_next_exit_port : 4;
1520 bdrkreg_t lt0_next_vch_lsb : 1;
1521 bdrkreg_t lt0_rsvd : 59;
1522 } ni_local_table_0_fld_s;
1523 } ni_local_table_0_u_t;
1527 typedef union ni_local_table_0_u {
1528 bdrkreg_t ni_local_table_0_regval;
1530 bdrkreg_t lt0_rsvd : 59;
1531 bdrkreg_t lt0_next_vch_lsb : 1;
1532 bdrkreg_t lt0_next_exit_port : 4;
1533 } ni_local_table_0_fld_s;
1534 } ni_local_table_0_u_t;
1541 /************************************************************************
1543 * Lookup table for the next hop's exit port. The table entry *
1544 * selection is based on the 7-bit LocalCube routing destination. *
1546 ************************************************************************/
1551 #ifdef LITTLE_ENDIAN
1553 typedef union ni_local_table_127_u {
1554 bdrkreg_t ni_local_table_127_regval;
1556 bdrkreg_t lt1_next_exit_port : 4;
1557 bdrkreg_t lt1_next_vch_lsb : 1;
1558 bdrkreg_t lt1_rsvd : 59;
1559 } ni_local_table_127_fld_s;
1560 } ni_local_table_127_u_t;
1564 typedef union ni_local_table_127_u {
1565 bdrkreg_t ni_local_table_127_regval;
1567 bdrkreg_t lt1_rsvd : 59;
1568 bdrkreg_t lt1_next_vch_lsb : 1;
1569 bdrkreg_t lt1_next_exit_port : 4;
1570 } ni_local_table_127_fld_s;
1571 } ni_local_table_127_u_t;
1578 /************************************************************************
1580 * Lookup table for the next hop's exit port. The table entry *
1581 * selection is based on the 1-bit MetaCube routing destination. *
1583 ************************************************************************/
1588 #ifdef LITTLE_ENDIAN
1590 typedef union ni_global_table_u {
1591 bdrkreg_t ni_global_table_regval;
1593 bdrkreg_t gt_next_exit_port : 4;
1594 bdrkreg_t gt_next_vch_lsb : 1;
1595 bdrkreg_t gt_rsvd : 59;
1596 } ni_global_table_fld_s;
1597 } ni_global_table_u_t;
1601 typedef union ni_global_table_u {
1602 bdrkreg_t ni_global_table_regval;
1604 bdrkreg_t gt_rsvd : 59;
1605 bdrkreg_t gt_next_vch_lsb : 1;
1606 bdrkreg_t gt_next_exit_port : 4;
1607 } ni_global_table_fld_s;
1608 } ni_global_table_u_t;
1617 #endif /* __ASSEMBLY__ */
1619 /************************************************************************
1621 * The following defines which were not formed into structures are *
1622 * probably indentical to another register, and the name of the *
1623 * register is provided against each of these registers. This *
1624 * information needs to be checked carefully *
1626 * NI_LOCAL_TABLE_1 NI_LOCAL_TABLE_0 *
1627 * NI_LOCAL_TABLE_2 NI_LOCAL_TABLE_0 *
1628 * NI_LOCAL_TABLE_3 NI_LOCAL_TABLE_0 *
1629 * NI_LOCAL_TABLE_4 NI_LOCAL_TABLE_0 *
1630 * NI_LOCAL_TABLE_5 NI_LOCAL_TABLE_0 *
1631 * NI_LOCAL_TABLE_6 NI_LOCAL_TABLE_0 *
1632 * NI_LOCAL_TABLE_7 NI_LOCAL_TABLE_0 *
1633 * NI_LOCAL_TABLE_8 NI_LOCAL_TABLE_0 *
1634 * NI_LOCAL_TABLE_9 NI_LOCAL_TABLE_0 *
1635 * NI_LOCAL_TABLE_10 NI_LOCAL_TABLE_0 *
1636 * NI_LOCAL_TABLE_11 NI_LOCAL_TABLE_0 *
1637 * NI_LOCAL_TABLE_12 NI_LOCAL_TABLE_0 *
1638 * NI_LOCAL_TABLE_13 NI_LOCAL_TABLE_0 *
1639 * NI_LOCAL_TABLE_14 NI_LOCAL_TABLE_0 *
1640 * NI_LOCAL_TABLE_15 NI_LOCAL_TABLE_0 *
1641 * NI_LOCAL_TABLE_16 NI_LOCAL_TABLE_0 *
1642 * NI_LOCAL_TABLE_17 NI_LOCAL_TABLE_0 *
1643 * NI_LOCAL_TABLE_18 NI_LOCAL_TABLE_0 *
1644 * NI_LOCAL_TABLE_19 NI_LOCAL_TABLE_0 *
1645 * NI_LOCAL_TABLE_20 NI_LOCAL_TABLE_0 *
1646 * NI_LOCAL_TABLE_21 NI_LOCAL_TABLE_0 *
1647 * NI_LOCAL_TABLE_22 NI_LOCAL_TABLE_0 *
1648 * NI_LOCAL_TABLE_23 NI_LOCAL_TABLE_0 *
1649 * NI_LOCAL_TABLE_24 NI_LOCAL_TABLE_0 *
1650 * NI_LOCAL_TABLE_25 NI_LOCAL_TABLE_0 *
1651 * NI_LOCAL_TABLE_26 NI_LOCAL_TABLE_0 *
1652 * NI_LOCAL_TABLE_27 NI_LOCAL_TABLE_0 *
1653 * NI_LOCAL_TABLE_28 NI_LOCAL_TABLE_0 *
1654 * NI_LOCAL_TABLE_29 NI_LOCAL_TABLE_0 *
1655 * NI_LOCAL_TABLE_30 NI_LOCAL_TABLE_0 *
1656 * NI_LOCAL_TABLE_31 NI_LOCAL_TABLE_0 *
1657 * NI_LOCAL_TABLE_32 NI_LOCAL_TABLE_0 *
1658 * NI_LOCAL_TABLE_33 NI_LOCAL_TABLE_0 *
1659 * NI_LOCAL_TABLE_34 NI_LOCAL_TABLE_0 *
1660 * NI_LOCAL_TABLE_35 NI_LOCAL_TABLE_0 *
1661 * NI_LOCAL_TABLE_36 NI_LOCAL_TABLE_0 *
1662 * NI_LOCAL_TABLE_37 NI_LOCAL_TABLE_0 *
1663 * NI_LOCAL_TABLE_38 NI_LOCAL_TABLE_0 *
1664 * NI_LOCAL_TABLE_39 NI_LOCAL_TABLE_0 *
1665 * NI_LOCAL_TABLE_40 NI_LOCAL_TABLE_0 *
1666 * NI_LOCAL_TABLE_41 NI_LOCAL_TABLE_0 *
1667 * NI_LOCAL_TABLE_42 NI_LOCAL_TABLE_0 *
1668 * NI_LOCAL_TABLE_43 NI_LOCAL_TABLE_0 *
1669 * NI_LOCAL_TABLE_44 NI_LOCAL_TABLE_0 *
1670 * NI_LOCAL_TABLE_45 NI_LOCAL_TABLE_0 *
1671 * NI_LOCAL_TABLE_46 NI_LOCAL_TABLE_0 *
1672 * NI_LOCAL_TABLE_47 NI_LOCAL_TABLE_0 *
1673 * NI_LOCAL_TABLE_48 NI_LOCAL_TABLE_0 *
1674 * NI_LOCAL_TABLE_49 NI_LOCAL_TABLE_0 *
1675 * NI_LOCAL_TABLE_50 NI_LOCAL_TABLE_0 *
1676 * NI_LOCAL_TABLE_51 NI_LOCAL_TABLE_0 *
1677 * NI_LOCAL_TABLE_52 NI_LOCAL_TABLE_0 *
1678 * NI_LOCAL_TABLE_53 NI_LOCAL_TABLE_0 *
1679 * NI_LOCAL_TABLE_54 NI_LOCAL_TABLE_0 *
1680 * NI_LOCAL_TABLE_55 NI_LOCAL_TABLE_0 *
1681 * NI_LOCAL_TABLE_56 NI_LOCAL_TABLE_0 *
1682 * NI_LOCAL_TABLE_57 NI_LOCAL_TABLE_0 *
1683 * NI_LOCAL_TABLE_58 NI_LOCAL_TABLE_0 *
1684 * NI_LOCAL_TABLE_59 NI_LOCAL_TABLE_0 *
1685 * NI_LOCAL_TABLE_60 NI_LOCAL_TABLE_0 *
1686 * NI_LOCAL_TABLE_61 NI_LOCAL_TABLE_0 *
1687 * NI_LOCAL_TABLE_62 NI_LOCAL_TABLE_0 *
1688 * NI_LOCAL_TABLE_63 NI_LOCAL_TABLE_0 *
1689 * NI_LOCAL_TABLE_64 NI_LOCAL_TABLE_0 *
1690 * NI_LOCAL_TABLE_65 NI_LOCAL_TABLE_0 *
1691 * NI_LOCAL_TABLE_66 NI_LOCAL_TABLE_0 *
1692 * NI_LOCAL_TABLE_67 NI_LOCAL_TABLE_0 *
1693 * NI_LOCAL_TABLE_68 NI_LOCAL_TABLE_0 *
1694 * NI_LOCAL_TABLE_69 NI_LOCAL_TABLE_0 *
1695 * NI_LOCAL_TABLE_70 NI_LOCAL_TABLE_0 *
1696 * NI_LOCAL_TABLE_71 NI_LOCAL_TABLE_0 *
1697 * NI_LOCAL_TABLE_72 NI_LOCAL_TABLE_0 *
1698 * NI_LOCAL_TABLE_73 NI_LOCAL_TABLE_0 *
1699 * NI_LOCAL_TABLE_74 NI_LOCAL_TABLE_0 *
1700 * NI_LOCAL_TABLE_75 NI_LOCAL_TABLE_0 *
1701 * NI_LOCAL_TABLE_76 NI_LOCAL_TABLE_0 *
1702 * NI_LOCAL_TABLE_77 NI_LOCAL_TABLE_0 *
1703 * NI_LOCAL_TABLE_78 NI_LOCAL_TABLE_0 *
1704 * NI_LOCAL_TABLE_79 NI_LOCAL_TABLE_0 *
1705 * NI_LOCAL_TABLE_80 NI_LOCAL_TABLE_0 *
1706 * NI_LOCAL_TABLE_81 NI_LOCAL_TABLE_0 *
1707 * NI_LOCAL_TABLE_82 NI_LOCAL_TABLE_0 *
1708 * NI_LOCAL_TABLE_83 NI_LOCAL_TABLE_0 *
1709 * NI_LOCAL_TABLE_84 NI_LOCAL_TABLE_0 *
1710 * NI_LOCAL_TABLE_85 NI_LOCAL_TABLE_0 *
1711 * NI_LOCAL_TABLE_86 NI_LOCAL_TABLE_0 *
1712 * NI_LOCAL_TABLE_87 NI_LOCAL_TABLE_0 *
1713 * NI_LOCAL_TABLE_88 NI_LOCAL_TABLE_0 *
1714 * NI_LOCAL_TABLE_89 NI_LOCAL_TABLE_0 *
1715 * NI_LOCAL_TABLE_90 NI_LOCAL_TABLE_0 *
1716 * NI_LOCAL_TABLE_91 NI_LOCAL_TABLE_0 *
1717 * NI_LOCAL_TABLE_92 NI_LOCAL_TABLE_0 *
1718 * NI_LOCAL_TABLE_93 NI_LOCAL_TABLE_0 *
1719 * NI_LOCAL_TABLE_94 NI_LOCAL_TABLE_0 *
1720 * NI_LOCAL_TABLE_95 NI_LOCAL_TABLE_0 *
1721 * NI_LOCAL_TABLE_96 NI_LOCAL_TABLE_0 *
1722 * NI_LOCAL_TABLE_97 NI_LOCAL_TABLE_0 *
1723 * NI_LOCAL_TABLE_98 NI_LOCAL_TABLE_0 *
1724 * NI_LOCAL_TABLE_99 NI_LOCAL_TABLE_0 *
1725 * NI_LOCAL_TABLE_100 NI_LOCAL_TABLE_0 *
1726 * NI_LOCAL_TABLE_101 NI_LOCAL_TABLE_0 *
1727 * NI_LOCAL_TABLE_102 NI_LOCAL_TABLE_0 *
1728 * NI_LOCAL_TABLE_103 NI_LOCAL_TABLE_0 *
1729 * NI_LOCAL_TABLE_104 NI_LOCAL_TABLE_0 *
1730 * NI_LOCAL_TABLE_105 NI_LOCAL_TABLE_0 *
1731 * NI_LOCAL_TABLE_106 NI_LOCAL_TABLE_0 *
1732 * NI_LOCAL_TABLE_107 NI_LOCAL_TABLE_0 *
1733 * NI_LOCAL_TABLE_108 NI_LOCAL_TABLE_0 *
1734 * NI_LOCAL_TABLE_109 NI_LOCAL_TABLE_0 *
1735 * NI_LOCAL_TABLE_110 NI_LOCAL_TABLE_0 *
1736 * NI_LOCAL_TABLE_111 NI_LOCAL_TABLE_0 *
1737 * NI_LOCAL_TABLE_112 NI_LOCAL_TABLE_0 *
1738 * NI_LOCAL_TABLE_113 NI_LOCAL_TABLE_0 *
1739 * NI_LOCAL_TABLE_114 NI_LOCAL_TABLE_0 *
1740 * NI_LOCAL_TABLE_115 NI_LOCAL_TABLE_0 *
1741 * NI_LOCAL_TABLE_116 NI_LOCAL_TABLE_0 *
1742 * NI_LOCAL_TABLE_117 NI_LOCAL_TABLE_0 *
1743 * NI_LOCAL_TABLE_118 NI_LOCAL_TABLE_0 *
1744 * NI_LOCAL_TABLE_119 NI_LOCAL_TABLE_0 *
1745 * NI_LOCAL_TABLE_120 NI_LOCAL_TABLE_0 *
1746 * NI_LOCAL_TABLE_121 NI_LOCAL_TABLE_0 *
1747 * NI_LOCAL_TABLE_122 NI_LOCAL_TABLE_0 *
1748 * NI_LOCAL_TABLE_123 NI_LOCAL_TABLE_0 *
1749 * NI_LOCAL_TABLE_124 NI_LOCAL_TABLE_0 *
1750 * NI_LOCAL_TABLE_125 NI_LOCAL_TABLE_0 *
1751 * NI_LOCAL_TABLE_126 NI_LOCAL_TABLE_0 *
1753 ************************************************************************/
1756 /************************************************************************
1758 * The following defines were not formed into structures *
1760 * This could be because the document did not contain details of the *
1761 * register, or because the automated script did not recognize the *
1762 * register details in the documentation. If these register need *
1763 * structure definition, please create them manually *
1765 * NI_PORT_HEADER_A 0x680108 *
1766 * NI_PORT_HEADER_B 0x680110 *
1768 ************************************************************************/
1771 /************************************************************************
1773 * MAKE ALL ADDITIONS AFTER THIS LINE *
1775 ************************************************************************/
1781 #endif /* _ASM_IA64_SN_SN1_HUBNI_H */
projects / linux-flexiantxendom0-3.2.10.git / blob