3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
9 #ifndef _ASM_IA64_SN_SN1_HUBMD_H
10 #define _ASM_IA64_SN_SN1_HUBMD_H
13 /************************************************************************
15 * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! *
17 * This file is created by an automated script. Any (minimal) changes *
18 * made manually to this file should be made with care. *
20 * MAKE ALL ADDITIONS TO THE END OF THIS FILE *
22 ************************************************************************/
25 #define MD_CURRENT_CELL 0x00780000 /*
35 #define MD_MEMORY_CONFIG 0x00780008 /*
42 #define MD_ARBITRATION_CONTROL 0x00780010 /*
49 #define MD_MIG_CONFIG 0x00780018 /*
56 #define MD_FANDOP_CAC_STAT0 0x00780020 /*
63 #define MD_FANDOP_CAC_STAT1 0x00780028 /*
70 #define MD_MISC0_ERROR 0x00780040 /*
77 #define MD_MISC1_ERROR 0x00780048 /*
84 #define MD_MISC1_ERROR_CLR 0x00780058 /*
91 #define MD_OUTGOING_RP_QUEUE_SIZE 0x00780060 /*
98 #define MD_PERF_SEL0 0x00790000 /*
106 #define MD_PERF_SEL1 0x00790008 /*
114 #define MD_PERF_CNT0 0x00790010 /*
115 * Performance counter
121 #define MD_PERF_CNT1 0x00790018 /*
122 * Performance counter
128 #define MD_REFRESH_CONTROL 0x007A0000 /*
135 #define MD_JUNK_BUS_TIMING 0x007A0008 /* Junk Bus Timing */
139 #define MD_LED0 0x007A0010 /* Reads of 8-bit LED0 */
143 #define MD_LED1 0x007A0018 /* Reads of 8-bit LED1 */
147 #define MD_LED2 0x007A0020 /* Reads of 8-bit LED2 */
151 #define MD_LED3 0x007A0028 /* Reads of 8-bit LED3 */
155 #define MD_BIST_CTL 0x007A0030 /*
162 #define MD_BIST_DATA 0x007A0038 /*
170 #define MD_BIST_AB_ERR_ADDR 0x007A0040 /* BIST error address */
174 #define MD_BIST_STATUS 0x007A0048 /* BIST status */
178 #define MD_IB_DEBUG 0x007A0060 /* IB debug select */
182 #define MD_DIR_CONFIG 0x007C0000 /*
189 #define MD_DIR_ERROR 0x007C0010 /*
196 #define MD_DIR_ERROR_CLR 0x007C0018 /*
203 #define MD_PROTOCOL_ERROR 0x007C0020 /*
210 #define MD_PROTOCOL_ERR_CLR 0x007C0028 /*
217 #define MD_MIG_CANDIDATE 0x007C0030 /*
224 #define MD_MIG_CANDIDATE_CLR 0x007C0038 /*
231 #define MD_MIG_DIFF_THRESH 0x007C0040 /*
239 #define MD_MIG_VALUE_THRESH 0x007C0048 /*
247 #define MD_OUTGOING_RQ_QUEUE_SIZE 0x007C0050 /*
248 * MD outgoing request
254 #define MD_BIST_DB_ERR_DATA 0x007C0058 /*
261 #define MD_DB_DEBUG 0x007C0060 /* DB debug select */
265 #define MD_MB_ECC_CONFIG 0x007E0000 /*
272 #define MD_MEM_ERROR 0x007E0010 /* Memory DIMM error */
276 #define MD_MEM_ERROR_CLR 0x007E0018 /*
283 #define MD_BIST_MB_ERR_DATA_0 0x007E0020 /*
290 #define MD_BIST_MB_ERR_DATA_1 0x007E0028 /*
297 #define MD_BIST_MB_ERR_DATA_2 0x007E0030 /*
304 #define MD_BIST_MB_ERR_DATA_3 0x007E0038 /*
311 #define MD_MB_DEBUG 0x007E0040 /* MB debug select */
319 /************************************************************************
321 * Description: This register shows which regions are in the current *
322 * cell. If a region has its bit set in this register, then it uses *
323 * the Local Access protection in the directory instead of the *
324 * separate per-region protection (which would cause a small *
325 * performance penalty). In addition, writeback and write reply *
326 * commands from outside the current cell will always check the *
327 * directory protection before writing data to memory. Writeback and *
328 * write reply commands from inside the current cell will write *
329 * memory regardless of the protection value. *
330 * This register is also used as the access-rights bit-vector for *
331 * most of the ASIC-special (HSpec) portion of the address space. It *
332 * covers the BDDIR, LREG, LBOOT, RREG, and RBOOT spaces. It does not *
333 * cover the UALIAS and BDECC spaces, as they are covered by the *
334 * protection in the directory. If a bit in the bit-vector is set, *
335 * the region corresponding to that bit has read/write permission on *
336 * these spaces. If the bit is clear, then that region has read-only *
337 * access to these spaces (except for LREG/RREG which have no access *
338 * when the bit is clear). *
339 * The granularity of a region is set by the REGION_SIZE register in *
340 * the NI local register space. *
341 * NOTE: This means that no processor outside the current cell can *
342 * write into the BDDIR, LREG, LBOOT, RREG, or RBOOT spaces. *
344 ************************************************************************/
349 typedef union md_current_cell_u {
350 bdrkreg_t md_current_cell_regval;
352 bdrkreg_t cc_hspec_prot : 64;
353 } md_current_cell_fld_s;
354 } md_current_cell_u_t;
359 /************************************************************************
361 * Description: This register contains three sets of information. *
362 * The first set describes the size and configuration of DIMMs that *
363 * are plugged into a system, the second set controls which set of *
364 * protection checks are performed on each access and the third set *
365 * controls various DDR SDRAM timing parameters. *
366 * In order to config a DIMM bank, three fields must be initialized: *
367 * BANK_SIZE, DRAM_WIDTH, and BANK_ENABLE. The BANK_SIZE field sets *
368 * the address range that the MD unit will accept for that DIMM bank. *
369 * All addresses larger than the specified size will return errors on *
370 * access. In order to read from a DIMM bank, Bedrock must know *
371 * whether or not the bank contains x4 or x8/x16 DRAM. The operating *
372 * system must query the System Controller for this information and *
373 * then set the DRAM_WIDTH field accordingly. The BANK_ENABLE field *
374 * can be used to individually enable the two physical banks located *
375 * on each DIMM bank. *
376 * The contents of this register are preserved through soft-resets. *
378 ************************************************************************/
385 typedef union md_memory_config_u {
386 bdrkreg_t md_memory_config_regval;
388 bdrkreg_t mc_dimm0_bank_enable : 2;
389 bdrkreg_t mc_reserved_7 : 1;
390 bdrkreg_t mc_dimm0_dram_width : 1;
391 bdrkreg_t mc_dimm0_bank_size : 4;
392 bdrkreg_t mc_dimm1_bank_enable : 2;
393 bdrkreg_t mc_reserved_6 : 1;
394 bdrkreg_t mc_dimm1_dram_width : 1;
395 bdrkreg_t mc_dimm1_bank_size : 4;
396 bdrkreg_t mc_dimm2_bank_enable : 2;
397 bdrkreg_t mc_reserved_5 : 1;
398 bdrkreg_t mc_dimm2_dram_width : 1;
399 bdrkreg_t mc_dimm2_bank_size : 4;
400 bdrkreg_t mc_dimm3_bank_enable : 2;
401 bdrkreg_t mc_reserved_4 : 1;
402 bdrkreg_t mc_dimm3_dram_width : 1;
403 bdrkreg_t mc_dimm3_bank_size : 4;
404 bdrkreg_t mc_dimm0_sel : 2;
405 bdrkreg_t mc_reserved_3 : 10;
406 bdrkreg_t mc_cc_enable : 1;
407 bdrkreg_t mc_io_prot_en : 1;
408 bdrkreg_t mc_io_prot_ignore : 1;
409 bdrkreg_t mc_cpu_prot_ignore : 1;
410 bdrkreg_t mc_db_neg_edge : 1;
411 bdrkreg_t mc_phase_delay : 1;
412 bdrkreg_t mc_delay_mux_sel : 2;
413 bdrkreg_t mc_sample_time : 2;
414 bdrkreg_t mc_reserved_2 : 2;
415 bdrkreg_t mc_mb_neg_edge : 3;
416 bdrkreg_t mc_reserved_1 : 1;
417 bdrkreg_t mc_rcd_config : 1;
418 bdrkreg_t mc_rp_config : 1;
419 bdrkreg_t mc_reserved : 2;
420 } md_memory_config_fld_s;
421 } md_memory_config_u_t;
425 typedef union md_memory_config_u {
426 bdrkreg_t md_memory_config_regval;
428 bdrkreg_t mc_reserved : 2;
429 bdrkreg_t mc_rp_config : 1;
430 bdrkreg_t mc_rcd_config : 1;
431 bdrkreg_t mc_reserved_1 : 1;
432 bdrkreg_t mc_mb_neg_edge : 3;
433 bdrkreg_t mc_reserved_2 : 2;
434 bdrkreg_t mc_sample_time : 2;
435 bdrkreg_t mc_delay_mux_sel : 2;
436 bdrkreg_t mc_phase_delay : 1;
437 bdrkreg_t mc_db_neg_edge : 1;
438 bdrkreg_t mc_cpu_prot_ignore : 1;
439 bdrkreg_t mc_io_prot_ignore : 1;
440 bdrkreg_t mc_io_prot_en : 1;
441 bdrkreg_t mc_cc_enable : 1;
442 bdrkreg_t mc_reserved_3 : 10;
443 bdrkreg_t mc_dimm0_sel : 2;
444 bdrkreg_t mc_dimm3_bank_size : 4;
445 bdrkreg_t mc_dimm3_dram_width : 1;
446 bdrkreg_t mc_reserved_4 : 1;
447 bdrkreg_t mc_dimm3_bank_enable : 2;
448 bdrkreg_t mc_dimm2_bank_size : 4;
449 bdrkreg_t mc_dimm2_dram_width : 1;
450 bdrkreg_t mc_reserved_5 : 1;
451 bdrkreg_t mc_dimm2_bank_enable : 2;
452 bdrkreg_t mc_dimm1_bank_size : 4;
453 bdrkreg_t mc_dimm1_dram_width : 1;
454 bdrkreg_t mc_reserved_6 : 1;
455 bdrkreg_t mc_dimm1_bank_enable : 2;
456 bdrkreg_t mc_dimm0_bank_size : 4;
457 bdrkreg_t mc_dimm0_dram_width : 1;
458 bdrkreg_t mc_reserved_7 : 1;
459 bdrkreg_t mc_dimm0_bank_enable : 2;
460 } md_memory_config_fld_s;
461 } md_memory_config_u_t;
472 typedef union md_arbitration_control_u {
473 bdrkreg_t md_arbitration_control_regval;
475 bdrkreg_t ac_reply_guar : 4;
476 bdrkreg_t ac_write_guar : 4;
477 bdrkreg_t ac_reserved : 56;
478 } md_arbitration_control_fld_s;
479 } md_arbitration_control_u_t;
483 typedef union md_arbitration_control_u {
484 bdrkreg_t md_arbitration_control_regval;
486 bdrkreg_t ac_reserved : 56;
487 bdrkreg_t ac_write_guar : 4;
488 bdrkreg_t ac_reply_guar : 4;
489 } md_arbitration_control_fld_s;
490 } md_arbitration_control_u_t;
497 /************************************************************************
499 * Contains page migration control fields. *
501 ************************************************************************/
508 typedef union md_mig_config_u {
509 bdrkreg_t md_mig_config_regval;
511 bdrkreg_t mc_mig_interval : 10;
512 bdrkreg_t mc_reserved_2 : 6;
513 bdrkreg_t mc_mig_node_mask : 8;
514 bdrkreg_t mc_reserved_1 : 8;
515 bdrkreg_t mc_mig_enable : 1;
516 bdrkreg_t mc_reserved : 31;
517 } md_mig_config_fld_s;
522 typedef union md_mig_config_u {
523 bdrkreg_t md_mig_config_regval;
525 bdrkreg_t mc_reserved : 31;
526 bdrkreg_t mc_mig_enable : 1;
527 bdrkreg_t mc_reserved_1 : 8;
528 bdrkreg_t mc_mig_node_mask : 8;
529 bdrkreg_t mc_reserved_2 : 6;
530 bdrkreg_t mc_mig_interval : 10;
531 } md_mig_config_fld_s;
539 /************************************************************************
541 * Each register contains the valid bit and address of the entry in *
542 * the fetch-and-op for cache 0 (or 1). *
544 ************************************************************************/
551 typedef union md_fandop_cac_stat0_u {
552 bdrkreg_t md_fandop_cac_stat0_regval;
554 bdrkreg_t fcs_reserved_1 : 6;
555 bdrkreg_t fcs_addr : 27;
556 bdrkreg_t fcs_reserved : 30;
557 bdrkreg_t fcs_valid : 1;
558 } md_fandop_cac_stat0_fld_s;
559 } md_fandop_cac_stat0_u_t;
563 typedef union md_fandop_cac_stat0_u {
564 bdrkreg_t md_fandop_cac_stat0_regval;
566 bdrkreg_t fcs_valid : 1;
567 bdrkreg_t fcs_reserved : 30;
568 bdrkreg_t fcs_addr : 27;
569 bdrkreg_t fcs_reserved_1 : 6;
570 } md_fandop_cac_stat0_fld_s;
571 } md_fandop_cac_stat0_u_t;
578 /************************************************************************
580 * Each register contains the valid bit and address of the entry in *
581 * the fetch-and-op for cache 0 (or 1). *
583 ************************************************************************/
590 typedef union md_fandop_cac_stat1_u {
591 bdrkreg_t md_fandop_cac_stat1_regval;
593 bdrkreg_t fcs_reserved_1 : 6;
594 bdrkreg_t fcs_addr : 27;
595 bdrkreg_t fcs_reserved : 30;
596 bdrkreg_t fcs_valid : 1;
597 } md_fandop_cac_stat1_fld_s;
598 } md_fandop_cac_stat1_u_t;
602 typedef union md_fandop_cac_stat1_u {
603 bdrkreg_t md_fandop_cac_stat1_regval;
605 bdrkreg_t fcs_valid : 1;
606 bdrkreg_t fcs_reserved : 30;
607 bdrkreg_t fcs_addr : 27;
608 bdrkreg_t fcs_reserved_1 : 6;
609 } md_fandop_cac_stat1_fld_s;
610 } md_fandop_cac_stat1_u_t;
617 /************************************************************************
619 * Description: Contains a number of fields to capture various *
620 * random memory/directory errors. For each 2-bit field, the LSB *
621 * indicates that additional information has been captured for the *
622 * error and the MSB indicates overrun, thus: *
623 * x1: bits 51...0 of this register contain additional information *
624 * for the message that caused this error *
625 * 1x: overrun occurred *
627 ************************************************************************/
634 typedef union md_misc0_error_u {
635 bdrkreg_t md_misc0_error_regval;
637 bdrkreg_t me_command : 7;
638 bdrkreg_t me_reserved_4 : 1;
639 bdrkreg_t me_source : 11;
640 bdrkreg_t me_reserved_3 : 1;
641 bdrkreg_t me_suppl : 11;
642 bdrkreg_t me_reserved_2 : 1;
643 bdrkreg_t me_virtual_channel : 2;
644 bdrkreg_t me_reserved_1 : 2;
645 bdrkreg_t me_tail : 1;
646 bdrkreg_t me_reserved : 11;
647 bdrkreg_t me_xb_error : 4;
648 bdrkreg_t me_bad_partial_data : 2;
649 bdrkreg_t me_missing_dv : 2;
650 bdrkreg_t me_short_pack : 2;
651 bdrkreg_t me_long_pack : 2;
652 bdrkreg_t me_ill_msg : 2;
653 bdrkreg_t me_ill_revision : 2;
654 } md_misc0_error_fld_s;
655 } md_misc0_error_u_t;
659 typedef union md_misc0_error_u {
660 bdrkreg_t md_misc0_error_regval;
662 bdrkreg_t me_ill_revision : 2;
663 bdrkreg_t me_ill_msg : 2;
664 bdrkreg_t me_long_pack : 2;
665 bdrkreg_t me_short_pack : 2;
666 bdrkreg_t me_missing_dv : 2;
667 bdrkreg_t me_bad_partial_data : 2;
668 bdrkreg_t me_xb_error : 4;
669 bdrkreg_t me_reserved : 11;
670 bdrkreg_t me_tail : 1;
671 bdrkreg_t me_reserved_1 : 2;
672 bdrkreg_t me_virtual_channel : 2;
673 bdrkreg_t me_reserved_2 : 1;
674 bdrkreg_t me_suppl : 11;
675 bdrkreg_t me_reserved_3 : 1;
676 bdrkreg_t me_source : 11;
677 bdrkreg_t me_reserved_4 : 1;
678 bdrkreg_t me_command : 7;
679 } md_misc0_error_fld_s;
680 } md_misc0_error_u_t;
687 /************************************************************************
689 * Address for error captured in MISC0_ERROR. Error valid bits are *
690 * repeated in both MISC0_ERROR and MISC1_ERROR (allowing them to be *
691 * read sequentially without missing any errors). *
693 ************************************************************************/
700 typedef union md_misc1_error_u {
701 bdrkreg_t md_misc1_error_regval;
703 bdrkreg_t me_reserved_1 : 3;
704 bdrkreg_t me_address : 38;
705 bdrkreg_t me_reserved : 7;
706 bdrkreg_t me_xb_error : 4;
707 bdrkreg_t me_bad_partial_data : 2;
708 bdrkreg_t me_missing_dv : 2;
709 bdrkreg_t me_short_pack : 2;
710 bdrkreg_t me_long_pack : 2;
711 bdrkreg_t me_ill_msg : 2;
712 bdrkreg_t me_ill_revision : 2;
713 } md_misc1_error_fld_s;
714 } md_misc1_error_u_t;
718 typedef union md_misc1_error_u {
719 bdrkreg_t md_misc1_error_regval;
721 bdrkreg_t me_ill_revision : 2;
722 bdrkreg_t me_ill_msg : 2;
723 bdrkreg_t me_long_pack : 2;
724 bdrkreg_t me_short_pack : 2;
725 bdrkreg_t me_missing_dv : 2;
726 bdrkreg_t me_bad_partial_data : 2;
727 bdrkreg_t me_xb_error : 4;
728 bdrkreg_t me_reserved : 7;
729 bdrkreg_t me_address : 38;
730 bdrkreg_t me_reserved_1 : 3;
731 } md_misc1_error_fld_s;
732 } md_misc1_error_u_t;
739 /************************************************************************
741 * Address for error captured in MISC0_ERROR. Error valid bits are *
742 * repeated in both MISC0_ERROR and MISC1_ERROR (allowing them to be *
743 * read sequentially without missing any errors). *
745 ************************************************************************/
752 typedef union md_misc1_error_clr_u {
753 bdrkreg_t md_misc1_error_clr_regval;
755 bdrkreg_t mec_reserved_1 : 3;
756 bdrkreg_t mec_address : 38;
757 bdrkreg_t mec_reserved : 7;
758 bdrkreg_t mec_xb_error : 4;
759 bdrkreg_t mec_bad_partial_data : 2;
760 bdrkreg_t mec_missing_dv : 2;
761 bdrkreg_t mec_short_pack : 2;
762 bdrkreg_t mec_long_pack : 2;
763 bdrkreg_t mec_ill_msg : 2;
764 bdrkreg_t mec_ill_revision : 2;
765 } md_misc1_error_clr_fld_s;
766 } md_misc1_error_clr_u_t;
770 typedef union md_misc1_error_clr_u {
771 bdrkreg_t md_misc1_error_clr_regval;
773 bdrkreg_t mec_ill_revision : 2;
774 bdrkreg_t mec_ill_msg : 2;
775 bdrkreg_t mec_long_pack : 2;
776 bdrkreg_t mec_short_pack : 2;
777 bdrkreg_t mec_missing_dv : 2;
778 bdrkreg_t mec_bad_partial_data : 2;
779 bdrkreg_t mec_xb_error : 4;
780 bdrkreg_t mec_reserved : 7;
781 bdrkreg_t mec_address : 38;
782 bdrkreg_t mec_reserved_1 : 3;
783 } md_misc1_error_clr_fld_s;
784 } md_misc1_error_clr_u_t;
791 /************************************************************************
793 * Description: The MD no longer allows for arbitrarily sizing the *
794 * reply queues, so all of the fields in this register are read-only *
795 * and contain the reset default value of 12 for the MOQHs (for *
796 * headers) and 24 for the MOQDs (for data). *
797 * Reading from this register returns the values currently held in *
798 * the MD's credit counters. Writing to the register resets the *
799 * counters to the default reset values specified in the table below. *
801 ************************************************************************/
808 typedef union md_outgoing_rp_queue_size_u {
809 bdrkreg_t md_outgoing_rp_queue_size_regval;
811 bdrkreg_t orqs_reserved_6 : 8;
812 bdrkreg_t orqs_moqh_p0_rp_size : 4;
813 bdrkreg_t orqs_reserved_5 : 4;
814 bdrkreg_t orqs_moqh_p1_rp_size : 4;
815 bdrkreg_t orqs_reserved_4 : 4;
816 bdrkreg_t orqs_moqh_np_rp_size : 4;
817 bdrkreg_t orqs_reserved_3 : 4;
818 bdrkreg_t orqs_moqd_pi0_rp_size : 5;
819 bdrkreg_t orqs_reserved_2 : 3;
820 bdrkreg_t orqs_moqd_pi1_rp_size : 5;
821 bdrkreg_t orqs_reserved_1 : 3;
822 bdrkreg_t orqs_moqd_np_rp_size : 5;
823 bdrkreg_t orqs_reserved : 11;
824 } md_outgoing_rp_queue_size_fld_s;
825 } md_outgoing_rp_queue_size_u_t;
829 typedef union md_outgoing_rp_queue_size_u {
830 bdrkreg_t md_outgoing_rp_queue_size_regval;
832 bdrkreg_t orqs_reserved : 11;
833 bdrkreg_t orqs_moqd_np_rp_size : 5;
834 bdrkreg_t orqs_reserved_1 : 3;
835 bdrkreg_t orqs_moqd_pi1_rp_size : 5;
836 bdrkreg_t orqs_reserved_2 : 3;
837 bdrkreg_t orqs_moqd_pi0_rp_size : 5;
838 bdrkreg_t orqs_reserved_3 : 4;
839 bdrkreg_t orqs_moqh_np_rp_size : 4;
840 bdrkreg_t orqs_reserved_4 : 4;
841 bdrkreg_t orqs_moqh_p1_rp_size : 4;
842 bdrkreg_t orqs_reserved_5 : 4;
843 bdrkreg_t orqs_moqh_p0_rp_size : 4;
844 bdrkreg_t orqs_reserved_6 : 8;
845 } md_outgoing_rp_queue_size_fld_s;
846 } md_outgoing_rp_queue_size_u_t;
857 typedef union md_perf_sel0_u {
858 bdrkreg_t md_perf_sel0_regval;
860 bdrkreg_t ps_cnt_mode : 2;
861 bdrkreg_t ps_reserved_2 : 2;
862 bdrkreg_t ps_activity : 4;
863 bdrkreg_t ps_source : 7;
864 bdrkreg_t ps_reserved_1 : 1;
865 bdrkreg_t ps_channel : 4;
866 bdrkreg_t ps_command : 40;
867 bdrkreg_t ps_reserved : 3;
868 bdrkreg_t ps_interrupt : 1;
869 } md_perf_sel0_fld_s;
874 typedef union md_perf_sel0_u {
875 bdrkreg_t md_perf_sel0_regval;
877 bdrkreg_t ps_interrupt : 1;
878 bdrkreg_t ps_reserved : 3;
879 bdrkreg_t ps_command : 40;
880 bdrkreg_t ps_channel : 4;
881 bdrkreg_t ps_reserved_1 : 1;
882 bdrkreg_t ps_source : 7;
883 bdrkreg_t ps_activity : 4;
884 bdrkreg_t ps_reserved_2 : 2;
885 bdrkreg_t ps_cnt_mode : 2;
886 } md_perf_sel0_fld_s;
896 typedef union md_perf_sel1_u {
897 bdrkreg_t md_perf_sel1_regval;
899 bdrkreg_t ps_cnt_mode : 2;
900 bdrkreg_t ps_reserved_2 : 2;
901 bdrkreg_t ps_activity : 4;
902 bdrkreg_t ps_source : 7;
903 bdrkreg_t ps_reserved_1 : 1;
904 bdrkreg_t ps_channel : 4;
905 bdrkreg_t ps_command : 40;
906 bdrkreg_t ps_reserved : 3;
907 bdrkreg_t ps_interrupt : 1;
908 } md_perf_sel1_fld_s;
913 typedef union md_perf_sel1_u {
914 bdrkreg_t md_perf_sel1_regval;
916 bdrkreg_t ps_interrupt : 1;
917 bdrkreg_t ps_reserved : 3;
918 bdrkreg_t ps_command : 40;
919 bdrkreg_t ps_channel : 4;
920 bdrkreg_t ps_reserved_1 : 1;
921 bdrkreg_t ps_source : 7;
922 bdrkreg_t ps_activity : 4;
923 bdrkreg_t ps_reserved_2 : 2;
924 bdrkreg_t ps_cnt_mode : 2;
925 } md_perf_sel1_fld_s;
933 /************************************************************************
935 * Performance counter. *
937 ************************************************************************/
944 typedef union md_perf_cnt0_u {
945 bdrkreg_t md_perf_cnt0_regval;
947 bdrkreg_t pc_perf_cnt : 41;
948 bdrkreg_t pc_reserved : 23;
949 } md_perf_cnt0_fld_s;
954 typedef union md_perf_cnt0_u {
955 bdrkreg_t md_perf_cnt0_regval;
957 bdrkreg_t pc_reserved : 23;
958 bdrkreg_t pc_perf_cnt : 41;
959 } md_perf_cnt0_fld_s;
967 /************************************************************************
969 * Performance counter. *
971 ************************************************************************/
978 typedef union md_perf_cnt1_u {
979 bdrkreg_t md_perf_cnt1_regval;
981 bdrkreg_t pc_perf_cnt : 41;
982 bdrkreg_t pc_reserved : 23;
983 } md_perf_cnt1_fld_s;
988 typedef union md_perf_cnt1_u {
989 bdrkreg_t md_perf_cnt1_regval;
991 bdrkreg_t pc_reserved : 23;
992 bdrkreg_t pc_perf_cnt : 41;
993 } md_perf_cnt1_fld_s;
1001 /************************************************************************
1003 * Description: This register contains the control for *
1004 * memory/directory refresh. Once the MEMORY_CONFIG register contains *
1005 * the correct DIMM information, the hardware takes care of *
1006 * refreshing all the banks in the system. Therefore, the value in *
1007 * the counter threshold is corresponds exactly to the refresh value *
1008 * required by the SDRAM parts (expressed in Bedrock clock cycles). *
1009 * The refresh will execute whenever there is a free cycle and there *
1010 * are still banks that have not been refreshed in the current *
1011 * window. If the window expires with banks still waiting to be *
1012 * refreshed, all other transactions are halted until the banks are *
1014 * The upper order bit contains an enable, which may be needed for *
1015 * correct initialization of the DIMMs (according to the specs, the *
1016 * first operation to the DIMMs should be a mode register write, not *
1017 * a refresh, so this bit is cleared on reset) and is also useful for *
1018 * diagnostic purposes. *
1019 * For the SDRAM parts used by Bedrock, 4096 refreshes need to be *
1020 * issued during every 64 ms window, resulting in a refresh threshold *
1021 * of 3125 Bedrock cycles. *
1022 * The ENABLE and CNT_THRESH fields of this register are preserved *
1023 * through soft-resets. *
1025 ************************************************************************/
1030 #ifdef LITTLE_ENDIAN
1032 typedef union md_refresh_control_u {
1033 bdrkreg_t md_refresh_control_regval;
1035 bdrkreg_t rc_cnt_thresh : 12;
1036 bdrkreg_t rc_counter : 12;
1037 bdrkreg_t rc_reserved : 39;
1038 bdrkreg_t rc_enable : 1;
1039 } md_refresh_control_fld_s;
1040 } md_refresh_control_u_t;
1044 typedef union md_refresh_control_u {
1045 bdrkreg_t md_refresh_control_regval;
1047 bdrkreg_t rc_enable : 1;
1048 bdrkreg_t rc_reserved : 39;
1049 bdrkreg_t rc_counter : 12;
1050 bdrkreg_t rc_cnt_thresh : 12;
1051 } md_refresh_control_fld_s;
1052 } md_refresh_control_u_t;
1059 /************************************************************************
1061 * This register controls the read and write timing for Flash PROM, *
1062 * UART and Synergy junk bus devices. *
1064 ************************************************************************/
1069 #ifdef LITTLE_ENDIAN
1071 typedef union md_junk_bus_timing_u {
1072 bdrkreg_t md_junk_bus_timing_regval;
1074 bdrkreg_t jbt_fprom_setup_hold : 8;
1075 bdrkreg_t jbt_fprom_enable : 8;
1076 bdrkreg_t jbt_uart_setup_hold : 8;
1077 bdrkreg_t jbt_uart_enable : 8;
1078 bdrkreg_t jbt_synergy_setup_hold : 8;
1079 bdrkreg_t jbt_synergy_enable : 8;
1080 bdrkreg_t jbt_reserved : 16;
1081 } md_junk_bus_timing_fld_s;
1082 } md_junk_bus_timing_u_t;
1086 typedef union md_junk_bus_timing_u {
1087 bdrkreg_t md_junk_bus_timing_regval;
1089 bdrkreg_t jbt_reserved : 16;
1090 bdrkreg_t jbt_synergy_enable : 8;
1091 bdrkreg_t jbt_synergy_setup_hold : 8;
1092 bdrkreg_t jbt_uart_enable : 8;
1093 bdrkreg_t jbt_uart_setup_hold : 8;
1094 bdrkreg_t jbt_fprom_enable : 8;
1095 bdrkreg_t jbt_fprom_setup_hold : 8;
1096 } md_junk_bus_timing_fld_s;
1097 } md_junk_bus_timing_u_t;
1104 /************************************************************************
1106 * Each of these addresses allows the value on one 8-bit bank of *
1107 * LEDs to be read. *
1109 ************************************************************************/
1114 #ifdef LITTLE_ENDIAN
1116 typedef union md_led0_u {
1117 bdrkreg_t md_led0_regval;
1119 bdrkreg_t l_data : 8;
1120 bdrkreg_t l_reserved : 56;
1126 typedef union md_led0_u {
1127 bdrkreg_t md_led0_regval;
1129 bdrkreg_t l_reserved : 56;
1130 bdrkreg_t l_data : 8;
1139 /************************************************************************
1141 * Each of these addresses allows the value on one 8-bit bank of *
1142 * LEDs to be read. *
1144 ************************************************************************/
1149 #ifdef LITTLE_ENDIAN
1151 typedef union md_led1_u {
1152 bdrkreg_t md_led1_regval;
1154 bdrkreg_t l_data : 8;
1155 bdrkreg_t l_reserved : 56;
1161 typedef union md_led1_u {
1162 bdrkreg_t md_led1_regval;
1164 bdrkreg_t l_reserved : 56;
1165 bdrkreg_t l_data : 8;
1174 /************************************************************************
1176 * Each of these addresses allows the value on one 8-bit bank of *
1177 * LEDs to be read. *
1179 ************************************************************************/
1184 #ifdef LITTLE_ENDIAN
1186 typedef union md_led2_u {
1187 bdrkreg_t md_led2_regval;
1189 bdrkreg_t l_data : 8;
1190 bdrkreg_t l_reserved : 56;
1196 typedef union md_led2_u {
1197 bdrkreg_t md_led2_regval;
1199 bdrkreg_t l_reserved : 56;
1200 bdrkreg_t l_data : 8;
1209 /************************************************************************
1211 * Each of these addresses allows the value on one 8-bit bank of *
1212 * LEDs to be read. *
1214 ************************************************************************/
1219 #ifdef LITTLE_ENDIAN
1221 typedef union md_led3_u {
1222 bdrkreg_t md_led3_regval;
1224 bdrkreg_t l_data : 8;
1225 bdrkreg_t l_reserved : 56;
1231 typedef union md_led3_u {
1232 bdrkreg_t md_led3_regval;
1234 bdrkreg_t l_reserved : 56;
1235 bdrkreg_t l_data : 8;
1244 /************************************************************************
1246 * Core control for the BIST function. Start and stop BIST at any *
1249 ************************************************************************/
1254 #ifdef LITTLE_ENDIAN
1256 typedef union md_bist_ctl_u {
1257 bdrkreg_t md_bist_ctl_regval;
1259 bdrkreg_t bc_bist_start : 1;
1260 bdrkreg_t bc_bist_stop : 1;
1261 bdrkreg_t bc_bist_reset : 1;
1262 bdrkreg_t bc_reserved_1 : 1;
1263 bdrkreg_t bc_bank_num : 1;
1264 bdrkreg_t bc_dimm_num : 2;
1265 bdrkreg_t bc_reserved : 57;
1266 } md_bist_ctl_fld_s;
1271 typedef union md_bist_ctl_u {
1272 bdrkreg_t md_bist_ctl_regval;
1274 bdrkreg_t bc_reserved : 57;
1275 bdrkreg_t bc_dimm_num : 2;
1276 bdrkreg_t bc_bank_num : 1;
1277 bdrkreg_t bc_reserved_1 : 1;
1278 bdrkreg_t bc_bist_reset : 1;
1279 bdrkreg_t bc_bist_stop : 1;
1280 bdrkreg_t bc_bist_start : 1;
1281 } md_bist_ctl_fld_s;
1289 /************************************************************************
1291 * Contain the initial BIST data nibble and the 4-bit data control *
1294 ************************************************************************/
1298 #ifdef LITTLE_ENDIAN
1300 typedef union md_bist_data_u {
1301 bdrkreg_t md_bist_data_regval;
1303 bdrkreg_t bd_bist_data : 4;
1304 bdrkreg_t bd_bist_nibble : 1;
1305 bdrkreg_t bd_bist_byte : 1;
1306 bdrkreg_t bd_bist_cycle : 1;
1307 bdrkreg_t bd_bist_write : 1;
1308 bdrkreg_t bd_reserved : 56;
1309 } md_bist_data_fld_s;
1314 typedef union md_bist_data_u {
1315 bdrkreg_t md_bist_data_regval;
1317 bdrkreg_t bd_reserved : 56;
1318 bdrkreg_t bd_bist_write : 1;
1319 bdrkreg_t bd_bist_cycle : 1;
1320 bdrkreg_t bd_bist_byte : 1;
1321 bdrkreg_t bd_bist_nibble : 1;
1322 bdrkreg_t bd_bist_data : 4;
1323 } md_bist_data_fld_s;
1331 /************************************************************************
1333 * Captures the BIST error address and indicates whether it is an MB *
1334 * error or DB error. *
1336 ************************************************************************/
1341 #ifdef LITTLE_ENDIAN
1343 typedef union md_bist_ab_err_addr_u {
1344 bdrkreg_t md_bist_ab_err_addr_regval;
1346 bdrkreg_t baea_be_db_cas_addr : 15;
1347 bdrkreg_t baea_reserved_3 : 1;
1348 bdrkreg_t baea_be_mb_cas_addr : 15;
1349 bdrkreg_t baea_reserved_2 : 1;
1350 bdrkreg_t baea_be_ras_addr : 15;
1351 bdrkreg_t baea_reserved_1 : 1;
1352 bdrkreg_t baea_bist_mb_error : 1;
1353 bdrkreg_t baea_bist_db_error : 1;
1354 bdrkreg_t baea_reserved : 14;
1355 } md_bist_ab_err_addr_fld_s;
1356 } md_bist_ab_err_addr_u_t;
1360 typedef union md_bist_ab_err_addr_u {
1361 bdrkreg_t md_bist_ab_err_addr_regval;
1363 bdrkreg_t baea_reserved : 14;
1364 bdrkreg_t baea_bist_db_error : 1;
1365 bdrkreg_t baea_bist_mb_error : 1;
1366 bdrkreg_t baea_reserved_1 : 1;
1367 bdrkreg_t baea_be_ras_addr : 15;
1368 bdrkreg_t baea_reserved_2 : 1;
1369 bdrkreg_t baea_be_mb_cas_addr : 15;
1370 bdrkreg_t baea_reserved_3 : 1;
1371 bdrkreg_t baea_be_db_cas_addr : 15;
1372 } md_bist_ab_err_addr_fld_s;
1373 } md_bist_ab_err_addr_u_t;
1379 /************************************************************************
1381 * Contains information on BIST progress and memory bank currently *
1384 ************************************************************************/
1389 #ifdef LITTLE_ENDIAN
1391 typedef union md_bist_status_u {
1392 bdrkreg_t md_bist_status_regval;
1394 bdrkreg_t bs_bist_passed : 1;
1395 bdrkreg_t bs_bist_done : 1;
1396 bdrkreg_t bs_reserved : 62;
1397 } md_bist_status_fld_s;
1398 } md_bist_status_u_t;
1402 typedef union md_bist_status_u {
1403 bdrkreg_t md_bist_status_regval;
1405 bdrkreg_t bs_reserved : 62;
1406 bdrkreg_t bs_bist_done : 1;
1407 bdrkreg_t bs_bist_passed : 1;
1408 } md_bist_status_fld_s;
1409 } md_bist_status_u_t;
1416 /************************************************************************
1418 * Contains 3 bits that allow the selection of IB debug information *
1419 * at the debug port (see design specification for available debug *
1422 ************************************************************************/
1427 #ifdef LITTLE_ENDIAN
1429 typedef union md_ib_debug_u {
1430 bdrkreg_t md_ib_debug_regval;
1432 bdrkreg_t id_ib_debug_sel : 2;
1433 bdrkreg_t id_reserved : 62;
1434 } md_ib_debug_fld_s;
1439 typedef union md_ib_debug_u {
1440 bdrkreg_t md_ib_debug_regval;
1442 bdrkreg_t id_reserved : 62;
1443 bdrkreg_t id_ib_debug_sel : 2;
1444 } md_ib_debug_fld_s;
1452 /************************************************************************
1454 * Contains the directory specific mode bits. The contents of this *
1455 * register are preserved through soft-resets. *
1457 ************************************************************************/
1462 #ifdef LITTLE_ENDIAN
1464 typedef union md_dir_config_u {
1465 bdrkreg_t md_dir_config_regval;
1467 bdrkreg_t dc_dir_flavor : 1;
1468 bdrkreg_t dc_ignore_dir_ecc : 1;
1469 bdrkreg_t dc_reserved : 62;
1470 } md_dir_config_fld_s;
1471 } md_dir_config_u_t;
1475 typedef union md_dir_config_u {
1476 bdrkreg_t md_dir_config_regval;
1478 bdrkreg_t dc_reserved : 62;
1479 bdrkreg_t dc_ignore_dir_ecc : 1;
1480 bdrkreg_t dc_dir_flavor : 1;
1481 } md_dir_config_fld_s;
1482 } md_dir_config_u_t;
1489 /************************************************************************
1491 * Description: Contains information on uncorrectable and *
1492 * correctable directory ECC errors, along with protection ECC *
1493 * errors. The priority of ECC errors latched is: uncorrectable *
1494 * directory, protection error, correctable directory. Thus the valid *
1496 * 1xxx: uncorrectable directory ECC error (UCE) *
1497 * 01xx: access protection double bit error (AE) *
1498 * 001x: correctable directory ECC error (CE) *
1499 * 0001: access protection correctable error (ACE) *
1500 * If the UCE valid bit is set, the address field contains a pointer *
1501 * to the Hspec address of the offending directory entry, the *
1502 * syndrome field contains the bad syndrome, and the UCE overrun bit *
1503 * indicates whether multiple double-bit errors were received. *
1504 * If the UCE valid bit is clear but the AE valid bit is set, the *
1505 * address field contains a pointer to the Hspec address of the *
1506 * offending protection entry, the Bad Protection field contains the *
1507 * 4-bit bad protection value, the PROT_INDEX field shows which of *
1508 * the 8 protection values in the word was bad and the AE overrun bit *
1509 * indicates whether multiple AE errors were received. *
1510 * If the UCE and AE valid bits are clear, but the CE valid bit is *
1511 * set, the address field contains a pointer to the Hspec address of *
1512 * the offending directory entry, the syndrome field contains the bad *
1513 * syndrome, and the CE overrun bit indicates whether multiple *
1514 * single-bit errors were received. *
1516 ************************************************************************/
1521 #ifdef LITTLE_ENDIAN
1523 typedef union md_dir_error_u {
1524 bdrkreg_t md_dir_error_regval;
1526 bdrkreg_t de_reserved_3 : 3;
1527 bdrkreg_t de_hspec_addr : 30;
1528 bdrkreg_t de_reserved_2 : 7;
1529 bdrkreg_t de_bad_syn : 7;
1530 bdrkreg_t de_reserved_1 : 1;
1531 bdrkreg_t de_bad_protect : 4;
1532 bdrkreg_t de_prot_index : 3;
1533 bdrkreg_t de_reserved : 1;
1534 bdrkreg_t de_ace_overrun : 1;
1535 bdrkreg_t de_ce_overrun : 1;
1536 bdrkreg_t de_ae_overrun : 1;
1537 bdrkreg_t de_uce_overrun : 1;
1538 bdrkreg_t de_ace_valid : 1;
1539 bdrkreg_t de_ce_valid : 1;
1540 bdrkreg_t de_ae_valid : 1;
1541 bdrkreg_t de_uce_valid : 1;
1542 } md_dir_error_fld_s;
1547 typedef union md_dir_error_u {
1548 bdrkreg_t md_dir_error_regval;
1550 bdrkreg_t de_uce_valid : 1;
1551 bdrkreg_t de_ae_valid : 1;
1552 bdrkreg_t de_ce_valid : 1;
1553 bdrkreg_t de_ace_valid : 1;
1554 bdrkreg_t de_uce_overrun : 1;
1555 bdrkreg_t de_ae_overrun : 1;
1556 bdrkreg_t de_ce_overrun : 1;
1557 bdrkreg_t de_ace_overrun : 1;
1558 bdrkreg_t de_reserved : 1;
1559 bdrkreg_t de_prot_index : 3;
1560 bdrkreg_t de_bad_protect : 4;
1561 bdrkreg_t de_reserved_1 : 1;
1562 bdrkreg_t de_bad_syn : 7;
1563 bdrkreg_t de_reserved_2 : 7;
1564 bdrkreg_t de_hspec_addr : 30;
1565 bdrkreg_t de_reserved_3 : 3;
1566 } md_dir_error_fld_s;
1574 /************************************************************************
1576 * Description: Contains information on uncorrectable and *
1577 * correctable directory ECC errors, along with protection ECC *
1578 * errors. The priority of ECC errors latched is: uncorrectable *
1579 * directory, protection error, correctable directory. Thus the valid *
1581 * 1xxx: uncorrectable directory ECC error (UCE) *
1582 * 01xx: access protection double bit error (AE) *
1583 * 001x: correctable directory ECC error (CE) *
1584 * 0001: access protection correctable error (ACE) *
1585 * If the UCE valid bit is set, the address field contains a pointer *
1586 * to the Hspec address of the offending directory entry, the *
1587 * syndrome field contains the bad syndrome, and the UCE overrun bit *
1588 * indicates whether multiple double-bit errors were received. *
1589 * If the UCE valid bit is clear but the AE valid bit is set, the *
1590 * address field contains a pointer to the Hspec address of the *
1591 * offending protection entry, the Bad Protection field contains the *
1592 * 4-bit bad protection value, the PROT_INDEX field shows which of *
1593 * the 8 protection values in the word was bad and the AE overrun bit *
1594 * indicates whether multiple AE errors were received. *
1595 * If the UCE and AE valid bits are clear, but the CE valid bit is *
1596 * set, the address field contains a pointer to the Hspec address of *
1597 * the offending directory entry, the syndrome field contains the bad *
1598 * syndrome, and the CE overrun bit indicates whether multiple *
1599 * single-bit errors were received. *
1601 ************************************************************************/
1606 #ifdef LITTLE_ENDIAN
1608 typedef union md_dir_error_clr_u {
1609 bdrkreg_t md_dir_error_clr_regval;
1611 bdrkreg_t dec_reserved_3 : 3;
1612 bdrkreg_t dec_hspec_addr : 30;
1613 bdrkreg_t dec_reserved_2 : 7;
1614 bdrkreg_t dec_bad_syn : 7;
1615 bdrkreg_t dec_reserved_1 : 1;
1616 bdrkreg_t dec_bad_protect : 4;
1617 bdrkreg_t dec_prot_index : 3;
1618 bdrkreg_t dec_reserved : 1;
1619 bdrkreg_t dec_ace_overrun : 1;
1620 bdrkreg_t dec_ce_overrun : 1;
1621 bdrkreg_t dec_ae_overrun : 1;
1622 bdrkreg_t dec_uce_overrun : 1;
1623 bdrkreg_t dec_ace_valid : 1;
1624 bdrkreg_t dec_ce_valid : 1;
1625 bdrkreg_t dec_ae_valid : 1;
1626 bdrkreg_t dec_uce_valid : 1;
1627 } md_dir_error_clr_fld_s;
1628 } md_dir_error_clr_u_t;
1632 typedef union md_dir_error_clr_u {
1633 bdrkreg_t md_dir_error_clr_regval;
1635 bdrkreg_t dec_uce_valid : 1;
1636 bdrkreg_t dec_ae_valid : 1;
1637 bdrkreg_t dec_ce_valid : 1;
1638 bdrkreg_t dec_ace_valid : 1;
1639 bdrkreg_t dec_uce_overrun : 1;
1640 bdrkreg_t dec_ae_overrun : 1;
1641 bdrkreg_t dec_ce_overrun : 1;
1642 bdrkreg_t dec_ace_overrun : 1;
1643 bdrkreg_t dec_reserved : 1;
1644 bdrkreg_t dec_prot_index : 3;
1645 bdrkreg_t dec_bad_protect : 4;
1646 bdrkreg_t dec_reserved_1 : 1;
1647 bdrkreg_t dec_bad_syn : 7;
1648 bdrkreg_t dec_reserved_2 : 7;
1649 bdrkreg_t dec_hspec_addr : 30;
1650 bdrkreg_t dec_reserved_3 : 3;
1651 } md_dir_error_clr_fld_s;
1652 } md_dir_error_clr_u_t;
1659 /************************************************************************
1661 * Contains information on requests that encounter no valid protocol *
1664 ************************************************************************/
1669 #ifdef LITTLE_ENDIAN
1671 typedef union md_protocol_error_u {
1672 bdrkreg_t md_protocol_error_regval;
1674 bdrkreg_t pe_overrun : 1;
1675 bdrkreg_t pe_pointer_me : 1;
1676 bdrkreg_t pe_reserved_1 : 1;
1677 bdrkreg_t pe_address : 30;
1678 bdrkreg_t pe_reserved : 1;
1679 bdrkreg_t pe_ptr1_btmbits : 3;
1680 bdrkreg_t pe_dir_format : 2;
1681 bdrkreg_t pe_dir_state : 3;
1682 bdrkreg_t pe_priority : 1;
1683 bdrkreg_t pe_access : 1;
1684 bdrkreg_t pe_msg_type : 8;
1685 bdrkreg_t pe_initiator : 11;
1686 bdrkreg_t pe_valid : 1;
1687 } md_protocol_error_fld_s;
1688 } md_protocol_error_u_t;
1692 typedef union md_protocol_error_u {
1693 bdrkreg_t md_protocol_error_regval;
1695 bdrkreg_t pe_valid : 1;
1696 bdrkreg_t pe_initiator : 11;
1697 bdrkreg_t pe_msg_type : 8;
1698 bdrkreg_t pe_access : 1;
1699 bdrkreg_t pe_priority : 1;
1700 bdrkreg_t pe_dir_state : 3;
1701 bdrkreg_t pe_dir_format : 2;
1702 bdrkreg_t pe_ptr1_btmbits : 3;
1703 bdrkreg_t pe_reserved : 1;
1704 bdrkreg_t pe_address : 30;
1705 bdrkreg_t pe_reserved_1 : 1;
1706 bdrkreg_t pe_pointer_me : 1;
1707 bdrkreg_t pe_overrun : 1;
1708 } md_protocol_error_fld_s;
1709 } md_protocol_error_u_t;
1716 /************************************************************************
1718 * Contains information on requests that encounter no valid protocol *
1721 ************************************************************************/
1726 #ifdef LITTLE_ENDIAN
1728 typedef union md_protocol_err_clr_u {
1729 bdrkreg_t md_protocol_err_clr_regval;
1731 bdrkreg_t pec_overrun : 1;
1732 bdrkreg_t pec_pointer_me : 1;
1733 bdrkreg_t pec_reserved_1 : 1;
1734 bdrkreg_t pec_address : 30;
1735 bdrkreg_t pec_reserved : 1;
1736 bdrkreg_t pec_ptr1_btmbits : 3;
1737 bdrkreg_t pec_dir_format : 2;
1738 bdrkreg_t pec_dir_state : 3;
1739 bdrkreg_t pec_priority : 1;
1740 bdrkreg_t pec_access : 1;
1741 bdrkreg_t pec_msg_type : 8;
1742 bdrkreg_t pec_initiator : 11;
1743 bdrkreg_t pec_valid : 1;
1744 } md_protocol_err_clr_fld_s;
1745 } md_protocol_err_clr_u_t;
1749 typedef union md_protocol_err_clr_u {
1750 bdrkreg_t md_protocol_err_clr_regval;
1752 bdrkreg_t pec_valid : 1;
1753 bdrkreg_t pec_initiator : 11;
1754 bdrkreg_t pec_msg_type : 8;
1755 bdrkreg_t pec_access : 1;
1756 bdrkreg_t pec_priority : 1;
1757 bdrkreg_t pec_dir_state : 3;
1758 bdrkreg_t pec_dir_format : 2;
1759 bdrkreg_t pec_ptr1_btmbits : 3;
1760 bdrkreg_t pec_reserved : 1;
1761 bdrkreg_t pec_address : 30;
1762 bdrkreg_t pec_reserved_1 : 1;
1763 bdrkreg_t pec_pointer_me : 1;
1764 bdrkreg_t pec_overrun : 1;
1765 } md_protocol_err_clr_fld_s;
1766 } md_protocol_err_clr_u_t;
1773 /************************************************************************
1775 * Contains the address of the page and the requestor which caused a *
1776 * migration threshold to be exceeded. Also contains the type of *
1777 * threshold exceeded and an overrun bit. For Value mode type *
1778 * interrupts, it indicates whether the local or the remote counter *
1779 * triggered the interrupt. Unlike most registers, when the overrun *
1780 * bit is set the register contains information on the most recent *
1781 * (the last) migration candidate. *
1783 ************************************************************************/
1788 #ifdef LITTLE_ENDIAN
1790 typedef union md_mig_candidate_u {
1791 bdrkreg_t md_mig_candidate_regval;
1793 bdrkreg_t mc_address : 21;
1794 bdrkreg_t mc_initiator : 11;
1795 bdrkreg_t mc_overrun : 1;
1796 bdrkreg_t mc_type : 1;
1797 bdrkreg_t mc_local : 1;
1798 bdrkreg_t mc_reserved : 28;
1799 bdrkreg_t mc_valid : 1;
1800 } md_mig_candidate_fld_s;
1801 } md_mig_candidate_u_t;
1805 typedef union md_mig_candidate_u {
1806 bdrkreg_t md_mig_candidate_regval;
1808 bdrkreg_t mc_valid : 1;
1809 bdrkreg_t mc_reserved : 28;
1810 bdrkreg_t mc_local : 1;
1811 bdrkreg_t mc_type : 1;
1812 bdrkreg_t mc_overrun : 1;
1813 bdrkreg_t mc_initiator : 11;
1814 bdrkreg_t mc_address : 21;
1815 } md_mig_candidate_fld_s;
1816 } md_mig_candidate_u_t;
1823 /************************************************************************
1825 * Contains the address of the page and the requestor which caused a *
1826 * migration threshold to be exceeded. Also contains the type of *
1827 * threshold exceeded and an overrun bit. For Value mode type *
1828 * interrupts, it indicates whether the local or the remote counter *
1829 * triggered the interrupt. Unlike most registers, when the overrun *
1830 * bit is set the register contains information on the most recent *
1831 * (the last) migration candidate. *
1833 ************************************************************************/
1838 #ifdef LITTLE_ENDIAN
1840 typedef union md_mig_candidate_clr_u {
1841 bdrkreg_t md_mig_candidate_clr_regval;
1843 bdrkreg_t mcc_address : 21;
1844 bdrkreg_t mcc_initiator : 11;
1845 bdrkreg_t mcc_overrun : 1;
1846 bdrkreg_t mcc_type : 1;
1847 bdrkreg_t mcc_local : 1;
1848 bdrkreg_t mcc_reserved : 28;
1849 bdrkreg_t mcc_valid : 1;
1850 } md_mig_candidate_clr_fld_s;
1851 } md_mig_candidate_clr_u_t;
1855 typedef union md_mig_candidate_clr_u {
1856 bdrkreg_t md_mig_candidate_clr_regval;
1858 bdrkreg_t mcc_valid : 1;
1859 bdrkreg_t mcc_reserved : 28;
1860 bdrkreg_t mcc_local : 1;
1861 bdrkreg_t mcc_type : 1;
1862 bdrkreg_t mcc_overrun : 1;
1863 bdrkreg_t mcc_initiator : 11;
1864 bdrkreg_t mcc_address : 21;
1865 } md_mig_candidate_clr_fld_s;
1866 } md_mig_candidate_clr_u_t;
1873 /************************************************************************
1875 * Controls the generation of page-migration interrupts and loading *
1876 * of the MIGRATION_CANDIDATE register for pages which are using the *
1877 * difference between the requestor and home counts. If the *
1878 * difference is greater-than or equal to than the threshold *
1879 * contained in the register, and the valid bit is set, the migration *
1880 * candidate is loaded (and an interrupt generated if enabled by the *
1881 * page migration mode). *
1883 ************************************************************************/
1888 #ifdef LITTLE_ENDIAN
1890 typedef union md_mig_diff_thresh_u {
1891 bdrkreg_t md_mig_diff_thresh_regval;
1893 bdrkreg_t mdt_threshold : 15;
1894 bdrkreg_t mdt_reserved_1 : 17;
1895 bdrkreg_t mdt_th_action : 3;
1896 bdrkreg_t mdt_sat_action : 3;
1897 bdrkreg_t mdt_reserved : 25;
1898 bdrkreg_t mdt_valid : 1;
1899 } md_mig_diff_thresh_fld_s;
1900 } md_mig_diff_thresh_u_t;
1904 typedef union md_mig_diff_thresh_u {
1905 bdrkreg_t md_mig_diff_thresh_regval;
1907 bdrkreg_t mdt_valid : 1;
1908 bdrkreg_t mdt_reserved : 25;
1909 bdrkreg_t mdt_sat_action : 3;
1910 bdrkreg_t mdt_th_action : 3;
1911 bdrkreg_t mdt_reserved_1 : 17;
1912 bdrkreg_t mdt_threshold : 15;
1913 } md_mig_diff_thresh_fld_s;
1914 } md_mig_diff_thresh_u_t;
1921 /************************************************************************
1923 * Controls the generation of page-migration interrupts and loading *
1924 * of the MIGRATION_CANDIDATE register for pages that are using the *
1925 * absolute value of the requestor count. If the value is *
1926 * greater-than or equal to the threshold contained in the register, *
1927 * and the register valid bit is set, the migration candidate is *
1928 * loaded and an interrupt generated. For the value mode of page *
1929 * migration, there are two variations. In the first variation, *
1930 * interrupts are only generated when the remote counter reaches the *
1931 * threshold, not when the local counter reaches the threshold. In *
1932 * the second mode, both the local counter and the remote counter *
1933 * generate interrupts if they reach the threshold. This second mode *
1934 * is useful for performance monitoring, to track the number of local *
1935 * and remote references to a page. LOCAL_INT determines whether we *
1936 * will generate interrupts when the local counter reaches the *
1939 ************************************************************************/
1944 #ifdef LITTLE_ENDIAN
1946 typedef union md_mig_value_thresh_u {
1947 bdrkreg_t md_mig_value_thresh_regval;
1949 bdrkreg_t mvt_threshold : 15;
1950 bdrkreg_t mvt_reserved_1 : 17;
1951 bdrkreg_t mvt_th_action : 3;
1952 bdrkreg_t mvt_sat_action : 3;
1953 bdrkreg_t mvt_reserved : 24;
1954 bdrkreg_t mvt_local_int : 1;
1955 bdrkreg_t mvt_valid : 1;
1956 } md_mig_value_thresh_fld_s;
1957 } md_mig_value_thresh_u_t;
1961 typedef union md_mig_value_thresh_u {
1962 bdrkreg_t md_mig_value_thresh_regval;
1964 bdrkreg_t mvt_valid : 1;
1965 bdrkreg_t mvt_local_int : 1;
1966 bdrkreg_t mvt_reserved : 24;
1967 bdrkreg_t mvt_sat_action : 3;
1968 bdrkreg_t mvt_th_action : 3;
1969 bdrkreg_t mvt_reserved_1 : 17;
1970 bdrkreg_t mvt_threshold : 15;
1971 } md_mig_value_thresh_fld_s;
1972 } md_mig_value_thresh_u_t;
1979 /************************************************************************
1981 * Contains the controls for the sizing of the three MOQH request *
1982 * queues. The maximum (and default) value is 4. Queue sizes are in *
1983 * flits. One header equals one flit. *
1985 ************************************************************************/
1990 #ifdef LITTLE_ENDIAN
1992 typedef union md_outgoing_rq_queue_size_u {
1993 bdrkreg_t md_outgoing_rq_queue_size_regval;
1995 bdrkreg_t orqs_reserved_3 : 8;
1996 bdrkreg_t orqs_moqh_p0_rq_size : 3;
1997 bdrkreg_t orqs_reserved_2 : 5;
1998 bdrkreg_t orqs_moqh_p1_rq_size : 3;
1999 bdrkreg_t orqs_reserved_1 : 5;
2000 bdrkreg_t orqs_moqh_np_rq_size : 3;
2001 bdrkreg_t orqs_reserved : 37;
2002 } md_outgoing_rq_queue_size_fld_s;
2003 } md_outgoing_rq_queue_size_u_t;
2007 typedef union md_outgoing_rq_queue_size_u {
2008 bdrkreg_t md_outgoing_rq_queue_size_regval;
2010 bdrkreg_t orqs_reserved : 37;
2011 bdrkreg_t orqs_moqh_np_rq_size : 3;
2012 bdrkreg_t orqs_reserved_1 : 5;
2013 bdrkreg_t orqs_moqh_p1_rq_size : 3;
2014 bdrkreg_t orqs_reserved_2 : 5;
2015 bdrkreg_t orqs_moqh_p0_rq_size : 3;
2016 bdrkreg_t orqs_reserved_3 : 8;
2017 } md_outgoing_rq_queue_size_fld_s;
2018 } md_outgoing_rq_queue_size_u_t;
2025 /************************************************************************
2027 * Contains the 32-bit directory word failing BIST. *
2029 ************************************************************************/
2034 #ifdef LITTLE_ENDIAN
2036 typedef union md_bist_db_err_data_u {
2037 bdrkreg_t md_bist_db_err_data_regval;
2039 bdrkreg_t bded_db_er_d : 32;
2040 bdrkreg_t bded_reserved : 32;
2041 } md_bist_db_err_data_fld_s;
2042 } md_bist_db_err_data_u_t;
2046 typedef union md_bist_db_err_data_u {
2047 bdrkreg_t md_bist_db_err_data_regval;
2049 bdrkreg_t bded_reserved : 32;
2050 bdrkreg_t bded_db_er_d : 32;
2051 } md_bist_db_err_data_fld_s;
2052 } md_bist_db_err_data_u_t;
2058 /************************************************************************
2060 * Contains 2 bits that allow the selection of DB debug information *
2061 * at the debug port (see the design specification for descrition of *
2062 * the available debug information). *
2064 ************************************************************************/
2069 #ifdef LITTLE_ENDIAN
2071 typedef union md_db_debug_u {
2072 bdrkreg_t md_db_debug_regval;
2074 bdrkreg_t dd_db_debug_sel : 2;
2075 bdrkreg_t dd_reserved : 62;
2076 } md_db_debug_fld_s;
2081 typedef union md_db_debug_u {
2082 bdrkreg_t md_db_debug_regval;
2084 bdrkreg_t dd_reserved : 62;
2085 bdrkreg_t dd_db_debug_sel : 2;
2086 } md_db_debug_fld_s;
2094 /************************************************************************
2096 * Contains the IgnoreECC bit. When this bit is set, all ECC errors *
2097 * are ignored. ECC bits will still be generated on writebacks. *
2099 ************************************************************************/
2104 #ifdef LITTLE_ENDIAN
2106 typedef union md_mb_ecc_config_u {
2107 bdrkreg_t md_mb_ecc_config_regval;
2109 bdrkreg_t mec_ignore_dataecc : 1;
2110 bdrkreg_t mec_reserved : 63;
2111 } md_mb_ecc_config_fld_s;
2112 } md_mb_ecc_config_u_t;
2116 typedef union md_mb_ecc_config_u {
2117 bdrkreg_t md_mb_ecc_config_regval;
2119 bdrkreg_t mec_reserved : 63;
2120 bdrkreg_t mec_ignore_dataecc : 1;
2121 } md_mb_ecc_config_fld_s;
2122 } md_mb_ecc_config_u_t;
2129 /************************************************************************
2131 * Description: Contains information on read memory errors (both *
2132 * correctable and uncorrectable) and write memory errors (always *
2133 * uncorrectable). The errors are prioritized as follows: *
2134 * highest: uncorrectable read error (READ_UCE) *
2135 * middle: write error (WRITE_UCE) *
2136 * lowest: correctable read error (READ_CE) *
2137 * Each type of error maintains a two-bit valid/overrun field *
2138 * (READ_UCE, WRITE_UCE, or READ_CE). Bit 0 of each two-bit field *
2139 * corresponds to the valid bit, and bit 1 of each two-bit field *
2140 * corresponds to the overrun bit. *
2141 * The rule for the valid bit is that it gets set whenever that error *
2142 * occurs, regardless of whether a higher priority error has occurred. *
2143 * The rule for the overrun bit is that it gets set whenever we are *
2144 * unable to record the address information for this particular *
2145 * error, due to a previous error of the same or higher priority. *
2146 * Note that the syndrome and address information always corresponds *
2147 * to the earliest, highest priority error. *
2148 * Finally, the UCE_DIFF_ADDR bit is set whenever there have been *
2149 * several uncorrectable errors, to different cache line addresses. *
2150 * If all the UCEs were to the same cache line address, then *
2151 * UCE_DIFF_ADDR will be 0. This allows the operating system to *
2152 * detect the case where a UCE error is read exclusively, and then *
2153 * written back by the processor. If the bit is 0, it indicates that *
2154 * no information has been lost about UCEs on other cache lines. In *
2155 * particular, partial writes do a read modify write of the cache *
2156 * line. A UCE read error will be set when the cache line is read, *
2157 * and a UCE write error will occur when the cache line is written *
2158 * back, but the UCE_DIFF_ADDR will not be set. *
2160 ************************************************************************/
2165 #ifdef LITTLE_ENDIAN
2167 typedef union md_mem_error_u {
2168 bdrkreg_t md_mem_error_regval;
2170 bdrkreg_t me_reserved_5 : 3;
2171 bdrkreg_t me_address : 30;
2172 bdrkreg_t me_reserved_4 : 7;
2173 bdrkreg_t me_bad_syn : 8;
2174 bdrkreg_t me_reserved_3 : 4;
2175 bdrkreg_t me_read_ce : 2;
2176 bdrkreg_t me_reserved_2 : 2;
2177 bdrkreg_t me_write_uce : 2;
2178 bdrkreg_t me_reserved_1 : 2;
2179 bdrkreg_t me_read_uce : 2;
2180 bdrkreg_t me_reserved : 1;
2181 bdrkreg_t me_uce_diff_addr : 1;
2182 } md_mem_error_fld_s;
2187 typedef union md_mem_error_u {
2188 bdrkreg_t md_mem_error_regval;
2190 bdrkreg_t me_uce_diff_addr : 1;
2191 bdrkreg_t me_reserved : 1;
2192 bdrkreg_t me_read_uce : 2;
2193 bdrkreg_t me_reserved_1 : 2;
2194 bdrkreg_t me_write_uce : 2;
2195 bdrkreg_t me_reserved_2 : 2;
2196 bdrkreg_t me_read_ce : 2;
2197 bdrkreg_t me_reserved_3 : 4;
2198 bdrkreg_t me_bad_syn : 8;
2199 bdrkreg_t me_reserved_4 : 7;
2200 bdrkreg_t me_address : 30;
2201 bdrkreg_t me_reserved_5 : 3;
2202 } md_mem_error_fld_s;
2210 /************************************************************************
2212 * Description: Contains information on read memory errors (both *
2213 * correctable and uncorrectable) and write memory errors (always *
2214 * uncorrectable). The errors are prioritized as follows: *
2215 * highest: uncorrectable read error (READ_UCE) *
2216 * middle: write error (WRITE_UCE) *
2217 * lowest: correctable read error (READ_CE) *
2218 * Each type of error maintains a two-bit valid/overrun field *
2219 * (READ_UCE, WRITE_UCE, or READ_CE). Bit 0 of each two-bit field *
2220 * corresponds to the valid bit, and bit 1 of each two-bit field *
2221 * corresponds to the overrun bit. *
2222 * The rule for the valid bit is that it gets set whenever that error *
2223 * occurs, regardless of whether a higher priority error has occurred. *
2224 * The rule for the overrun bit is that it gets set whenever we are *
2225 * unable to record the address information for this particular *
2226 * error, due to a previous error of the same or higher priority. *
2227 * Note that the syndrome and address information always corresponds *
2228 * to the earliest, highest priority error. *
2229 * Finally, the UCE_DIFF_ADDR bit is set whenever there have been *
2230 * several uncorrectable errors, to different cache line addresses. *
2231 * If all the UCEs were to the same cache line address, then *
2232 * UCE_DIFF_ADDR will be 0. This allows the operating system to *
2233 * detect the case where a UCE error is read exclusively, and then *
2234 * written back by the processor. If the bit is 0, it indicates that *
2235 * no information has been lost about UCEs on other cache lines. In *
2236 * particular, partial writes do a read modify write of the cache *
2237 * line. A UCE read error will be set when the cache line is read, *
2238 * and a UCE write error will occur when the cache line is written *
2239 * back, but the UCE_DIFF_ADDR will not be set. *
2241 ************************************************************************/
2246 #ifdef LITTLE_ENDIAN
2248 typedef union md_mem_error_clr_u {
2249 bdrkreg_t md_mem_error_clr_regval;
2251 bdrkreg_t mec_reserved_5 : 3;
2252 bdrkreg_t mec_address : 30;
2253 bdrkreg_t mec_reserved_4 : 7;
2254 bdrkreg_t mec_bad_syn : 8;
2255 bdrkreg_t mec_reserved_3 : 4;
2256 bdrkreg_t mec_read_ce : 2;
2257 bdrkreg_t mec_reserved_2 : 2;
2258 bdrkreg_t mec_write_uce : 2;
2259 bdrkreg_t mec_reserved_1 : 2;
2260 bdrkreg_t mec_read_uce : 2;
2261 bdrkreg_t mec_reserved : 1;
2262 bdrkreg_t mec_uce_diff_addr : 1;
2263 } md_mem_error_clr_fld_s;
2264 } md_mem_error_clr_u_t;
2268 typedef union md_mem_error_clr_u {
2269 bdrkreg_t md_mem_error_clr_regval;
2271 bdrkreg_t mec_uce_diff_addr : 1;
2272 bdrkreg_t mec_reserved : 1;
2273 bdrkreg_t mec_read_uce : 2;
2274 bdrkreg_t mec_reserved_1 : 2;
2275 bdrkreg_t mec_write_uce : 2;
2276 bdrkreg_t mec_reserved_2 : 2;
2277 bdrkreg_t mec_read_ce : 2;
2278 bdrkreg_t mec_reserved_3 : 4;
2279 bdrkreg_t mec_bad_syn : 8;
2280 bdrkreg_t mec_reserved_4 : 7;
2281 bdrkreg_t mec_address : 30;
2282 bdrkreg_t mec_reserved_5 : 3;
2283 } md_mem_error_clr_fld_s;
2284 } md_mem_error_clr_u_t;
2291 /************************************************************************
2293 * Contains one-quarter of the error memory line failing BIST. *
2295 ************************************************************************/
2300 #ifdef LITTLE_ENDIAN
2302 typedef union md_bist_mb_err_data_0_u {
2303 bdrkreg_t md_bist_mb_err_data_0_regval;
2305 bdrkreg_t bmed0_mb_er_d : 36;
2306 bdrkreg_t bmed0_reserved : 28;
2307 } md_bist_mb_err_data_0_fld_s;
2308 } md_bist_mb_err_data_0_u_t;
2312 typedef union md_bist_mb_err_data_0_u {
2313 bdrkreg_t md_bist_mb_err_data_0_regval;
2315 bdrkreg_t bmed0_reserved : 28;
2316 bdrkreg_t bmed0_mb_er_d : 36;
2317 } md_bist_mb_err_data_0_fld_s;
2318 } md_bist_mb_err_data_0_u_t;
2325 /************************************************************************
2327 * Contains one-quarter of the error memory line failing BIST. *
2329 ************************************************************************/
2334 #ifdef LITTLE_ENDIAN
2336 typedef union md_bist_mb_err_data_1_u {
2337 bdrkreg_t md_bist_mb_err_data_1_regval;
2339 bdrkreg_t bmed1_mb_er_d : 36;
2340 bdrkreg_t bmed1_reserved : 28;
2341 } md_bist_mb_err_data_1_fld_s;
2342 } md_bist_mb_err_data_1_u_t;
2346 typedef union md_bist_mb_err_data_1_u {
2347 bdrkreg_t md_bist_mb_err_data_1_regval;
2349 bdrkreg_t bmed1_reserved : 28;
2350 bdrkreg_t bmed1_mb_er_d : 36;
2351 } md_bist_mb_err_data_1_fld_s;
2352 } md_bist_mb_err_data_1_u_t;
2359 /************************************************************************
2361 * Contains one-quarter of the error memory line failing BIST. *
2363 ************************************************************************/
2368 #ifdef LITTLE_ENDIAN
2370 typedef union md_bist_mb_err_data_2_u {
2371 bdrkreg_t md_bist_mb_err_data_2_regval;
2373 bdrkreg_t bmed2_mb_er_d : 36;
2374 bdrkreg_t bmed2_reserved : 28;
2375 } md_bist_mb_err_data_2_fld_s;
2376 } md_bist_mb_err_data_2_u_t;
2380 typedef union md_bist_mb_err_data_2_u {
2381 bdrkreg_t md_bist_mb_err_data_2_regval;
2383 bdrkreg_t bmed2_reserved : 28;
2384 bdrkreg_t bmed2_mb_er_d : 36;
2385 } md_bist_mb_err_data_2_fld_s;
2386 } md_bist_mb_err_data_2_u_t;
2393 /************************************************************************
2395 * Contains one-quarter of the error memory line failing BIST. *
2397 ************************************************************************/
2402 #ifdef LITTLE_ENDIAN
2404 typedef union md_bist_mb_err_data_3_u {
2405 bdrkreg_t md_bist_mb_err_data_3_regval;
2407 bdrkreg_t bmed3_mb_er_d : 36;
2408 bdrkreg_t bmed3_reserved : 28;
2409 } md_bist_mb_err_data_3_fld_s;
2410 } md_bist_mb_err_data_3_u_t;
2414 typedef union md_bist_mb_err_data_3_u {
2415 bdrkreg_t md_bist_mb_err_data_3_regval;
2417 bdrkreg_t bmed3_reserved : 28;
2418 bdrkreg_t bmed3_mb_er_d : 36;
2419 } md_bist_mb_err_data_3_fld_s;
2420 } md_bist_mb_err_data_3_u_t;
2427 /************************************************************************
2429 * Contains 1 bit that allow the selection of MB debug information *
2430 * at the debug port (see the design specification for the available *
2431 * debug information). *
2433 ************************************************************************/
2438 #ifdef LITTLE_ENDIAN
2440 typedef union md_mb_debug_u {
2441 bdrkreg_t md_mb_debug_regval;
2443 bdrkreg_t md_mb_debug_sel : 1;
2444 bdrkreg_t md_reserved : 63;
2445 } md_mb_debug_fld_s;
2450 typedef union md_mb_debug_u {
2451 bdrkreg_t md_mb_debug_regval;
2453 bdrkreg_t md_reserved : 63;
2454 bdrkreg_t md_mb_debug_sel : 1;
2455 } md_mb_debug_fld_s;
2465 #endif /* __ASSEMBLY__ */
2467 /************************************************************************
2469 * MAKE ALL ADDITIONS AFTER THIS LINE *
2471 ************************************************************************/
2476 #endif /* _ASM_IA64_SN_SN1_HUBMD_H */
projects / linux-flexiantxendom0-3.2.10.git / blob