include/asm-ia64/sn/sn1/hublb.h

   1 /* $Id$
   2  *
   3  * This file is subject to the terms and conditions of the GNU General Public
   4  * License.  See the file "COPYING" in the main directory of this archive
   5  * for more details.
   6  *
   7  * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
   8  */
   9
  10 /************************************************************************
  11  *                                                                      *
  12  *      WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!      *
  13  *                                                                      *
  14  * This file is created by an automated script. Any (minimal) changes   *
  15  * made manually to this  file should be made with care.                *
  16  *                                                                      *
  17  *               MAKE ALL ADDITIONS TO THE END OF THIS FILE             *
  18  *                                                                      *
  19  ************************************************************************/
  20
  21
  22 #ifndef _ASM_IA64_SN_SN1_HUBLB_H
  23 #define _ASM_IA64_SN_SN1_HUBLB_H
  24
  25
  26 #define    LB_REV_ID                 0x00600000    /*
  27                                                     * Bedrock Revision
  28                                                     * and ID
  29                                                     */
  30
  31
  32
  33 #define    LB_CPU_PERMISSION         0x00604000    /*
  34                                                     * CPU PIO access
  35                                                     * permission bits
  36                                                     */
  37
  38
  39
  40 #define    LB_CPU_PERM_OVRRD         0x00604008    /*
  41                                                     * CPU PIO access
  42                                                     * permission bit
  43                                                     * override
  44                                                     */
  45
  46
  47
  48 #define    LB_IO_PERMISSION          0x00604010    /*
  49                                                     * IO PIO access
  50                                                     * permission bits
  51                                                     */
  52
  53
  54
  55 #define    LB_SOFT_RESET             0x00604018    /*
  56                                                     * Soft reset the
  57                                                     * Bedrock chip
  58                                                     */
  59
  60
  61
  62 #define    LB_REGION_PRESENT         0x00604020    /*
  63                                                     * Regions Present for
  64                                                     * Invalidates
  65                                                     */
  66
  67
  68
  69 #define    LB_NODES_ABSENT           0x00604028    /*
  70                                                     * Nodes Absent for
  71                                                     * Invalidates
  72                                                     */
  73
  74
  75
  76 #define    LB_MICROLAN_CTL           0x00604030    /*
  77                                                     * Microlan Control
  78                                                     * (NIC)
  79                                                     */
  80
  81
  82
  83 #define    LB_ERROR_BITS             0x00604040    /*
  84                                                     * Local Block error
  85                                                     * bits
  86                                                     */
  87
  88
  89
  90 #define    LB_ERROR_MASK_CLR         0x00604048    /*
  91                                                     * Bit mask write to
  92                                                     * clear error bits
  93                                                     */
  94
  95
  96
  97 #define    LB_ERROR_HDR1             0x00604050    /*
  98                                                     * Source, Suppl and
  99                                                     * Cmd fields
 100                                                     */
 101
 102
 103
 104 #define    LB_ERROR_HDR2             0x00604058    /*
 105                                                     * Address field from
 106                                                     * first error
 107                                                     */
 108
 109
 110
 111 #define    LB_ERROR_DATA             0x00604060    /*
 112                                                     * Data flit (if any)
 113                                                     * from first error
 114                                                     */
 115
 116
 117
 118 #define    LB_DEBUG_SELECT           0x00604100    /*
 119                                                     * Choice of debug
 120                                                     * signals from chip
 121                                                     */
 122
 123
 124
 125 #define    LB_DEBUG_PINS             0x00604108    /*
 126                                                     * Value on the chip's
 127                                                     * debug pins
 128                                                     */
 129
 130
 131
 132 #define    LB_RT_LOCAL_CTRL          0x00604200    /*
 133                                                     * Local generation of
 134                                                     * real-time clock
 135                                                     */
 136
 137
 138
 139 #define    LB_RT_FILTER_CTRL         0x00604208    /*
 140                                                     * Control of
 141                                                     * filtering of global
 142                                                     * clock
 143                                                     */
 144
 145
 146
 147 #define    LB_SCRATCH_REG0           0x00608000    /* Scratch Register 0     */
 148
 149
 150
 151 #define    LB_SCRATCH_REG1           0x00608008    /* Scratch Register 1     */
 152
 153
 154
 155 #define    LB_SCRATCH_REG2           0x00608010    /* Scratch Register 2     */
 156
 157
 158
 159 #define    LB_SCRATCH_REG3           0x00608018    /* Scratch Register 3     */
 160
 161
 162
 163 #define    LB_SCRATCH_REG4           0x00608020    /* Scratch Register 4     */
 164
 165
 166
 167 #define    LB_SCRATCH_REG0_WZ        0x00608040    /*
 168                                                     * Scratch Register 0
 169                                                     * (WZ alias)
 170                                                     */
 171
 172
 173
 174 #define    LB_SCRATCH_REG1_WZ        0x00608048    /*
 175                                                     * Scratch Register 1
 176                                                     * (WZ alias)
 177                                                     */
 178
 179
 180
 181 #define    LB_SCRATCH_REG2_WZ        0x00608050    /*
 182                                                     * Scratch Register 2
 183                                                     * (WZ alias)
 184                                                     */
 185
 186
 187
 188 #define    LB_SCRATCH_REG3_RZ        0x00608058    /*
 189                                                     * Scratch Register 3
 190                                                     * (RZ alias)
 191                                                     */
 192
 193
 194
 195 #define    LB_SCRATCH_REG4_RZ        0x00608060    /*
 196                                                     * Scratch Register 4
 197                                                     * (RZ alias)
 198                                                     */
 199
 200
 201
 202 #define    LB_VECTOR_PARMS           0x0060C000    /*
 203                                                     * Vector PIO
 204                                                     * parameters
 205                                                     */
 206
 207
 208
 209 #define    LB_VECTOR_ROUTE           0x0060C008    /*
 210                                                     * Vector PIO Vector
 211                                                     * Route
 212                                                     */
 213
 214
 215
 216 #define    LB_VECTOR_DATA            0x0060C010    /*
 217                                                     * Vector PIO Write
 218                                                     * Data
 219                                                     */
 220
 221
 222
 223 #define    LB_VECTOR_STATUS          0x0060C020    /*
 224                                                     * Vector PIO Return
 225                                                     * Status
 226                                                     */
 227
 228
 229
 230 #define    LB_VECTOR_RETURN          0x0060C028    /*
 231                                                     * Vector PIO Return
 232                                                     * Route
 233                                                     */
 234
 235
 236
 237 #define    LB_VECTOR_READ_DATA       0x0060C030    /*
 238                                                     * Vector PIO Read
 239                                                     * Data
 240                                                     */
 241
 242
 243
 244 #define    LB_VECTOR_STATUS_CLEAR    0x0060C038    /*
 245                                                     * Clear Vector PIO
 246                                                     * Return Status
 247                                                     */
 248
 249
 250
 251
 252
 253 #ifndef __ASSEMBLY__
 254
 255 /************************************************************************
 256  *                                                                      *
 257  * Description:  This register contains information that allows         *
 258  * exploratory software to probe for chip type. This is also the        *
 259  * register that sets this node's ID and the size of each region        *
 260  * (which affects the maximum possible system size). IBM assigns the    *
 261  * values for the REVISION, PART_NUMBER and MANUFACTURER fields, in     *
 262  * accordance with the IEEE 1149.1 standard; SGI is not at liberty to   *
 263  * unilaterally change the values of these fields.                      *
 264  *  .                                                                   *
 265  *                                                                      *
 266  ************************************************************************/
 267
 268
 269
 270
 271 #ifdef LITTLE_ENDIAN
 272
 273 typedef union lb_rev_id_u {
 274         bdrkreg_t       lb_rev_id_regval;
 275         struct  {
 276                 bdrkreg_t       ri_reserved_2             :      1;
 277                 bdrkreg_t       ri_manufacturer           :     11;
 278                 bdrkreg_t       ri_part_number            :     16;
 279                 bdrkreg_t       ri_revision               :      4;
 280                 bdrkreg_t       ri_node_id                :      8;
 281                 bdrkreg_t       ri_reserved_1             :      6;
 282                 bdrkreg_t       ri_region_size            :      2;
 283                 bdrkreg_t       ri_reserved               :     16;
 284         } lb_rev_id_fld_s;
 285 } lb_rev_id_u_t;
 286
 287 #else
 288
 289 typedef union lb_rev_id_u {
 290         bdrkreg_t       lb_rev_id_regval;
 291         struct  {
 292                 bdrkreg_t       ri_reserved               :     16;
 293                 bdrkreg_t       ri_region_size            :      2;
 294                 bdrkreg_t       ri_reserved_1             :      6;
 295                 bdrkreg_t       ri_node_id                :      8;
 296                 bdrkreg_t       ri_revision               :      4;
 297                 bdrkreg_t       ri_part_number            :     16;
 298                 bdrkreg_t       ri_manufacturer           :     11;
 299                 bdrkreg_t       ri_reserved_2             :      1;
 300         } lb_rev_id_fld_s;
 301 } lb_rev_id_u_t;
 302
 303 #endif
 304
 305
 306
 307
 308 /************************************************************************
 309  *                                                                      *
 310  *  This register contains the PI-access-rights bit-vector for the      *
 311  * LB, NI, XB and MD portions of the Bedrock local register space. If   *
 312  * a bit in the bit-vector is set, the region corresponding to that     *
 313  * bit has read/write permission on the LB, NI, XB and MD local         *
 314  * registers. If the bit is clear, that region has no write access to   *
 315  * the local registers and no read access if the read will cause any    *
 316  * state change. If a write or a read with side effects is attempted    *
 317  * by a PI in a region for which access is restricted, the LB will      *
 318  * not perform the operation and will send back a reply which           *
 319  * indicates an error.                                                  *
 320  *                                                                      *
 321  ************************************************************************/
 322
 323
 324
 325
 326 typedef union lb_cpu_permission_u {
 327         bdrkreg_t       lb_cpu_permission_regval;
 328         struct  {
 329                 bdrkreg_t       cp_cpu_access             :     64;
 330         } lb_cpu_permission_fld_s;
 331 } lb_cpu_permission_u_t;
 332
 333
 334
 335
 336 /************************************************************************
 337  *                                                                      *
 338  *  A write to this register of the 64-bit value "SGIrules" will        *
 339  * cause the bit in the LB_CPU_PROTECT register corresponding to the    *
 340  * region of the requester to be set.                                   *
 341  *                                                                      *
 342  ************************************************************************/
 343
 344
 345
 346
 347 typedef union lb_cpu_perm_ovrrd_u {
 348         bdrkreg_t       lb_cpu_perm_ovrrd_regval;
 349         struct  {
 350                 bdrkreg_t       cpo_cpu_perm_ovr          :     64;
 351         } lb_cpu_perm_ovrrd_fld_s;
 352 } lb_cpu_perm_ovrrd_u_t;
 353
 354
 355
 356
 357 /************************************************************************
 358  *                                                                      *
 359  *  This register contains the II-access-rights bit-vector for the      *
 360  * LB, NI, XB and MD portions of the Bedrock local register space. If   *
 361  * a bit in the bit-vector is set, the region corresponding to that     *
 362  * bit has read/write permission on the LB, NI, XB and MD local         *
 363  * registers. If the bit is clear, then that region has no write        *
 364  * access to the local registers and no read access if the read         *
 365  * results in any state change. If a write or a read with side          *
 366  * effects is attempted by an II in a region for which access is        *
 367  * restricted, the LB will not perform the operation and will send      *
 368  * back a reply which indicates an error.                               *
 369  *                                                                      *
 370  ************************************************************************/
 371
 372
 373
 374
 375 typedef union lb_io_permission_u {
 376         bdrkreg_t       lb_io_permission_regval;
 377         struct  {
 378                 bdrkreg_t       ip_io_permission          :     64;
 379         } lb_io_permission_fld_s;
 380 } lb_io_permission_u_t;
 381
 382
 383
 384
 385 /************************************************************************
 386  *                                                                      *
 387  *  A write to this bit resets the Bedrock chip with a soft reset.      *
 388  *                                                                      *
 389  ************************************************************************/
 390
 391
 392
 393
 394 #ifdef LITTLE_ENDIAN
 395
 396 typedef union lb_soft_reset_u {
 397         bdrkreg_t       lb_soft_reset_regval;
 398         struct  {
 399                 bdrkreg_t       sr_soft_reset             :      1;
 400                 bdrkreg_t       sr_reserved               :     63;
 401         } lb_soft_reset_fld_s;
 402 } lb_soft_reset_u_t;
 403
 404 #else
 405
 406 typedef union lb_soft_reset_u {
 407         bdrkreg_t       lb_soft_reset_regval;
 408         struct  {
 409                 bdrkreg_t       sr_reserved               :     63;
 410                 bdrkreg_t       sr_soft_reset             :      1;
 411         } lb_soft_reset_fld_s;
 412 } lb_soft_reset_u_t;
 413
 414 #endif
 415
 416
 417
 418 /************************************************************************
 419  *                                                                      *
 420  *  This register indicates which regions are present and capable of    *
 421  * receiving an invalidate (INVAL) request. The LB samples this         *
 422  * register at the start of processing each LINVAL. When an LINVAL      *
 423  * indicates that a particular PI unit might hold a shared copy of a    *
 424  * cache block but this PI is in a region which is not present (i.e.,   *
 425  * its bit in LB_REGION_PRESENT is clear), then the LB sends an IVACK   *
 426  * reply packet on behalf of this PI. The REGION_SIZE field in the      *
 427  * LB_REV_ID register determines the number of nodes per region (and    *
 428  * hence, the number of PI units which share a common bit in the        *
 429  * LB_REGION_PRESENT register).                                         *
 430  *                                                                      *
 431  ************************************************************************/
 432
 433
 434
 435
 436 typedef union lb_region_present_u {
 437         bdrkreg_t       lb_region_present_regval;
 438         struct  {
 439                 bdrkreg_t       rp_present_bits           :     64;
 440         } lb_region_present_fld_s;
 441 } lb_region_present_u_t;
 442
 443
 444
 445
 446 /************************************************************************
 447  *                                                                      *
 448  * Description:  This register indicates which nodes are absent and     *
 449  * not capable of receiving an invalidate (INVAL) request. The LB       *
 450  * samples this register at the start of processing each LINVAL. When   *
 451  * an LINVAL indicates that a particular PI unit might hold a shared    *
 452  * copy of a cache block but this PI unit's node is not present         *
 453  * (i.e., its node ID is listed in the LB_NODES_ABSENT register),       *
 454  * then the LB sends an IVACK reply packet on behalf of this PI.        *
 455  *                                                                      *
 456  *                                                                      *
 457  ************************************************************************/
 458
 459
 460
 461
 462 #ifdef LITTLE_ENDIAN
 463
 464 typedef union lb_nodes_absent_u {
 465         bdrkreg_t       lb_nodes_absent_regval;
 466         struct  {
 467                 bdrkreg_t       na_node_0                 :      8;
 468                 bdrkreg_t       na_reserved_3             :      7;
 469                 bdrkreg_t       na_node_0_valid           :      1;
 470                 bdrkreg_t       na_node_1                 :      8;
 471                 bdrkreg_t       na_reserved_2             :      7;
 472                 bdrkreg_t       na_node_1_valid           :      1;
 473                 bdrkreg_t       na_node_2                 :      8;
 474                 bdrkreg_t       na_reserved_1             :      7;
 475                 bdrkreg_t       na_node_2_valid           :      1;
 476                 bdrkreg_t       na_node_3                 :      8;
 477                 bdrkreg_t       na_reserved               :      7;
 478                 bdrkreg_t       na_node_3_valid           :      1;
 479         } lb_nodes_absent_fld_s;
 480 } lb_nodes_absent_u_t;
 481
 482 #else
 483
 484 typedef union lb_nodes_absent_u {
 485         bdrkreg_t       lb_nodes_absent_regval;
 486         struct  {
 487                 bdrkreg_t       na_node_3_valid           :      1;
 488                 bdrkreg_t       na_reserved               :      7;
 489                 bdrkreg_t       na_node_3                 :      8;
 490                 bdrkreg_t       na_node_2_valid           :      1;
 491                 bdrkreg_t       na_reserved_1             :      7;
 492                 bdrkreg_t       na_node_2                 :      8;
 493                 bdrkreg_t       na_node_1_valid           :      1;
 494                 bdrkreg_t       na_reserved_2             :      7;
 495                 bdrkreg_t       na_node_1                 :      8;
 496                 bdrkreg_t       na_node_0_valid           :      1;
 497                 bdrkreg_t       na_reserved_3             :      7;
 498                 bdrkreg_t       na_node_0                 :      8;
 499         } lb_nodes_absent_fld_s;
 500 } lb_nodes_absent_u_t;
 501
 502 #endif
 503
 504
 505
 506
 507 /************************************************************************
 508  *                                                                      *
 509  *  This register provides access to the Number-In-a-Can add-only       *
 510  * serial PROM that is used to store node board serial number and       *
 511  * configuration information. (Refer to NIC datasheet Dallas 1990A      *
 512  * that is viewable at                                                  *
 513  * URL::http://www.dalsemi.com/DocControl/PDFs/pdfindex.html). Data     *
 514  * comes from this interface LSB first.                                 *
 515  *                                                                      *
 516  ************************************************************************/
 517
 518
 519
 520
 521 #ifdef LITTLE_ENDIAN
 522
 523 typedef union lb_microlan_ctl_u {
 524         bdrkreg_t       lb_microlan_ctl_regval;
 525         struct  {
 526                 bdrkreg_t       mc_rd_data                :      1;
 527                 bdrkreg_t       mc_done                   :      1;
 528                 bdrkreg_t       mc_sample                 :      8;
 529                 bdrkreg_t       mc_pulse                  :     10;
 530                 bdrkreg_t       mc_clkdiv_phi0            :      7;
 531                 bdrkreg_t       mc_clkdiv_phi1            :      7;
 532                 bdrkreg_t       mc_reserved               :     30;
 533         } lb_microlan_ctl_fld_s;
 534 } lb_microlan_ctl_u_t;
 535
 536 #else
 537
 538 typedef union lb_microlan_ctl_u {
 539         bdrkreg_t       lb_microlan_ctl_regval;
 540         struct  {
 541                 bdrkreg_t       mc_reserved               :     30;
 542                 bdrkreg_t       mc_clkdiv_phi1            :      7;
 543                 bdrkreg_t       mc_clkdiv_phi0            :      7;
 544                 bdrkreg_t       mc_pulse                  :     10;
 545                 bdrkreg_t       mc_sample                 :      8;
 546                 bdrkreg_t       mc_done                   :      1;
 547                 bdrkreg_t       mc_rd_data                :      1;
 548         } lb_microlan_ctl_fld_s;
 549 } lb_microlan_ctl_u_t;
 550
 551 #endif
 552
 553
 554
 555
 556 /************************************************************************
 557  *                                                                      *
 558  * Description:  This register contains the LB error status bits.       *
 559  * Whenever a particular type of error occurs, the LB sets its bit in   *
 560  * this register so that software will be aware that such an event      *
 561  * has happened. Reads from this register are non-destructive and the   *
 562  * contents of this register remain intact across reset operations.     *
 563  * Whenever any of these bits is set, the LB will assert its            *
 564  * interrupt request output signals that go to the PI units.            *
 565  *  Software can simulate the occurrence of an error by first writing   *
 566  * appropriate values into the LB_ERROR_HDR1, LB_ERROR_HDR2 and         *
 567  * LB_ERROR_DATA registers, and then writing to the LB_ERROR_BITS       *
 568  * register to set the error bits in a particular way. Setting one or   *
 569  * more error bits will cause the LB to interrupt a processor and       *
 570  * invoke error-handling software.                                      *
 571  *                                                                      *
 572  ************************************************************************/
 573
 574
 575
 576
 577 #ifdef LITTLE_ENDIAN
 578
 579 typedef union lb_error_bits_u {
 580         bdrkreg_t       lb_error_bits_regval;
 581         struct  {
 582                 bdrkreg_t       eb_rq_bad_cmd             :      1;
 583                 bdrkreg_t       eb_rp_bad_cmd             :      1;
 584                 bdrkreg_t       eb_rq_short               :      1;
 585                 bdrkreg_t       eb_rp_short               :      1;
 586                 bdrkreg_t       eb_rq_long                :      1;
 587                 bdrkreg_t       eb_rp_long                :      1;
 588                 bdrkreg_t       eb_rq_bad_data            :      1;
 589                 bdrkreg_t       eb_rp_bad_data            :      1;
 590                 bdrkreg_t       eb_rq_bad_addr            :      1;
 591                 bdrkreg_t       eb_rq_bad_linval          :      1;
 592                 bdrkreg_t       eb_gclk_drop              :      1;
 593                 bdrkreg_t       eb_reserved               :     53;
 594         } lb_error_bits_fld_s;
 595 } lb_error_bits_u_t;
 596
 597 #else
 598
 599 typedef union lb_error_bits_u {
 600         bdrkreg_t       lb_error_bits_regval;
 601         struct  {
 602                 bdrkreg_t       eb_reserved               :     53;
 603                 bdrkreg_t       eb_gclk_drop              :      1;
 604                 bdrkreg_t       eb_rq_bad_linval          :      1;
 605                 bdrkreg_t       eb_rq_bad_addr            :      1;
 606                 bdrkreg_t       eb_rp_bad_data            :      1;
 607                 bdrkreg_t       eb_rq_bad_data            :      1;
 608                 bdrkreg_t       eb_rp_long                :      1;
 609                 bdrkreg_t       eb_rq_long                :      1;
 610                 bdrkreg_t       eb_rp_short               :      1;
 611                 bdrkreg_t       eb_rq_short               :      1;
 612                 bdrkreg_t       eb_rp_bad_cmd             :      1;
 613                 bdrkreg_t       eb_rq_bad_cmd             :      1;
 614         } lb_error_bits_fld_s;
 615 } lb_error_bits_u_t;
 616
 617 #endif
 618
 619
 620
 621
 622 /************************************************************************
 623  *                                                                      *
 624  *  This register lets software clear some of the bits in the           *
 625  * LB_ERROR_BITS register without affecting other bits.  Essentially,   *
 626  * it provides bit mask functionality. When software writes to the      *
 627  * LB_ERROR_MASK_CLR register, the bits which are set in the data       *
 628  * value indicate which bits are to be cleared in LB_ERROR_BITS. If a   *
 629  * bit is clear in the data value written to the LB_ERROR_MASK_CLR      *
 630  * register, then its corresponding bit in the LB_ERROR_BITS register   *
 631  * is not affected. Hence, software can atomically clear any subset     *
 632  * of the error bits in the LB_ERROR_BITS register.                     *
 633  *                                                                      *
 634  ************************************************************************/
 635
 636
 637
 638
 639 #ifdef LITTLE_ENDIAN
 640
 641 typedef union lb_error_mask_clr_u {
 642         bdrkreg_t       lb_error_mask_clr_regval;
 643         struct  {
 644                 bdrkreg_t       emc_clr_rq_bad_cmd        :      1;
 645                 bdrkreg_t       emc_clr_rp_bad_cmd        :      1;
 646                 bdrkreg_t       emc_clr_rq_short          :      1;
 647                 bdrkreg_t       emc_clr_rp_short          :      1;
 648                 bdrkreg_t       emc_clr_rq_long           :      1;
 649                 bdrkreg_t       emc_clr_rp_long           :      1;
 650                 bdrkreg_t       emc_clr_rq_bad_data       :      1;
 651                 bdrkreg_t       emc_clr_rp_bad_data       :      1;
 652                 bdrkreg_t       emc_clr_rq_bad_addr       :      1;
 653                 bdrkreg_t       emc_clr_rq_bad_linval     :      1;
 654                 bdrkreg_t       emc_clr_gclk_drop         :      1;
 655                 bdrkreg_t       emc_reserved              :     53;
 656         } lb_error_mask_clr_fld_s;
 657 } lb_error_mask_clr_u_t;
 658
 659 #else
 660
 661 typedef union lb_error_mask_clr_u {
 662         bdrkreg_t       lb_error_mask_clr_regval;
 663         struct  {
 664                 bdrkreg_t       emc_reserved              :     53;
 665                 bdrkreg_t       emc_clr_gclk_drop         :      1;
 666                 bdrkreg_t       emc_clr_rq_bad_linval     :      1;
 667                 bdrkreg_t       emc_clr_rq_bad_addr       :      1;
 668                 bdrkreg_t       emc_clr_rp_bad_data       :      1;
 669                 bdrkreg_t       emc_clr_rq_bad_data       :      1;
 670                 bdrkreg_t       emc_clr_rp_long           :      1;
 671                 bdrkreg_t       emc_clr_rq_long           :      1;
 672                 bdrkreg_t       emc_clr_rp_short          :      1;
 673                 bdrkreg_t       emc_clr_rq_short          :      1;
 674                 bdrkreg_t       emc_clr_rp_bad_cmd        :      1;
 675                 bdrkreg_t       emc_clr_rq_bad_cmd        :      1;
 676         } lb_error_mask_clr_fld_s;
 677 } lb_error_mask_clr_u_t;
 678
 679 #endif
 680
 681
 682
 683
 684 /************************************************************************
 685  *                                                                      *
 686  *  If the LB detects an error when VALID==0 in the LB_ERROR_HDR1       *
 687  * register, then it saves the contents of the offending packet's       *
 688  * header flit in the LB_ERROR_HDR1 and LB_ERROR_HDR2 registers, sets   *
 689  * the VALID bit in LB_ERROR_HDR1 and clears the OVERRUN bit in         *
 690  * LB_ERROR_HDR1 (and it will also set the corresponding bit in the     *
 691  * LB_ERROR_BITS register). The ERR_TYPE field indicates specifically   *
 692  * what kind of error occurred.  Its encoding corresponds to the bit    *
 693  * positions in the LB_ERROR_BITS register (e.g., ERR_TYPE==5           *
 694  * indicates a RP_LONG error).  If an error (of any type except         *
 695  * GCLK_DROP) subsequently happens while VALID==1, then the LB sets     *
 696  * the OVERRUN bit in LB_ERROR_HDR1. This register is not relevant      *
 697  * when a GCLK_DROP error occurs; the LB does not even attempt to       *
 698  * change the ERR_TYPE, VALID or OVERRUN field when a GCLK_DROP error   *
 699  * happens.                                                             *
 700  *                                                                      *
 701  ************************************************************************/
 702
 703
 704
 705
 706 #ifdef LITTLE_ENDIAN
 707
 708 typedef union lb_error_hdr1_u {
 709         bdrkreg_t       lb_error_hdr1_regval;
 710         struct  {
 711                 bdrkreg_t       eh_command                :      7;
 712                 bdrkreg_t       eh_reserved_5             :      1;
 713                 bdrkreg_t       eh_suppl                  :     11;
 714                 bdrkreg_t       eh_reserved_4             :      1;
 715                 bdrkreg_t       eh_source                 :     11;
 716                 bdrkreg_t       eh_reserved_3             :      1;
 717                 bdrkreg_t       eh_err_type               :      4;
 718                 bdrkreg_t       eh_reserved_2             :      4;
 719                 bdrkreg_t       eh_overrun                :      1;
 720                 bdrkreg_t       eh_reserved_1             :      3;
 721                 bdrkreg_t       eh_valid                  :      1;
 722                 bdrkreg_t       eh_reserved               :     19;
 723         } lb_error_hdr1_fld_s;
 724 } lb_error_hdr1_u_t;
 725
 726 #else
 727
 728 typedef union lb_error_hdr1_u {
 729         bdrkreg_t       lb_error_hdr1_regval;
 730         struct  {
 731                 bdrkreg_t       eh_reserved               :     19;
 732                 bdrkreg_t       eh_valid                  :      1;
 733                 bdrkreg_t       eh_reserved_1             :      3;
 734                 bdrkreg_t       eh_overrun                :      1;
 735                 bdrkreg_t       eh_reserved_2             :      4;
 736                 bdrkreg_t       eh_err_type               :      4;
 737                 bdrkreg_t       eh_reserved_3             :      1;
 738                 bdrkreg_t       eh_source                 :     11;
 739                 bdrkreg_t       eh_reserved_4             :      1;
 740                 bdrkreg_t       eh_suppl                  :     11;
 741                 bdrkreg_t       eh_reserved_5             :      1;
 742                 bdrkreg_t       eh_command                :      7;
 743         } lb_error_hdr1_fld_s;
 744 } lb_error_hdr1_u_t;
 745
 746 #endif
 747
 748
 749
 750
 751 /************************************************************************
 752  *                                                                      *
 753  *  Contents of the Address field from header flit of first packet      *
 754  * that causes an error. This register is not relevant when a           *
 755  * GCLK_DROP error occurs.                                              *
 756  *                                                                      *
 757  ************************************************************************/
 758
 759
 760
 761
 762 #ifdef LITTLE_ENDIAN
 763
 764 typedef union lb_error_hdr2_u {
 765         bdrkreg_t       lb_error_hdr2_regval;
 766         struct  {
 767                 bdrkreg_t       eh_address                :     38;
 768                 bdrkreg_t       eh_reserved               :     26;
 769         } lb_error_hdr2_fld_s;
 770 } lb_error_hdr2_u_t;
 771
 772 #else
 773
 774 typedef union lb_error_hdr2_u {
 775         bdrkreg_t       lb_error_hdr2_regval;
 776         struct  {
 777                 bdrkreg_t       eh_reserved               :     26;
 778                 bdrkreg_t       eh_address                :     38;
 779         } lb_error_hdr2_fld_s;
 780 } lb_error_hdr2_u_t;
 781
 782 #endif
 783
 784
 785
 786
 787 /************************************************************************
 788  *                                                                      *
 789  * Description:  This register accompanies the LB_ERROR_HDR1 and        *
 790  * LB_ERROR_HDR2 registers.  The LB updates the value in this           *
 791  * register when an incoming packet with a data flit causes an error    *
 792  * while VALID==0 in the LB_ERROR_HDR1 register.  This register         *
 793  * retains the contents of the data flit from the incoming packet       *
 794  * that caused the error. This register is relevant for the following   *
 795  * types of errors:                                                     *
 796  * <UL >                                                                *
 797  * <UL >                                                                *
 798  * <UL >                                                                *
 799  * <UL >                                                                *
 800  * <UL >                                                                *
 801  * <LI >RQ_BAD_LINVAL for a LINVAL request.                             *
 802  * <LI >RQ_BAD_ADDR for a normal or vector PIO request.                 *
 803  * <LI >RP_BAD_DATA for a vector PIO reply.                             *
 804  * <LI >RQ_BAD DATA for an incoming request with data.                  *
 805  * <LI >RP_LONG for a vector PIO reply.                                 *
 806  * <LI >RQ_LONG for an incoming request with expected data.             *
 807  * <BLOCKQUOTE >                                                        *
 808  * In the case of RQ_BAD_LINVAL, the register retains the 64-bit data   *
 809  * value that followed the header flit.  In the case of RQ_BAD_ADDR     *
 810  * or RQ_BAD_DATA, the register retains the incoming packet's 64-bit    *
 811  * data value (i.e., 2nd flit in the packet for a normal PIO write or   *
 812  * an LINVAL, 3rd flit for a vector PIO read or write). In the case     *
 813  * of RP_BAD_DATA, the register retains the 64-bit data value in the    *
 814  * 3rd flit of the packet. When a RP_LONG or RQ_LONG error occurs,      *
 815  * the LB loads the LB_ERROR_DATA register with the contents of the     *
 816  * expected data flit (i.e., the 3rd flit in the packet for a vector    *
 817  * PIO request or reply, the 2nd flit for other packets), if any. The   *
 818  * contents of the LB_ERROR_DATA register are undefined after a         *
 819  * RP_SHORT, RQ_SHORT, RP_BAD_CMD or RQ_BAD_CMD error. The contents     *
 820  * of the LB_ERROR_DATA register are also undefined after an incoming   *
 821  * normal PIO read request which encounters a RQ_LONG error.            *
 822  *                                                                      *
 823  ************************************************************************/
 824
 825
 826
 827
 828 typedef union lb_error_data_u {
 829         bdrkreg_t       lb_error_data_regval;
 830         struct  {
 831                 bdrkreg_t       ed_data                   :     64;
 832         } lb_error_data_fld_s;
 833 } lb_error_data_u_t;
 834
 835
 836
 837
 838 /************************************************************************
 839  *                                                                      *
 840  *  This register enables software to control what internal Bedrock     *
 841  * signals are visible on the chip's debug pins. The LB provides the    *
 842  * 6-bit value in this register to Bedrock's DEBUG unit. The JTAG       *
 843  * unit provides a similar 6-bit selection input to the DEBUG unit,     *
 844  * along with another signal that tells the DEBUG unit whether to use   *
 845  * the selection signal from the LB or the JTAG unit. For a             *
 846  * description of the menu of choices for debug signals, refer to the   *
 847  * documentation for the DEBUG unit.                                    *
 848  *                                                                      *
 849  ************************************************************************/
 850
 851
 852
 853
 854 #ifdef LITTLE_ENDIAN
 855
 856 typedef union lb_debug_select_u {
 857         bdrkreg_t       lb_debug_select_regval;
 858         struct  {
 859                 bdrkreg_t       ds_debug_sel              :      6;
 860                 bdrkreg_t       ds_reserved               :     58;
 861         } lb_debug_select_fld_s;
 862 } lb_debug_select_u_t;
 863
 864 #else
 865
 866 typedef union lb_debug_select_u {
 867         bdrkreg_t       lb_debug_select_regval;
 868         struct  {
 869                 bdrkreg_t       ds_reserved               :     58;
 870                 bdrkreg_t       ds_debug_sel              :      6;
 871         } lb_debug_select_fld_s;
 872 } lb_debug_select_u_t;
 873
 874 #endif
 875
 876
 877
 878
 879 /************************************************************************
 880  *                                                                      *
 881  *  A PIO read from this register returns the 32-bit value that is      *
 882  * currently on the Bedrock chip's debug pins. This register allows     *
 883  * software to observe debug pin output values which do not change      *
 884  * frequently (i.e., they remain constant over a period of many         *
 885  * cycles).                                                             *
 886  *                                                                      *
 887  ************************************************************************/
 888
 889
 890
 891
 892 #ifdef LITTLE_ENDIAN
 893
 894 typedef union lb_debug_pins_u {
 895         bdrkreg_t       lb_debug_pins_regval;
 896         struct  {
 897                 bdrkreg_t       dp_debug_pins             :     32;
 898                 bdrkreg_t       dp_reserved               :     32;
 899         } lb_debug_pins_fld_s;
 900 } lb_debug_pins_u_t;
 901
 902 #else
 903
 904 typedef union lb_debug_pins_u {
 905         bdrkreg_t       lb_debug_pins_regval;
 906         struct  {
 907                 bdrkreg_t       dp_reserved               :     32;
 908                 bdrkreg_t       dp_debug_pins             :     32;
 909         } lb_debug_pins_fld_s;
 910 } lb_debug_pins_u_t;
 911
 912 #endif
 913
 914
 915
 916
 917 /************************************************************************
 918  *                                                                      *
 919  *  The LB unit provides the PI0 and PI1 units with a real-time clock   *
 920  * signal. The LB can generate this signal itself, based on the         *
 921  * Bedrock chip's system clock which the LB receives as an input.       *
 922  * Alternatively, the LB can filter a global clock signal which it      *
 923  * receives as an input and provide the filtered version to PI0 and     *
 924  * PI1. The user can program the LB_RT_LOCAL_CTRL register to choose    *
 925  * the source of the real-time clock. If the user chooses to generate   *
 926  * the real-time clock internally within the LB, then the user can      *
 927  * specify the period for the real-time clock signal.                   *
 928  *                                                                      *
 929  ************************************************************************/
 930
 931
 932
 933
 934 #ifdef LITTLE_ENDIAN
 935
 936 typedef union lb_rt_local_ctrl_u {
 937         bdrkreg_t       lb_rt_local_ctrl_regval;
 938         struct  {
 939                 bdrkreg_t       rlc_gclk_enable           :      1;
 940                 bdrkreg_t       rlc_reserved_4            :      3;
 941                 bdrkreg_t       rlc_max_count             :     10;
 942                 bdrkreg_t       rlc_reserved_3            :      2;
 943                 bdrkreg_t       rlc_gclk_counter          :     10;
 944                 bdrkreg_t       rlc_reserved_2            :      2;
 945                 bdrkreg_t       rlc_gclk                  :      1;
 946                 bdrkreg_t       rlc_reserved_1            :      3;
 947                 bdrkreg_t       rlc_use_internal          :      1;
 948                 bdrkreg_t       rlc_reserved              :     31;
 949         } lb_rt_local_ctrl_fld_s;
 950 } lb_rt_local_ctrl_u_t;
 951
 952 #else
 953
 954 typedef union lb_rt_local_ctrl_u {
 955         bdrkreg_t       lb_rt_local_ctrl_regval;
 956         struct  {
 957                 bdrkreg_t       rlc_reserved              :     31;
 958                 bdrkreg_t       rlc_use_internal          :      1;
 959                 bdrkreg_t       rlc_reserved_1            :      3;
 960                 bdrkreg_t       rlc_gclk                  :      1;
 961                 bdrkreg_t       rlc_reserved_2            :      2;
 962                 bdrkreg_t       rlc_gclk_counter          :     10;
 963                 bdrkreg_t       rlc_reserved_3            :      2;
 964                 bdrkreg_t       rlc_max_count             :     10;
 965                 bdrkreg_t       rlc_reserved_4            :      3;
 966                 bdrkreg_t       rlc_gclk_enable           :      1;
 967         } lb_rt_local_ctrl_fld_s;
 968 } lb_rt_local_ctrl_u_t;
 969
 970 #endif
 971
 972
 973
 974
 975 /************************************************************************
 976  *                                                                      *
 977  *  When the value of the USE_INTERNAL field in the LB_RT_LOCAL_CTRL    *
 978  * register is 0, the LB filters an incoming global clock signal and    *
 979  * provides the result to PI0 and PI1 for their real-time clock         *
 980  * inputs. The LB can perform either simple filtering or complex        *
 981  * filtering, depending on the value of the MASK_ENABLE bit. For the    *
 982  * simple filtering option, the LB merely removes glitches from the     *
 983  * incoming global clock; if the global clock goes high (or low) for    *
 984  * only a single cycle, the LB considers it to be a glitch and does     *
 985  * not pass it through to PI0 and PI1. For the complex filtering        *
 986  * option, the LB expects positive edges on the incoming global clock   *
 987  * to be spaced at fairly regular intervals and it looks for them at    *
 988  * these times; the LB keeps track of unexpected or missing positive    *
 989  * edges, and it generates an edge itself whenever the incoming         *
 990  * global clock apparently misses an edge. For each filtering option,   *
 991  * the real-time clock which the LB provides to PI0 and PI1 is not      *
 992  * necessarily a square wave; when a positive edge happens, the         *
 993  * real-time clock stays high for (2*MAX_COUNT+1-OFFSET)/2 cycles of    *
 994  * the LB's system clock, and then is low until the next positive       *
 995  * edge.                                                                *
 996  *                                                                      *
 997  ************************************************************************/
 998
 999
1000
1001
1002 #ifdef LITTLE_ENDIAN
1003
1004 typedef union lb_rt_filter_ctrl_u {
1005         bdrkreg_t       lb_rt_filter_ctrl_regval;
1006         struct  {
1007                 bdrkreg_t       rfc_offset                :      5;
1008                 bdrkreg_t       rfc_reserved_4            :      3;
1009                 bdrkreg_t       rfc_mask_counter          :     12;
1010                 bdrkreg_t       rfc_mask_enable           :      1;
1011                 bdrkreg_t       rfc_reserved_3            :      3;
1012                 bdrkreg_t       rfc_dropout_counter       :     10;
1013                 bdrkreg_t       rfc_reserved_2            :      2;
1014                 bdrkreg_t       rfc_dropout_thresh        :     10;
1015                 bdrkreg_t       rfc_reserved_1            :      2;
1016                 bdrkreg_t       rfc_error_counter         :     10;
1017                 bdrkreg_t       rfc_reserved              :      6;
1018         } lb_rt_filter_ctrl_fld_s;
1019 } lb_rt_filter_ctrl_u_t;
1020
1021 #else
1022
1023 typedef union lb_rt_filter_ctrl_u {
1024         bdrkreg_t       lb_rt_filter_ctrl_regval;
1025         struct  {
1026                 bdrkreg_t       rfc_reserved              :      6;
1027                 bdrkreg_t       rfc_error_counter         :     10;
1028                 bdrkreg_t       rfc_reserved_1            :      2;
1029                 bdrkreg_t       rfc_dropout_thresh        :     10;
1030                 bdrkreg_t       rfc_reserved_2            :      2;
1031                 bdrkreg_t       rfc_dropout_counter       :     10;
1032                 bdrkreg_t       rfc_reserved_3            :      3;
1033                 bdrkreg_t       rfc_mask_enable           :      1;
1034                 bdrkreg_t       rfc_mask_counter          :     12;
1035                 bdrkreg_t       rfc_reserved_4            :      3;
1036                 bdrkreg_t       rfc_offset                :      5;
1037         } lb_rt_filter_ctrl_fld_s;
1038 } lb_rt_filter_ctrl_u_t;
1039
1040 #endif
1041
1042
1043
1044
1045 /************************************************************************
1046  *                                                                      *
1047  *  This register is a scratch register that is reset to 0x0. At the    *
1048  * normal address, the register is a simple storage location. At the    *
1049  * Write-If-Zero address, the register accepts a new value from a       *
1050  * write operation only if the current value is zero.                   *
1051  *                                                                      *
1052  ************************************************************************/
1053
1054
1055
1056
1057 typedef union lb_scratch_reg0_u {
1058         bdrkreg_t       lb_scratch_reg0_regval;
1059         struct  {
1060                 bdrkreg_t       sr_scratch_bits           :     64;
1061         } lb_scratch_reg0_fld_s;
1062 } lb_scratch_reg0_u_t;
1063
1064
1065
1066
1067 /************************************************************************
1068  *                                                                      *
1069  *  These registers are scratch registers that are not reset. At a      *
1070  * register's normal address, it is a simple storage location. At a     *
1071  * register's Write-If-Zero address, it accepts a new value from a      *
1072  * write operation only if the current value is zero.                   *
1073  *                                                                      *
1074  ************************************************************************/
1075
1076
1077
1078
1079 typedef union lb_scratch_reg1_u {
1080         bdrkreg_t       lb_scratch_reg1_regval;
1081         struct  {
1082                 bdrkreg_t       sr_scratch_bits           :     64;
1083         } lb_scratch_reg1_fld_s;
1084 } lb_scratch_reg1_u_t;
1085
1086
1087
1088
1089 /************************************************************************
1090  *                                                                      *
1091  *  These registers are scratch registers that are not reset. At a      *
1092  * register's normal address, it is a simple storage location. At a     *
1093  * register's Write-If-Zero address, it accepts a new value from a      *
1094  * write operation only if the current value is zero.                   *
1095  *                                                                      *
1096  ************************************************************************/
1097
1098
1099
1100
1101 typedef union lb_scratch_reg2_u {
1102         bdrkreg_t       lb_scratch_reg2_regval;
1103         struct  {
1104                 bdrkreg_t       sr_scratch_bits           :     64;
1105         } lb_scratch_reg2_fld_s;
1106 } lb_scratch_reg2_u_t;
1107
1108
1109
1110
1111 /************************************************************************
1112  *                                                                      *
1113  *  These one-bit registers are scratch registers. At a register's      *
1114  * normal address, it is a simple storage location. At a register's     *
1115  * Read-Set-If-Zero address, it returns the original contents and       *
1116  * sets the bit if the original value is zero.                          *
1117  *                                                                      *
1118  ************************************************************************/
1119
1120
1121
1122
1123 #ifdef LITTLE_ENDIAN
1124
1125 typedef union lb_scratch_reg3_u {
1126         bdrkreg_t       lb_scratch_reg3_regval;
1127         struct  {
1128                 bdrkreg_t       sr_scratch_bit            :      1;
1129                 bdrkreg_t       sr_reserved               :     63;
1130         } lb_scratch_reg3_fld_s;
1131 } lb_scratch_reg3_u_t;
1132
1133 #else
1134
1135 typedef union lb_scratch_reg3_u {
1136         bdrkreg_t       lb_scratch_reg3_regval;
1137         struct  {
1138                 bdrkreg_t       sr_reserved               :     63;
1139                 bdrkreg_t       sr_scratch_bit            :      1;
1140         } lb_scratch_reg3_fld_s;
1141 } lb_scratch_reg3_u_t;
1142
1143 #endif
1144
1145
1146
1147
1148 /************************************************************************
1149  *                                                                      *
1150  *  These one-bit registers are scratch registers. At a register's      *
1151  * normal address, it is a simple storage location. At a register's     *
1152  * Read-Set-If-Zero address, it returns the original contents and       *
1153  * sets the bit if the original value is zero.                          *
1154  *                                                                      *
1155  ************************************************************************/
1156
1157
1158
1159
1160 #ifdef LITTLE_ENDIAN
1161
1162 typedef union lb_scratch_reg4_u {
1163         bdrkreg_t       lb_scratch_reg4_regval;
1164         struct  {
1165                 bdrkreg_t       sr_scratch_bit            :      1;
1166                 bdrkreg_t       sr_reserved               :     63;
1167         } lb_scratch_reg4_fld_s;
1168 } lb_scratch_reg4_u_t;
1169
1170 #else
1171
1172 typedef union lb_scratch_reg4_u {
1173         bdrkreg_t       lb_scratch_reg4_regval;
1174         struct  {
1175                 bdrkreg_t       sr_reserved               :     63;
1176                 bdrkreg_t       sr_scratch_bit            :      1;
1177         } lb_scratch_reg4_fld_s;
1178 } lb_scratch_reg4_u_t;
1179
1180 #endif
1181
1182
1183
1184
1185 /************************************************************************
1186  *                                                                      *
1187  *  This register is a scratch register that is reset to 0x0. At the    *
1188  * normal address, the register is a simple storage location. At the    *
1189  * Write-If-Zero address, the register accepts a new value from a       *
1190  * write operation only if the current value is zero.                   *
1191  *                                                                      *
1192  ************************************************************************/
1193
1194
1195
1196
1197 typedef union lb_scratch_reg0_wz_u {
1198         bdrkreg_t       lb_scratch_reg0_wz_regval;
1199         struct  {
1200                 bdrkreg_t       srw_scratch_bits          :     64;
1201         } lb_scratch_reg0_wz_fld_s;
1202 } lb_scratch_reg0_wz_u_t;
1203
1204
1205
1206
1207 /************************************************************************
1208  *                                                                      *
1209  *  These registers are scratch registers that are not reset. At a      *
1210  * register's normal address, it is a simple storage location. At a     *
1211  * register's Write-If-Zero address, it accepts a new value from a      *
1212  * write operation only if the current value is zero.                   *
1213  *                                                                      *
1214  ************************************************************************/
1215
1216
1217
1218
1219 typedef union lb_scratch_reg1_wz_u {
1220         bdrkreg_t       lb_scratch_reg1_wz_regval;
1221         struct  {
1222                 bdrkreg_t       srw_scratch_bits          :     64;
1223         } lb_scratch_reg1_wz_fld_s;
1224 } lb_scratch_reg1_wz_u_t;
1225
1226
1227
1228
1229 /************************************************************************
1230  *                                                                      *
1231  *  These registers are scratch registers that are not reset. At a      *
1232  * register's normal address, it is a simple storage location. At a     *
1233  * register's Write-If-Zero address, it accepts a new value from a      *
1234  * write operation only if the current value is zero.                   *
1235  *                                                                      *
1236  ************************************************************************/
1237
1238
1239
1240
1241 typedef union lb_scratch_reg2_wz_u {
1242         bdrkreg_t       lb_scratch_reg2_wz_regval;
1243         struct  {
1244                 bdrkreg_t       srw_scratch_bits          :     64;
1245         } lb_scratch_reg2_wz_fld_s;
1246 } lb_scratch_reg2_wz_u_t;
1247
1248
1249
1250
1251 /************************************************************************
1252  *                                                                      *
1253  *  These one-bit registers are scratch registers. At a register's      *
1254  * normal address, it is a simple storage location. At a register's     *
1255  * Read-Set-If-Zero address, it returns the original contents and       *
1256  * sets the bit if the original value is zero.                          *
1257  *                                                                      *
1258  ************************************************************************/
1259
1260
1261
1262
1263 #ifdef LITTLE_ENDIAN
1264
1265 typedef union lb_scratch_reg3_rz_u {
1266         bdrkreg_t       lb_scratch_reg3_rz_regval;
1267         struct  {
1268                 bdrkreg_t       srr_scratch_bit           :      1;
1269                 bdrkreg_t       srr_reserved              :     63;
1270         } lb_scratch_reg3_rz_fld_s;
1271 } lb_scratch_reg3_rz_u_t;
1272
1273 #else
1274
1275 typedef union lb_scratch_reg3_rz_u {
1276         bdrkreg_t       lb_scratch_reg3_rz_regval;
1277         struct  {
1278                 bdrkreg_t       srr_reserved              :     63;
1279                 bdrkreg_t       srr_scratch_bit           :      1;
1280         } lb_scratch_reg3_rz_fld_s;
1281 } lb_scratch_reg3_rz_u_t;
1282
1283 #endif
1284
1285
1286
1287
1288 /************************************************************************
1289  *                                                                      *
1290  *  These one-bit registers are scratch registers. At a register's      *
1291  * normal address, it is a simple storage location. At a register's     *
1292  * Read-Set-If-Zero address, it returns the original contents and       *
1293  * sets the bit if the original value is zero.                          *
1294  *                                                                      *
1295  ************************************************************************/
1296
1297
1298
1299
1300 #ifdef LITTLE_ENDIAN
1301
1302 typedef union lb_scratch_reg4_rz_u {
1303         bdrkreg_t       lb_scratch_reg4_rz_regval;
1304         struct  {
1305                 bdrkreg_t       srr_scratch_bit           :      1;
1306                 bdrkreg_t       srr_reserved              :     63;
1307         } lb_scratch_reg4_rz_fld_s;
1308 } lb_scratch_reg4_rz_u_t;
1309
1310 #else
1311
1312 typedef union lb_scratch_reg4_rz_u {
1313         bdrkreg_t       lb_scratch_reg4_rz_regval;
1314         struct  {
1315                 bdrkreg_t       srr_reserved              :     63;
1316                 bdrkreg_t       srr_scratch_bit           :      1;
1317         } lb_scratch_reg4_rz_fld_s;
1318 } lb_scratch_reg4_rz_u_t;
1319
1320 #endif
1321
1322
1323
1324
1325 /************************************************************************
1326  *                                                                      *
1327  * Description:  This register contains vector PIO parameters. A        *
1328  * write to this register triggers the LB to send out a vector PIO      *
1329  * request packet. Immediately after servicing a write request to the   *
1330  * LB_VECTOR_PARMS register, the LB sends back a reply (i.e., the LB    *
1331  * doesn't wait for the vector PIO operation to finish first). Three    *
1332  * LB registers provide the contents for an outgoing vector PIO         *
1333  * request packet. Software should wait until the BUSY bit in           *
1334  * LB_VECTOR_PARMS is clear and then initialize all three of these      *
1335  * registers before initiating a vector PIO operation. The three        *
1336  * vector PIO registers are:                                            *
1337  * LB_VECTOR_ROUTE                                                      *
1338  * LB_VECTOR_DATA                                                       *
1339  * LB_VECTOR_PARMS (should be written last)                             *
1340  *                                                                      *
1341  ************************************************************************/
1342
1343
1344
1345
1346 #ifdef LITTLE_ENDIAN
1347
1348 typedef union lb_vector_parms_u {
1349         bdrkreg_t       lb_vector_parms_regval;
1350         struct  {
1351                 bdrkreg_t       vp_type                   :      1;
1352                 bdrkreg_t       vp_reserved_2             :      2;
1353                 bdrkreg_t       vp_address                :     21;
1354                 bdrkreg_t       vp_reserved_1             :      8;
1355                 bdrkreg_t       vp_write_id               :      8;
1356                 bdrkreg_t       vp_pio_id                 :     11;
1357                 bdrkreg_t       vp_reserved               :     12;
1358                 bdrkreg_t       vp_busy                   :      1;
1359         } lb_vector_parms_fld_s;
1360 } lb_vector_parms_u_t;
1361
1362 #else
1363
1364 typedef union lb_vector_parms_u {
1365         bdrkreg_t       lb_vector_parms_regval;
1366         struct  {
1367                 bdrkreg_t       vp_busy                   :      1;
1368                 bdrkreg_t       vp_reserved               :     12;
1369                 bdrkreg_t       vp_pio_id                 :     11;
1370                 bdrkreg_t       vp_write_id               :      8;
1371                 bdrkreg_t       vp_reserved_1             :      8;
1372                 bdrkreg_t       vp_address                :     21;
1373                 bdrkreg_t       vp_reserved_2             :      2;
1374                 bdrkreg_t       vp_type                   :      1;
1375         } lb_vector_parms_fld_s;
1376 } lb_vector_parms_u_t;
1377
1378 #endif
1379
1380
1381
1382
1383 /************************************************************************
1384  *                                                                      *
1385  *  This register contains the vector PIO route. This is one of the 3   *
1386  * vector PIO control registers.                                        *
1387  *                                                                      *
1388  ************************************************************************/
1389
1390
1391
1392
1393 typedef union lb_vector_route_u {
1394         bdrkreg_t       lb_vector_route_regval;
1395         struct  {
1396                 bdrkreg_t       vr_vector                 :     64;
1397         } lb_vector_route_fld_s;
1398 } lb_vector_route_u_t;
1399
1400
1401
1402
1403 /************************************************************************
1404  *                                                                      *
1405  *  This register contains the vector PIO write data. This is one of    *
1406  * the 3 vector PIO control registers. The contents of this register    *
1407  * also provide the data value to be sent in outgoing vector PIO read   *
1408  * requests and vector PIO write replies.                               *
1409  *                                                                      *
1410  ************************************************************************/
1411
1412
1413
1414
1415 typedef union lb_vector_data_u {
1416         bdrkreg_t       lb_vector_data_regval;
1417         struct  {
1418                 bdrkreg_t       vd_write_data             :     64;
1419         } lb_vector_data_fld_s;
1420 } lb_vector_data_u_t;
1421
1422
1423
1424
1425 /************************************************************************
1426  *                                                                      *
1427  * Description:  This register contains the vector PIO return status.   *
1428  * Software should clear this register before launching a vector PIO    *
1429  * request from the LB. The LB will not modify this register's value    *
1430  * if an incoming reply packet encounters any kind of error. If an      *
1431  * incoming reply packet does not encounter an error but the            *
1432  * STATUS_VALID bit is already set, then the LB sets the OVERRUN bit    *
1433  * and leaves the other fields unchanged. The LB updates the values     *
1434  * of the SOURCE, PIO_ID, WRITE_ID, ADDRESS and TYPE fields only if     *
1435  * an incoming vector PIO reply packet does not encounter an error      *
1436  * and the STATUS_VALID bit is clear; at the same time, the LB sets     *
1437  * the STATUS_VALID bit and will also update the LB_VECTOR_RETURN and   *
1438  * LB_VECTOR_READ_DATA registers.                                       *
1439  *                                                                      *
1440  *                                                                      *
1441  ************************************************************************/
1442
1443
1444
1445
1446 #ifdef LITTLE_ENDIAN
1447
1448 typedef union lb_vector_status_u {
1449         bdrkreg_t       lb_vector_status_regval;
1450         struct  {
1451                 bdrkreg_t       vs_type                   :      3;
1452                 bdrkreg_t       vs_address                :     21;
1453                 bdrkreg_t       vs_reserved               :      8;
1454                 bdrkreg_t       vs_write_id               :      8;
1455                 bdrkreg_t       vs_pio_id                 :     11;
1456                 bdrkreg_t       vs_source                 :     11;
1457                 bdrkreg_t       vs_overrun                :      1;
1458                 bdrkreg_t       vs_status_valid           :      1;
1459         } lb_vector_status_fld_s;
1460 } lb_vector_status_u_t;
1461
1462 #else
1463
1464 typedef union lb_vector_status_u {
1465         bdrkreg_t       lb_vector_status_regval;
1466         struct  {
1467                 bdrkreg_t       vs_status_valid           :      1;
1468                 bdrkreg_t       vs_overrun                :      1;
1469                 bdrkreg_t       vs_source                 :     11;
1470                 bdrkreg_t       vs_pio_id                 :     11;
1471                 bdrkreg_t       vs_write_id               :      8;
1472                 bdrkreg_t       vs_reserved               :      8;
1473                 bdrkreg_t       vs_address                :     21;
1474                 bdrkreg_t       vs_type                   :      3;
1475         } lb_vector_status_fld_s;
1476 } lb_vector_status_u_t;
1477
1478 #endif
1479
1480
1481
1482
1483 /************************************************************************
1484  *                                                                      *
1485  *  This register contains the return vector PIO route. The LB will     *
1486  * not modify this register's value if an incoming reply packet         *
1487  * encounters any kind of error. The LB also will not modify this       *
1488  * register's value if the STATUS_VALID bit in the LB_VECTOR_STATUS     *
1489  * register is set when it receives an incoming vector PIO reply. The   *
1490  * LB stores an incoming vector PIO reply packet's vector route flit    *
1491  * in this register only if the packet does not encounter an error      *
1492  * and the STATUS_VALID bit is clear.                                   *
1493  *                                                                      *
1494  ************************************************************************/
1495
1496
1497
1498
1499 typedef union lb_vector_return_u {
1500         bdrkreg_t       lb_vector_return_regval;
1501         struct  {
1502                 bdrkreg_t       vr_return_vector          :     64;
1503         } lb_vector_return_fld_s;
1504 } lb_vector_return_u_t;
1505
1506
1507
1508
1509 /************************************************************************
1510  *                                                                      *
1511  *  This register contains the vector PIO read data, if any. The LB     *
1512  * will not modify this register's value if an incoming reply packet    *
1513  * encounters any kind of error. The LB also will not modify this       *
1514  * register's value if the STATUS_VALID bit in the LB_VECTOR_STATUS     *
1515  * register is set when it receives an incoming vector PIO reply. The   *
1516  * LB stores an incoming vector PIO reply packet's data flit in this    *
1517  * register only if the packet does not encounter an error and the      *
1518  * STATUS_VALID bit is clear.                                           *
1519  *                                                                      *
1520  ************************************************************************/
1521
1522
1523
1524
1525 typedef union lb_vector_read_data_u {
1526         bdrkreg_t       lb_vector_read_data_regval;
1527         struct  {
1528                 bdrkreg_t       vrd_read_data             :     64;
1529         } lb_vector_read_data_fld_s;
1530 } lb_vector_read_data_u_t;
1531
1532
1533
1534
1535 /************************************************************************
1536  *                                                                      *
1537  * Description:  This register contains the vector PIO return status.   *
1538  * Software should clear this register before launching a vector PIO    *
1539  * request from the LB. The LB will not modify this register's value    *
1540  * if an incoming reply packet encounters any kind of error. If an      *
1541  * incoming reply packet does not encounter an error but the            *
1542  * STATUS_VALID bit is already set, then the LB sets the OVERRUN bit    *
1543  * and leaves the other fields unchanged. The LB updates the values     *
1544  * of the SOURCE, PIO_ID, WRITE_ID, ADDRESS and TYPE fields only if     *
1545  * an incoming vector PIO reply packet does not encounter an error      *
1546  * and the STATUS_VALID bit is clear; at the same time, the LB sets     *
1547  * the STATUS_VALID bit and will also update the LB_VECTOR_RETURN and   *
1548  * LB_VECTOR_READ_DATA registers.                                       *
1549  *                                                                      *
1550  *                                                                      *
1551  ************************************************************************/
1552
1553
1554
1555
1556 #ifdef LITTLE_ENDIAN
1557
1558 typedef union lb_vector_status_clear_u {
1559         bdrkreg_t       lb_vector_status_clear_regval;
1560         struct  {
1561                 bdrkreg_t       vsc_type                  :      3;
1562                 bdrkreg_t       vsc_address               :     21;
1563                 bdrkreg_t       vsc_reserved              :      8;
1564                 bdrkreg_t       vsc_write_id              :      8;
1565                 bdrkreg_t       vsc_pio_id                :     11;
1566                 bdrkreg_t       vsc_source                :     11;
1567                 bdrkreg_t       vsc_overrun               :      1;
1568                 bdrkreg_t       vsc_status_valid          :      1;
1569         } lb_vector_status_clear_fld_s;
1570 } lb_vector_status_clear_u_t;
1571
1572 #else
1573
1574 typedef union lb_vector_status_clear_u {
1575         bdrkreg_t       lb_vector_status_clear_regval;
1576         struct  {
1577                 bdrkreg_t       vsc_status_valid          :      1;
1578                 bdrkreg_t       vsc_overrun               :      1;
1579                 bdrkreg_t       vsc_source                :     11;
1580                 bdrkreg_t       vsc_pio_id                :     11;
1581                 bdrkreg_t       vsc_write_id              :      8;
1582                 bdrkreg_t       vsc_reserved              :      8;
1583                 bdrkreg_t       vsc_address               :     21;
1584                 bdrkreg_t       vsc_type                  :      3;
1585         } lb_vector_status_clear_fld_s;
1586 } lb_vector_status_clear_u_t;
1587
1588 #endif
1589
1590
1591
1592
1593
1594
1595 #endif /* __ASSEMBLY__ */
1596
1597 /************************************************************************
1598  *                                                                      *
1599  *               MAKE ALL ADDITIONS AFTER THIS LINE                     *
1600  *                                                                      *
1601  ************************************************************************/
1602
1603
1604
1605
1606
1607 #endif /* _ASM_IA64_SN_SN1_HUBLB_H */