2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2000,2002 Silicon Graphics, Inc. All rights reserved.
8 * Routines for PCI DMA mapping. See Documentation/DMA-mapping.txt for
9 * a description of how these routines should be used.
12 #include <linux/config.h>
13 #include <linux/types.h>
15 #include <linux/string.h>
16 #include <linux/pci.h>
17 #include <linux/slab.h>
18 #include <linux/devfs_fs_kernel.h>
19 #include <linux/module.h>
21 #include <asm/delay.h>
23 #include <asm/sn/sgi.h>
24 #include <asm/sn/io.h>
25 #include <asm/sn/invent.h>
26 #include <asm/sn/hcl.h>
27 #include <asm/sn/pci/pcibr.h>
28 #include <asm/sn/pci/pcibr_private.h>
29 #include <asm/sn/driver.h>
30 #include <asm/sn/types.h>
31 #include <asm/sn/alenlist.h>
32 #include <asm/sn/pci/pci_bus_cvlink.h>
33 #include <asm/sn/nag.h>
38 pciio_dmamap_t get_free_pciio_dmamap(devfs_handle_t);
39 void free_pciio_dmamap(pcibr_dmamap_t);
40 static struct sn_dma_maps_s *find_sn_dma_map(dma_addr_t, unsigned char);
45 extern devfs_handle_t busnum_to_pcibr_vhdl[];
46 extern nasid_t busnum_to_nid[];
47 extern void * busnum_to_atedmamaps[];
50 * get_free_pciio_dmamap - find and allocate an ATE
51 * @pci_bus: PCI bus to get an entry for
53 * Finds and allocates an ATE on the PCI bus specified
57 get_free_pciio_dmamap(devfs_handle_t pci_bus)
60 struct sn_dma_maps_s *sn_dma_map = NULL;
63 * Darn, we need to get the maps allocated for this bus.
65 for (i = 0; i < MAX_PCI_XWIDGET; i++) {
66 if (busnum_to_pcibr_vhdl[i] == pci_bus) {
67 sn_dma_map = busnum_to_atedmamaps[i];
72 * Now get a free dmamap entry from this list.
74 for (i = 0; i < MAX_ATE_MAPS; i++, sn_dma_map++) {
75 if (!sn_dma_map->dma_addr) {
76 sn_dma_map->dma_addr = -1;
77 return( (pciio_dmamap_t) sn_dma_map );
85 * free_pciio_dmamap - free an ATE
86 * @dma_map: ATE to free
88 * Frees the ATE specified by @dma_map.
91 free_pciio_dmamap(pcibr_dmamap_t dma_map)
93 struct sn_dma_maps_s *sn_dma_map;
95 sn_dma_map = (struct sn_dma_maps_s *) dma_map;
96 sn_dma_map->dma_addr = 0;
100 * find_sn_dma_map - find an ATE associated with @dma_addr and @busnum
101 * @dma_addr: DMA address to look for
102 * @busnum: PCI bus to look on
104 * Finds the ATE associated with @dma_addr and @busnum.
106 static struct sn_dma_maps_s *
107 find_sn_dma_map(dma_addr_t dma_addr, unsigned char busnum)
110 struct sn_dma_maps_s *sn_dma_map = NULL;
113 sn_dma_map = busnum_to_atedmamaps[busnum];
115 for (i = 0; i < MAX_ATE_MAPS; i++, sn_dma_map++) {
116 if (sn_dma_map->dma_addr == dma_addr) {
125 * sn_dma_sync - try to flush DMA buffers into the coherence domain
126 * @hwdev: device to flush
128 * This routine flushes all DMA buffers for the device into the II of
129 * the destination hub.
131 * NOTE!: this does not mean that the data is in the "coherence domain",
132 * but it is very close. In other words, this routine *does not work*
133 * as advertised due to hardware bugs. That said, it should be good enough for
137 sn_dma_sync(struct pci_dev *hwdev)
142 struct sn_device_sysdata *device_sysdata;
143 volatile unsigned long dummy;
146 * A DMA sync is supposed to ensure that
147 * all the DMA from a particular device
148 * is complete and coherent. We
150 * 1. flushing the write wuffers from Bridge
151 * 2. flushing the Xbow port.
152 * Unfortunately, this only gets the DMA transactions 'very close' to
153 * the coherence domain, but not quite in it.
155 device_sysdata = (struct sn_device_sysdata *)hwdev->sysdata;
156 dummy = (volatile unsigned long ) *device_sysdata->dma_buf_sync;
159 * For the Xbow port flush, we may be denied the request because
160 * someone else may be flushing the port .. try again.
162 while((volatile unsigned long ) *device_sysdata->xbow_buf_sync) {
169 * sn_pci_alloc_consistent - allocate memory for coherent DMA
170 * @hwdev: device to allocate for
171 * @size: size of the region
172 * @dma_handle: DMA (bus) address
174 * pci_alloc_consistent() returns a pointer to a memory region suitable for
175 * coherent DMA traffic to/from a PCI device. On SN platforms, this means
176 * that @dma_handle will have the %PCIIO_DMA_CMD flag set.
178 * This interface is usually used for "command" streams (e.g. the command
179 * queue for a SCSI controller). See Documentation/DMA-mapping.txt for
180 * more information. Note that this routine will always put a 32 bit
181 * DMA address into @dma_handle. This is because most devices
182 * that are capable of 64 bit PCI DMA transactions can't do 64 bit _coherent_
183 * DMAs, and unfortunately this interface has to cater to the LCD. Oh well.
185 * Also known as platform_pci_alloc_consistent() by the IA64 machvec code.
188 sn_pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle)
192 struct sn_device_sysdata *device_sysdata;
193 unsigned long phys_addr;
194 pciio_dmamap_t dma_map = 0;
195 struct sn_dma_maps_s *sn_dma_map;
199 /* We can't easily support < 32 bit devices */
200 if (IS_PCI32L(hwdev))
204 * Get hwgraph vertex for the device
206 device_sysdata = (struct sn_device_sysdata *) hwdev->sysdata;
207 vhdl = device_sysdata->vhdl;
210 * Allocate the memory. FIXME: if we're allocating for
211 * two devices on the same bus, we should at least try to
212 * allocate memory in the same 2 GB window to avoid using
213 * ATEs for the translation. See the comment above about the
214 * 32 bit requirement for this function.
216 if(!(cpuaddr = (void *)__get_free_pages(GFP_ATOMIC, get_order(size))))
219 memset(cpuaddr, 0, size); /* have to zero it out */
221 /* physical addr. of the memory we just got */
222 phys_addr = __pa(cpuaddr);
225 * This will try to use a Direct Map register to do the
226 * 32 bit DMA mapping, but it may not succeed if another
227 * device on the same bus is already mapped with different
228 * attributes or to a different memory region.
230 #ifdef CONFIG_IA64_SGI_SN1
231 *dma_handle = pciio_dmatrans_addr(vhdl, NULL, phys_addr, size,
234 #elif defined(CONFIG_IA64_SGI_SN2)
235 *dma_handle = pciio_dmatrans_addr(vhdl, NULL, phys_addr, size,
236 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
239 #error unsupported platform
243 * It is a 32 bit card and we cannot do direct mapping,
244 * so we try to use an ATE.
246 if (!(*dma_handle)) {
247 #ifdef CONFIG_IA64_SGI_SN1
248 dma_map = pciio_dmamap_alloc(vhdl, NULL, size,
251 #elif defined(CONFIG_IA64_SGI_SN2)
252 dma_map = pciio_dmamap_alloc(vhdl, NULL, size,
253 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
256 #error unsupported platform
259 printk(KERN_ERR "sn_pci_alloc_consistent: Unable to "
260 "allocate anymore 32 bit page map entries.\n");
263 *dma_handle = (dma_addr_t) pciio_dmamap_addr(dma_map,phys_addr,
265 sn_dma_map = (struct sn_dma_maps_s *)dma_map;
266 sn_dma_map->dma_addr = *dma_handle;
273 * sn_pci_free_consistent - free memory associated with coherent DMAable region
274 * @hwdev: device to free for
275 * @size: size to free
276 * @vaddr: kernel virtual address to free
277 * @dma_handle: DMA address associated with this region
279 * Frees the memory allocated by pci_alloc_consistent(). Also known
280 * as platform_pci_free_consistent() by the IA64 machvec code.
283 sn_pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle)
285 struct sn_dma_maps_s *sn_dma_map = NULL;
288 * Get the sn_dma_map entry.
290 if (IS_PCI32_MAPPED(dma_handle))
291 sn_dma_map = find_sn_dma_map(dma_handle, hwdev->bus->number);
294 * and free it if necessary...
297 pciio_dmamap_done((pciio_dmamap_t)sn_dma_map);
298 pciio_dmamap_free((pciio_dmamap_t)sn_dma_map);
299 sn_dma_map->dma_addr = (dma_addr_t)NULL;
301 free_pages((unsigned long) vaddr, get_order(size));
305 * sn_pci_map_sg - map a scatter-gather list for DMA
306 * @hwdev: device to map for
307 * @sg: scatterlist to map
308 * @nents: number of entries
309 * @direction: direction of the DMA transaction
311 * Maps each entry of @sg for DMA. Also known as platform_pci_map_sg by the
315 sn_pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction)
321 unsigned long phys_addr;
322 struct sn_device_sysdata *device_sysdata;
323 pciio_dmamap_t dma_map;
325 /* can't go anywhere w/o a direction in life */
326 if (direction == PCI_DMA_NONE)
330 * Get the hwgraph vertex for the device
332 device_sysdata = (struct sn_device_sysdata *) hwdev->sysdata;
333 vhdl = device_sysdata->vhdl;
336 * Setup a DMA address for each entry in the
339 for (i = 0; i < nents; i++, sg++) {
340 /* this catches incorrectly written drivers that
341 attempt to map scatterlists that they have
342 previously mapped. we print a warning and
343 continue, but the driver should be fixed */
344 switch (((u64)sg->dma_address) >> 60) {
348 /* This needs to be cleaned up at some point. */
349 NAG("A PCI driver (for device at%8s) has attempted to "
350 "map a scatterlist that was previously mapped at "
351 "%p - this is currently being worked around.\n",
352 hwdev->slot_name, (void *)sg->dma_address);
353 phys_addr = (u64)sg->dma_address & TO_PHYS_MASK;
356 default: /* not previously mapped, get the phys. addr */
357 phys_addr = __pa(sg->dma_address);
364 * Handle the most common case: 64 bit cards. This
365 * call should always succeed.
367 if (IS_PCIA64(hwdev)) {
368 dma_addr = pciio_dmatrans_addr(vhdl, NULL, phys_addr,
370 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
373 sg->dma_address = (char *)dma_addr;
378 * Handle 32-63 bit cards via direct mapping
380 if (IS_PCI32G(hwdev)) {
381 #ifdef CONFIG_IA64_SGI_SN1
382 dma_addr = pciio_dmatrans_addr(vhdl, NULL, phys_addr,
386 #elif defined(CONFIG_IA64_SGI_SN2)
387 dma_addr = pciio_dmatrans_addr(vhdl, NULL, phys_addr,
389 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
392 #error unsupported platform
395 * See if we got a direct map entry
398 sg->dma_address = (char *)dma_addr;
405 * It is a 32 bit card and we cannot do direct mapping,
409 #ifdef CONFIG_IA64_SGI_SN1
410 dma_map = pciio_dmamap_alloc(vhdl, NULL, sg->length,
413 #elif defined(CONFIG_IA64_SGI_SN2)
414 dma_map = pciio_dmamap_alloc(vhdl, NULL, sg->length,
415 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
418 #error unsupported platform
421 printk(KERN_ERR "sn_pci_map_sg: Unable to allocate "
422 "anymore 32 bit page map entries.\n");
425 dma_addr = pciio_dmamap_addr(dma_map, phys_addr, sg->length);
426 sg->dma_address = (char *)dma_addr;
427 sg->page = (struct page *)dma_map;
436 * sn_pci_unmap_sg - unmap a scatter-gather list
437 * @hwdev: device to unmap
438 * @sg: scatterlist to unmap
439 * @nents: number of scatterlist entries
440 * @direction: DMA direction
442 * Unmap a set of streaming mode DMA translations. Again, cpu read rules
443 * concerning calls here are the same as for pci_unmap_single() below. Also
444 * known as sn_pci_unmap_sg() by the IA64 machvec code.
447 sn_pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction)
450 struct sn_dma_maps_s *sn_dma_map;
452 /* can't go anywhere w/o a direction in life */
453 if (direction == PCI_DMA_NONE)
456 for (i = 0; i < nents; i++, sg++)
459 * We maintain the DMA Map pointer in sg->page if
460 * it is ever allocated.
463 sn_dma_map = (struct sn_dma_maps_s *)sg->page;
464 pciio_dmamap_done((pciio_dmamap_t)sn_dma_map);
465 pciio_dmamap_free((pciio_dmamap_t)sn_dma_map);
466 sn_dma_map->dma_addr = 0;
473 * sn_pci_map_single - map a single region for DMA
474 * @hwdev: device to map for
475 * @ptr: kernel virtual address of the region to map
476 * @size: size of the region
477 * @direction: DMA direction
479 * Map the region pointed to by @ptr for DMA and return the
480 * DMA address. Also known as platform_pci_map_single() by
481 * the IA64 machvec code.
483 * We map this to the one step pciio_dmamap_trans interface rather than
484 * the two step pciio_dmamap_alloc/pciio_dmamap_addr because we have
485 * no way of saving the dmamap handle from the alloc to later free
486 * (which is pretty much unacceptable).
488 * TODO: simplify our interface;
489 * get rid of dev_desc and vhdl (seems redundant given a pci_dev);
490 * figure out how to save dmamap handle so can use two step.
493 sn_pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction)
497 unsigned long phys_addr;
498 struct sn_device_sysdata *device_sysdata;
499 pciio_dmamap_t dma_map = NULL;
500 struct sn_dma_maps_s *sn_dma_map;
502 if (direction == PCI_DMA_NONE)
505 /* SN cannot support DMA addresses smaller than 32 bits. */
506 if (IS_PCI32L(hwdev))
510 * find vertex for the device
512 device_sysdata = (struct sn_device_sysdata *)hwdev->sysdata;
513 vhdl = device_sysdata->vhdl;
516 * Call our dmamap interface
519 phys_addr = __pa(ptr);
521 if (IS_PCIA64(hwdev)) {
522 /* This device supports 64 bit DMA addresses. */
523 dma_addr = pciio_dmatrans_addr(vhdl, NULL, phys_addr, size,
524 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
531 * Devices that support 32 bit to 63 bit DMA addresses get
532 * 32 bit DMA addresses.
534 * First try to get a 32 bit direct map register.
536 if (IS_PCI32G(hwdev)) {
537 #ifdef CONFIG_IA64_SGI_SN1
538 dma_addr = pciio_dmatrans_addr(vhdl, NULL, phys_addr, size,
541 #elif defined(CONFIG_IA64_SGI_SN2)
542 dma_addr = pciio_dmatrans_addr(vhdl, NULL, phys_addr, size,
543 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
546 #error unsupported platform
553 * It's a 32 bit card and we cannot do direct mapping so
554 * let's use the PMU instead.
557 #ifdef CONFIG_IA64_SGI_SN1
558 dma_map = pciio_dmamap_alloc(vhdl, NULL, size, PCIIO_BYTE_STREAM |
560 #elif defined(CONFIG_IA64_SGI_SN2)
561 dma_map = pciio_dmamap_alloc(vhdl, NULL, size,
562 ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
565 #error unsupported platform
569 printk(KERN_ERR "pci_map_single: Unable to allocate anymore "
570 "32 bit page map entries.\n");
574 dma_addr = (dma_addr_t) pciio_dmamap_addr(dma_map, phys_addr, size);
575 sn_dma_map = (struct sn_dma_maps_s *)dma_map;
576 sn_dma_map->dma_addr = dma_addr;
578 return ((dma_addr_t)dma_addr);
582 * sn_pci_unmap_single - unmap a region used for DMA
583 * @hwdev: device to unmap
584 * @dma_addr: DMA address to unmap
585 * @size: size of region
586 * @direction: DMA direction
588 * Unmaps the region pointed to by @dma_addr. Also known as
589 * platform_pci_unmap_single() by the IA64 machvec code.
592 sn_pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction)
594 struct sn_dma_maps_s *sn_dma_map = NULL;
596 if (direction == PCI_DMA_NONE)
600 * Get the sn_dma_map entry.
602 if (IS_PCI32_MAPPED(dma_addr))
603 sn_dma_map = find_sn_dma_map(dma_addr, hwdev->bus->number);
606 * and free it if necessary...
609 pciio_dmamap_done((pciio_dmamap_t)sn_dma_map);
610 pciio_dmamap_free((pciio_dmamap_t)sn_dma_map);
611 sn_dma_map->dma_addr = (dma_addr_t)NULL;
616 * sn_pci_dma_sync_single - make sure all DMAs have completed
617 * @hwdev: device to sync
618 * @dma_handle: DMA address to sync
619 * @size: size of region
620 * @direction: DMA direction
622 * This routine is supposed to sync the DMA region specified
623 * by @dma_handle into the 'coherence domain'. See sn_dma_sync()
624 * above for more information. Also known as
625 * platform_pci_dma_sync_single() by the IA64 machvec code.
628 sn_pci_dma_sync_single(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction)
630 if (direction == PCI_DMA_NONE)
637 * sn_pci_dma_sync_sg - make sure all DMAs have completed
638 * @hwdev: device to sync
639 * @sg: scatterlist to sync
640 * @nents: number of entries in the scatterlist
641 * @direction: DMA direction
643 * This routine is supposed to sync the DMA regions specified
644 * by @sg into the 'coherence domain'. See sn_dma_sync()
645 * above for more information. Also known as
646 * platform_pci_dma_sync_sg() by the IA64 machvec code.
649 sn_pci_dma_sync_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction)
651 if (direction == PCI_DMA_NONE)
658 * sn_dma_address - get the DMA address for the first entry of a scatterlist
661 * Gets the DMA address for the scatterlist @sg. Also known as
662 * platform_dma_address() by the IA64 machvec code.
665 sn_dma_address(struct scatterlist *sg)
667 return ((unsigned long)sg->dma_address);
671 * sn_dma_supported - test a DMA mask
672 * @hwdev: device to test
673 * @mask: DMA mask to test
675 * Return whether the given PCI device DMA address mask can be supported
676 * properly. For example, if your device can only drive the low 24-bits
677 * during PCI bus mastering, then you would pass 0x00ffffff as the mask to
678 * this function. Of course, SN only supports devices that have 32 or more
679 * address bits when using the PMU. We could theoretically support <32 bit
680 * cards using direct mapping, but we'll worry about that later--on the off
681 * chance that someone actually wants to use such a card.
684 sn_pci_dma_supported(struct pci_dev *hwdev, u64 mask)
686 if (mask < 0xffffffff)
691 EXPORT_SYMBOL(sn_pci_unmap_single);
692 EXPORT_SYMBOL(sn_pci_map_single);
693 EXPORT_SYMBOL(sn_pci_dma_sync_single);
694 EXPORT_SYMBOL(sn_pci_map_sg);
695 EXPORT_SYMBOL(sn_pci_unmap_sg);
696 EXPORT_SYMBOL(sn_pci_alloc_consistent);
697 EXPORT_SYMBOL(sn_pci_free_consistent);
698 EXPORT_SYMBOL(sn_dma_address);
699 EXPORT_SYMBOL(sn_pci_dma_supported);