drivers/mfd/rc5t583.c

   1 /*
   2  * Core driver access RC5T583 power management chip.
   3  *
   4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   5  * Author: Laxman dewangan <ldewangan@nvidia.com>
   6  *
   7  * Based on code
   8  *      Copyright (C) 2011 RICOH COMPANY,LTD
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms and conditions of the GNU General Public License,
  12  * version 2, as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  *
  22  */
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/init.h>
  28 #include <linux/err.h>
  29 #include <linux/slab.h>
  30 #include <linux/i2c.h>
  31 #include <linux/mfd/core.h>
  32 #include <linux/mfd/rc5t583.h>
  33 #include <linux/regmap.h>
  34
  35 #define RICOH_ONOFFSEL_REG      0x10
  36 #define RICOH_SWCTL_REG         0x5E
  37
  38 struct deepsleep_control_data {
  39         u8 reg_add;
  40         u8 ds_pos_bit;
  41 };
  42
  43 #define DEEPSLEEP_INIT(_id, _reg, _pos)         \
  44         {                                       \
  45                 .reg_add = RC5T583_##_reg,      \
  46                 .ds_pos_bit = _pos,             \
  47         }
  48
  49 static struct deepsleep_control_data deepsleep_data[] = {
  50         DEEPSLEEP_INIT(DC0, SLPSEQ1, 0),
  51         DEEPSLEEP_INIT(DC1, SLPSEQ1, 4),
  52         DEEPSLEEP_INIT(DC2, SLPSEQ2, 0),
  53         DEEPSLEEP_INIT(DC3, SLPSEQ2, 4),
  54         DEEPSLEEP_INIT(LDO0, SLPSEQ3, 0),
  55         DEEPSLEEP_INIT(LDO1, SLPSEQ3, 4),
  56         DEEPSLEEP_INIT(LDO2, SLPSEQ4, 0),
  57         DEEPSLEEP_INIT(LDO3, SLPSEQ4, 4),
  58         DEEPSLEEP_INIT(LDO4, SLPSEQ5, 0),
  59         DEEPSLEEP_INIT(LDO5, SLPSEQ5, 4),
  60         DEEPSLEEP_INIT(LDO6, SLPSEQ6, 0),
  61         DEEPSLEEP_INIT(LDO7, SLPSEQ6, 4),
  62         DEEPSLEEP_INIT(LDO8, SLPSEQ7, 0),
  63         DEEPSLEEP_INIT(LDO9, SLPSEQ7, 4),
  64         DEEPSLEEP_INIT(PSO0, SLPSEQ8, 0),
  65         DEEPSLEEP_INIT(PSO1, SLPSEQ8, 4),
  66         DEEPSLEEP_INIT(PSO2, SLPSEQ9, 0),
  67         DEEPSLEEP_INIT(PSO3, SLPSEQ9, 4),
  68         DEEPSLEEP_INIT(PSO4, SLPSEQ10, 0),
  69         DEEPSLEEP_INIT(PSO5, SLPSEQ10, 4),
  70         DEEPSLEEP_INIT(PSO6, SLPSEQ11, 0),
  71         DEEPSLEEP_INIT(PSO7, SLPSEQ11, 4),
  72 };
  73
  74 #define EXT_PWR_REQ             \
  75         (RC5T583_EXT_PWRREQ1_CONTROL | RC5T583_EXT_PWRREQ2_CONTROL)
  76
  77 static struct mfd_cell rc5t583_subdevs[] = {
  78         {.name = "rc5t583-regulator",},
  79         {.name = "rc5t583-rtc",      },
  80         {.name = "rc5t583-key",      }
  81 };
  82
  83 int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val)
  84 {
  85         struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
  86         return regmap_write(rc5t583->regmap, reg, val);
  87 }
  88
  89 int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val)
  90 {
  91         struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
  92         unsigned int ival;
  93         int ret;
  94         ret = regmap_read(rc5t583->regmap, reg, &ival);
  95         if (!ret)
  96                 *val = (uint8_t)ival;
  97         return ret;
  98 }
  99
 100 int rc5t583_set_bits(struct device *dev, unsigned int reg,
 101                         unsigned int bit_mask)
 102 {
 103         struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
 104         return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask);
 105 }
 106
 107 int rc5t583_clear_bits(struct device *dev, unsigned int reg,
 108                         unsigned int bit_mask)
 109 {
 110         struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
 111         return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0);
 112 }
 113
 114 int rc5t583_update(struct device *dev, unsigned int reg,
 115                 unsigned int val, unsigned int mask)
 116 {
 117         struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
 118         return regmap_update_bits(rc5t583->regmap, reg, mask, val);
 119 }
 120
 121 static int __rc5t583_set_ext_pwrreq1_control(struct device *dev,
 122         int id, int ext_pwr, int slots)
 123 {
 124         int ret;
 125         uint8_t sleepseq_val;
 126         unsigned int en_bit;
 127         unsigned int slot_bit;
 128
 129         if (id == RC5T583_DS_DC0) {
 130                 dev_err(dev, "PWRREQ1 is invalid control for rail %d\n", id);
 131                 return -EINVAL;
 132         }
 133
 134         en_bit = deepsleep_data[id].ds_pos_bit;
 135         slot_bit = en_bit + 1;
 136         ret = rc5t583_read(dev, deepsleep_data[id].reg_add, &sleepseq_val);
 137         if (ret < 0) {
 138                 dev_err(dev, "Error in reading reg 0x%x\n",
 139                                 deepsleep_data[id].reg_add);
 140                 return ret;
 141         }
 142
 143         sleepseq_val &= ~(0xF << en_bit);
 144         sleepseq_val |= BIT(en_bit);
 145         sleepseq_val |= ((slots & 0x7) << slot_bit);
 146         ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(1));
 147         if (ret < 0) {
 148                 dev_err(dev, "Error in updating the 0x%02x register\n",
 149                                 RICOH_ONOFFSEL_REG);
 150                 return ret;
 151         }
 152
 153         ret = rc5t583_write(dev, deepsleep_data[id].reg_add, sleepseq_val);
 154         if (ret < 0) {
 155                 dev_err(dev, "Error in writing reg 0x%x\n",
 156                                 deepsleep_data[id].reg_add);
 157                 return ret;
 158         }
 159
 160         if (id == RC5T583_DS_LDO4) {
 161                 ret = rc5t583_write(dev, RICOH_SWCTL_REG, 0x1);
 162                 if (ret < 0)
 163                         dev_err(dev, "Error in writing reg 0x%x\n",
 164                                 RICOH_SWCTL_REG);
 165         }
 166         return ret;
 167 }
 168
 169 static int __rc5t583_set_ext_pwrreq2_control(struct device *dev,
 170         int id, int ext_pwr)
 171 {
 172         int ret;
 173
 174         if (id != RC5T583_DS_DC0) {
 175                 dev_err(dev, "PWRREQ2 is invalid control for rail %d\n", id);
 176                 return -EINVAL;
 177         }
 178
 179         ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(2));
 180         if (ret < 0)
 181                 dev_err(dev, "Error in updating the ONOFFSEL 0x10 register\n");
 182         return ret;
 183 }
 184
 185 int rc5t583_ext_power_req_config(struct device *dev, int ds_id,
 186         int ext_pwr_req, int deepsleep_slot_nr)
 187 {
 188         if ((ext_pwr_req & EXT_PWR_REQ) == EXT_PWR_REQ)
 189                 return -EINVAL;
 190
 191         if (ext_pwr_req & RC5T583_EXT_PWRREQ1_CONTROL)
 192                 return __rc5t583_set_ext_pwrreq1_control(dev, ds_id,
 193                                 ext_pwr_req, deepsleep_slot_nr);
 194
 195         if (ext_pwr_req & RC5T583_EXT_PWRREQ2_CONTROL)
 196                 return __rc5t583_set_ext_pwrreq2_control(dev,
 197                         ds_id, ext_pwr_req);
 198         return 0;
 199 }
 200
 201 static int rc5t583_clear_ext_power_req(struct rc5t583 *rc5t583,
 202         struct rc5t583_platform_data *pdata)
 203 {
 204         int ret;
 205         int i;
 206         uint8_t on_off_val = 0;
 207
 208         /*  Clear ONOFFSEL register */
 209         if (pdata->enable_shutdown)
 210                 on_off_val = 0x1;
 211
 212         ret = rc5t583_write(rc5t583->dev, RICOH_ONOFFSEL_REG, on_off_val);
 213         if (ret < 0)
 214                 dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
 215                                         RICOH_ONOFFSEL_REG, ret);
 216
 217         ret = rc5t583_write(rc5t583->dev, RICOH_SWCTL_REG, 0x0);
 218         if (ret < 0)
 219                 dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
 220                                         RICOH_SWCTL_REG, ret);
 221
 222         /* Clear sleep sequence register */
 223         for (i = RC5T583_SLPSEQ1; i <= RC5T583_SLPSEQ11; ++i) {
 224                 ret = rc5t583_write(rc5t583->dev, i, 0x0);
 225                 if (ret < 0)
 226                         dev_warn(rc5t583->dev,
 227                                 "Error in writing reg 0x%02x error: %d\n",
 228                                 i, ret);
 229         }
 230         return 0;
 231 }
 232
 233 static bool volatile_reg(struct device *dev, unsigned int reg)
 234 {
 235         /* Enable caching in interrupt registers */
 236         switch (reg) {
 237         case RC5T583_INT_EN_SYS1:
 238         case RC5T583_INT_EN_SYS2:
 239         case RC5T583_INT_EN_DCDC:
 240         case RC5T583_INT_EN_RTC:
 241         case RC5T583_INT_EN_ADC1:
 242         case RC5T583_INT_EN_ADC2:
 243         case RC5T583_INT_EN_ADC3:
 244         case RC5T583_GPIO_GPEDGE1:
 245         case RC5T583_GPIO_GPEDGE2:
 246         case RC5T583_GPIO_EN_INT:
 247                 return false;
 248
 249         case RC5T583_GPIO_MON_IOIN:
 250                 /* This is gpio input register */
 251                 return true;
 252
 253         default:
 254                 /* Enable caching in gpio registers */
 255                 if ((reg >= RC5T583_GPIO_IOSEL) &&
 256                                 (reg <= RC5T583_GPIO_GPOFUNC))
 257                         return false;
 258
 259                 /* Enable caching in sleep seq registers */
 260                 if ((reg >= RC5T583_SLPSEQ1) && (reg <= RC5T583_SLPSEQ11))
 261                         return false;
 262
 263                 /* Enable caching of regulator registers */
 264                 if ((reg >= RC5T583_REG_DC0CTL) && (reg <= RC5T583_REG_SR3CTL))
 265                         return false;
 266                 if ((reg >= RC5T583_REG_LDOEN1) &&
 267                                         (reg <= RC5T583_REG_LDO9DAC_DS))
 268                         return false;
 269
 270                 break;
 271         }
 272
 273         return true;
 274 }
 275
 276 static const struct regmap_config rc5t583_regmap_config = {
 277         .reg_bits = 8,
 278         .val_bits = 8,
 279         .volatile_reg = volatile_reg,
 280         .max_register = RC5T583_MAX_REGS,
 281         .num_reg_defaults_raw = RC5T583_MAX_REGS,
 282         .cache_type = REGCACHE_RBTREE,
 283 };
 284
 285 static int __devinit rc5t583_i2c_probe(struct i2c_client *i2c,
 286                               const struct i2c_device_id *id)
 287 {
 288         struct rc5t583 *rc5t583;
 289         struct rc5t583_platform_data *pdata = i2c->dev.platform_data;
 290         int ret;
 291         bool irq_init_success = false;
 292
 293         if (!pdata) {
 294                 dev_err(&i2c->dev, "Err: Platform data not found\n");
 295                 return -EINVAL;
 296         }
 297
 298         rc5t583 = devm_kzalloc(&i2c->dev, sizeof(struct rc5t583), GFP_KERNEL);
 299         if (!rc5t583) {
 300                 dev_err(&i2c->dev, "Memory allocation failed\n");
 301                 return -ENOMEM;
 302         }
 303
 304         rc5t583->dev = &i2c->dev;
 305         i2c_set_clientdata(i2c, rc5t583);
 306
 307         rc5t583->regmap = regmap_init_i2c(i2c, &rc5t583_regmap_config);
 308         if (IS_ERR(rc5t583->regmap)) {
 309                 ret = PTR_ERR(rc5t583->regmap);
 310                 dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret);
 311                 return ret;
 312         }
 313
 314         ret = rc5t583_clear_ext_power_req(rc5t583, pdata);
 315         if (ret < 0)
 316                 goto err_irq_init;
 317
 318         if (i2c->irq) {
 319                 ret = rc5t583_irq_init(rc5t583, i2c->irq, pdata->irq_base);
 320                 /* Still continue with waring if irq init fails */
 321                 if (ret)
 322                         dev_warn(&i2c->dev, "IRQ init failed: %d\n", ret);
 323                 else
 324                         irq_init_success = true;
 325         }
 326
 327         ret = mfd_add_devices(rc5t583->dev, -1, rc5t583_subdevs,
 328                         ARRAY_SIZE(rc5t583_subdevs), NULL, 0);
 329         if (ret) {
 330                 dev_err(&i2c->dev, "add mfd devices failed: %d\n", ret);
 331                 goto err_add_devs;
 332         }
 333
 334         return 0;
 335
 336 err_add_devs:
 337         if (irq_init_success)
 338                 rc5t583_irq_exit(rc5t583);
 339 err_irq_init:
 340         regmap_exit(rc5t583->regmap);
 341         return ret;
 342 }
 343
 344 static int  __devexit rc5t583_i2c_remove(struct i2c_client *i2c)
 345 {
 346         struct rc5t583 *rc5t583 = i2c_get_clientdata(i2c);
 347
 348         mfd_remove_devices(rc5t583->dev);
 349         rc5t583_irq_exit(rc5t583);
 350         regmap_exit(rc5t583->regmap);
 351         return 0;
 352 }
 353
 354 static const struct i2c_device_id rc5t583_i2c_id[] = {
 355         {.name = "rc5t583", .driver_data = 0},
 356         {}
 357 };
 358
 359 MODULE_DEVICE_TABLE(i2c, rc5t583_i2c_id);
 360
 361 static struct i2c_driver rc5t583_i2c_driver = {
 362         .driver = {
 363                    .name = "rc5t583",
 364                    .owner = THIS_MODULE,
 365                    },
 366         .probe = rc5t583_i2c_probe,
 367         .remove = __devexit_p(rc5t583_i2c_remove),
 368         .id_table = rc5t583_i2c_id,
 369 };
 370
 371 static int __init rc5t583_i2c_init(void)
 372 {
 373         return i2c_add_driver(&rc5t583_i2c_driver);
 374 }
 375 subsys_initcall(rc5t583_i2c_init);
 376
 377 static void __exit rc5t583_i2c_exit(void)
 378 {
 379         i2c_del_driver(&rc5t583_i2c_driver);
 380 }
 381
 382 module_exit(rc5t583_i2c_exit);
 383
 384 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
 385 MODULE_DESCRIPTION("RICOH RC5T583 power management system device driver");
 386 MODULE_LICENSE("GPL v2");