drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_gpio.h"
  40 #include "nouveau_pm.h"
  41 #include "nv50_display.h"
  42
  43 static void nouveau_stub_takedown(struct drm_device *dev) {}
  44 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  45
  46 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  47 {
  48         struct drm_nouveau_private *dev_priv = dev->dev_private;
  49         struct nouveau_engine *engine = &dev_priv->engine;
  50
  51         switch (dev_priv->chipset & 0xf0) {
  52         case 0x00:
  53                 engine->instmem.init            = nv04_instmem_init;
  54                 engine->instmem.takedown        = nv04_instmem_takedown;
  55                 engine->instmem.suspend         = nv04_instmem_suspend;
  56                 engine->instmem.resume          = nv04_instmem_resume;
  57                 engine->instmem.get             = nv04_instmem_get;
  58                 engine->instmem.put             = nv04_instmem_put;
  59                 engine->instmem.map             = nv04_instmem_map;
  60                 engine->instmem.unmap           = nv04_instmem_unmap;
  61                 engine->instmem.flush           = nv04_instmem_flush;
  62                 engine->mc.init                 = nv04_mc_init;
  63                 engine->mc.takedown             = nv04_mc_takedown;
  64                 engine->timer.init              = nv04_timer_init;
  65                 engine->timer.read              = nv04_timer_read;
  66                 engine->timer.takedown          = nv04_timer_takedown;
  67                 engine->fb.init                 = nv04_fb_init;
  68                 engine->fb.takedown             = nv04_fb_takedown;
  69                 engine->fifo.channels           = 16;
  70                 engine->fifo.init               = nv04_fifo_init;
  71                 engine->fifo.takedown           = nv04_fifo_fini;
  72                 engine->fifo.disable            = nv04_fifo_disable;
  73                 engine->fifo.enable             = nv04_fifo_enable;
  74                 engine->fifo.reassign           = nv04_fifo_reassign;
  75                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  76                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  77                 engine->fifo.create_context     = nv04_fifo_create_context;
  78                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  79                 engine->fifo.load_context       = nv04_fifo_load_context;
  80                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  81                 engine->display.early_init      = nv04_display_early_init;
  82                 engine->display.late_takedown   = nv04_display_late_takedown;
  83                 engine->display.create          = nv04_display_create;
  84                 engine->display.destroy         = nv04_display_destroy;
  85                 engine->display.init            = nv04_display_init;
  86                 engine->display.fini            = nv04_display_fini;
  87                 engine->pm.clocks_get           = nv04_pm_clocks_get;
  88                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
  89                 engine->pm.clocks_set           = nv04_pm_clocks_set;
  90                 engine->vram.init               = nv04_fb_vram_init;
  91                 engine->vram.takedown           = nouveau_stub_takedown;
  92                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
  93                 break;
  94         case 0x10:
  95                 engine->instmem.init            = nv04_instmem_init;
  96                 engine->instmem.takedown        = nv04_instmem_takedown;
  97                 engine->instmem.suspend         = nv04_instmem_suspend;
  98                 engine->instmem.resume          = nv04_instmem_resume;
  99                 engine->instmem.get             = nv04_instmem_get;
 100                 engine->instmem.put             = nv04_instmem_put;
 101                 engine->instmem.map             = nv04_instmem_map;
 102                 engine->instmem.unmap           = nv04_instmem_unmap;
 103                 engine->instmem.flush           = nv04_instmem_flush;
 104                 engine->mc.init                 = nv04_mc_init;
 105                 engine->mc.takedown             = nv04_mc_takedown;
 106                 engine->timer.init              = nv04_timer_init;
 107                 engine->timer.read              = nv04_timer_read;
 108                 engine->timer.takedown          = nv04_timer_takedown;
 109                 engine->fb.init                 = nv10_fb_init;
 110                 engine->fb.takedown             = nv10_fb_takedown;
 111                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 112                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 113                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 114                 engine->fifo.channels           = 32;
 115                 engine->fifo.init               = nv10_fifo_init;
 116                 engine->fifo.takedown           = nv04_fifo_fini;
 117                 engine->fifo.disable            = nv04_fifo_disable;
 118                 engine->fifo.enable             = nv04_fifo_enable;
 119                 engine->fifo.reassign           = nv04_fifo_reassign;
 120                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 121                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 122                 engine->fifo.create_context     = nv10_fifo_create_context;
 123                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 124                 engine->fifo.load_context       = nv10_fifo_load_context;
 125                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 126                 engine->display.early_init      = nv04_display_early_init;
 127                 engine->display.late_takedown   = nv04_display_late_takedown;
 128                 engine->display.create          = nv04_display_create;
 129                 engine->display.destroy         = nv04_display_destroy;
 130                 engine->display.init            = nv04_display_init;
 131                 engine->display.fini            = nv04_display_fini;
 132                 engine->gpio.drive              = nv10_gpio_drive;
 133                 engine->gpio.sense              = nv10_gpio_sense;
 134                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 135                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 136                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 137                 if (dev_priv->chipset == 0x1a ||
 138                     dev_priv->chipset == 0x1f)
 139                         engine->vram.init       = nv1a_fb_vram_init;
 140                 else
 141                         engine->vram.init       = nv10_fb_vram_init;
 142                 engine->vram.takedown           = nouveau_stub_takedown;
 143                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 144                 break;
 145         case 0x20:
 146                 engine->instmem.init            = nv04_instmem_init;
 147                 engine->instmem.takedown        = nv04_instmem_takedown;
 148                 engine->instmem.suspend         = nv04_instmem_suspend;
 149                 engine->instmem.resume          = nv04_instmem_resume;
 150                 engine->instmem.get             = nv04_instmem_get;
 151                 engine->instmem.put             = nv04_instmem_put;
 152                 engine->instmem.map             = nv04_instmem_map;
 153                 engine->instmem.unmap           = nv04_instmem_unmap;
 154                 engine->instmem.flush           = nv04_instmem_flush;
 155                 engine->mc.init                 = nv04_mc_init;
 156                 engine->mc.takedown             = nv04_mc_takedown;
 157                 engine->timer.init              = nv04_timer_init;
 158                 engine->timer.read              = nv04_timer_read;
 159                 engine->timer.takedown          = nv04_timer_takedown;
 160                 engine->fb.init                 = nv20_fb_init;
 161                 engine->fb.takedown             = nv20_fb_takedown;
 162                 engine->fb.init_tile_region     = nv20_fb_init_tile_region;
 163                 engine->fb.set_tile_region      = nv20_fb_set_tile_region;
 164                 engine->fb.free_tile_region     = nv20_fb_free_tile_region;
 165                 engine->fifo.channels           = 32;
 166                 engine->fifo.init               = nv10_fifo_init;
 167                 engine->fifo.takedown           = nv04_fifo_fini;
 168                 engine->fifo.disable            = nv04_fifo_disable;
 169                 engine->fifo.enable             = nv04_fifo_enable;
 170                 engine->fifo.reassign           = nv04_fifo_reassign;
 171                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 172                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 173                 engine->fifo.create_context     = nv10_fifo_create_context;
 174                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 175                 engine->fifo.load_context       = nv10_fifo_load_context;
 176                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 177                 engine->display.early_init      = nv04_display_early_init;
 178                 engine->display.late_takedown   = nv04_display_late_takedown;
 179                 engine->display.create          = nv04_display_create;
 180                 engine->display.destroy         = nv04_display_destroy;
 181                 engine->display.init            = nv04_display_init;
 182                 engine->display.fini            = nv04_display_fini;
 183                 engine->gpio.drive              = nv10_gpio_drive;
 184                 engine->gpio.sense              = nv10_gpio_sense;
 185                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 186                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 187                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 188                 engine->vram.init               = nv20_fb_vram_init;
 189                 engine->vram.takedown           = nouveau_stub_takedown;
 190                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 191                 break;
 192         case 0x30:
 193                 engine->instmem.init            = nv04_instmem_init;
 194                 engine->instmem.takedown        = nv04_instmem_takedown;
 195                 engine->instmem.suspend         = nv04_instmem_suspend;
 196                 engine->instmem.resume          = nv04_instmem_resume;
 197                 engine->instmem.get             = nv04_instmem_get;
 198                 engine->instmem.put             = nv04_instmem_put;
 199                 engine->instmem.map             = nv04_instmem_map;
 200                 engine->instmem.unmap           = nv04_instmem_unmap;
 201                 engine->instmem.flush           = nv04_instmem_flush;
 202                 engine->mc.init                 = nv04_mc_init;
 203                 engine->mc.takedown             = nv04_mc_takedown;
 204                 engine->timer.init              = nv04_timer_init;
 205                 engine->timer.read              = nv04_timer_read;
 206                 engine->timer.takedown          = nv04_timer_takedown;
 207                 engine->fb.init                 = nv30_fb_init;
 208                 engine->fb.takedown             = nv30_fb_takedown;
 209                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 210                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 211                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 212                 engine->fifo.channels           = 32;
 213                 engine->fifo.init               = nv10_fifo_init;
 214                 engine->fifo.takedown           = nv04_fifo_fini;
 215                 engine->fifo.disable            = nv04_fifo_disable;
 216                 engine->fifo.enable             = nv04_fifo_enable;
 217                 engine->fifo.reassign           = nv04_fifo_reassign;
 218                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 219                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 220                 engine->fifo.create_context     = nv10_fifo_create_context;
 221                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 222                 engine->fifo.load_context       = nv10_fifo_load_context;
 223                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 224                 engine->display.early_init      = nv04_display_early_init;
 225                 engine->display.late_takedown   = nv04_display_late_takedown;
 226                 engine->display.create          = nv04_display_create;
 227                 engine->display.destroy         = nv04_display_destroy;
 228                 engine->display.init            = nv04_display_init;
 229                 engine->display.fini            = nv04_display_fini;
 230                 engine->gpio.drive              = nv10_gpio_drive;
 231                 engine->gpio.sense              = nv10_gpio_sense;
 232                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 233                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 234                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 235                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 236                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 237                 engine->vram.init               = nv20_fb_vram_init;
 238                 engine->vram.takedown           = nouveau_stub_takedown;
 239                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 240                 break;
 241         case 0x40:
 242         case 0x60:
 243                 engine->instmem.init            = nv04_instmem_init;
 244                 engine->instmem.takedown        = nv04_instmem_takedown;
 245                 engine->instmem.suspend         = nv04_instmem_suspend;
 246                 engine->instmem.resume          = nv04_instmem_resume;
 247                 engine->instmem.get             = nv04_instmem_get;
 248                 engine->instmem.put             = nv04_instmem_put;
 249                 engine->instmem.map             = nv04_instmem_map;
 250                 engine->instmem.unmap           = nv04_instmem_unmap;
 251                 engine->instmem.flush           = nv04_instmem_flush;
 252                 engine->mc.init                 = nv40_mc_init;
 253                 engine->mc.takedown             = nv40_mc_takedown;
 254                 engine->timer.init              = nv04_timer_init;
 255                 engine->timer.read              = nv04_timer_read;
 256                 engine->timer.takedown          = nv04_timer_takedown;
 257                 engine->fb.init                 = nv40_fb_init;
 258                 engine->fb.takedown             = nv40_fb_takedown;
 259                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 260                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 261                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 262                 engine->fifo.channels           = 32;
 263                 engine->fifo.init               = nv40_fifo_init;
 264                 engine->fifo.takedown           = nv04_fifo_fini;
 265                 engine->fifo.disable            = nv04_fifo_disable;
 266                 engine->fifo.enable             = nv04_fifo_enable;
 267                 engine->fifo.reassign           = nv04_fifo_reassign;
 268                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 269                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 270                 engine->fifo.create_context     = nv40_fifo_create_context;
 271                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 272                 engine->fifo.load_context       = nv40_fifo_load_context;
 273                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 274                 engine->display.early_init      = nv04_display_early_init;
 275                 engine->display.late_takedown   = nv04_display_late_takedown;
 276                 engine->display.create          = nv04_display_create;
 277                 engine->display.destroy         = nv04_display_destroy;
 278                 engine->display.init            = nv04_display_init;
 279                 engine->display.fini            = nv04_display_fini;
 280                 engine->gpio.init               = nv10_gpio_init;
 281                 engine->gpio.fini               = nv10_gpio_fini;
 282                 engine->gpio.drive              = nv10_gpio_drive;
 283                 engine->gpio.sense              = nv10_gpio_sense;
 284                 engine->gpio.irq_enable         = nv10_gpio_irq_enable;
 285                 engine->pm.clocks_get           = nv40_pm_clocks_get;
 286                 engine->pm.clocks_pre           = nv40_pm_clocks_pre;
 287                 engine->pm.clocks_set           = nv40_pm_clocks_set;
 288                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 289                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 290                 engine->pm.temp_get             = nv40_temp_get;
 291                 engine->pm.pwm_get              = nv40_pm_pwm_get;
 292                 engine->pm.pwm_set              = nv40_pm_pwm_set;
 293                 engine->vram.init               = nv40_fb_vram_init;
 294                 engine->vram.takedown           = nouveau_stub_takedown;
 295                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 296                 break;
 297         case 0x50:
 298         case 0x80: /* gotta love NVIDIA's consistency.. */
 299         case 0x90:
 300         case 0xa0:
 301                 engine->instmem.init            = nv50_instmem_init;
 302                 engine->instmem.takedown        = nv50_instmem_takedown;
 303                 engine->instmem.suspend         = nv50_instmem_suspend;
 304                 engine->instmem.resume          = nv50_instmem_resume;
 305                 engine->instmem.get             = nv50_instmem_get;
 306                 engine->instmem.put             = nv50_instmem_put;
 307                 engine->instmem.map             = nv50_instmem_map;
 308                 engine->instmem.unmap           = nv50_instmem_unmap;
 309                 if (dev_priv->chipset == 0x50)
 310                         engine->instmem.flush   = nv50_instmem_flush;
 311                 else
 312                         engine->instmem.flush   = nv84_instmem_flush;
 313                 engine->mc.init                 = nv50_mc_init;
 314                 engine->mc.takedown             = nv50_mc_takedown;
 315                 engine->timer.init              = nv04_timer_init;
 316                 engine->timer.read              = nv04_timer_read;
 317                 engine->timer.takedown          = nv04_timer_takedown;
 318                 engine->fb.init                 = nv50_fb_init;
 319                 engine->fb.takedown             = nv50_fb_takedown;
 320                 engine->fifo.channels           = 128;
 321                 engine->fifo.init               = nv50_fifo_init;
 322                 engine->fifo.takedown           = nv50_fifo_takedown;
 323                 engine->fifo.disable            = nv04_fifo_disable;
 324                 engine->fifo.enable             = nv04_fifo_enable;
 325                 engine->fifo.reassign           = nv04_fifo_reassign;
 326                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 327                 engine->fifo.create_context     = nv50_fifo_create_context;
 328                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 329                 engine->fifo.load_context       = nv50_fifo_load_context;
 330                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 331                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
 332                 engine->display.early_init      = nv50_display_early_init;
 333                 engine->display.late_takedown   = nv50_display_late_takedown;
 334                 engine->display.create          = nv50_display_create;
 335                 engine->display.destroy         = nv50_display_destroy;
 336                 engine->display.init            = nv50_display_init;
 337                 engine->display.fini            = nv50_display_fini;
 338                 engine->gpio.init               = nv50_gpio_init;
 339                 engine->gpio.fini               = nv50_gpio_fini;
 340                 engine->gpio.drive              = nv50_gpio_drive;
 341                 engine->gpio.sense              = nv50_gpio_sense;
 342                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 343                 switch (dev_priv->chipset) {
 344                 case 0x84:
 345                 case 0x86:
 346                 case 0x92:
 347                 case 0x94:
 348                 case 0x96:
 349                 case 0x98:
 350                 case 0xa0:
 351                 case 0xaa:
 352                 case 0xac:
 353                 case 0x50:
 354                         engine->pm.clocks_get   = nv50_pm_clocks_get;
 355                         engine->pm.clocks_pre   = nv50_pm_clocks_pre;
 356                         engine->pm.clocks_set   = nv50_pm_clocks_set;
 357                         break;
 358                 default:
 359                         engine->pm.clocks_get   = nva3_pm_clocks_get;
 360                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
 361                         engine->pm.clocks_set   = nva3_pm_clocks_set;
 362                         break;
 363                 }
 364                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 365                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 366                 if (dev_priv->chipset >= 0x84)
 367                         engine->pm.temp_get     = nv84_temp_get;
 368                 else
 369                         engine->pm.temp_get     = nv40_temp_get;
 370                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 371                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 372                 engine->vram.init               = nv50_vram_init;
 373                 engine->vram.takedown           = nv50_vram_fini;
 374                 engine->vram.get                = nv50_vram_new;
 375                 engine->vram.put                = nv50_vram_del;
 376                 engine->vram.flags_valid        = nv50_vram_flags_valid;
 377                 break;
 378         case 0xc0:
 379                 engine->instmem.init            = nvc0_instmem_init;
 380                 engine->instmem.takedown        = nvc0_instmem_takedown;
 381                 engine->instmem.suspend         = nvc0_instmem_suspend;
 382                 engine->instmem.resume          = nvc0_instmem_resume;
 383                 engine->instmem.get             = nv50_instmem_get;
 384                 engine->instmem.put             = nv50_instmem_put;
 385                 engine->instmem.map             = nv50_instmem_map;
 386                 engine->instmem.unmap           = nv50_instmem_unmap;
 387                 engine->instmem.flush           = nv84_instmem_flush;
 388                 engine->mc.init                 = nv50_mc_init;
 389                 engine->mc.takedown             = nv50_mc_takedown;
 390                 engine->timer.init              = nv04_timer_init;
 391                 engine->timer.read              = nv04_timer_read;
 392                 engine->timer.takedown          = nv04_timer_takedown;
 393                 engine->fb.init                 = nvc0_fb_init;
 394                 engine->fb.takedown             = nvc0_fb_takedown;
 395                 engine->fifo.channels           = 128;
 396                 engine->fifo.init               = nvc0_fifo_init;
 397                 engine->fifo.takedown           = nvc0_fifo_takedown;
 398                 engine->fifo.disable            = nvc0_fifo_disable;
 399                 engine->fifo.enable             = nvc0_fifo_enable;
 400                 engine->fifo.reassign           = nvc0_fifo_reassign;
 401                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 402                 engine->fifo.create_context     = nvc0_fifo_create_context;
 403                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 404                 engine->fifo.load_context       = nvc0_fifo_load_context;
 405                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 406                 engine->display.early_init      = nv50_display_early_init;
 407                 engine->display.late_takedown   = nv50_display_late_takedown;
 408                 engine->display.create          = nv50_display_create;
 409                 engine->display.destroy         = nv50_display_destroy;
 410                 engine->display.init            = nv50_display_init;
 411                 engine->display.fini            = nv50_display_fini;
 412                 engine->gpio.init               = nv50_gpio_init;
 413                 engine->gpio.fini               = nv50_gpio_fini;
 414                 engine->gpio.drive              = nv50_gpio_drive;
 415                 engine->gpio.sense              = nv50_gpio_sense;
 416                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 417                 engine->vram.init               = nvc0_vram_init;
 418                 engine->vram.takedown           = nv50_vram_fini;
 419                 engine->vram.get                = nvc0_vram_new;
 420                 engine->vram.put                = nv50_vram_del;
 421                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 422                 engine->pm.temp_get             = nv84_temp_get;
 423                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 424                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 425                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 426                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 427                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 428                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 429                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 430                 break;
 431         case 0xd0:
 432                 engine->instmem.init            = nvc0_instmem_init;
 433                 engine->instmem.takedown        = nvc0_instmem_takedown;
 434                 engine->instmem.suspend         = nvc0_instmem_suspend;
 435                 engine->instmem.resume          = nvc0_instmem_resume;
 436                 engine->instmem.get             = nv50_instmem_get;
 437                 engine->instmem.put             = nv50_instmem_put;
 438                 engine->instmem.map             = nv50_instmem_map;
 439                 engine->instmem.unmap           = nv50_instmem_unmap;
 440                 engine->instmem.flush           = nv84_instmem_flush;
 441                 engine->mc.init                 = nv50_mc_init;
 442                 engine->mc.takedown             = nv50_mc_takedown;
 443                 engine->timer.init              = nv04_timer_init;
 444                 engine->timer.read              = nv04_timer_read;
 445                 engine->timer.takedown          = nv04_timer_takedown;
 446                 engine->fb.init                 = nvc0_fb_init;
 447                 engine->fb.takedown             = nvc0_fb_takedown;
 448                 engine->fifo.channels           = 128;
 449                 engine->fifo.init               = nvc0_fifo_init;
 450                 engine->fifo.takedown           = nvc0_fifo_takedown;
 451                 engine->fifo.disable            = nvc0_fifo_disable;
 452                 engine->fifo.enable             = nvc0_fifo_enable;
 453                 engine->fifo.reassign           = nvc0_fifo_reassign;
 454                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 455                 engine->fifo.create_context     = nvc0_fifo_create_context;
 456                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 457                 engine->fifo.load_context       = nvc0_fifo_load_context;
 458                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 459                 engine->display.early_init      = nouveau_stub_init;
 460                 engine->display.late_takedown   = nouveau_stub_takedown;
 461                 engine->display.create          = nvd0_display_create;
 462                 engine->display.destroy         = nvd0_display_destroy;
 463                 engine->display.init            = nvd0_display_init;
 464                 engine->display.fini            = nvd0_display_fini;
 465                 engine->gpio.init               = nv50_gpio_init;
 466                 engine->gpio.fini               = nv50_gpio_fini;
 467                 engine->gpio.drive              = nvd0_gpio_drive;
 468                 engine->gpio.sense              = nvd0_gpio_sense;
 469                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 470                 engine->vram.init               = nvc0_vram_init;
 471                 engine->vram.takedown           = nv50_vram_fini;
 472                 engine->vram.get                = nvc0_vram_new;
 473                 engine->vram.put                = nv50_vram_del;
 474                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 475                 engine->pm.temp_get             = nv84_temp_get;
 476                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 477                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 478                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 479                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 480                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 481                 break;
 482         case 0xe0:
 483                 engine->instmem.init            = nvc0_instmem_init;
 484                 engine->instmem.takedown        = nvc0_instmem_takedown;
 485                 engine->instmem.suspend         = nvc0_instmem_suspend;
 486                 engine->instmem.resume          = nvc0_instmem_resume;
 487                 engine->instmem.get             = nv50_instmem_get;
 488                 engine->instmem.put             = nv50_instmem_put;
 489                 engine->instmem.map             = nv50_instmem_map;
 490                 engine->instmem.unmap           = nv50_instmem_unmap;
 491                 engine->instmem.flush           = nv84_instmem_flush;
 492                 engine->mc.init                 = nv50_mc_init;
 493                 engine->mc.takedown             = nv50_mc_takedown;
 494                 engine->timer.init              = nv04_timer_init;
 495                 engine->timer.read              = nv04_timer_read;
 496                 engine->timer.takedown          = nv04_timer_takedown;
 497                 engine->fb.init                 = nvc0_fb_init;
 498                 engine->fb.takedown             = nvc0_fb_takedown;
 499                 engine->fifo.channels           = 0;
 500                 engine->fifo.init               = nouveau_stub_init;
 501                 engine->fifo.takedown           = nouveau_stub_takedown;
 502                 engine->fifo.disable            = nvc0_fifo_disable;
 503                 engine->fifo.enable             = nvc0_fifo_enable;
 504                 engine->fifo.reassign           = nvc0_fifo_reassign;
 505                 engine->fifo.unload_context     = nouveau_stub_init;
 506                 engine->display.early_init      = nouveau_stub_init;
 507                 engine->display.late_takedown   = nouveau_stub_takedown;
 508                 engine->display.create          = nvd0_display_create;
 509                 engine->display.destroy         = nvd0_display_destroy;
 510                 engine->display.init            = nvd0_display_init;
 511                 engine->display.fini            = nvd0_display_fini;
 512                 engine->gpio.init               = nv50_gpio_init;
 513                 engine->gpio.fini               = nv50_gpio_fini;
 514                 engine->gpio.drive              = nvd0_gpio_drive;
 515                 engine->gpio.sense              = nvd0_gpio_sense;
 516                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 517                 engine->vram.init               = nvc0_vram_init;
 518                 engine->vram.takedown           = nv50_vram_fini;
 519                 engine->vram.get                = nvc0_vram_new;
 520                 engine->vram.put                = nv50_vram_del;
 521                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 522                 break;
 523         default:
 524                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 525                 return 1;
 526         }
 527
 528         /* headless mode */
 529         if (nouveau_modeset == 2) {
 530                 engine->display.early_init = nouveau_stub_init;
 531                 engine->display.late_takedown = nouveau_stub_takedown;
 532                 engine->display.create = nouveau_stub_init;
 533                 engine->display.init = nouveau_stub_init;
 534                 engine->display.destroy = nouveau_stub_takedown;
 535         }
 536
 537         return 0;
 538 }
 539
 540 static unsigned int
 541 nouveau_vga_set_decode(void *priv, bool state)
 542 {
 543         struct drm_device *dev = priv;
 544         struct drm_nouveau_private *dev_priv = dev->dev_private;
 545
 546         if (dev_priv->chipset >= 0x40)
 547                 nv_wr32(dev, 0x88054, state);
 548         else
 549                 nv_wr32(dev, 0x1854, state);
 550
 551         if (state)
 552                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 553                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 554         else
 555                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 556 }
 557
 558 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 559                                          enum vga_switcheroo_state state)
 560 {
 561         struct drm_device *dev = pci_get_drvdata(pdev);
 562         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 563         if (state == VGA_SWITCHEROO_ON) {
 564                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 565                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 566                 nouveau_pci_resume(pdev);
 567                 drm_kms_helper_poll_enable(dev);
 568                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 569         } else {
 570                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 571                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 572                 drm_kms_helper_poll_disable(dev);
 573                 nouveau_switcheroo_optimus_dsm();
 574                 nouveau_pci_suspend(pdev, pmm);
 575                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 576         }
 577 }
 578
 579 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 580 {
 581         struct drm_device *dev = pci_get_drvdata(pdev);
 582         nouveau_fbcon_output_poll_changed(dev);
 583 }
 584
 585 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 586 {
 587         struct drm_device *dev = pci_get_drvdata(pdev);
 588         bool can_switch;
 589
 590         spin_lock(&dev->count_lock);
 591         can_switch = (dev->open_count == 0);
 592         spin_unlock(&dev->count_lock);
 593         return can_switch;
 594 }
 595
 596 static void
 597 nouveau_card_channel_fini(struct drm_device *dev)
 598 {
 599         struct drm_nouveau_private *dev_priv = dev->dev_private;
 600
 601         if (dev_priv->channel)
 602                 nouveau_channel_put_unlocked(&dev_priv->channel);
 603 }
 604
 605 static int
 606 nouveau_card_channel_init(struct drm_device *dev)
 607 {
 608         struct drm_nouveau_private *dev_priv = dev->dev_private;
 609         struct nouveau_channel *chan;
 610         int ret, oclass;
 611
 612         ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT);
 613         dev_priv->channel = chan;
 614         if (ret)
 615                 return ret;
 616
 617         mutex_unlock(&dev_priv->channel->mutex);
 618
 619         if (dev_priv->card_type <= NV_50) {
 620                 if (dev_priv->card_type < NV_50)
 621                         oclass = 0x0039;
 622                 else
 623                         oclass = 0x5039;
 624
 625                 ret = nouveau_gpuobj_gr_new(chan, NvM2MF, oclass);
 626                 if (ret)
 627                         goto error;
 628
 629                 ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfe0, 0x1000,
 630                                              &chan->m2mf_ntfy);
 631                 if (ret)
 632                         goto error;
 633
 634                 ret = RING_SPACE(chan, 6);
 635                 if (ret)
 636                         goto error;
 637
 638                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
 639                 OUT_RING  (chan, NvM2MF);
 640                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3);
 641                 OUT_RING  (chan, NvNotify0);
 642                 OUT_RING  (chan, chan->vram_handle);
 643                 OUT_RING  (chan, chan->gart_handle);
 644         } else
 645         if (dev_priv->card_type <= NV_C0) {
 646                 ret = nouveau_gpuobj_gr_new(chan, 0x9039, 0x9039);
 647                 if (ret)
 648                         goto error;
 649
 650                 ret = RING_SPACE(chan, 2);
 651                 if (ret)
 652                         goto error;
 653
 654                 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0000, 1);
 655                 OUT_RING  (chan, 0x00009039);
 656         }
 657
 658         FIRE_RING (chan);
 659 error:
 660         if (ret)
 661                 nouveau_card_channel_fini(dev);
 662         return ret;
 663 }
 664
 665 int
 666 nouveau_card_init(struct drm_device *dev)
 667 {
 668         struct drm_nouveau_private *dev_priv = dev->dev_private;
 669         struct nouveau_engine *engine;
 670         int ret, e = 0;
 671
 672         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 673         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 674                                        nouveau_switcheroo_reprobe,
 675                                        nouveau_switcheroo_can_switch);
 676
 677         /* Initialise internal driver API hooks */
 678         ret = nouveau_init_engine_ptrs(dev);
 679         if (ret)
 680                 goto out;
 681         engine = &dev_priv->engine;
 682         spin_lock_init(&dev_priv->channels.lock);
 683         spin_lock_init(&dev_priv->tile.lock);
 684         spin_lock_init(&dev_priv->context_switch_lock);
 685         spin_lock_init(&dev_priv->vm_lock);
 686
 687         /* Make the CRTCs and I2C buses accessible */
 688         ret = engine->display.early_init(dev);
 689         if (ret)
 690                 goto out;
 691
 692         /* Parse BIOS tables / Run init tables if card not POSTed */
 693         ret = nouveau_bios_init(dev);
 694         if (ret)
 695                 goto out_display_early;
 696
 697         /* workaround an odd issue on nvc1 by disabling the device's
 698          * nosnoop capability.  hopefully won't cause issues until a
 699          * better fix is found - assuming there is one...
 700          */
 701         if (dev_priv->chipset == 0xc1) {
 702                 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
 703         }
 704
 705         /* PMC */
 706         ret = engine->mc.init(dev);
 707         if (ret)
 708                 goto out_bios;
 709
 710         /* PTIMER */
 711         ret = engine->timer.init(dev);
 712         if (ret)
 713                 goto out_mc;
 714
 715         /* PFB */
 716         ret = engine->fb.init(dev);
 717         if (ret)
 718                 goto out_timer;
 719
 720         ret = engine->vram.init(dev);
 721         if (ret)
 722                 goto out_fb;
 723
 724         /* PGPIO */
 725         ret = nouveau_gpio_create(dev);
 726         if (ret)
 727                 goto out_vram;
 728
 729         ret = nouveau_gpuobj_init(dev);
 730         if (ret)
 731                 goto out_gpio;
 732
 733         ret = engine->instmem.init(dev);
 734         if (ret)
 735                 goto out_gpuobj;
 736
 737         ret = nouveau_mem_vram_init(dev);
 738         if (ret)
 739                 goto out_instmem;
 740
 741         ret = nouveau_mem_gart_init(dev);
 742         if (ret)
 743                 goto out_ttmvram;
 744
 745         if (!dev_priv->noaccel) {
 746                 switch (dev_priv->card_type) {
 747                 case NV_04:
 748                         nv04_graph_create(dev);
 749                         break;
 750                 case NV_10:
 751                         nv10_graph_create(dev);
 752                         break;
 753                 case NV_20:
 754                 case NV_30:
 755                         nv20_graph_create(dev);
 756                         break;
 757                 case NV_40:
 758                         nv40_graph_create(dev);
 759                         break;
 760                 case NV_50:
 761                         nv50_graph_create(dev);
 762                         break;
 763                 case NV_C0:
 764                 case NV_D0:
 765                         nvc0_graph_create(dev);
 766                         break;
 767                 default:
 768                         break;
 769                 }
 770
 771                 switch (dev_priv->chipset) {
 772                 case 0x84:
 773                 case 0x86:
 774                 case 0x92:
 775                 case 0x94:
 776                 case 0x96:
 777                 case 0xa0:
 778                         nv84_crypt_create(dev);
 779                         break;
 780                 case 0x98:
 781                 case 0xaa:
 782                 case 0xac:
 783                         nv98_crypt_create(dev);
 784                         break;
 785                 }
 786
 787                 switch (dev_priv->card_type) {
 788                 case NV_50:
 789                         switch (dev_priv->chipset) {
 790                         case 0xa3:
 791                         case 0xa5:
 792                         case 0xa8:
 793                         case 0xaf:
 794                                 nva3_copy_create(dev);
 795                                 break;
 796                         }
 797                         break;
 798                 case NV_C0:
 799                         nvc0_copy_create(dev, 0);
 800                         nvc0_copy_create(dev, 1);
 801                         break;
 802                 default:
 803                         break;
 804                 }
 805
 806                 if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) {
 807                         nv84_bsp_create(dev);
 808                         nv84_vp_create(dev);
 809                         nv98_ppp_create(dev);
 810                 } else
 811                 if (dev_priv->chipset >= 0x84) {
 812                         nv50_mpeg_create(dev);
 813                         nv84_bsp_create(dev);
 814                         nv84_vp_create(dev);
 815                 } else
 816                 if (dev_priv->chipset >= 0x50) {
 817                         nv50_mpeg_create(dev);
 818                 } else
 819                 if (dev_priv->card_type == NV_40 ||
 820                     dev_priv->chipset == 0x31 ||
 821                     dev_priv->chipset == 0x34 ||
 822                     dev_priv->chipset == 0x36) {
 823                         nv31_mpeg_create(dev);
 824                 }
 825
 826                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
 827                         if (dev_priv->eng[e]) {
 828                                 ret = dev_priv->eng[e]->init(dev, e);
 829                                 if (ret)
 830                                         goto out_engine;
 831                         }
 832                 }
 833
 834                 /* PFIFO */
 835                 ret = engine->fifo.init(dev);
 836                 if (ret)
 837                         goto out_engine;
 838         }
 839
 840         ret = nouveau_irq_init(dev);
 841         if (ret)
 842                 goto out_fifo;
 843
 844         ret = nouveau_display_create(dev);
 845         if (ret)
 846                 goto out_irq;
 847
 848         nouveau_backlight_init(dev);
 849         nouveau_pm_init(dev);
 850
 851         ret = nouveau_fence_init(dev);
 852         if (ret)
 853                 goto out_pm;
 854
 855         if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
 856                 ret = nouveau_card_channel_init(dev);
 857                 if (ret)
 858                         goto out_fence;
 859         }
 860
 861         if (dev->mode_config.num_crtc) {
 862                 ret = nouveau_display_init(dev);
 863                 if (ret)
 864                         goto out_chan;
 865
 866                 nouveau_fbcon_init(dev);
 867         }
 868
 869         return 0;
 870
 871 out_chan:
 872         nouveau_card_channel_fini(dev);
 873 out_fence:
 874         nouveau_fence_fini(dev);
 875 out_pm:
 876         nouveau_pm_fini(dev);
 877         nouveau_backlight_exit(dev);
 878         nouveau_display_destroy(dev);
 879 out_irq:
 880         nouveau_irq_fini(dev);
 881 out_fifo:
 882         if (!dev_priv->noaccel)
 883                 engine->fifo.takedown(dev);
 884 out_engine:
 885         if (!dev_priv->noaccel) {
 886                 for (e = e - 1; e >= 0; e--) {
 887                         if (!dev_priv->eng[e])
 888                                 continue;
 889                         dev_priv->eng[e]->fini(dev, e, false);
 890                         dev_priv->eng[e]->destroy(dev,e );
 891                 }
 892         }
 893         nouveau_mem_gart_fini(dev);
 894 out_ttmvram:
 895         nouveau_mem_vram_fini(dev);
 896 out_instmem:
 897         engine->instmem.takedown(dev);
 898 out_gpuobj:
 899         nouveau_gpuobj_takedown(dev);
 900 out_gpio:
 901         nouveau_gpio_destroy(dev);
 902 out_vram:
 903         engine->vram.takedown(dev);
 904 out_fb:
 905         engine->fb.takedown(dev);
 906 out_timer:
 907         engine->timer.takedown(dev);
 908 out_mc:
 909         engine->mc.takedown(dev);
 910 out_bios:
 911         nouveau_bios_takedown(dev);
 912 out_display_early:
 913         engine->display.late_takedown(dev);
 914 out:
 915         vga_client_register(dev->pdev, NULL, NULL, NULL);
 916         return ret;
 917 }
 918
 919 static void nouveau_card_takedown(struct drm_device *dev)
 920 {
 921         struct drm_nouveau_private *dev_priv = dev->dev_private;
 922         struct nouveau_engine *engine = &dev_priv->engine;
 923         int e;
 924
 925         if (dev->mode_config.num_crtc) {
 926                 nouveau_fbcon_fini(dev);
 927                 nouveau_display_fini(dev);
 928         }
 929
 930         nouveau_card_channel_fini(dev);
 931         nouveau_fence_fini(dev);
 932         nouveau_pm_fini(dev);
 933         nouveau_backlight_exit(dev);
 934         nouveau_display_destroy(dev);
 935
 936         if (!dev_priv->noaccel) {
 937                 engine->fifo.takedown(dev);
 938                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
 939                         if (dev_priv->eng[e]) {
 940                                 dev_priv->eng[e]->fini(dev, e, false);
 941                                 dev_priv->eng[e]->destroy(dev,e );
 942                         }
 943                 }
 944         }
 945
 946         if (dev_priv->vga_ram) {
 947                 nouveau_bo_unpin(dev_priv->vga_ram);
 948                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 949         }
 950
 951         mutex_lock(&dev->struct_mutex);
 952         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 953         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 954         mutex_unlock(&dev->struct_mutex);
 955         nouveau_mem_gart_fini(dev);
 956         nouveau_mem_vram_fini(dev);
 957
 958         engine->instmem.takedown(dev);
 959         nouveau_gpuobj_takedown(dev);
 960
 961         nouveau_gpio_destroy(dev);
 962         engine->vram.takedown(dev);
 963         engine->fb.takedown(dev);
 964         engine->timer.takedown(dev);
 965         engine->mc.takedown(dev);
 966
 967         nouveau_bios_takedown(dev);
 968         engine->display.late_takedown(dev);
 969
 970         nouveau_irq_fini(dev);
 971
 972         vga_client_register(dev->pdev, NULL, NULL, NULL);
 973 }
 974
 975 int
 976 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
 977 {
 978         struct drm_nouveau_private *dev_priv = dev->dev_private;
 979         struct nouveau_fpriv *fpriv;
 980         int ret;
 981
 982         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 983         if (unlikely(!fpriv))
 984                 return -ENOMEM;
 985
 986         spin_lock_init(&fpriv->lock);
 987         INIT_LIST_HEAD(&fpriv->channels);
 988
 989         if (dev_priv->card_type == NV_50) {
 990                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
 991                                      &fpriv->vm);
 992                 if (ret) {
 993                         kfree(fpriv);
 994                         return ret;
 995                 }
 996         } else
 997         if (dev_priv->card_type >= NV_C0) {
 998                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
 999                                      &fpriv->vm);
1000                 if (ret) {
1001                         kfree(fpriv);
1002                         return ret;
1003                 }
1004         }
1005
1006         file_priv->driver_priv = fpriv;
1007         return 0;
1008 }
1009
1010 /* here a client dies, release the stuff that was allocated for its
1011  * file_priv */
1012 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
1013 {
1014         nouveau_channel_cleanup(dev, file_priv);
1015 }
1016
1017 void
1018 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
1019 {
1020         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
1021         nouveau_vm_ref(NULL, &fpriv->vm, NULL);
1022         kfree(fpriv);
1023 }
1024
1025 /* first module load, setup the mmio/fb mapping */
1026 /* KMS: we need mmio at load time, not when the first drm client opens. */
1027 int nouveau_firstopen(struct drm_device *dev)
1028 {
1029         return 0;
1030 }
1031
1032 /* if we have an OF card, copy vbios to RAMIN */
1033 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
1034 {
1035 #if defined(__powerpc__)
1036         int size, i;
1037         const uint32_t *bios;
1038         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
1039         if (!dn) {
1040                 NV_INFO(dev, "Unable to get the OF node\n");
1041                 return;
1042         }
1043
1044         bios = of_get_property(dn, "NVDA,BMP", &size);
1045         if (bios) {
1046                 for (i = 0; i < size; i += 4)
1047                         nv_wi32(dev, i, bios[i/4]);
1048                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
1049         } else {
1050                 NV_INFO(dev, "Unable to get the OF bios\n");
1051         }
1052 #endif
1053 }
1054
1055 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
1056 {
1057         struct pci_dev *pdev = dev->pdev;
1058         struct apertures_struct *aper = alloc_apertures(3);
1059         if (!aper)
1060                 return NULL;
1061
1062         aper->ranges[0].base = pci_resource_start(pdev, 1);
1063         aper->ranges[0].size = pci_resource_len(pdev, 1);
1064         aper->count = 1;
1065
1066         if (pci_resource_len(pdev, 2)) {
1067                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
1068                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
1069                 aper->count++;
1070         }
1071
1072         if (pci_resource_len(pdev, 3)) {
1073                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
1074                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
1075                 aper->count++;
1076         }
1077
1078         return aper;
1079 }
1080
1081 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
1082 {
1083         struct drm_nouveau_private *dev_priv = dev->dev_private;
1084         bool primary = false;
1085         dev_priv->apertures = nouveau_get_apertures(dev);
1086         if (!dev_priv->apertures)
1087                 return -ENOMEM;
1088
1089 #ifdef CONFIG_X86
1090         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1091 #endif
1092
1093         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
1094         return 0;
1095 }
1096
1097 int nouveau_load(struct drm_device *dev, unsigned long flags)
1098 {
1099         struct drm_nouveau_private *dev_priv;
1100         unsigned long long offset, length;
1101         uint32_t reg0 = ~0, strap;
1102         int ret;
1103
1104         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1105         if (!dev_priv) {
1106                 ret = -ENOMEM;
1107                 goto err_out;
1108         }
1109         dev->dev_private = dev_priv;
1110         dev_priv->dev = dev;
1111
1112         pci_set_master(dev->pdev);
1113
1114         dev_priv->flags = flags & NOUVEAU_FLAGS;
1115
1116         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1117                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
1118
1119         /* first up, map the start of mmio and determine the chipset */
1120         dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE);
1121         if (dev_priv->mmio) {
1122 #ifdef __BIG_ENDIAN
1123                 /* put the card into big-endian mode if it's not */
1124                 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1125                         nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1126                 DRM_MEMORYBARRIER();
1127 #endif
1128
1129                 /* determine chipset and derive architecture from it */
1130                 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1131                 if ((reg0 & 0x0f000000) > 0) {
1132                         dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1133                         switch (dev_priv->chipset & 0xf0) {
1134                         case 0x10:
1135                         case 0x20:
1136                         case 0x30:
1137                                 dev_priv->card_type = dev_priv->chipset & 0xf0;
1138                                 break;
1139                         case 0x40:
1140                         case 0x60:
1141                                 dev_priv->card_type = NV_40;
1142                                 break;
1143                         case 0x50:
1144                         case 0x80:
1145                         case 0x90:
1146                         case 0xa0:
1147                                 dev_priv->card_type = NV_50;
1148                                 break;
1149                         case 0xc0:
1150                                 dev_priv->card_type = NV_C0;
1151                                 break;
1152                         case 0xd0:
1153                                 dev_priv->card_type = NV_D0;
1154                                 break;
1155                         case 0xe0:
1156                                 dev_priv->card_type = NV_E0;
1157                                 break;
1158                         default:
1159                                 break;
1160                         }
1161                 } else
1162                 if ((reg0 & 0xff00fff0) == 0x20004000) {
1163                         if (reg0 & 0x00f00000)
1164                                 dev_priv->chipset = 0x05;
1165                         else
1166                                 dev_priv->chipset = 0x04;
1167                         dev_priv->card_type = NV_04;
1168                 }
1169
1170                 iounmap(dev_priv->mmio);
1171         }
1172
1173         if (!dev_priv->card_type) {
1174                 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
1175                 ret = -EINVAL;
1176                 goto err_priv;
1177         }
1178
1179         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1180                      dev_priv->card_type, reg0);
1181
1182         /* map the mmio regs, limiting the amount to preserve vmap space */
1183         offset = pci_resource_start(dev->pdev, 0);
1184         length = pci_resource_len(dev->pdev, 0);
1185         if (dev_priv->card_type < NV_E0)
1186                 length = min(length, (unsigned long long)0x00800000);
1187
1188         dev_priv->mmio = ioremap(offset, length);
1189         if (!dev_priv->mmio) {
1190                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1191                          "Please report your setup to " DRIVER_EMAIL "\n");
1192                 ret = -EINVAL;
1193                 goto err_priv;
1194         }
1195         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", offset);
1196
1197         /* determine frequency of timing crystal */
1198         strap = nv_rd32(dev, 0x101000);
1199         if ( dev_priv->chipset < 0x17 ||
1200             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1201                 strap &= 0x00000040;
1202         else
1203                 strap &= 0x00400040;
1204
1205         switch (strap) {
1206         case 0x00000000: dev_priv->crystal = 13500; break;
1207         case 0x00000040: dev_priv->crystal = 14318; break;
1208         case 0x00400000: dev_priv->crystal = 27000; break;
1209         case 0x00400040: dev_priv->crystal = 25000; break;
1210         }
1211
1212         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1213
1214         /* Determine whether we'll attempt acceleration or not, some
1215          * cards are disabled by default here due to them being known
1216          * non-functional, or never been tested due to lack of hw.
1217          */
1218         dev_priv->noaccel = !!nouveau_noaccel;
1219         if (nouveau_noaccel == -1) {
1220                 switch (dev_priv->chipset) {
1221                 case 0xd9: /* known broken */
1222                         NV_INFO(dev, "acceleration disabled by default, pass "
1223                                      "noaccel=0 to force enable\n");
1224                         dev_priv->noaccel = true;
1225                         break;
1226                 default:
1227                         dev_priv->noaccel = false;
1228                         break;
1229                 }
1230         }
1231
1232         ret = nouveau_remove_conflicting_drivers(dev);
1233         if (ret)
1234                 goto err_mmio;
1235
1236         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1237         if (dev_priv->card_type >= NV_40) {
1238                 int ramin_bar = 2;
1239                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1240                         ramin_bar = 3;
1241
1242                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1243                 dev_priv->ramin =
1244                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
1245                                 dev_priv->ramin_size);
1246                 if (!dev_priv->ramin) {
1247                         NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1248                         ret = -ENOMEM;
1249                         goto err_mmio;
1250                 }
1251         } else {
1252                 dev_priv->ramin_size = 1 * 1024 * 1024;
1253                 dev_priv->ramin = ioremap(offset + NV_RAMIN,
1254                                           dev_priv->ramin_size);
1255                 if (!dev_priv->ramin) {
1256                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1257                         ret = -ENOMEM;
1258                         goto err_mmio;
1259                 }
1260         }
1261
1262         nouveau_OF_copy_vbios_to_ramin(dev);
1263
1264         /* Special flags */
1265         if (dev->pci_device == 0x01a0)
1266                 dev_priv->flags |= NV_NFORCE;
1267         else if (dev->pci_device == 0x01f0)
1268                 dev_priv->flags |= NV_NFORCE2;
1269
1270         /* For kernel modesetting, init card now and bring up fbcon */
1271         ret = nouveau_card_init(dev);
1272         if (ret)
1273                 goto err_ramin;
1274
1275         return 0;
1276
1277 err_ramin:
1278         iounmap(dev_priv->ramin);
1279 err_mmio:
1280         iounmap(dev_priv->mmio);
1281 err_priv:
1282         kfree(dev_priv);
1283         dev->dev_private = NULL;
1284 err_out:
1285         return ret;
1286 }
1287
1288 void nouveau_lastclose(struct drm_device *dev)
1289 {
1290         vga_switcheroo_process_delayed_switch();
1291 }
1292
1293 int nouveau_unload(struct drm_device *dev)
1294 {
1295         struct drm_nouveau_private *dev_priv = dev->dev_private;
1296
1297         nouveau_card_takedown(dev);
1298
1299         iounmap(dev_priv->mmio);
1300         iounmap(dev_priv->ramin);
1301
1302         kfree(dev_priv);
1303         dev->dev_private = NULL;
1304         return 0;
1305 }
1306
1307 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1308                                                 struct drm_file *file_priv)
1309 {
1310         struct drm_nouveau_private *dev_priv = dev->dev_private;
1311         struct drm_nouveau_getparam *getparam = data;
1312
1313         switch (getparam->param) {
1314         case NOUVEAU_GETPARAM_CHIPSET_ID:
1315                 getparam->value = dev_priv->chipset;
1316                 break;
1317         case NOUVEAU_GETPARAM_PCI_VENDOR:
1318                 getparam->value = dev->pci_vendor;
1319                 break;
1320         case NOUVEAU_GETPARAM_PCI_DEVICE:
1321                 getparam->value = dev->pci_device;
1322                 break;
1323         case NOUVEAU_GETPARAM_BUS_TYPE:
1324                 if (drm_pci_device_is_agp(dev))
1325                         getparam->value = NV_AGP;
1326                 else if (pci_is_pcie(dev->pdev))
1327                         getparam->value = NV_PCIE;
1328                 else
1329                         getparam->value = NV_PCI;
1330                 break;
1331         case NOUVEAU_GETPARAM_FB_SIZE:
1332                 getparam->value = dev_priv->fb_available_size;
1333                 break;
1334         case NOUVEAU_GETPARAM_AGP_SIZE:
1335                 getparam->value = dev_priv->gart_info.aper_size;
1336                 break;
1337         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1338                 getparam->value = 0; /* deprecated */
1339                 break;
1340         case NOUVEAU_GETPARAM_PTIMER_TIME:
1341                 getparam->value = dev_priv->engine.timer.read(dev);
1342                 break;
1343         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1344                 getparam->value = 1;
1345                 break;
1346         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1347                 getparam->value = 1;
1348                 break;
1349         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1350                 /* NV40 and NV50 versions are quite different, but register
1351                  * address is the same. User is supposed to know the card
1352                  * family anyway... */
1353                 if (dev_priv->chipset >= 0x40) {
1354                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1355                         break;
1356                 }
1357                 /* FALLTHRU */
1358         default:
1359                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1360                 return -EINVAL;
1361         }
1362
1363         return 0;
1364 }
1365
1366 int
1367 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1368                        struct drm_file *file_priv)
1369 {
1370         struct drm_nouveau_setparam *setparam = data;
1371
1372         switch (setparam->param) {
1373         default:
1374                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1375                 return -EINVAL;
1376         }
1377
1378         return 0;
1379 }
1380
1381 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1382 bool
1383 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1384                 uint32_t reg, uint32_t mask, uint32_t val)
1385 {
1386         struct drm_nouveau_private *dev_priv = dev->dev_private;
1387         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1388         uint64_t start = ptimer->read(dev);
1389
1390         do {
1391                 if ((nv_rd32(dev, reg) & mask) == val)
1392                         return true;
1393         } while (ptimer->read(dev) - start < timeout);
1394
1395         return false;
1396 }
1397
1398 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1399 bool
1400 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1401                 uint32_t reg, uint32_t mask, uint32_t val)
1402 {
1403         struct drm_nouveau_private *dev_priv = dev->dev_private;
1404         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1405         uint64_t start = ptimer->read(dev);
1406
1407         do {
1408                 if ((nv_rd32(dev, reg) & mask) != val)
1409                         return true;
1410         } while (ptimer->read(dev) - start < timeout);
1411
1412         return false;
1413 }
1414
1415 /* Wait until cond(data) == true, up until timeout has hit */
1416 bool
1417 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1418                 bool (*cond)(void *), void *data)
1419 {
1420         struct drm_nouveau_private *dev_priv = dev->dev_private;
1421         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1422         u64 start = ptimer->read(dev);
1423
1424         do {
1425                 if (cond(data) == true)
1426                         return true;
1427         } while (ptimer->read(dev) - start < timeout);
1428
1429         return false;
1430 }
1431
1432 /* Waits for PGRAPH to go completely idle */
1433 bool nouveau_wait_for_idle(struct drm_device *dev)
1434 {
1435         struct drm_nouveau_private *dev_priv = dev->dev_private;
1436         uint32_t mask = ~0;
1437
1438         if (dev_priv->card_type == NV_40)
1439                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1440
1441         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1442                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1443                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1444                 return false;
1445         }
1446
1447         return true;
1448 }
1449