1 /*******************************************************************************
4 Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/init.h>
35 #include <linux/errno.h>
36 #include <linux/ioport.h>
37 #include <linux/pci.h>
38 #include <linux/kernel.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/skbuff.h>
42 #include <linux/delay.h>
43 #include <linux/timer.h>
44 #include <linux/slab.h>
45 #include <linux/interrupt.h>
46 #include <linux/string.h>
47 #include <linux/wait.h>
48 #include <linux/reboot.h>
50 #include <asm/unaligned.h>
51 #include <asm/processor.h>
52 #include <linux/ethtool.h>
53 #include <linux/inetdevice.h>
54 #include <linux/bitops.h>
57 #include <asm/uaccess.h>
59 #include <linux/if_vlan.h>
60 #include <linux/mii.h>
62 #define E100_CABLE_UNKNOWN 0
63 #define E100_CABLE_OK 1
64 #define E100_CABLE_OPEN_NEAR 2 /* Open Circuit Near End */
65 #define E100_CABLE_OPEN_FAR 3 /* Open Circuit Far End */
66 #define E100_CABLE_SHORT_NEAR 4 /* Short Circuit Near End */
67 #define E100_CABLE_SHORT_FAR 5 /* Short Circuit Far End */
69 #define E100_REGS_LEN 2
71 * Configure parameters for buffers per controller.
72 * If the machine this is being used on is a faster machine (i.e. > 150MHz)
73 * and running on a 10MBS network then more queueing of data occurs. This
74 * may indicate the some of the numbers below should be adjusted. Here are
75 * some typical numbers:
78 * The default numbers give work well on most systems tests so no real
79 * adjustments really need to take place. Also, if the machine is connected
80 * to a 100MBS network the numbers described above can be lowered from the
81 * defaults as considerably less data will be queued.
84 #define TX_FRAME_CNT 8 /* consecutive transmit frames per interrupt */
85 /* TX_FRAME_CNT must be less than MAX_TCB */
87 #define E100_DEFAULT_TCB 64
88 #define E100_MIN_TCB 2*TX_FRAME_CNT + 3 /* make room for at least 2 interrupts */
89 #define E100_MAX_TCB 1024
91 #define E100_DEFAULT_RFD 64
92 #define E100_MIN_RFD 8
93 #define E100_MAX_RFD 1024
95 #define E100_DEFAULT_XSUM true
96 #define E100_DEFAULT_BER ZLOCK_MAX_ERRORS
97 #define E100_DEFAULT_SPEED_DUPLEX 0
98 #define E100_DEFAULT_FC 0
99 #define E100_DEFAULT_IFS true
100 #define E100_DEFAULT_UCODE true
105 #define MIN_NUMBER_OF_TRANSMITS_100 1000
106 #define MIN_NUMBER_OF_TRANSMITS_10 100
108 #define E100_MAX_NIC 16
110 #define E100_MAX_SCB_WAIT 100 /* Max udelays in wait_scb */
111 #define E100_MAX_CU_IDLE_WAIT 50 /* Max udelays in wait_cus_idle */
113 /* HWI feature related constant */
114 #define HWI_REGISTER_GRANULARITY 80 /* register granularity = 80 Cm */
115 #define HWI_NEAR_END_BOUNDARY 1000 /* Near end is defined as < 10 meters */
117 /* CPUSAVER_BUNDLE_MAX: Sets the maximum number of frames that will be bundled.
118 * In some situations, such as the TCP windowing algorithm, it may be
119 * better to limit the growth of the bundle size than let it go as
120 * high as it can, because that could cause too much added latency.
121 * The default is six, because this is the number of packets in the
122 * default TCP window size. A value of 1 would make CPUSaver indicate
123 * an interrupt for every frame received. If you do not want to put
124 * a limit on the bundle size, set this value to xFFFF.
126 #define E100_DEFAULT_CPUSAVER_BUNDLE_MAX 6
127 #define E100_DEFAULT_CPUSAVER_INTERRUPT_DELAY 0x600
128 #define E100_DEFAULT_BUNDLE_SMALL_FR false
130 /* end of configurables */
132 /* ====================================================================== */
134 /* ====================================================================== */
136 /* timeout for command completion */
137 #define E100_CMD_WAIT 100 /* iterations */
139 struct driver_stats {
140 struct net_device_stats net_stats;
142 unsigned long tx_late_col;
143 unsigned long tx_ok_defrd;
144 unsigned long tx_one_retry;
145 unsigned long tx_mt_one_retry;
146 unsigned long rcv_cdt_frames;
147 unsigned long xmt_fc_pkts;
148 unsigned long rcv_fc_pkts;
149 unsigned long rcv_fc_unsupported;
150 unsigned long xmt_tco_pkts;
151 unsigned long rcv_tco_pkts;
152 unsigned long rx_intr_pkts;
155 /* TODO: kill me when we can do C99 */
159 /* Changed for 82558 and 82559 enhancements */
160 /* defines for 82558/9 flow control CSR values */
161 #define DFLT_FC_THLD 0x00 /* Rx FIFO threshold of 0.5KB free */
162 #define DFLT_FC_CMD 0x00 /* FC Command in CSR */
164 /* ====================================================================== */
166 /* ====================================================================== */
169 * These are general purpose defines
172 /* Bit Mask definitions */
183 #define BIT_10 0x0400
184 #define BIT_11 0x0800
185 #define BIT_12 0x1000
186 #define BIT_13 0x2000
187 #define BIT_14 0x4000
188 #define BIT_15 0x8000
189 #define BIT_28 0x10000000
191 #define BIT_0_2 0x0007
192 #define BIT_0_3 0x000F
193 #define BIT_0_4 0x001F
194 #define BIT_0_5 0x003F
195 #define BIT_0_6 0x007F
196 #define BIT_0_7 0x00FF
197 #define BIT_0_8 0x01FF
198 #define BIT_0_13 0x3FFF
199 #define BIT_0_15 0xFFFF
200 #define BIT_1_2 0x0006
201 #define BIT_1_3 0x000E
202 #define BIT_2_5 0x003C
203 #define BIT_3_4 0x0018
204 #define BIT_4_5 0x0030
205 #define BIT_4_6 0x0070
206 #define BIT_4_7 0x00F0
207 #define BIT_5_7 0x00E0
208 #define BIT_5_12 0x1FE0
209 #define BIT_5_15 0xFFE0
210 #define BIT_6_7 0x00c0
211 #define BIT_7_11 0x0F80
212 #define BIT_8_10 0x0700
213 #define BIT_9_13 0x3E00
214 #define BIT_12_15 0xF000
215 #define BIT_8_15 0xFF00
217 #define BIT_16_20 0x001F0000
218 #define BIT_21_25 0x03E00000
219 #define BIT_26_27 0x0C000000
221 /* Transmit Threshold related constants */
222 #define DEFAULT_TX_PER_UNDERRUN 20000
224 #define MAX_MULTICAST_ADDRS 64
225 #define MAX_FILTER 16
227 #define FULL_DUPLEX 2
228 #define HALF_DUPLEX 1
231 * These defines are specific to the 82557
234 /* E100 PORT functions -- lower 4 bits */
235 #define PORT_SOFTWARE_RESET 0
236 #define PORT_SELFTEST 1
237 #define PORT_SELECTIVE_RESET 2
240 /* SCB Status Word bit definitions */
241 /* Interrupt status/ack fields */
242 /* ER and FCP interrupts for 82558 masks */
243 #define SCB_STATUS_ACK_MASK BIT_8_15 /* Status Mask */
244 #define SCB_STATUS_ACK_CX BIT_15 /* CU Completed Action Cmd */
245 #define SCB_STATUS_ACK_FR BIT_14 /* RU Received A Frame */
246 #define SCB_STATUS_ACK_CNA BIT_13 /* CU Became Inactive (IDLE) */
247 #define SCB_STATUS_ACK_RNR BIT_12 /* RU Became Not Ready */
248 #define SCB_STATUS_ACK_MDI BIT_11 /* MDI read or write done */
249 #define SCB_STATUS_ACK_SWI BIT_10 /* S/W generated interrupt */
250 #define SCB_STATUS_ACK_ER BIT_9 /* Early Receive */
251 #define SCB_STATUS_ACK_FCP BIT_8 /* Flow Control Pause */
254 #define SCB_CUS_MASK (BIT_6 | BIT_7) /* CUS 2-bit Mask */
255 #define SCB_CUS_IDLE 0 /* CU Idle */
256 #define SCB_CUS_SUSPEND BIT_6 /* CU Suspended */
257 #define SCB_CUS_ACTIVE BIT_7 /* CU Active */
260 #define SCB_RUS_IDLE 0 /* RU Idle */
261 #define SCB_RUS_MASK BIT_2_5 /* RUS 3-bit Mask */
262 #define SCB_RUS_SUSPEND BIT_2 /* RU Suspended */
263 #define SCB_RUS_NO_RESOURCES BIT_3 /* RU Out Of Resources */
264 #define SCB_RUS_READY BIT_4 /* RU Ready */
265 #define SCB_RUS_SUSP_NO_RBDS (BIT_2 | BIT_5) /* RU No More RBDs */
266 #define SCB_RUS_NO_RBDS (BIT_3 | BIT_5) /* RU No More RBDs */
267 #define SCB_RUS_READY_NO_RBDS (BIT_4 | BIT_5) /* RU Ready, No RBDs */
269 /* SCB Command Word bit definitions */
271 /* Changing mask to 4 bits */
272 #define SCB_CUC_MASK BIT_4_7 /* CUC 4-bit Mask */
273 #define SCB_CUC_NOOP 0
274 #define SCB_CUC_START BIT_4 /* CU Start */
275 #define SCB_CUC_RESUME BIT_5 /* CU Resume */
276 #define SCB_CUC_UNKNOWN BIT_7 /* CU unknown command */
277 /* Changed for 82558 enhancements */
278 #define SCB_CUC_STATIC_RESUME (BIT_5 | BIT_7) /* 82558/9 Static Resume */
279 #define SCB_CUC_DUMP_ADDR BIT_6 /* CU Dump Counters Address */
280 #define SCB_CUC_DUMP_STAT (BIT_4 | BIT_6) /* CU Dump stat. counters */
281 #define SCB_CUC_LOAD_BASE (BIT_5 | BIT_6) /* Load the CU base */
282 /* Below was defined as BIT_4_7 */
283 #define SCB_CUC_DUMP_RST_STAT BIT_4_6 /* CU Dump & reset statistics cntrs */
286 #define SCB_RUC_MASK BIT_0_2 /* RUC 3-bit Mask */
287 #define SCB_RUC_START BIT_0 /* RU Start */
288 #define SCB_RUC_RESUME BIT_1 /* RU Resume */
289 #define SCB_RUC_ABORT BIT_2 /* RU Abort */
290 #define SCB_RUC_LOAD_HDS (BIT_0 | BIT_2) /* Load RFD Header Data Size */
291 #define SCB_RUC_LOAD_BASE (BIT_1 | BIT_2) /* Load the RU base */
292 #define SCB_RUC_RBD_RESUME BIT_0_2 /* RBD resume */
294 /* Interrupt fields (assuming byte addressing) */
295 #define SCB_INT_MASK BIT_0 /* Mask interrupts */
296 #define SCB_SOFT_INT BIT_1 /* Generate a S/W interrupt */
297 /* Specific Interrupt Mask Bits (upper byte of SCB Command word) */
298 #define SCB_FCP_INT_MASK BIT_2 /* Flow Control Pause */
299 #define SCB_ER_INT_MASK BIT_3 /* Early Receive */
300 #define SCB_RNR_INT_MASK BIT_4 /* RU Not Ready */
301 #define SCB_CNA_INT_MASK BIT_5 /* CU Not Active */
302 #define SCB_FR_INT_MASK BIT_6 /* Frame Received */
303 #define SCB_CX_INT_MASK BIT_7 /* CU eXecution w/ I-bit done */
304 #define SCB_BACHELOR_INT_MASK BIT_2_7 /* 82558 interrupt mask bits */
306 #define SCB_GCR2_EEPROM_ACCESS_SEMAPHORE BIT_7
308 /* EEPROM bit definitions */
309 /*- EEPROM control register bits */
310 #define EEPROM_FLAG_ASF 0x8000
311 #define EEPROM_FLAG_GCL 0x4000
313 #define EN_TRNF 0x10 /* Enable turnoff */
314 #define EEDO 0x08 /* EEPROM data out */
315 #define EEDI 0x04 /* EEPROM data in (set for writing data) */
316 #define EECS 0x02 /* EEPROM chip select (1=hi, 0=lo) */
317 #define EESK 0x01 /* EEPROM shift clock (1=hi, 0=lo) */
319 /*- EEPROM opcodes */
320 #define EEPROM_READ_OPCODE 06
321 #define EEPROM_WRITE_OPCODE 05
322 #define EEPROM_ERASE_OPCODE 07
323 #define EEPROM_EWEN_OPCODE 19 /* Erase/write enable */
324 #define EEPROM_EWDS_OPCODE 16 /* Erase/write disable */
326 /*- EEPROM data locations */
327 #define EEPROM_NODE_ADDRESS_BYTE_0 0
328 #define EEPROM_COMPATIBILITY_WORD 3
329 #define EEPROM_PWA_NO 8
330 #define EEPROM_ID_WORD 0x0A
331 #define EEPROM_CONFIG_ASF 0x0D
332 #define EEPROM_SMBUS_ADDR 0x90
334 #define EEPROM_SUM 0xbaba
336 // Zero Locking Algorithm definitions:
337 #define ZLOCK_ZERO_MASK 0x00F0
338 #define ZLOCK_MAX_READS 50
339 #define ZLOCK_SET_ZERO 0x2010
340 #define ZLOCK_MAX_SLEEP 300 * HZ
341 #define ZLOCK_MAX_ERRORS 300
343 /* E100 Action Commands */
344 #define CB_IA_ADDRESS 1
345 #define CB_CONFIGURE 2
346 #define CB_MULTICAST 3
347 #define CB_TRANSMIT 4
348 #define CB_LOAD_MICROCODE 5
349 #define CB_LOAD_FILTER 8
350 #define CB_MAX_NONTX_CMD 9
351 #define CB_IPCB_TRANSMIT 9
353 /* Pre-defined Filter Bits */
354 #define CB_FILTER_EL 0x80000000
355 #define CB_FILTER_FIX 0x40000000
356 #define CB_FILTER_ARP 0x08000000
357 #define CB_FILTER_IA_MATCH 0x02000000
359 /* Command Block (CB) Field Definitions */
360 /*- CB Command Word */
361 #define CB_EL_BIT BIT_15 /* CB EL Bit */
362 #define CB_S_BIT BIT_14 /* CB Suspend Bit */
363 #define CB_I_BIT BIT_13 /* CB Interrupt Bit */
364 #define CB_TX_SF_BIT BIT_3 /* TX CB Flexible Mode */
365 #define CB_CMD_MASK BIT_0_3 /* CB 4-bit CMD Mask */
366 #define CB_CID_DEFAULT (0x1f << 8) /* CB 5-bit CID (max value) */
368 /*- CB Status Word */
369 #define CB_STATUS_MASK BIT_12_15 /* CB Status Mask (4-bits) */
370 #define CB_STATUS_COMPLETE BIT_15 /* CB Complete Bit */
371 #define CB_STATUS_OK BIT_13 /* CB OK Bit */
372 #define CB_STATUS_VLAN BIT_12 /* CB Valn detected Bit */
373 #define CB_STATUS_FAIL BIT_11 /* CB Fail (F) Bit */
375 /*misc command bits */
376 #define CB_TX_EOF_BIT BIT_15 /* TX CB/TBD EOF Bit */
379 #define CB_CFIG_BYTE_COUNT 22 /* 22 config bytes */
380 #define CB_CFIG_D102_BYTE_COUNT 10
382 /* Receive Frame Descriptor Fields */
384 /*- RFD Status Bits */
385 #define RFD_RECEIVE_COLLISION BIT_0 /* Collision detected on Receive */
386 #define RFD_IA_MATCH BIT_1 /* Indv Address Match Bit */
387 #define RFD_RX_ERR BIT_4 /* RX_ERR pin on Phy was set */
388 #define RFD_FRAME_TOO_SHORT BIT_7 /* Receive Frame Short */
389 #define RFD_DMA_OVERRUN BIT_8 /* Receive DMA Overrun */
390 #define RFD_NO_RESOURCES BIT_9 /* No Buffer Space */
391 #define RFD_ALIGNMENT_ERROR BIT_10 /* Alignment Error */
392 #define RFD_CRC_ERROR BIT_11 /* CRC Error */
393 #define RFD_STATUS_OK BIT_13 /* RFD OK Bit */
394 #define RFD_STATUS_COMPLETE BIT_15 /* RFD Complete Bit */
396 /*- RFD Command Bits*/
397 #define RFD_EL_BIT BIT_15 /* RFD EL Bit */
398 #define RFD_S_BIT BIT_14 /* RFD Suspend Bit */
399 #define RFD_H_BIT BIT_4 /* Header RFD Bit */
400 #define RFD_SF_BIT BIT_3 /* RFD Flexible Mode */
403 #define RFD_EOF_BIT BIT_15 /* RFD End-Of-Frame Bit */
404 #define RFD_F_BIT BIT_14 /* RFD Buffer Fetch Bit */
405 #define RFD_ACT_COUNT_MASK BIT_0_13 /* RFD Actual Count Mask */
407 /* Receive Buffer Descriptor Fields*/
408 #define RBD_EOF_BIT BIT_15 /* RBD End-Of-Frame Bit */
409 #define RBD_F_BIT BIT_14 /* RBD Buffer Fetch Bit */
410 #define RBD_ACT_COUNT_MASK BIT_0_13 /* RBD Actual Count Mask */
412 #define SIZE_FIELD_MASK BIT_0_13 /* Size of the associated buffer */
413 #define RBD_EL_BIT BIT_15 /* RBD EL Bit */
415 /* Self Test Results*/
416 #define CB_SELFTEST_FAIL_BIT BIT_12
417 #define CB_SELFTEST_DIAG_BIT BIT_5
418 #define CB_SELFTEST_REGISTER_BIT BIT_3
419 #define CB_SELFTEST_ROM_BIT BIT_2
421 #define CB_SELFTEST_ERROR_MASK ( \
422 CB_SELFTEST_FAIL_BIT | CB_SELFTEST_DIAG_BIT | \
423 CB_SELFTEST_REGISTER_BIT | CB_SELFTEST_ROM_BIT)
425 /* adapter vendor & device ids */
426 #define PCI_OHIO_BOARD 0x10f0 /* subdevice ID, Ohio dual port nic */
428 /* Values for PCI_REV_ID_REGISTER values */
429 #define D101A4_REV_ID 4 /* 82558 A4 stepping */
430 #define D101B0_REV_ID 5 /* 82558 B0 stepping */
431 #define D101MA_REV_ID 8 /* 82559 A0 stepping */
432 #define D101S_REV_ID 9 /* 82559S A-step */
433 #define D102_REV_ID 12
434 #define D102C_REV_ID 13 /* 82550 step C */
435 #define D102E_REV_ID 15
437 /* ############Start of 82555 specific defines################## */
439 #define PHY_82555_LED_SWITCH_CONTROL 0x1b /* 82555 led switch control register */
441 /* 82555 led switch control reg. opcodes */
442 #define PHY_82555_LED_NORMAL_CONTROL 0 // control back to the 8255X
443 #define PHY_82555_LED_DRIVER_CONTROL BIT_2 // the driver is in control
444 #define PHY_82555_LED_OFF BIT_2 // activity LED is off
445 #define PHY_82555_LED_ON_559 (BIT_0 | BIT_2) // activity LED is on for 559 and later
446 #define PHY_82555_LED_ON_PRE_559 (BIT_0 | BIT_1 | BIT_2) // activity LED is on for 558 and before
448 // Describe the state of the phy led.
449 // needed for the function : 'e100_blink_timer'
455 /* ############End of 82555 specific defines##################### */
457 #define RFD_PARSE_BIT BIT_3
458 #define RFD_TCP_PACKET 0x00
459 #define RFD_UDP_PACKET 0x01
460 #define TCPUDP_CHECKSUM_BIT_VALID BIT_4
461 #define TCPUDP_CHECKSUM_VALID BIT_5
462 #define CHECKSUM_PROTOCOL_MASK 0x03
465 #define CHKSUM_SIZE 2
466 #define RFD_DATA_SIZE (ETH_FRAME_LEN + CHKSUM_SIZE + VLAN_SIZE)
468 /* Bits for bdp->flags */
469 #define DF_LINK_FC_CAP 0x00000001 /* Link is flow control capable */
470 #define DF_CSUM_OFFLOAD 0x00000002
471 #define DF_UCODE_LOADED 0x00000004
472 #define USE_IPCB 0x00000008 /* set if using ipcb for transmits */
473 #define IS_BACHELOR 0x00000010 /* set if 82558 or newer board */
474 #define IS_ICH 0x00000020
475 #define DF_SPEED_FORCED 0x00000040 /* set if speed is forced */
476 #define LED_IS_ON 0x00000080 /* LED is turned ON by the driver */
477 #define DF_LINK_FC_TX_ONLY 0x00000100 /* Received PAUSE frames are honored*/
479 typedef struct net_device_stats net_dev_stats_t;
482 /* These macros use the bdp pointer. If you use them it better be defined */
483 #define PREV_TCB_USED(X) ((X).tail ? (X).tail - 1 : bdp->params.TxDescriptors - 1)
484 #define NEXT_TCB_TOUSE(X) ((((X) + 1) >= bdp->params.TxDescriptors) ? 0 : (X) + 1)
485 #define TCB_TO_USE(X) ((X).tail)
486 #define TCBS_AVAIL(X) (NEXT_TCB_TOUSE( NEXT_TCB_TOUSE((X).tail)) != (X).head)
488 #define RFD_POINTER(skb,bdp) ((rfd_t *) (((unsigned char *)((skb)->data))-((bdp)->rfd_size)))
489 #define SKB_RFD_STATUS(skb,bdp) ((RFD_POINTER((skb),(bdp)))->rfd_header.cb_status)
491 /* ====================================================================== */
493 /* ====================================================================== */
495 /* Changed for 82558 enhancement */
496 typedef struct _d101_scb_ext_t {
497 u32 scb_rx_dma_cnt; /* Rx DMA byte count */
498 u8 scb_early_rx_int; /* Early Rx DMA byte count */
499 u8 scb_fc_thld; /* Flow Control threshold */
500 u8 scb_fc_xon_xoff; /* Flow Control XON/XOFF values */
501 u8 scb_pmdr; /* Power Mgmt. Driver Reg */
502 } d101_scb_ext __attribute__ ((__packed__));
504 /* Changed for 82559 enhancement */
505 typedef struct _d101m_scb_ext_t {
506 u32 scb_rx_dma_cnt; /* Rx DMA byte count */
507 u8 scb_early_rx_int; /* Early Rx DMA byte count */
508 u8 scb_fc_thld; /* Flow Control threshold */
509 u8 scb_fc_xon_xoff; /* Flow Control XON/XOFF values */
510 u8 scb_pmdr; /* Power Mgmt. Driver Reg */
511 u8 scb_gen_ctrl; /* General Control */
512 u8 scb_gen_stat; /* General Status */
513 u16 scb_reserved; /* Reserved */
514 u32 scb_function_event; /* Cardbus Function Event */
515 u32 scb_function_event_mask; /* Cardbus Function Mask */
516 u32 scb_function_present_state; /* Cardbus Function state */
517 u32 scb_force_event; /* Cardbus Force Event */
518 } d101m_scb_ext __attribute__ ((__packed__));
520 /* Changed for 82550 enhancement */
521 typedef struct _d102_scb_ext_t {
522 u32 scb_rx_dma_cnt; /* Rx DMA byte count */
523 u8 scb_early_rx_int; /* Early Rx DMA byte count */
524 u8 scb_fc_thld; /* Flow Control threshold */
525 u8 scb_fc_xon_xoff; /* Flow Control XON/XOFF values */
526 u8 scb_pmdr; /* Power Mgmt. Driver Reg */
527 u8 scb_gen_ctrl; /* General Control */
528 u8 scb_gen_stat; /* General Status */
530 u8 scb_reserved; /* Reserved */
531 u32 scb_scheduling_reg;
533 u32 scb_function_event; /* Cardbus Function Event */
534 u32 scb_function_event_mask; /* Cardbus Function Mask */
535 u32 scb_function_present_state; /* Cardbus Function state */
536 u32 scb_force_event; /* Cardbus Force Event */
537 } d102_scb_ext __attribute__ ((__packed__));
540 * 82557 status control block. this will be memory mapped & will hang of the
541 * the bdp, which hangs of the bdp. This is the brain of it.
543 typedef struct _scb_t {
544 u16 scb_status; /* SCB Status register */
545 u8 scb_cmd_low; /* SCB Command register (low byte) */
546 u8 scb_cmd_hi; /* SCB Command register (high byte) */
547 u32 scb_gen_ptr; /* SCB General pointer */
548 u32 scb_port; /* PORT register */
549 u16 scb_flsh_cntrl; /* Flash Control register */
550 u16 scb_eprm_cntrl; /* EEPROM control register */
551 u32 scb_mdi_cntrl; /* MDI Control Register */
552 /* Changed for 82558 enhancement */
554 u32 scb_rx_dma_cnt; /* Rx DMA byte count */
555 d101_scb_ext d101_scb; /* 82558/9 specific fields */
556 d101m_scb_ext d101m_scb; /* 82559 specific fields */
557 d102_scb_ext d102_scb;
559 } scb_t __attribute__ ((__packed__));
562 * This is used to dump results of the self test
564 typedef struct _self_test_t {
565 u32 st_sign; /* Self Test Signature */
566 u32 st_result; /* Self Test Results */
567 } self_test_t __attribute__ ((__packed__));
570 * Statistical Counters
573 typedef struct _basic_cntr_t {
574 u32 xmt_gd_frames; /* Good frames transmitted */
575 u32 xmt_max_coll; /* Fatal frames -- had max collisions */
576 u32 xmt_late_coll; /* Fatal frames -- had a late coll. */
577 u32 xmt_uruns; /* Xmit underruns (fatal or re-transmit) */
578 u32 xmt_lost_crs; /* Frames transmitted without CRS */
579 u32 xmt_deferred; /* Deferred transmits */
580 u32 xmt_sngl_coll; /* Transmits that had 1 and only 1 coll. */
581 u32 xmt_mlt_coll; /* Transmits that had multiple coll. */
582 u32 xmt_ttl_coll; /* Transmits that had 1+ collisions. */
583 u32 rcv_gd_frames; /* Good frames received */
584 u32 rcv_crc_errs; /* Aligned frames that had a CRC error */
585 u32 rcv_algn_errs; /* Receives that had alignment errors */
586 u32 rcv_rsrc_err; /* Good frame dropped cuz no resources */
587 u32 rcv_oruns; /* Overrun errors - bus was busy */
588 u32 rcv_err_coll; /* Received frms. that encountered coll. */
589 u32 rcv_shrt_frames; /* Received frames that were to short */
592 /* 82558 extended statistic counters */
593 typedef struct _ext_cntr_t {
596 u32 rcv_fc_unsupported;
599 /* 82559 TCO statistic counters */
600 typedef struct _tco_cntr_t {
605 /* Structures to access thet physical dump area */
606 /* Use one of these types, according to the statisitcal counters mode,
607 to cast the pointer to the physical dump area and access the cmd_complete
610 /* 557-mode : only basic counters + cmd_complete */
611 typedef struct _err_cntr_557_t {
612 basic_cntr_t basic_stats;
616 /* 558-mode : basic + extended counters + cmd_complete */
617 typedef struct _err_cntr_558_t {
618 basic_cntr_t basic_stats;
619 ext_cntr_t extended_stats;
623 /* 559-mode : basic + extended + TCO counters + cmd_complete */
624 typedef struct _err_cntr_559_t {
625 basic_cntr_t basic_stats;
626 ext_cntr_t extended_stats;
627 tco_cntr_t tco_stats;
631 /* This typedef defines the struct needed to hold the largest number of counters */
632 typedef err_cntr_559_t max_counters_t;
634 /* Different statistical-counters mode the controller may be in */
635 typedef enum _stat_mode_t {
636 E100_BASIC_STATS = 0, /* 82557 stats : 16 counters / 16 dw */
637 E100_EXTENDED_STATS, /* 82558 stats : 19 counters / 19 dw */
638 E100_TCO_STATS /* 82559 stats : 21 counters / 20 dw */
641 /* dump statistical counters complete codes */
642 #define DUMP_STAT_COMPLETED 0xA005
643 #define DUMP_RST_STAT_COMPLETED 0xA007
645 /* Command Block (CB) Generic Header Structure*/
646 typedef struct _cb_header_t {
647 u16 cb_status; /* Command Block Status */
648 u16 cb_cmd; /* Command Block Command */
649 u32 cb_lnk_ptr; /* Link To Next CB */
650 } cb_header_t __attribute__ ((__packed__));
652 //* Individual Address Command Block (IA_CB)*/
653 typedef struct _ia_cb_t {
654 cb_header_t ia_cb_hdr;
655 u8 ia_addr[ETH_ALEN];
656 } ia_cb_t __attribute__ ((__packed__));
658 /* Configure Command Block (CONFIG_CB)*/
659 typedef struct _config_cb_t {
660 cb_header_t cfg_cbhdr;
661 u8 cfg_byte[CB_CFIG_BYTE_COUNT + CB_CFIG_D102_BYTE_COUNT];
662 } config_cb_t __attribute__ ((__packed__));
664 /* MultiCast Command Block (MULTICAST_CB)*/
665 typedef struct _multicast_cb_t {
666 cb_header_t mc_cbhdr;
667 u16 mc_count; /* Number of multicast addresses */
668 u8 mc_addr[(ETH_ALEN * MAX_MULTICAST_ADDRS)];
669 } mltcst_cb_t __attribute__ ((__packed__));
671 #define UCODE_MAX_DWORDS 134
672 /* Load Microcode Command Block (LOAD_UCODE_CB)*/
673 typedef struct _load_ucode_cb_t {
674 cb_header_t load_ucode_cbhdr;
675 u32 ucode_dword[UCODE_MAX_DWORDS];
676 } load_ucode_cb_t __attribute__ ((__packed__));
678 /* Load Programmable Filter Data*/
679 typedef struct _filter_cb_t {
680 cb_header_t filter_cb_hdr;
681 u32 filter_data[MAX_FILTER];
682 } filter_cb_t __attribute__ ((__packed__));
684 /* NON_TRANSMIT_CB -- Generic Non-Transmit Command Block
686 typedef struct _nxmit_cb_t {
690 load_ucode_cb_t load_ucode;
691 mltcst_cb_t multicast;
694 } nxmit_cb_t __attribute__ ((__packed__));
696 /*Block for queuing for postponed execution of the non-transmit commands*/
697 typedef struct _nxmit_cb_entry_t {
698 struct list_head list_elem;
699 nxmit_cb_t *non_tx_cmd;
701 unsigned long expiration_time;
704 /* States for postponed non tx commands execution */
705 typedef enum _non_tx_cmd_state_t {
706 E100_NON_TX_IDLE = 0, /* No queued NON-TX commands */
707 E100_WAIT_TX_FINISH, /* Wait for completion of the TX activities */
708 E100_WAIT_NON_TX_FINISH /* Wait for completion of the non TX command */
709 } non_tx_cmd_state_t;
711 /* some defines for the ipcb */
712 #define IPCB_IP_CHECKSUM_ENABLE BIT_4
713 #define IPCB_TCPUDP_CHECKSUM_ENABLE BIT_5
714 #define IPCB_TCP_PACKET BIT_6
715 #define IPCB_LARGESEND_ENABLE BIT_7
716 #define IPCB_HARDWAREPARSING_ENABLE BIT_0
717 #define IPCB_INSERTVLAN_ENABLE BIT_1
718 #define IPCB_IP_ACTIVATION_DEFAULT IPCB_HARDWAREPARSING_ENABLE
720 /* Transmit Buffer Descriptor (TBD)*/
721 typedef struct _tbd_t {
722 u32 tbd_buf_addr; /* Physical Transmit Buffer Address */
723 u16 tbd_buf_cnt; /* Actual Count Of Bytes */
725 } tbd_t __attribute__ ((__packed__));
727 /* d102 specific fields */
728 typedef struct _tcb_ipcb_t {
731 u8 ip_activation_high;
734 u8 tcp_header_offset;
736 u32 sec_rec_phys_addr;
737 u32 tbd_zero_address;
743 u16 total_tcp_payload;
744 } tcb_ipcb_t __attribute__ ((__packed__));
746 #define E100_TBD_ARRAY_SIZE (2+MAX_SKB_FRAGS)
748 /* Transmit Command Block (TCB)*/
751 u32 tcb_tbd_ptr; /* TBD address */
752 u16 tcb_cnt; /* Data Bytes In TCB past header */
753 u8 tcb_thrshld; /* TX Threshold for FIFO Extender */
757 tcb_ipcb_t ipcb; /* d102 ipcb fields */
758 tbd_t tbd_array[E100_TBD_ARRAY_SIZE];
761 /* From here onward we can dump anything we want as long as the
762 * size of the total structure is a multiple of a paragraph
763 * boundary ( i.e. -16 bit aligned ).
767 u32 tcb_tbd_dflt_ptr; /* TBD address for non-segmented packet */
768 u32 tcb_tbd_expand_ptr; /* TBD address for segmented packet */
770 struct sk_buff *tcb_skb; /* the associated socket buffer */
771 dma_addr_t tcb_phys; /* phys addr of the TCB */
772 } __attribute__ ((__packed__));
775 typedef struct _tcb_t tcb_t;
777 /* Receive Frame Descriptor (RFD) - will be using the simple model*/
780 cb_header_t rfd_header;
781 u32 rfd_rbd_ptr; /* Receive Buffer Descriptor Addr */
782 u16 rfd_act_cnt; /* Number Of Bytes Received */
783 u16 rfd_sz; /* Number Of Bytes In RFD */
791 u8 pad[8]; /* data should be 16 byte aligned */
792 u8 data[RFD_DATA_SIZE];
794 } __attribute__ ((__packed__));
797 typedef struct _rfd_t rfd_t;
799 /* Receive Buffer Descriptor (RBD)*/
800 typedef struct _rbd_t {
801 u16 rbd_act_cnt; /* Number Of Bytes Received */
803 u32 rbd_lnk_addr; /* Link To Next RBD */
804 u32 rbd_rcb_addr; /* Receive Buffer Address */
805 u16 rbd_sz; /* Receive Buffer Size */
807 } rbd_t __attribute__ ((__packed__));
810 * This structure is used to maintain a FIFO access to a resource that is
811 * maintained as a circular queue. The resource to be maintained is pointed
812 * to by the "data" field in the structure below. In this driver the TCBs',
813 * TBDs' & RFDs' are maintained as a circular queue & are managed thru this
816 typedef struct _buf_pool_t {
817 unsigned int head; /* index to first used resource */
818 unsigned int tail; /* index to last used resource */
819 void *data; /* points to resource pool */
822 /*Rx skb holding structure*/
823 struct rx_list_elem {
824 struct list_head list_elem;
829 enum next_cu_cmd_e { RESUME_NO_WAIT = 0, RESUME_WAIT, START_WAIT };
830 enum zlock_state_e { ZLOCK_INITIAL, ZLOCK_READING, ZLOCK_SLEEPING };
831 enum tx_queue_stop_type { LONG_STOP = 0, SHORT_STOP };
833 /* 64 bit aligned size */
834 #define E100_SIZE_64A(X) ((sizeof(X) + 7) & ~0x7)
836 typedef struct _bd_dma_able_t {
837 char selftest[E100_SIZE_64A(self_test_t)];
838 char stats_counters[E100_SIZE_64A(max_counters_t)];
841 /* bit masks for bool parameters */
842 #define PRM_XSUMRX 0x00000001
843 #define PRM_UCODE 0x00000002
844 #define PRM_FC 0x00000004
845 #define PRM_IFS 0x00000008
846 #define PRM_BUNDLE_SMALL 0x00000010
849 int e100_speed_duplex;
857 struct ethtool_lpbk_data{
858 dma_addr_t dma_handle;
864 struct e100_private {
865 struct vlan_group *vlgrp;
866 u32 flags; /* board management flags */
867 u32 tx_per_underrun; /* number of good tx frames per underrun */
868 unsigned int tx_count; /* count of tx frames, so we can request an interrupt */
869 u8 tx_thld; /* stores transmit threshold */
871 u32 pwa_no; /* PWA: xxxxxx-0xx */
872 u8 perm_node_address[ETH_ALEN];
873 struct list_head active_rx_list; /* list of rx buffers */
874 struct list_head rx_struct_pool; /* pool of rx buffer struct headers */
875 u16 rfd_size; /* size of the adapter's RFD struct */
876 int skb_req; /* number of skbs neede by the adapter */
877 u8 intr_mask; /* mask for interrupt status */
879 void *dma_able; /* dma allocated structs */
880 dma_addr_t dma_able_phys;
881 self_test_t *selftest; /* pointer to self test area */
882 dma_addr_t selftest_phys; /* phys addr of selftest */
883 max_counters_t *stats_counters; /* pointer to stats table */
884 dma_addr_t stat_cnt_phys; /* phys addr of stat counter area */
886 stat_mode_t stat_mode; /* statistics mode: extended, TCO, basic */
887 scb_t *scb; /* memory mapped ptr to 82557 scb */
889 tcb_t *last_tcb; /* pointer to last tcb sent */
890 buf_pool_t tcb_pool; /* adapter's TCB array */
891 dma_addr_t tcb_phys; /* phys addr of start of TCBs */
896 struct net_device *device;
897 struct pci_dev *pdev;
898 struct driver_stats drv_stats;
900 u8 rev_id; /* adapter PCI revision ID */
902 unsigned int phy_addr; /* address of PHY component */
903 unsigned int PhyId; /* ID of PHY component */
904 unsigned int PhyState; /* state for the fix squelch algorithm */
905 unsigned int PhyDelay; /* delay for the fix squelch algorithm */
907 /* Lock defintions for the driver */
908 spinlock_t bd_lock; /* board lock */
909 spinlock_t bd_non_tx_lock; /* Non transmit command lock */
910 spinlock_t config_lock; /* config block lock */
911 spinlock_t mdi_access_lock; /* mdi lock */
913 struct timer_list watchdog_timer; /* watchdog timer id */
915 /* non-tx commands parameters */
916 struct timer_list nontx_timer_id; /* non-tx timer id */
917 struct list_head non_tx_cmd_list;
918 non_tx_cmd_state_t non_tx_command_state;
919 nxmit_cb_entry_t *same_cmd_entry[CB_MAX_NONTX_CMD];
921 enum next_cu_cmd_e next_cu_cmd;
923 /* Zero Locking Algorithm data members */
924 enum zlock_state_e zlock_state;
925 u8 zlock_read_data[16]; /* number of times each value 0-15 was read */
926 u16 zlock_read_cnt; /* counts number of reads */
927 ulong zlock_sleep_cnt; /* keeps track of "sleep" time */
929 u8 config[CB_CFIG_BYTE_COUNT + CB_CFIG_D102_BYTE_COUNT];
935 struct cfg_params params; /* adapter's command line parameters */
937 u32 speed_duplex_caps; /* adapter's speed/duplex capabilities */
939 /* WOL params for ethtool */
943 struct ethtool_lpbk_data loopback;
944 struct timer_list blink_timer; /* led blink timer id */
955 #define E100_AUTONEG 0
956 #define E100_SPEED_10_HALF 1
957 #define E100_SPEED_10_FULL 2
958 #define E100_SPEED_100_HALF 3
959 #define E100_SPEED_100_FULL 4
961 /********* function prototypes *************/
962 extern int e100_open(struct net_device *);
963 extern int e100_close(struct net_device *);
964 extern void e100_isolate_driver(struct e100_private *bdp);
965 extern unsigned char e100_hw_init(struct e100_private *);
966 extern void e100_sw_reset(struct e100_private *bdp, u32 reset_cmd);
967 extern u8 e100_start_cu(struct e100_private *bdp, tcb_t *tcb);
968 extern void e100_free_non_tx_cmd(struct e100_private *bdp,
969 nxmit_cb_entry_t *non_tx_cmd);
970 extern nxmit_cb_entry_t *e100_alloc_non_tx_cmd(struct e100_private *bdp);
971 extern unsigned char e100_exec_non_cu_cmd(struct e100_private *bdp,
972 nxmit_cb_entry_t *cmd);
973 extern unsigned char e100_selftest(struct e100_private *bdp, u32 *st_timeout,
975 extern unsigned char e100_get_link_state(struct e100_private *bdp);
976 extern unsigned char e100_wait_scb(struct e100_private *bdp);
978 extern void e100_deisolate_driver(struct e100_private *bdp, u8 full_reset);
979 extern unsigned char e100_configure_device(struct e100_private *bdp);
981 extern unsigned char e100_cu_unknown_state(struct e100_private *bdp);
984 #define ROM_TEST_FAIL 0x01
985 #define REGISTER_TEST_FAIL 0x02
986 #define SELF_TEST_FAIL 0x04
987 #define TEST_TIMEOUT 0x08
996 max_test_res, /* must be last */