sound/pci/ens1370.c

   1 /*
   2  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
   3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
   4  *                   Thomas Sailer <sailer@ife.ee.ethz.ch>
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *   GNU General Public License for more details.
  15  *
  16  *   You should have received a copy of the GNU General Public License
  17  *   along with this program; if not, write to the Free Software
  18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  */
  21
  22 #include <sound/driver.h>
  23 #include <asm/io.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/pci.h>
  28 #include <linux/slab.h>
  29 #include <linux/gameport.h>
  30 #include <sound/core.h>
  31 #include <sound/control.h>
  32 #include <sound/pcm.h>
  33 #include <sound/rawmidi.h>
  34 #ifdef CHIP1371
  35 #include <sound/ac97_codec.h>
  36 #else
  37 #include <sound/ak4531_codec.h>
  38 #endif
  39 #define SNDRV_GET_ID
  40 #include <sound/initval.h>
  41 #include <sound/asoundef.h>
  42
  43 #define chip_t ensoniq_t
  44
  45 #ifndef CHIP1371
  46 #undef CHIP1370
  47 #define CHIP1370
  48 #endif
  49
  50 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
  51 MODULE_LICENSE("GPL");
  52 MODULE_CLASSES("{sound}");
  53 #ifdef CHIP1370
  54 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
  55 MODULE_DEVICES("{{Ensoniq,AudioPCI-97 ES1370},"
  56                 "{Creative Labs,SB PCI64/128 (ES1370)}}");
  57 #endif
  58 #ifdef CHIP1371
  59 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
  60 MODULE_DEVICES("{{Ensoniq,AudioPCI ES1371/73},"
  61                 "{Ensoniq,AudioPCI ES1373},"
  62                 "{Creative Labs,Ectiva EV1938},"
  63                 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
  64                 "{Creative Labs,Vibra PCI128},"
  65                 "{Ectiva,EV1938}}");
  66 #endif
  67
  68 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  69 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  70 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  71
  72 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  73 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
  74 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
  75 MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
  76 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
  77 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
  78 MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  79 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
  80 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
  81
  82 #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
  83 #define PCI_DEVICE_ID_ENSONIQ_CT5880    0x5880
  84 #endif
  85 #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
  86 #define PCI_DEVICE_ID_ENSONIQ_ES1371    0x1371
  87 #endif
  88
  89 /* ES1371 chip ID */
  90 /* This is a little confusing because all ES1371 compatible chips have the
  91    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
  92    This is only significant if you want to enable features on the later parts.
  93    Yes, I know it's stupid and why didn't we use the sub IDs?
  94 */
  95 #define ES1371REV_ES1373_A  0x04
  96 #define ES1371REV_ES1373_B  0x06
  97 #define ES1371REV_CT5880_A  0x07
  98 #define CT5880REV_CT5880_C  0x02
  99 #define CT5880REV_CT5880_D  0x03        /* ??? -jk */
 100 #define CT5880REV_CT5880_E  0x04        /* mw */
 101 #define ES1371REV_ES1371_B  0x09
 102 #define EV1938REV_EV1938_A  0x00
 103 #define ES1371REV_ES1373_8  0x08
 104
 105 /*
 106  * Direct registers
 107  */
 108
 109 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
 110
 111 #define ES_REG_CONTROL  0x00    /* R/W: Interrupt/Chip select control register */
 112 #define   ES_1370_ADC_STOP      (1<<31)         /* disable capture buffer transfers */
 113 #define   ES_1370_XCTL1         (1<<30)         /* general purpose output bit */
 114 #define   ES_1373_BYPASS_P1     (1<<31)         /* bypass SRC for PB1 */
 115 #define   ES_1373_BYPASS_P2     (1<<30)         /* bypass SRC for PB2 */
 116 #define   ES_1373_BYPASS_R      (1<<29)         /* bypass SRC for REC */
 117 #define   ES_1373_TEST_BIT      (1<<28)         /* should be set to 0 for normal operation */
 118 #define   ES_1373_RECEN_B       (1<<27)         /* mix record with playback for I2S/SPDIF out */
 119 #define   ES_1373_SPDIF_THRU    (1<<26)         /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
 120 #define   ES_1371_JOY_ASEL(o)   (((o)&0x03)<<24)/* joystick port mapping */
 121 #define   ES_1371_JOY_ASELM     (0x03<<24)      /* mask for above */
 122 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
 123 #define   ES_1371_GPIO_IN(i)    (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
 124 #define   ES_1370_PCLKDIVO(o)   (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
 125 #define   ES_1370_PCLKDIVM      ((0x1fff)<<16)  /* mask for above */
 126 #define   ES_1370_PCLKDIVI(i)   (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
 127 #define   ES_1371_GPIO_OUT(o)   (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
 128 #define   ES_1371_GPIO_OUTM     (0x0f<<16)      /* mask for above */
 129 #define   ES_MSFMTSEL           (1<<15)         /* MPEG serial data format; 0 = SONY, 1 = I2S */
 130 #define   ES_1370_M_SBB         (1<<14)         /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
 131 #define   ES_1371_SYNC_RES      (1<<14)         /* Warm AC97 reset */
 132 #define   ES_1370_WTSRSEL(o)    (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
 133 #define   ES_1370_WTSRSELM      (0x03<<12)      /* mask for above */
 134 #define   ES_1371_ADC_STOP      (1<<13)         /* disable CCB transfer capture information */
 135 #define   ES_1371_PWR_INTRM     (1<<12)         /* power level change interrupts enable */
 136 #define   ES_1370_DAC_SYNC      (1<<11)         /* DAC's are synchronous */
 137 #define   ES_1371_M_CB          (1<<11)         /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
 138 #define   ES_CCB_INTRM          (1<<10)         /* CCB voice interrupts enable */
 139 #define   ES_1370_M_CB          (1<<9)          /* capture clock source; 0 = ADC; 1 = MPEG */
 140 #define   ES_1370_XCTL0         (1<<8)          /* generap purpose output bit */
 141 #define   ES_1371_PDLEV(o)      (((o)&0x03)<<8) /* current power down level */
 142 #define   ES_1371_PDLEVM        (0x03<<8)       /* mask for above */
 143 #define   ES_BREQ               (1<<7)          /* memory bus request enable */
 144 #define   ES_DAC1_EN            (1<<6)          /* DAC1 playback channel enable */
 145 #define   ES_DAC2_EN            (1<<5)          /* DAC2 playback channel enable */
 146 #define   ES_ADC_EN             (1<<4)          /* ADC capture channel enable */
 147 #define   ES_UART_EN            (1<<3)          /* UART enable */
 148 #define   ES_JYSTK_EN           (1<<2)          /* Joystick module enable */
 149 #define   ES_1370_CDC_EN        (1<<1)          /* Codec interface enable */
 150 #define   ES_1371_XTALCKDIS     (1<<1)          /* Xtal clock disable */
 151 #define   ES_1370_SERR_DISABLE  (1<<0)          /* PCI serr signal disable */
 152 #define   ES_1371_PCICLKDIS     (1<<0)          /* PCI clock disable */
 153 #define ES_REG_STATUS   0x04    /* R/O: Interrupt/Chip select status register */
 154 #define   ES_INTR               (1<<31)         /* Interrupt is pending */
 155 #define   ES_1371_ST_AC97_RST   (1<<29)         /* CT5880 AC'97 Reset bit */
 156 #define   ES_1373_REAR_BIT27    (1<<27)         /* rear bits: 000 - front, 010 - mirror, 101 - separate */
 157 #define   ES_1373_REAR_BIT26    (1<<26)
 158 #define   ES_1373_REAR_BIT24    (1<<24)
 159 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
 160 #define   ES_1373_SPDIF_EN      (1<<18)         /* SPDIF enable */
 161 #define   ES_1373_SPDIF_TEST    (1<<17)         /* SPDIF test */
 162 #define   ES_1371_TEST          (1<<16)         /* test ASIC */
 163 #define   ES_1373_GPIO_INT(i)   (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
 164 #define   ES_1370_CSTAT         (1<<10)         /* CODEC is busy or register write in progress */
 165 #define   ES_1370_CBUSY         (1<<9)          /* CODEC is busy */
 166 #define   ES_1370_CWRIP         (1<<8)          /* CODEC register write in progress */
 167 #define   ES_1371_SYNC_ERR      (1<<8)          /* CODEC synchronization error occurred */
 168 #define   ES_1371_VC(i)         (((i)>>6)&0x03) /* voice code from CCB module */
 169 #define   ES_1370_VC(i)         (((i)>>5)&0x03) /* voice code from CCB module */
 170 #define   ES_1371_MPWR          (1<<5)          /* power level interrupt pending */
 171 #define   ES_MCCB               (1<<4)          /* CCB interrupt pending */
 172 #define   ES_UART               (1<<3)          /* UART interrupt pending */
 173 #define   ES_DAC1               (1<<2)          /* DAC1 channel interrupt pending */
 174 #define   ES_DAC2               (1<<1)          /* DAC2 channel interrupt pending */
 175 #define   ES_ADC                (1<<0)          /* ADC channel interrupt pending */
 176 #define ES_REG_UART_DATA 0x08   /* R/W: UART data register */
 177 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
 178 #define   ES_RXINT              (1<<7)          /* RX interrupt occurred */
 179 #define   ES_TXINT              (1<<2)          /* TX interrupt occurred */
 180 #define   ES_TXRDY              (1<<1)          /* transmitter ready */
 181 #define   ES_RXRDY              (1<<0)          /* receiver ready */
 182 #define ES_REG_UART_CONTROL 0x09        /* W/O: UART control register */
 183 #define   ES_RXINTEN            (1<<7)          /* RX interrupt enable */
 184 #define   ES_TXINTENO(o)        (((o)&0x03)<<5) /* TX interrupt enable */
 185 #define   ES_TXINTENM           (0x03<<5)       /* mask for above */
 186 #define   ES_TXINTENI(i)        (((i)>>5)&0x03)
 187 #define   ES_CNTRL(o)           (((o)&0x03)<<0) /* control */
 188 #define   ES_CNTRLM             (0x03<<0)       /* mask for above */
 189 #define ES_REG_UART_RES 0x0a    /* R/W: UART reserver register */
 190 #define   ES_TEST_MODE          (1<<0)          /* test mode enabled */
 191 #define ES_REG_MEM_PAGE 0x0c    /* R/W: Memory page register */
 192 #define   ES_MEM_PAGEO(o)       (((o)&0x0f)<<0) /* memory page select - out */
 193 #define   ES_MEM_PAGEM          (0x0f<<0)       /* mask for above */
 194 #define   ES_MEM_PAGEI(i)       (((i)>>0)&0x0f) /* memory page select - in */
 195 #define ES_REG_1370_CODEC 0x10  /* W/O: Codec write register address */
 196 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
 197 #define ES_REG_1371_CODEC 0x14  /* W/R: Codec Read/Write register address */
 198 #define   ES_1371_CODEC_RDY        (1<<31)      /* codec ready */
 199 #define   ES_1371_CODEC_WIP        (1<<30)      /* codec register access in progress */
 200 #define   ES_1371_CODEC_PIRD       (1<<23)      /* codec read/write select register */
 201 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
 202 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
 203 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
 204
 205 #define ES_REG_1371_SMPRATE 0x10        /* W/R: Codec rate converter interface register */
 206 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
 207 #define   ES_1371_SRC_RAM_ADDRM    (0x7f<<25)   /* mask for above */
 208 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
 209 #define   ES_1371_SRC_RAM_WE       (1<<24)      /* R/W: read/write control for sample rate converter */
 210 #define   ES_1371_SRC_RAM_BUSY     (1<<23)      /* R/O: sample rate memory is busy */
 211 #define   ES_1371_SRC_DISABLE      (1<<22)      /* sample rate converter disable */
 212 #define   ES_1371_DIS_P1           (1<<21)      /* playback channel 1 accumulator update disable */
 213 #define   ES_1371_DIS_P2           (1<<20)      /* playback channel 1 accumulator update disable */
 214 #define   ES_1371_DIS_R1           (1<<19)      /* capture channel accumulator update disable */
 215 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
 216 #define   ES_1371_SRC_RAM_DATAM    (0xffff<<0)  /* mask for above */
 217 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
 218
 219 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
 220 #define   ES_1371_JFAST         (1<<31)         /* fast joystick timing */
 221 #define   ES_1371_HIB           (1<<30)         /* host interrupt blocking enable */
 222 #define   ES_1371_VSB           (1<<29)         /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
 223 #define   ES_1371_VMPUO(o)      (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
 224 #define   ES_1371_VMPUM         (0x03<<27)      /* mask for above */
 225 #define   ES_1371_VMPUI(i)      (((i)>>27)&0x03)/* base register address */
 226 #define   ES_1371_VCDCO(o)      (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
 227 #define   ES_1371_VCDCM         (0x03<<25)      /* mask for above */
 228 #define   ES_1371_VCDCI(i)      (((i)>>25)&0x03)/* CODEC address */
 229 #define   ES_1371_FIRQ          (1<<24)         /* force an interrupt */
 230 #define   ES_1371_SDMACAP       (1<<23)         /* enable event capture for slave DMA controller */
 231 #define   ES_1371_SPICAP        (1<<22)         /* enable event capture for slave IRQ controller */
 232 #define   ES_1371_MDMACAP       (1<<21)         /* enable event capture for master DMA controller */
 233 #define   ES_1371_MPICAP        (1<<20)         /* enable event capture for master IRQ controller */
 234 #define   ES_1371_ADCAP         (1<<19)         /* enable event capture for ADLIB register; 0x388xH */
 235 #define   ES_1371_SVCAP         (1<<18)         /* enable event capture for SB registers */
 236 #define   ES_1371_CDCCAP        (1<<17)         /* enable event capture for CODEC registers */
 237 #define   ES_1371_BACAP         (1<<16)         /* enable event capture for SoundScape base address */
 238 #define   ES_1371_EXI(i)        (((i)>>8)&0x07) /* event number */
 239 #define   ES_1371_AI(i)         (((i)>>3)&0x1f) /* event significant I/O address */
 240 #define   ES_1371_WR            (1<<2)  /* event capture; 0 = read; 1 = write */
 241 #define   ES_1371_LEGINT        (1<<0)  /* interrupt for legacy events; 0 = interrupt did occur */
 242
 243 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
 244
 245 #define ES_REG_SERIAL   0x20    /* R/W: Serial interface control register */
 246 #define   ES_1371_DAC_TEST      (1<<22)         /* DAC test mode enable */
 247 #define   ES_P2_END_INCO(o)     (((o)&0x07)<<19)/* binary offset value to increment / loop end */
 248 #define   ES_P2_END_INCM        (0x07<<19)      /* mask for above */
 249 #define   ES_P2_END_INCI(i)     (((i)>>16)&0x07)/* binary offset value to increment / loop end */
 250 #define   ES_P2_ST_INCO(o)      (((o)&0x07)<<16)/* binary offset value to increment / start */
 251 #define   ES_P2_ST_INCM         (0x07<<16)      /* mask for above */
 252 #define   ES_P2_ST_INCI(i)      (((i)<<16)&0x07)/* binary offset value to increment / start */
 253 #define   ES_R1_LOOP_SEL        (1<<15)         /* ADC; 0 - loop mode; 1 = stop mode */
 254 #define   ES_P2_LOOP_SEL        (1<<14)         /* DAC2; 0 - loop mode; 1 = stop mode */
 255 #define   ES_P1_LOOP_SEL        (1<<13)         /* DAC1; 0 - loop mode; 1 = stop mode */
 256 #define   ES_P2_PAUSE           (1<<12)         /* DAC2; 0 - play mode; 1 = pause mode */
 257 #define   ES_P1_PAUSE           (1<<11)         /* DAC1; 0 - play mode; 1 = pause mode */
 258 #define   ES_R1_INT_EN          (1<<10)         /* ADC interrupt enable */
 259 #define   ES_P2_INT_EN          (1<<9)          /* DAC2 interrupt enable */
 260 #define   ES_P1_INT_EN          (1<<8)          /* DAC1 interrupt enable */
 261 #define   ES_P1_SCT_RLD         (1<<7)          /* force sample counter reload for DAC1 */
 262 #define   ES_P2_DAC_SEN         (1<<6)          /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
 263 #define   ES_R1_MODEO(o)        (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
 264 #define   ES_R1_MODEM           (0x03<<4)       /* mask for above */
 265 #define   ES_R1_MODEI(i)        (((i)>>4)&0x03)
 266 #define   ES_P2_MODEO(o)        (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
 267 #define   ES_P2_MODEM           (0x03<<2)       /* mask for above */
 268 #define   ES_P2_MODEI(i)        (((i)>>2)&0x03)
 269 #define   ES_P1_MODEO(o)        (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
 270 #define   ES_P1_MODEM           (0x03<<0)       /* mask for above */
 271 #define   ES_P1_MODEI(i)        (((i)>>0)&0x03)
 272
 273 #define ES_REG_DAC1_COUNT 0x24  /* R/W: DAC1 sample count register */
 274 #define ES_REG_DAC2_COUNT 0x28  /* R/W: DAC2 sample count register */
 275 #define ES_REG_ADC_COUNT  0x2c  /* R/W: ADC sample count register */
 276 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
 277 #define   ES_REG_COUNTO(o)      (((o)&0xffff)<<0)
 278 #define   ES_REG_COUNTM         (0xffff<<0)
 279 #define   ES_REG_COUNTI(i)      (((i)>>0)&0xffff)
 280
 281 #define ES_REG_DAC1_FRAME 0x30  /* R/W: PAGE 0x0c; DAC1 frame address */
 282 #define ES_REG_DAC1_SIZE  0x34  /* R/W: PAGE 0x0c; DAC1 frame size */
 283 #define ES_REG_DAC2_FRAME 0x38  /* R/W: PAGE 0x0c; DAC2 frame address */
 284 #define ES_REG_DAC2_SIZE  0x3c  /* R/W: PAGE 0x0c; DAC2 frame size */
 285 #define ES_REG_ADC_FRAME  0x30  /* R/W: PAGE 0x0d; ADC frame address */
 286 #define ES_REG_ADC_SIZE   0x34  /* R/W: PAGE 0x0d; ADC frame size */
 287 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
 288 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
 289 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
 290 #define   ES_REG_FSIZEO(o)       (((o)&0xffff)<<0)
 291 #define   ES_REG_FSIZEM          (0xffff<<0)
 292 #define   ES_REG_FSIZEI(i)       (((i)>>0)&0xffff)
 293 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
 294 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
 295
 296 #define ES_REG_UART_FIFO  0x30  /* R/W: PAGE 0x0e; UART FIFO register */
 297 #define   ES_REG_UF_VALID        (1<<8)
 298 #define   ES_REG_UF_BYTEO(o)     (((o)&0xff)<<0)
 299 #define   ES_REG_UF_BYTEM        (0xff<<0)
 300 #define   ES_REG_UF_BYTEI(i)     (((i)>>0)&0xff)
 301
 302
 303 /*
 304  *  Pages
 305  */
 306
 307 #define ES_PAGE_DAC     0x0c
 308 #define ES_PAGE_ADC     0x0d
 309 #define ES_PAGE_UART    0x0e
 310 #define ES_PAGE_UART1   0x0f
 311
 312 /*
 313  *  Sample rate converter addresses
 314  */
 315
 316 #define ES_SMPREG_DAC1          0x70
 317 #define ES_SMPREG_DAC2          0x74
 318 #define ES_SMPREG_ADC           0x78
 319 #define ES_SMPREG_VOL_ADC       0x6c
 320 #define ES_SMPREG_VOL_DAC1      0x7c
 321 #define ES_SMPREG_VOL_DAC2      0x7e
 322 #define ES_SMPREG_TRUNC_N       0x00
 323 #define ES_SMPREG_INT_REGS      0x01
 324 #define ES_SMPREG_ACCUM_FRAC    0x02
 325 #define ES_SMPREG_VFREQ_FRAC    0x03
 326
 327 /*
 328  *  Some contants
 329  */
 330
 331 #define ES_1370_SRCLOCK    1411200
 332 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
 333
 334 /*
 335  *  Open modes
 336  */
 337
 338 #define ES_MODE_PLAY1   0x0001
 339 #define ES_MODE_PLAY2   0x0002
 340 #define ES_MODE_CAPTURE 0x0004
 341
 342 #define ES_MODE_OUTPUT  0x0001  /* for MIDI */
 343 #define ES_MODE_INPUT   0x0002  /* for MIDI */
 344
 345 /*
 346
 347  */
 348
 349 typedef struct _snd_ensoniq ensoniq_t;
 350
 351 struct _snd_ensoniq {
 352         spinlock_t reg_lock;
 353
 354         int irq;
 355
 356         unsigned long playback1size;
 357         unsigned long playback2size;
 358         unsigned long capture3size;
 359
 360         unsigned long port;
 361         struct resource *res_port;
 362         unsigned int mode;
 363         unsigned int uartm;     /* UART mode */
 364
 365         unsigned int ctrl;      /* control register */
 366         unsigned int sctrl;     /* serial control register */
 367         unsigned int cssr;      /* control status register */
 368         unsigned int uartc;     /* uart control register */
 369         unsigned int rev;       /* chip revision */
 370
 371         union {
 372 #ifdef CHIP1371
 373                 struct {
 374                         ac97_t *ac97;
 375                 } es1371;
 376 #else
 377                 struct {
 378                         int pclkdiv_lock;
 379                         ak4531_t *ak4531;
 380                 } es1370;
 381 #endif
 382         } u;
 383
 384         struct pci_dev *pci;
 385         unsigned short subsystem_vendor_id;
 386         unsigned short subsystem_device_id;
 387         snd_card_t *card;
 388         snd_pcm_t *pcm1;        /* DAC1/ADC PCM */
 389         snd_pcm_t *pcm2;        /* DAC2 PCM */
 390         snd_pcm_substream_t *playback1_substream;
 391         snd_pcm_substream_t *playback2_substream;
 392         snd_pcm_substream_t *capture_substream;
 393         unsigned int p1_dma_size;
 394         unsigned int p2_dma_size;
 395         unsigned int c_dma_size;
 396         unsigned int p1_period_size;
 397         unsigned int p2_period_size;
 398         unsigned int c_period_size;
 399         snd_rawmidi_t *rmidi;
 400         snd_rawmidi_substream_t *midi_input;
 401         snd_rawmidi_substream_t *midi_output;
 402
 403         unsigned int spdif;
 404         unsigned int spdif_default;
 405         unsigned int spdif_stream;
 406
 407 #ifdef CHIP1370
 408         unsigned char *bugbuf;
 409         dma_addr_t bugbuf_addr;
 410 #endif
 411
 412 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
 413         struct gameport gameport;
 414         struct semaphore joy_sem;       // gameport configuration semaphore
 415 #endif
 416 };
 417
 418 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 419
 420 static struct pci_device_id snd_audiopci_ids[] = {
 421 #ifdef CHIP1370
 422         { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1370 */
 423 #endif
 424 #ifdef CHIP1371
 425         { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1371 */
 426         { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1373 - CT5880 */
 427         { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* Ectiva EV1938 */
 428 #endif
 429         { 0, }
 430 };
 431
 432 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
 433
 434 /*
 435  *  constants
 436  */
 437
 438 #define POLL_COUNT      0xa000
 439
 440 #ifdef CHIP1370
 441 static unsigned int snd_es1370_fixed_rates[] =
 442         {5512, 11025, 22050, 44100};
 443 static snd_pcm_hw_constraint_list_t snd_es1370_hw_constraints_rates = {
 444         .count = 4,
 445         .list = snd_es1370_fixed_rates,
 446         .mask = 0,
 447 };
 448 static ratnum_t es1370_clock = {
 449         .num = ES_1370_SRCLOCK,
 450         .den_min = 29,
 451         .den_max = 353,
 452         .den_step = 1,
 453 };
 454 static snd_pcm_hw_constraint_ratnums_t snd_es1370_hw_constraints_clock = {
 455         .nrats = 1,
 456         .rats = &es1370_clock,
 457 };
 458 #else
 459 static ratden_t es1371_dac_clock = {
 460         .num_min = 3000 * (1 << 15),
 461         .num_max = 48000 * (1 << 15),
 462         .num_step = 3000,
 463         .den = 1 << 15,
 464 };
 465 static snd_pcm_hw_constraint_ratdens_t snd_es1371_hw_constraints_dac_clock = {
 466         .nrats = 1,
 467         .rats = &es1371_dac_clock,
 468 };
 469 static ratnum_t es1371_adc_clock = {
 470         .num = 48000 << 15,
 471         .den_min = 32768,
 472         .den_max = 393216,
 473         .den_step = 1,
 474 };
 475 static snd_pcm_hw_constraint_ratnums_t snd_es1371_hw_constraints_adc_clock = {
 476         .nrats = 1,
 477         .rats = &es1371_adc_clock,
 478 };
 479 #endif
 480 static const unsigned int snd_ensoniq_sample_shift[] =
 481         {0, 1, 1, 2};
 482
 483 /*
 484  *  common I/O routines
 485  */
 486
 487 #ifdef CHIP1371
 488
 489 static unsigned int snd_es1371_wait_src_ready(ensoniq_t * ensoniq)
 490 {
 491         unsigned int t, r = 0;
 492
 493         for (t = 0; t < POLL_COUNT; t++) {
 494                 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
 495                 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
 496                         return r;
 497         }
 498         snd_printk("wait source ready timeout 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_SMPRATE), r);
 499         return 0;
 500 }
 501
 502 static unsigned int snd_es1371_src_read(ensoniq_t * ensoniq, unsigned short reg)
 503 {
 504         unsigned int temp, i, orig, r;
 505
 506         /* wait for ready */
 507         temp = orig = snd_es1371_wait_src_ready(ensoniq);
 508
 509         /* expose the SRC state bits */
 510         r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 511                     ES_1371_DIS_P2 | ES_1371_DIS_R1);
 512         r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
 513         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 514
 515         /* now, wait for busy and the correct time to read */
 516         temp = snd_es1371_wait_src_ready(ensoniq);
 517
 518         if ((temp & 0x00870000) != 0x00010000) {
 519                 /* wait for the right state */
 520                 for (i = 0; i < POLL_COUNT; i++) {
 521                         temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
 522                         if ((temp & 0x00870000) == 0x00010000)
 523                                 break;
 524                 }
 525         }
 526
 527         /* hide the state bits */
 528         r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 529                    ES_1371_DIS_P2 | ES_1371_DIS_R1);
 530         r |= ES_1371_SRC_RAM_ADDRO(reg);
 531         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 532
 533         return temp;
 534 }
 535
 536 static void snd_es1371_src_write(ensoniq_t * ensoniq,
 537                                  unsigned short reg, unsigned short data)
 538 {
 539         unsigned int r;
 540
 541         r = snd_es1371_wait_src_ready(ensoniq) &
 542             (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 543              ES_1371_DIS_P2 | ES_1371_DIS_R1);
 544         r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
 545         outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
 546 }
 547
 548 #endif /* CHIP1371 */
 549
 550 #ifdef CHIP1370
 551
 552 static void snd_es1370_codec_write(ak4531_t *ak4531,
 553                                    unsigned short reg, unsigned short val)
 554 {
 555         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, ak4531->private_data, return);
 556         unsigned long flags;
 557         unsigned long end_time = jiffies + HZ / 10;
 558
 559 #if 0
 560         printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 561 #endif
 562         do {
 563                 spin_lock_irqsave(&ensoniq->reg_lock, flags);
 564                 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
 565                         outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 566                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 567                         return;
 568                 }
 569                 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 570 #if 0
 571                 set_current_state(TASK_UNINTERRUPTIBLE);
 572                 schedule_timeout(1);
 573 #endif
 574         } while (time_after(end_time, jiffies));
 575         snd_printk("codec write timeout, status = 0x%x\n", inl(ES_REG(ensoniq, STATUS)));
 576 }
 577
 578 #endif /* CHIP1370 */
 579
 580 #ifdef CHIP1371
 581
 582 static void snd_es1371_codec_write(ac97_t *ac97,
 583                                    unsigned short reg, unsigned short val)
 584 {
 585         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, ac97->private_data, return);
 586         unsigned long flags;
 587         unsigned int t, x;
 588
 589         for (t = 0; t < POLL_COUNT; t++) {
 590                 spin_lock_irqsave(&ensoniq->reg_lock, flags);
 591                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 592                         /* save the current state for latter */
 593                         x = snd_es1371_wait_src_ready(ensoniq);
 594                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 595                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 596                              ES_REG(ensoniq, 1371_SMPRATE));
 597                         /* wait for not busy (state 0) first to avoid
 598                            transition states */
 599                         for (t = 0; t < POLL_COUNT; t++) {
 600                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
 601                                         break;
 602                         }
 603                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 604                         for (t = 0; t < POLL_COUNT; t++) {
 605                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
 606                                         break;
 607                         }
 608                         outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
 609                         /* restore SRC reg */
 610                         snd_es1371_wait_src_ready(ensoniq);
 611                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 612                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 613                         return;
 614                 }
 615                 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 616         }
 617         snd_printk("codec write timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 618 }
 619
 620 static unsigned short snd_es1371_codec_read(ac97_t *ac97,
 621                                             unsigned short reg)
 622 {
 623         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, ac97->private_data, return -ENXIO);
 624         unsigned long flags;
 625         unsigned int t, x, fail = 0;
 626
 627       __again:
 628         for (t = 0; t < POLL_COUNT; t++) {
 629                 spin_lock_irqsave(&ensoniq->reg_lock, flags);
 630                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 631                         /* save the current state for latter */
 632                         x = snd_es1371_wait_src_ready(ensoniq);
 633                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 634                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 635                              ES_REG(ensoniq, 1371_SMPRATE));
 636                         /* wait for not busy (state 0) first to avoid
 637                            transition states */
 638                         for (t = 0; t < POLL_COUNT; t++) {
 639                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
 640                                         break;
 641                         }
 642                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 643                         for (t = 0; t < POLL_COUNT; t++) {
 644                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
 645                                         break;
 646                         }
 647                         outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
 648                         /* restore SRC reg */
 649                         snd_es1371_wait_src_ready(ensoniq);
 650                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 651                         /* wait for WIP again */
 652                         for (t = 0; t < POLL_COUNT; t++) {
 653                                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
 654                                         break;
 655                         }
 656                         /* now wait for the stinkin' data (RDY) */
 657                         for (t = 0; t < POLL_COUNT; t++) {
 658                                 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
 659                                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 660                                         return ES_1371_CODEC_READ(x);
 661                                 }
 662                         }
 663                         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 664                         if (++fail > 10) {
 665                                 snd_printk("codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), reg, inl(ES_REG(ensoniq, 1371_CODEC)));
 666                                 return 0;
 667                         }
 668                         goto __again;
 669                 }
 670                 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 671         }
 672         snd_printk("es1371: codec read timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 673         return 0;
 674 }
 675
 676 static void snd_es1371_adc_rate(ensoniq_t * ensoniq, unsigned int rate)
 677 {
 678         unsigned int n, truncm, freq, result;
 679
 680         n = rate / 3000;
 681         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
 682                 n--;
 683         truncm = (21 * n - 1) | 1;
 684         freq = ((48000UL << 15) / rate) * n;
 685         result = (48000UL << 15) / (freq / n);
 686         if (rate >= 24000) {
 687                 if (truncm > 239)
 688                         truncm = 239;
 689                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 690                                 (((239 - truncm) >> 1) << 9) | (n << 4));
 691         } else {
 692                 if (truncm > 119)
 693                         truncm = 119;
 694                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 695                                 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
 696         }
 697         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
 698                              (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS) & 0x00ff) |
 699                                      ((freq >> 5) & 0xfc00));
 700         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 701         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
 702         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
 703 }
 704
 705 static void snd_es1371_dac1_rate(ensoniq_t * ensoniq, unsigned int rate)
 706 {
 707         unsigned int freq, r;
 708
 709         freq = ((rate << 15) + 1500) / 3000;
 710         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1)) | ES_1371_DIS_P1;
 711         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 712         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
 713                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS) & 0x00ff) |
 714                              ((freq >> 5) & 0xfc00));
 715         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 716         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1));
 717         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 718 }
 719
 720 static void snd_es1371_dac2_rate(ensoniq_t * ensoniq, unsigned int rate)
 721 {
 722         unsigned int freq, r;
 723
 724         freq = ((rate << 15) + 1500) / 3000;
 725         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1)) | ES_1371_DIS_P2;
 726         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 727         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
 728                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS) & 0x00ff) |
 729                              ((freq >> 5) & 0xfc00));
 730         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 731         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1));
 732         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 733 }
 734
 735 #endif /* CHIP1371 */
 736
 737 static int snd_ensoniq_trigger(snd_pcm_substream_t *substream, int cmd)
 738 {
 739         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 740         switch (cmd) {
 741         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 742         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 743         {
 744                 unsigned int what = 0;
 745                 struct list_head *pos;
 746                 snd_pcm_substream_t *s;
 747                 snd_pcm_group_for_each(pos, substream) {
 748                         s = snd_pcm_group_substream_entry(pos);
 749                         if (s == ensoniq->playback1_substream) {
 750                                 what |= ES_P1_PAUSE;
 751                                 snd_pcm_trigger_done(s, substream);
 752                         } else if (s == ensoniq->playback2_substream) {
 753                                 what |= ES_P2_PAUSE;
 754                                 snd_pcm_trigger_done(s, substream);
 755                         } else if (s == ensoniq->capture_substream)
 756                                 return -EINVAL;
 757                 }
 758                 spin_lock(&ensoniq->reg_lock);
 759                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 760                         ensoniq->sctrl |= what;
 761                 else
 762                         ensoniq->sctrl &= ~what;
 763                 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 764                 spin_unlock(&ensoniq->reg_lock);
 765                 break;
 766         }
 767         case SNDRV_PCM_TRIGGER_START:
 768         case SNDRV_PCM_TRIGGER_STOP:
 769         {
 770                 unsigned int what = 0;
 771                 struct list_head *pos;
 772                 snd_pcm_substream_t *s;
 773                 snd_pcm_group_for_each(pos, substream) {
 774                         s = snd_pcm_group_substream_entry(pos);
 775                         if (s == ensoniq->playback1_substream) {
 776                                 what |= ES_DAC1_EN;
 777                                 snd_pcm_trigger_done(s, substream);
 778                         } else if (s == ensoniq->playback2_substream) {
 779                                 what |= ES_DAC2_EN;
 780                                 snd_pcm_trigger_done(s, substream);
 781                         } else if (s == ensoniq->capture_substream) {
 782                                 what |= ES_ADC_EN;
 783                                 snd_pcm_trigger_done(s, substream);
 784                         }
 785                 }
 786                 spin_lock(&ensoniq->reg_lock);
 787                 if (cmd == SNDRV_PCM_TRIGGER_START)
 788                         ensoniq->ctrl |= what;
 789                 else
 790                         ensoniq->ctrl &= ~what;
 791                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 792                 spin_unlock(&ensoniq->reg_lock);
 793                 break;
 794         }
 795         default:
 796                 return -EINVAL;
 797         }
 798         return 0;
 799 }
 800
 801 /*
 802  *  PCM part
 803  */
 804
 805 static int snd_ensoniq_hw_params(snd_pcm_substream_t * substream,
 806                                  snd_pcm_hw_params_t * hw_params)
 807 {
 808         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 809 }
 810
 811 static int snd_ensoniq_hw_free(snd_pcm_substream_t * substream)
 812 {
 813         return snd_pcm_lib_free_pages(substream);
 814 }
 815
 816 static int snd_ensoniq_playback1_prepare(snd_pcm_substream_t * substream)
 817 {
 818         unsigned long flags;
 819         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 820         snd_pcm_runtime_t *runtime = substream->runtime;
 821         unsigned int mode = 0;
 822
 823         ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
 824         ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
 825         if (snd_pcm_format_width(runtime->format) == 16)
 826                 mode |= 0x02;
 827         if (runtime->channels > 1)
 828                 mode |= 0x01;
 829         spin_lock_irqsave(&ensoniq->reg_lock, flags);
 830         ensoniq->ctrl &= ~ES_DAC1_EN;
 831         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 832         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 833         outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
 834         outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
 835         ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
 836         ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
 837         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 838         outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC1_COUNT));
 839 #ifdef CHIP1370
 840         ensoniq->ctrl &= ~ES_1370_WTSRSELM;
 841         switch (runtime->rate) {
 842         case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
 843         case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
 844         case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
 845         case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
 846         default: snd_BUG();
 847         }
 848 #else
 849         snd_es1371_dac1_rate(ensoniq, runtime->rate);
 850 #endif
 851         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 852         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 853         return 0;
 854 }
 855
 856 static int snd_ensoniq_playback2_prepare(snd_pcm_substream_t * substream)
 857 {
 858         unsigned long flags;
 859         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 860         snd_pcm_runtime_t *runtime = substream->runtime;
 861         unsigned int mode = 0;
 862
 863         ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
 864         ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
 865         if (snd_pcm_format_width(runtime->format) == 16)
 866                 mode |= 0x02;
 867         if (runtime->channels > 1)
 868                 mode |= 0x01;
 869         spin_lock_irqsave(&ensoniq->reg_lock, flags);
 870         ensoniq->ctrl &= ~ES_DAC2_EN;
 871         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 872         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 873         outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
 874         outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
 875         ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
 876                             ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
 877         ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
 878                           ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
 879         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 880         outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC2_COUNT));
 881 #ifdef CHIP1370
 882         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
 883                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 884                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 885                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
 886         }
 887 #else
 888         snd_es1371_dac2_rate(ensoniq, runtime->rate);
 889 #endif
 890         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 891         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 892         return 0;
 893 }
 894
 895 static int snd_ensoniq_capture_prepare(snd_pcm_substream_t * substream)
 896 {
 897         unsigned long flags;
 898         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 899         snd_pcm_runtime_t *runtime = substream->runtime;
 900         unsigned int mode = 0;
 901
 902         ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
 903         ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
 904         if (snd_pcm_format_width(runtime->format) == 16)
 905                 mode |= 0x02;
 906         if (runtime->channels > 1)
 907                 mode |= 0x01;
 908         spin_lock_irqsave(&ensoniq->reg_lock, flags);
 909         ensoniq->ctrl &= ~ES_ADC_EN;
 910         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 911         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
 912         outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
 913         outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
 914         ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
 915         ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
 916         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 917         outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, ADC_COUNT));
 918 #ifdef CHIP1370
 919         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
 920                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 921                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 922                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
 923         }
 924 #else
 925         snd_es1371_adc_rate(ensoniq, runtime->rate);
 926 #endif
 927         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 928         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
 929         return 0;
 930 }
 931
 932 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(snd_pcm_substream_t * substream)
 933 {
 934         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 935         size_t ptr;
 936
 937         spin_lock(&ensoniq->reg_lock);
 938         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
 939                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 940                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
 941                 ptr = bytes_to_frames(substream->runtime, ptr);
 942         } else {
 943                 ptr = 0;
 944         }
 945         spin_unlock(&ensoniq->reg_lock);
 946         return ptr;
 947 }
 948
 949 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(snd_pcm_substream_t * substream)
 950 {
 951         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 952         size_t ptr;
 953
 954         spin_lock(&ensoniq->reg_lock);
 955         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
 956                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 957                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
 958                 ptr = bytes_to_frames(substream->runtime, ptr);
 959         } else {
 960                 ptr = 0;
 961         }
 962         spin_unlock(&ensoniq->reg_lock);
 963         return ptr;
 964 }
 965
 966 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(snd_pcm_substream_t * substream)
 967 {
 968         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
 969         size_t ptr;
 970
 971         spin_lock(&ensoniq->reg_lock);
 972         if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
 973                 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
 974                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
 975                 ptr = bytes_to_frames(substream->runtime, ptr);
 976         } else {
 977                 ptr = 0;
 978         }
 979         spin_unlock(&ensoniq->reg_lock);
 980         return ptr;
 981 }
 982
 983 static snd_pcm_hardware_t snd_ensoniq_playback1 =
 984 {
 985         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
 986                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 987                                  SNDRV_PCM_INFO_MMAP_VALID |
 988                                  SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
 989         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
 990         .rates =
 991 #ifndef CHIP1370
 992                                 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
 993 #else
 994                                 (SNDRV_PCM_RATE_KNOT |  /* 5512Hz rate */
 995                                  SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
 996                                  SNDRV_PCM_RATE_44100),
 997 #endif
 998         .rate_min =             4000,
 999         .rate_max =             48000,
1000         .channels_min =         1,
1001         .channels_max =         2,
1002         .buffer_bytes_max =     (128*1024),
1003         .period_bytes_min =     64,
1004         .period_bytes_max =     (128*1024),
1005         .periods_min =          1,
1006         .periods_max =          1024,
1007         .fifo_size =            0,
1008 };
1009
1010 static snd_pcm_hardware_t snd_ensoniq_playback2 =
1011 {
1012         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1013                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1014                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1015                                  SNDRV_PCM_INFO_SYNC_START),
1016         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1017         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1018         .rate_min =             4000,
1019         .rate_max =             48000,
1020         .channels_min =         1,
1021         .channels_max =         2,
1022         .buffer_bytes_max =     (128*1024),
1023         .period_bytes_min =     64,
1024         .period_bytes_max =     (128*1024),
1025         .periods_min =          1,
1026         .periods_max =          1024,
1027         .fifo_size =            0,
1028 };
1029
1030 static snd_pcm_hardware_t snd_ensoniq_capture =
1031 {
1032         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1033                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1034                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1035         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1036         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1037         .rate_min =             4000,
1038         .rate_max =             48000,
1039         .channels_min =         1,
1040         .channels_max =         2,
1041         .buffer_bytes_max =     (128*1024),
1042         .period_bytes_min =     64,
1043         .period_bytes_max =     (128*1024),
1044         .periods_min =          1,
1045         .periods_max =          1024,
1046         .fifo_size =            0,
1047 };
1048
1049 static int snd_ensoniq_playback1_open(snd_pcm_substream_t * substream)
1050 {
1051         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1052         snd_pcm_runtime_t *runtime = substream->runtime;
1053
1054         ensoniq->mode |= ES_MODE_PLAY1;
1055         ensoniq->playback1_substream = substream;
1056         runtime->hw = snd_ensoniq_playback1;
1057         snd_pcm_set_sync(substream);
1058         spin_lock_irq(&ensoniq->reg_lock);
1059         if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1060                 ensoniq->spdif_stream = ensoniq->spdif_default;
1061         spin_unlock_irq(&ensoniq->reg_lock);
1062 #ifdef CHIP1370
1063         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1064                                    &snd_es1370_hw_constraints_rates);
1065 #else
1066         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1067                                       &snd_es1371_hw_constraints_dac_clock);
1068 #endif
1069         return 0;
1070 }
1071
1072 static int snd_ensoniq_playback2_open(snd_pcm_substream_t * substream)
1073 {
1074         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1075         snd_pcm_runtime_t *runtime = substream->runtime;
1076
1077         ensoniq->mode |= ES_MODE_PLAY2;
1078         ensoniq->playback2_substream = substream;
1079         runtime->hw = snd_ensoniq_playback2;
1080         snd_pcm_set_sync(substream);
1081         spin_lock_irq(&ensoniq->reg_lock);
1082         if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1083                 ensoniq->spdif_stream = ensoniq->spdif_default;
1084         spin_unlock_irq(&ensoniq->reg_lock);
1085 #ifdef CHIP1370
1086         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1087                                       &snd_es1370_hw_constraints_clock);
1088 #else
1089         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1090                                       &snd_es1371_hw_constraints_dac_clock);
1091 #endif
1092         return 0;
1093 }
1094
1095 static int snd_ensoniq_capture_open(snd_pcm_substream_t * substream)
1096 {
1097         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1098         snd_pcm_runtime_t *runtime = substream->runtime;
1099
1100         ensoniq->mode |= ES_MODE_CAPTURE;
1101         ensoniq->capture_substream = substream;
1102         runtime->hw = snd_ensoniq_capture;
1103         snd_pcm_set_sync(substream);
1104 #ifdef CHIP1370
1105         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1106                                       &snd_es1370_hw_constraints_clock);
1107 #else
1108         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1109                                       &snd_es1371_hw_constraints_adc_clock);
1110 #endif
1111         return 0;
1112 }
1113
1114 static int snd_ensoniq_playback1_close(snd_pcm_substream_t * substream)
1115 {
1116         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1117
1118         ensoniq->playback1_substream = NULL;
1119         ensoniq->mode &= ~ES_MODE_PLAY1;
1120         return 0;
1121 }
1122
1123 static int snd_ensoniq_playback2_close(snd_pcm_substream_t * substream)
1124 {
1125         unsigned long flags;
1126         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1127
1128         ensoniq->playback2_substream = NULL;
1129         spin_lock_irqsave(&ensoniq->reg_lock, flags);
1130 #ifdef CHIP1370
1131         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1132 #endif
1133         ensoniq->mode &= ~ES_MODE_PLAY2;
1134         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1135         return 0;
1136 }
1137
1138 static int snd_ensoniq_capture_close(snd_pcm_substream_t * substream)
1139 {
1140         unsigned long flags;
1141         ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1142
1143         ensoniq->capture_substream = NULL;
1144         spin_lock_irqsave(&ensoniq->reg_lock, flags);
1145 #ifdef CHIP1370
1146         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1147 #endif
1148         ensoniq->mode &= ~ES_MODE_CAPTURE;
1149         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1150         return 0;
1151 }
1152
1153 static snd_pcm_ops_t snd_ensoniq_playback1_ops = {
1154         .open =         snd_ensoniq_playback1_open,
1155         .close =        snd_ensoniq_playback1_close,
1156         .ioctl =        snd_pcm_lib_ioctl,
1157         .hw_params =    snd_ensoniq_hw_params,
1158         .hw_free =      snd_ensoniq_hw_free,
1159         .prepare =      snd_ensoniq_playback1_prepare,
1160         .trigger =      snd_ensoniq_trigger,
1161         .pointer =      snd_ensoniq_playback1_pointer,
1162 };
1163
1164 static snd_pcm_ops_t snd_ensoniq_playback2_ops = {
1165         .open =         snd_ensoniq_playback2_open,
1166         .close =        snd_ensoniq_playback2_close,
1167         .ioctl =        snd_pcm_lib_ioctl,
1168         .hw_params =    snd_ensoniq_hw_params,
1169         .hw_free =      snd_ensoniq_hw_free,
1170         .prepare =      snd_ensoniq_playback2_prepare,
1171         .trigger =      snd_ensoniq_trigger,
1172         .pointer =      snd_ensoniq_playback2_pointer,
1173 };
1174
1175 static snd_pcm_ops_t snd_ensoniq_capture_ops = {
1176         .open =         snd_ensoniq_capture_open,
1177         .close =        snd_ensoniq_capture_close,
1178         .ioctl =        snd_pcm_lib_ioctl,
1179         .hw_params =    snd_ensoniq_hw_params,
1180         .hw_free =      snd_ensoniq_hw_free,
1181         .prepare =      snd_ensoniq_capture_prepare,
1182         .trigger =      snd_ensoniq_trigger,
1183         .pointer =      snd_ensoniq_capture_pointer,
1184 };
1185
1186 static void snd_ensoniq_pcm_free(snd_pcm_t *pcm)
1187 {
1188         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, pcm->private_data, return);
1189         ensoniq->pcm1 = NULL;
1190         snd_pcm_lib_preallocate_free_for_all(pcm);
1191 }
1192
1193 static int __devinit snd_ensoniq_pcm(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1194 {
1195         snd_pcm_t *pcm;
1196         int err;
1197
1198         if (rpcm)
1199                 *rpcm = NULL;
1200 #ifdef CHIP1370
1201         err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1202 #else
1203         err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1204 #endif
1205         if (err < 0)
1206                 return err;
1207
1208 #ifdef CHIP1370
1209         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1210 #else
1211         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1212 #endif
1213         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1214
1215         pcm->private_data = ensoniq;
1216         pcm->private_free = snd_ensoniq_pcm_free;
1217         pcm->info_flags = 0;
1218 #ifdef CHIP1370
1219         strcpy(pcm->name, "ES1370 DAC2/ADC");
1220 #else
1221         strcpy(pcm->name, "ES1371 DAC2/ADC");
1222 #endif
1223         ensoniq->pcm1 = pcm;
1224
1225         snd_pcm_lib_preallocate_pci_pages_for_all(ensoniq->pci, pcm, 64*1024, 128*1024);
1226
1227         if (rpcm)
1228                 *rpcm = pcm;
1229         return 0;
1230 }
1231
1232 static void snd_ensoniq_pcm_free2(snd_pcm_t *pcm)
1233 {
1234         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, pcm->private_data, return);
1235         ensoniq->pcm2 = NULL;
1236         snd_pcm_lib_preallocate_free_for_all(pcm);
1237 }
1238
1239 static int __devinit snd_ensoniq_pcm2(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1240 {
1241         snd_pcm_t *pcm;
1242         int err;
1243
1244         if (rpcm)
1245                 *rpcm = NULL;
1246 #ifdef CHIP1370
1247         err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1248 #else
1249         err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1250 #endif
1251         if (err < 0)
1252                 return err;
1253
1254 #ifdef CHIP1370
1255         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1256 #else
1257         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1258 #endif
1259         pcm->private_data = ensoniq;
1260         pcm->private_free = snd_ensoniq_pcm_free2;
1261         pcm->info_flags = 0;
1262 #ifdef CHIP1370
1263         strcpy(pcm->name, "ES1370 DAC1");
1264 #else
1265         strcpy(pcm->name, "ES1371 DAC1");
1266 #endif
1267         ensoniq->pcm2 = pcm;
1268
1269         snd_pcm_lib_preallocate_pci_pages_for_all(ensoniq->pci, pcm, 64*1024, 128*1024);
1270
1271         if (rpcm)
1272                 *rpcm = pcm;
1273         return 0;
1274 }
1275
1276 /*
1277  *  Mixer section
1278  */
1279
1280 /*
1281  * ENS1371 mixer (including SPDIF interface)
1282  */
1283 #ifdef CHIP1371
1284 static int snd_ens1373_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1285 {
1286         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1287         uinfo->count = 1;
1288         return 0;
1289 }
1290
1291 static int snd_ens1373_spdif_default_get(snd_kcontrol_t * kcontrol,
1292                                          snd_ctl_elem_value_t * ucontrol)
1293 {
1294         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1295         spin_lock_irq(&ensoniq->reg_lock);
1296         ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1297         ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1298         ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1299         ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1300         spin_unlock_irq(&ensoniq->reg_lock);
1301         return 0;
1302 }
1303
1304 static int snd_ens1373_spdif_default_put(snd_kcontrol_t * kcontrol,
1305                                          snd_ctl_elem_value_t * ucontrol)
1306 {
1307         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1308         unsigned int val;
1309         int change;
1310
1311         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1312               ((u32)ucontrol->value.iec958.status[1] << 8) |
1313               ((u32)ucontrol->value.iec958.status[2] << 16) |
1314               ((u32)ucontrol->value.iec958.status[3] << 24);
1315         spin_lock_irq(&ensoniq->reg_lock);
1316         change = ensoniq->spdif_default != val;
1317         ensoniq->spdif_default = val;
1318         if (change && ensoniq->playback1_substream == NULL && ensoniq->playback2_substream == NULL)
1319                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1320         spin_unlock_irq(&ensoniq->reg_lock);
1321         return change;
1322 }
1323
1324 static int snd_ens1373_spdif_mask_get(snd_kcontrol_t * kcontrol,
1325                                          snd_ctl_elem_value_t * ucontrol)
1326 {
1327         ucontrol->value.iec958.status[0] = 0xff;
1328         ucontrol->value.iec958.status[1] = 0xff;
1329         ucontrol->value.iec958.status[2] = 0xff;
1330         ucontrol->value.iec958.status[3] = 0xff;
1331         return 0;
1332 }
1333
1334 static int snd_ens1373_spdif_stream_get(snd_kcontrol_t * kcontrol,
1335                                          snd_ctl_elem_value_t * ucontrol)
1336 {
1337         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1338         spin_lock_irq(&ensoniq->reg_lock);
1339         ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1340         ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1341         ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1342         ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1343         spin_unlock_irq(&ensoniq->reg_lock);
1344         return 0;
1345 }
1346
1347 static int snd_ens1373_spdif_stream_put(snd_kcontrol_t * kcontrol,
1348                                         snd_ctl_elem_value_t * ucontrol)
1349 {
1350         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1351         unsigned int val;
1352         int change;
1353
1354         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1355               ((u32)ucontrol->value.iec958.status[1] << 8) |
1356               ((u32)ucontrol->value.iec958.status[2] << 16) |
1357               ((u32)ucontrol->value.iec958.status[3] << 24);
1358         spin_lock_irq(&ensoniq->reg_lock);
1359         change = ensoniq->spdif_stream != val;
1360         ensoniq->spdif_stream = val;
1361         if (change && (ensoniq->playback1_substream != NULL || ensoniq->playback2_substream != NULL))
1362                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1363         spin_unlock_irq(&ensoniq->reg_lock);
1364         return change;
1365 }
1366
1367 static snd_kcontrol_new_t snd_ens1373_spdif_default __devinitdata =
1368 {
1369         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1370         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1371         .info =         snd_ens1373_spdif_info,
1372         .get =          snd_ens1373_spdif_default_get,
1373         .put =          snd_ens1373_spdif_default_put,
1374 };
1375
1376 static snd_kcontrol_new_t snd_ens1373_spdif_mask __devinitdata =
1377 {
1378         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1379         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1380         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1381         .info =         snd_ens1373_spdif_info,
1382         .get =          snd_ens1373_spdif_mask_get
1383 };
1384
1385 static snd_kcontrol_new_t snd_ens1373_spdif_stream __devinitdata =
1386 {
1387         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1388         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1389         .info =         snd_ens1373_spdif_info,
1390         .get =          snd_ens1373_spdif_stream_get,
1391         .put =          snd_ens1373_spdif_stream_put
1392 };
1393
1394 #define ES1371_SPDIF(xname) \
1395 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1396   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1397
1398 static int snd_es1371_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1399 {
1400         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1401         uinfo->count = 1;
1402         uinfo->value.integer.min = 0;
1403         uinfo->value.integer.max = 1;
1404         return 0;
1405 }
1406
1407 static int snd_es1371_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1408 {
1409         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1410
1411         spin_lock_irq(&ensoniq->reg_lock);
1412         ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1413         spin_unlock_irq(&ensoniq->reg_lock);
1414         return 0;
1415 }
1416
1417 static int snd_es1371_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1418 {
1419         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1420         unsigned int nval1, nval2;
1421         int change;
1422
1423         nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1424         nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1425         spin_lock_irq(&ensoniq->reg_lock);
1426         change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1427         ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1428         ensoniq->ctrl |= nval1;
1429         ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1430         ensoniq->cssr |= nval2;
1431         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1432         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1433         spin_unlock_irq(&ensoniq->reg_lock);
1434         return change;
1435 }
1436
1437 static snd_kcontrol_new_t snd_es1371_mixer_spdif __devinitdata =
1438 ES1371_SPDIF("IEC958 Playback Switch");
1439
1440 static int snd_es1373_rear_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1441 {
1442         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1443         uinfo->count = 1;
1444         uinfo->value.integer.min = 0;
1445         uinfo->value.integer.max = 1;
1446         return 0;
1447 }
1448
1449 static int snd_es1373_rear_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1450 {
1451         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1452         int val = 0;
1453
1454         spin_lock_irq(&ensoniq->reg_lock);
1455         if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1456                 val = 1;
1457         ucontrol->value.integer.value[0] = val;
1458         spin_unlock_irq(&ensoniq->reg_lock);
1459         return 0;
1460 }
1461
1462 static int snd_es1373_rear_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1463 {
1464         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1465         unsigned int nval1;
1466         int change;
1467
1468         nval1 = ucontrol->value.integer.value[0] ? ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1469         spin_lock_irq(&ensoniq->reg_lock);
1470         change = (ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1471         ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1472         ensoniq->cssr |= nval1;
1473         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1474         spin_unlock_irq(&ensoniq->reg_lock);
1475         return change;
1476 }
1477
1478 static snd_kcontrol_new_t snd_ens1373_rear __devinitdata =
1479 {
1480         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1481         .name =         "AC97 2ch->4ch Copy Switch",
1482         .info =         snd_es1373_rear_info,
1483         .get =          snd_es1373_rear_get,
1484         .put =          snd_es1373_rear_put,
1485 };
1486
1487 static void snd_ensoniq_mixer_free_ac97(ac97_t *ac97)
1488 {
1489         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, ac97->private_data, return);
1490         ensoniq->u.es1371.ac97 = NULL;
1491 }
1492
1493 static struct {
1494         unsigned short vid;             /* vendor ID */
1495         unsigned short did;             /* device ID */
1496         unsigned char rev;              /* revision */
1497 } es1371_spdif_present[] __devinitdata = {
1498         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1499         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1500         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1501         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1502         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1503         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1504 };
1505
1506 static int snd_ensoniq_1371_mixer(ensoniq_t * ensoniq)
1507 {
1508         snd_card_t *card = ensoniq->card;
1509         ac97_t ac97;
1510         int err, idx;
1511
1512         memset(&ac97, 0, sizeof(ac97));
1513         ac97.write = snd_es1371_codec_write;
1514         ac97.read = snd_es1371_codec_read;
1515         ac97.private_data = ensoniq;
1516         ac97.private_free = snd_ensoniq_mixer_free_ac97;
1517         ac97.scaps = AC97_SCAP_AUDIO;
1518         if ((err = snd_ac97_mixer(card, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1519                 return err;
1520         for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1521                 if (ensoniq->pci->vendor == es1371_spdif_present[idx].vid &&
1522                     ensoniq->pci->device == es1371_spdif_present[idx].did &&
1523                     ensoniq->rev == es1371_spdif_present[idx].rev) {
1524                         snd_kcontrol_t *kctl;
1525                         int index = 0;
1526
1527                         ensoniq->spdif_default = ensoniq->spdif_stream = SNDRV_PCM_DEFAULT_CON_SPDIF;
1528                         outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1529
1530                         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1531                                 index++;
1532
1533                         kctl = snd_ctl_new1(&snd_es1371_mixer_spdif, ensoniq);
1534                         kctl->id.index = index;
1535                         snd_ctl_add(card, kctl);
1536
1537                         kctl = snd_ctl_new1(&snd_ens1373_spdif_default, ensoniq);
1538                         kctl->id.index = index;
1539                         snd_ctl_add(card, kctl);
1540
1541                         kctl = snd_ctl_new1(&snd_ens1373_spdif_mask, ensoniq);
1542                         kctl->id.index = index;
1543                         snd_ctl_add(card, kctl);
1544
1545                         kctl = snd_ctl_new1(&snd_ens1373_spdif_stream, ensoniq);
1546                         kctl->id.index = index;
1547                         snd_ctl_add(card, kctl);
1548                         break;
1549                 }
1550         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1551                 /* mirror rear to front speakers */
1552                 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1553                 ensoniq->cssr |= ES_1373_REAR_BIT26;
1554                 snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1555         }
1556         return 0;
1557 }
1558
1559 #endif /* CHIP1371 */
1560
1561 /* generic control callbacks for ens1370 and for joystick */
1562 #if defined(CHIP1370) || defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1563 #define ENSONIQ_CONTROL(xname, mask) \
1564 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1565   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1566   .private_value = mask }
1567
1568 static int snd_ensoniq_control_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1569 {
1570         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1571         uinfo->count = 1;
1572         uinfo->value.integer.min = 0;
1573         uinfo->value.integer.max = 1;
1574         return 0;
1575 }
1576
1577 static int snd_ensoniq_control_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1578 {
1579         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1580         unsigned long flags;
1581         int mask = kcontrol->private_value;
1582
1583         spin_lock_irqsave(&ensoniq->reg_lock, flags);
1584         ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1585         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1586         return 0;
1587 }
1588
1589 #ifdef CHIP1370
1590 static int snd_ensoniq_control_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1591 {
1592         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1593         unsigned long flags;
1594         int mask = kcontrol->private_value;
1595         unsigned int nval;
1596         int change;
1597
1598         nval = ucontrol->value.integer.value[0] ? mask : 0;
1599         spin_lock_irqsave(&ensoniq->reg_lock, flags);
1600         change = (ensoniq->ctrl & mask) != nval;
1601         ensoniq->ctrl &= ~mask;
1602         ensoniq->ctrl |= nval;
1603         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1604         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1605         return change;
1606 }
1607 #endif /* CHIP1370 */
1608 #endif /* CHIP1370 || GAMEPORT */
1609
1610 /*
1611  * ENS1370 mixer
1612  */
1613
1614 #ifdef CHIP1370
1615 static snd_kcontrol_new_t snd_es1370_controls[2] __devinitdata = {
1616 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1617 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1618 };
1619
1620 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1621
1622 static void snd_ensoniq_mixer_free_ak4531(ak4531_t *ak4531)
1623 {
1624         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, ak4531->private_data, return);
1625         ensoniq->u.es1370.ak4531 = NULL;
1626 }
1627
1628 static int __devinit snd_ensoniq_1370_mixer(ensoniq_t * ensoniq)
1629 {
1630         snd_card_t *card = ensoniq->card;
1631         ak4531_t ak4531;
1632         unsigned int idx;
1633         int err;
1634
1635         /* try reset AK4531 */
1636         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1637         inw(ES_REG(ensoniq, 1370_CODEC));
1638         udelay(100);
1639         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1640         inw(ES_REG(ensoniq, 1370_CODEC));
1641         udelay(100);
1642
1643         memset(&ak4531, 0, sizeof(ak4531));
1644         ak4531.write = snd_es1370_codec_write;
1645         ak4531.private_data = ensoniq;
1646         ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1647         if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1648                 return err;
1649         for (idx = 0; idx < ES1370_CONTROLS; idx++)
1650                 snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1651         return 0;
1652 }
1653
1654 #endif /* CHIP1370 */
1655
1656 /*
1657  *  General Switches...
1658  */
1659
1660 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1661 /* MQ: gameport driver connectivity */
1662 #define ENSONIQ_JOY_CONTROL(xname, mask) \
1663 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1664   .get = snd_ensoniq_control_get, .put = snd_ensoniq_joy_control_put, \
1665   .private_value = mask }
1666
1667 static int snd_ensoniq_joy_enable(ensoniq_t *ensoniq)
1668 {
1669         static unsigned long last_jiffies = 0;
1670         unsigned long flags;
1671
1672         if (!request_region(ensoniq->gameport.io, 8, "ens137x: gameport")) {
1673 #define ES___GAMEPORT_LOG_DELAY (30*HZ)
1674                 // avoid log pollution: limit to 2 infos per minute
1675                 if (time_after(jiffies, last_jiffies + ES___GAMEPORT_LOG_DELAY)) {
1676                         last_jiffies = jiffies;
1677                         snd_printk("gameport io port 0x%03x in use", ensoniq->gameport.io);
1678                 }
1679                 return 0;
1680         }
1681         spin_lock_irqsave(&ensoniq->reg_lock, flags);
1682         ensoniq->ctrl |= ES_JYSTK_EN;
1683         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1684         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1685         gameport_register_port(&ensoniq->gameport);
1686         return 1;
1687 }
1688
1689 static int snd_ensoniq_joy_disable(ensoniq_t *ensoniq)
1690 {
1691         unsigned long flags;
1692
1693         gameport_unregister_port(&ensoniq->gameport);
1694         spin_lock_irqsave(&ensoniq->reg_lock, flags);
1695         ensoniq->ctrl &= ~ES_JYSTK_EN;
1696         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1697         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1698         release_region(ensoniq->gameport.io, 8);
1699         return 1;
1700 }
1701
1702 static int snd_ensoniq_joy_control_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1703 {
1704         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1705         unsigned int nval;
1706         int change;
1707
1708         down(&ensoniq->joy_sem);
1709         nval = ucontrol->value.integer.value[0] ? ES_JYSTK_EN : 0;
1710         change = (ensoniq->ctrl & ES_JYSTK_EN) != nval; // spinlock shouldn't be needed because of joy_sem
1711         if (change) {
1712                 if (nval)       // enable
1713                         change = snd_ensoniq_joy_enable(ensoniq);
1714                 else    change = snd_ensoniq_joy_disable(ensoniq);
1715         }
1716         up(&ensoniq->joy_sem);
1717         return change;
1718 }
1719
1720 static snd_kcontrol_new_t snd_ensoniq_control_joystick __devinitdata =
1721 ENSONIQ_JOY_CONTROL("Joystick Enable", ES_JYSTK_EN);
1722
1723 #ifdef CHIP1371
1724
1725 #define ES1371_JOYSTICK_ADDR(xname) \
1726 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_es1371_joystick_addr_info, \
1727   .get = snd_es1371_joystick_addr_get, .put = snd_es1371_joystick_addr_put }
1728
1729 static int snd_es1371_joystick_addr_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1730 {
1731         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1732         uinfo->count = 1;
1733         uinfo->value.enumerated.items = 4;
1734         if (uinfo->value.enumerated.item >= 4)
1735                 uinfo->value.enumerated.item = 3;
1736         sprintf(uinfo->value.enumerated.name, "port 0x%x", (uinfo->value.enumerated.item * 8) + 0x200);
1737         return 0;
1738 }
1739
1740 static int snd_es1371_joystick_addr_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1741 {
1742         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1743         unsigned long flags;
1744
1745         spin_lock_irqsave(&ensoniq->reg_lock, flags);
1746         ucontrol->value.enumerated.item[0] = ES_1371_JOY_ASELI(ensoniq->ctrl);
1747         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1748         return 0;
1749 }
1750
1751 static int snd_es1371_joystick_addr_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1752 {
1753         ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1754         unsigned long flags;
1755         unsigned int nval;
1756         int change;
1757
1758         down(&ensoniq->joy_sem);
1759         nval = ES_1371_JOY_ASEL(ucontrol->value.integer.value[0]);
1760         spin_lock_irqsave(&ensoniq->reg_lock, flags);
1761         if (!(change = !(ensoniq->ctrl & ES_JYSTK_EN)))
1762                 goto no_change; // FIXME: now we allow change only when joystick is disabled
1763         change = (ensoniq->ctrl & ES_1371_JOY_ASELM) != nval;
1764         ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1765         ensoniq->ctrl |= nval;
1766         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1767         ensoniq->gameport.io = 0x200 + ES_1371_JOY_ASELI(nval) * 8;
1768 no_change:
1769         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1770         up(&ensoniq->joy_sem);
1771         return change;
1772 }
1773
1774 static snd_kcontrol_new_t snd_es1371_joystick_addr __devinitdata =
1775 ES1371_JOYSTICK_ADDR("Joystick Address");
1776
1777 #endif /* CHIP1371 */
1778 #endif /* CONFIG_GAMEPORT */
1779
1780 /*
1781
1782  */
1783
1784 static void snd_ensoniq_proc_read(snd_info_entry_t *entry,
1785                                   snd_info_buffer_t * buffer)
1786 {
1787         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, entry->private_data, return);
1788
1789 #ifdef CHIP1370
1790         snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1791 #else
1792         snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1793 #endif
1794         snd_iprintf(buffer, "Joystick enable  : %s\n", ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1795 #ifdef CHIP1370
1796         snd_iprintf(buffer, "MIC +5V bias     : %s\n", ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1797         snd_iprintf(buffer, "Line In to AOUT  : %s\n", ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1798 #else
1799         snd_iprintf(buffer, "Joystick port    : 0x%x\n", (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1800 #endif
1801 }
1802
1803 static void __devinit snd_ensoniq_proc_init(ensoniq_t * ensoniq)
1804 {
1805         snd_info_entry_t *entry;
1806
1807         if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1808                 snd_info_set_text_ops(entry, ensoniq, snd_ensoniq_proc_read);
1809 }
1810
1811 /*
1812
1813  */
1814
1815 static int snd_ensoniq_free(ensoniq_t *ensoniq)
1816 {
1817 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1818         if (ensoniq->ctrl & ES_JYSTK_EN)
1819                 snd_ensoniq_joy_disable(ensoniq);
1820 #endif
1821         if (ensoniq->irq < 0)
1822                 goto __hw_end;
1823 #ifdef CHIP1370
1824         outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));   /* switch everything off */
1825         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1826 #else
1827         outl(0, ES_REG(ensoniq, CONTROL));      /* switch everything off */
1828         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1829 #endif
1830         synchronize_irq(ensoniq->irq);
1831         pci_set_power_state(ensoniq->pci, 3);
1832       __hw_end:
1833 #ifdef CHIP1370
1834         if (ensoniq->bugbuf)
1835                 snd_free_pci_pages(ensoniq->pci, 16, ensoniq->bugbuf, ensoniq->bugbuf_addr);
1836 #endif
1837         if (ensoniq->res_port) {
1838                 release_resource(ensoniq->res_port);
1839                 kfree_nocheck(ensoniq->res_port);
1840         }
1841         if (ensoniq->irq >= 0)
1842                 free_irq(ensoniq->irq, (void *)ensoniq);
1843         snd_magic_kfree(ensoniq);
1844         return 0;
1845 }
1846
1847 static int snd_ensoniq_dev_free(snd_device_t *device)
1848 {
1849         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, device->device_data, return -ENXIO);
1850         return snd_ensoniq_free(ensoniq);
1851 }
1852
1853 #ifdef CHIP1371
1854 static struct {
1855         unsigned short svid;            /* subsystem vendor ID */
1856         unsigned short sdid;            /* subsystem device ID */
1857 } es1371_amplifier_hack[] = {
1858         { .svid = 0x107b, .sdid = 0x2150 },     /* Gateway Solo 2150 */
1859         { .svid = 0x13bd, .sdid = 0x100c },     /* EV1938 on Mebius PC-MJ100V */
1860         { .svid = 0x1102, .sdid = 0x5938 },     /* Targa Xtender300 */
1861         { .svid = 0x1102, .sdid = 0x8938 },     /* IPC Topnote G notebook */
1862         { .svid = PCI_ANY_ID, .sdid = PCI_ANY_ID }
1863 };
1864 static struct {
1865         unsigned short vid;             /* vendor ID */
1866         unsigned short did;             /* device ID */
1867         unsigned char rev;              /* revision */
1868 } es1371_ac97_reset_hack[] = {
1869         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1870         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1871         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1872         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1873         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1874         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1875 };
1876 #endif
1877
1878 static int __devinit snd_ensoniq_create(snd_card_t * card,
1879                                      struct pci_dev *pci,
1880                                      ensoniq_t ** rensoniq)
1881 {
1882         ensoniq_t *ensoniq;
1883         unsigned short cmdw;
1884         unsigned char cmdb;
1885 #ifdef CHIP1371
1886         int idx;
1887 #endif
1888         int err;
1889         static snd_device_ops_t ops = {
1890                 .dev_free =     snd_ensoniq_dev_free,
1891         };
1892
1893         *rensoniq = NULL;
1894         if ((err = pci_enable_device(pci)) < 0)
1895                 return err;
1896         ensoniq = snd_magic_kcalloc(ensoniq_t, 0, GFP_KERNEL);
1897         if (ensoniq == NULL)
1898                 return -ENOMEM;
1899         spin_lock_init(&ensoniq->reg_lock);
1900         ensoniq->card = card;
1901         ensoniq->pci = pci;
1902         ensoniq->irq = -1;
1903         ensoniq->port = pci_resource_start(pci, 0);
1904         if ((ensoniq->res_port = request_region(ensoniq->port, 0x40, "Ensoniq AudioPCI")) == NULL) {
1905                 snd_ensoniq_free(ensoniq);
1906                 snd_printk("unable to grab ports 0x%lx-0x%lx\n", ensoniq->port, ensoniq->port + 0x40 - 1);
1907                 return -EBUSY;
1908         }
1909         if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ, "Ensoniq AudioPCI", (void *)ensoniq)) {
1910                 snd_ensoniq_free(ensoniq);
1911                 snd_printk("unable to grab IRQ %d\n", pci->irq);
1912                 return -EBUSY;
1913         }
1914         ensoniq->irq = pci->irq;
1915 #ifdef CHIP1370
1916         if ((ensoniq->bugbuf = snd_malloc_pci_pages(pci, 16, &ensoniq->bugbuf_addr)) == NULL) {
1917                 snd_ensoniq_free(ensoniq);
1918                 snd_printk("unable to allocate space for phantom area - bugbuf\n");
1919                 return -EBUSY;
1920         }
1921 #endif
1922         pci_set_master(pci);
1923         pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
1924         ensoniq->rev = cmdb;
1925         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw);
1926         ensoniq->subsystem_vendor_id = cmdw;
1927         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw);
1928         ensoniq->subsystem_device_id = cmdw;
1929         snd_ensoniq_proc_init(ensoniq);
1930 #ifdef CHIP1370
1931 #if 0
1932         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1933 #else   /* get microphone working */
1934         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1935 #endif
1936         ensoniq->sctrl = 0;
1937         /* initialize the chips */
1938         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1939         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1940         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1941         outl(ensoniq->bugbuf_addr, ES_REG(ensoniq, PHANTOM_FRAME));
1942         outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1943 #else
1944         ensoniq->ctrl = 0;
1945         ensoniq->sctrl = 0;
1946         ensoniq->cssr = 0;
1947         for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++)
1948                 if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid &&
1949                     ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) {
1950                         ensoniq->ctrl |= ES_1371_GPIO_OUT(1);   /* turn amplifier on */
1951                         break;
1952                 }
1953         /* initialize the chips */
1954         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1955         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1956         outl(0, ES_REG(ensoniq, 1371_LEGACY));
1957         for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1958                 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
1959                     pci->device == es1371_ac97_reset_hack[idx].did &&
1960                     ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
1961                         unsigned long tmo;
1962                         signed long tmo2;
1963
1964                         ensoniq->cssr |= ES_1371_ST_AC97_RST;
1965                         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1966                         /* need to delay around 20ms(bleech) to give
1967                         some CODECs enough time to wakeup */
1968                         tmo = jiffies + (HZ / 50) + 1;
1969                         while (1) {
1970                                 tmo2 = tmo - jiffies;
1971                                 if (tmo2 <= 0)
1972                                         break;
1973                                 set_current_state(TASK_UNINTERRUPTIBLE);
1974                                 schedule_timeout(tmo2);
1975                         }
1976                         break;
1977                 }
1978         /* AC'97 warm reset to start the bitclk */
1979         outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1980         inl(ES_REG(ensoniq, CONTROL));
1981         udelay(20);
1982         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1983         /* Init the sample rate converter */
1984         snd_es1371_wait_src_ready(ensoniq);
1985         outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
1986         for (idx = 0; idx < 0x80; idx++)
1987                 snd_es1371_src_write(ensoniq, idx, 0);
1988         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
1989         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
1990         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
1991         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
1992         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
1993         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
1994         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
1995         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
1996         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
1997         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
1998         snd_es1371_adc_rate(ensoniq, 22050);
1999         snd_es1371_dac1_rate(ensoniq, 22050);
2000         snd_es1371_dac2_rate(ensoniq, 22050);
2001         /* WARNING:
2002          * enabling the sample rate converter without properly programming
2003          * its parameters causes the chip to lock up (the SRC busy bit will
2004          * be stuck high, and I've found no way to rectify this other than
2005          * power cycle) - Thomas Sailer
2006          */
2007         snd_es1371_wait_src_ready(ensoniq);
2008         outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2009         /* try reset codec directly */
2010         outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2011 #endif
2012         outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2013         outb(0x00, ES_REG(ensoniq, UART_RES));
2014         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2015 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2016         init_MUTEX(&ensoniq->joy_sem);
2017 #ifdef CHIP1371
2018         snd_ctl_add(card, snd_ctl_new1(&snd_es1371_joystick_addr, ensoniq));
2019 #endif
2020         snd_ctl_add(card, snd_ctl_new1(&snd_ensoniq_control_joystick, ensoniq));
2021         ensoniq->gameport.io = 0x200;   // FIXME: is ES1371 configured like this above ?
2022 #endif
2023         synchronize_irq(ensoniq->irq);
2024
2025         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2026                 snd_ensoniq_free(ensoniq);
2027                 return err;
2028         }
2029
2030         *rensoniq = ensoniq;
2031         return 0;
2032 }
2033
2034 /*
2035  *  MIDI section
2036  */
2037
2038 static void snd_ensoniq_midi_interrupt(ensoniq_t * ensoniq)
2039 {
2040         snd_rawmidi_t * rmidi = ensoniq->rmidi;
2041         unsigned char status, mask, byte;
2042
2043         if (rmidi == NULL)
2044                 return;
2045         /* do Rx at first */
2046         spin_lock(&ensoniq->reg_lock);
2047         mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2048         while (mask) {
2049                 status = inb(ES_REG(ensoniq, UART_STATUS));
2050                 if ((status & mask) == 0)
2051                         break;
2052                 byte = inb(ES_REG(ensoniq, UART_DATA));
2053                 spin_unlock(&ensoniq->reg_lock);
2054                 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2055                 spin_lock(&ensoniq->reg_lock);
2056         }
2057         spin_unlock(&ensoniq->reg_lock);
2058
2059         /* do Tx at second */
2060         spin_lock(&ensoniq->reg_lock);
2061         mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2062         while (mask) {
2063                 status = inb(ES_REG(ensoniq, UART_STATUS));
2064                 if ((status & mask) == 0)
2065                         break;
2066                 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2067                         ensoniq->uartc &= ~ES_TXINTENM;
2068                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2069                         mask &= ~ES_TXRDY;
2070                 } else {
2071                         outb(byte, ES_REG(ensoniq, UART_DATA));
2072                 }
2073         }
2074         spin_unlock(&ensoniq->reg_lock);
2075 }
2076
2077 static int snd_ensoniq_midi_input_open(snd_rawmidi_substream_t * substream)
2078 {
2079         unsigned long flags;
2080         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, substream->rmidi->private_data, return -ENXIO);
2081
2082         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2083         ensoniq->uartm |= ES_MODE_INPUT;
2084         ensoniq->midi_input = substream;
2085         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2086                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2087                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2088                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2089         }
2090         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2091         return 0;
2092 }
2093
2094 static int snd_ensoniq_midi_input_close(snd_rawmidi_substream_t * substream)
2095 {
2096         unsigned long flags;
2097         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, substream->rmidi->private_data, return -ENXIO);
2098
2099         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2100         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2101                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2102                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2103         } else {
2104                 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2105         }
2106         ensoniq->midi_input = NULL;
2107         ensoniq->uartm &= ~ES_MODE_INPUT;
2108         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2109         return 0;
2110 }
2111
2112 static int snd_ensoniq_midi_output_open(snd_rawmidi_substream_t * substream)
2113 {
2114         unsigned long flags;
2115         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, substream->rmidi->private_data, return -ENXIO);
2116
2117         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2118         ensoniq->uartm |= ES_MODE_OUTPUT;
2119         ensoniq->midi_output = substream;
2120         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2121                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2122                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2123                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2124         }
2125         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2126         return 0;
2127 }
2128
2129 static int snd_ensoniq_midi_output_close(snd_rawmidi_substream_t * substream)
2130 {
2131         unsigned long flags;
2132         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, substream->rmidi->private_data, return -ENXIO);
2133
2134         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2135         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2136                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2137                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2138         } else {
2139                 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2140         }
2141         ensoniq->midi_output = NULL;
2142         ensoniq->uartm &= ~ES_MODE_OUTPUT;
2143         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2144         return 0;
2145 }
2146
2147 static void snd_ensoniq_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2148 {
2149         unsigned long flags;
2150         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, substream->rmidi->private_data, return);
2151         int idx;
2152
2153         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2154         if (up) {
2155                 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2156                         /* empty input FIFO */
2157                         for (idx = 0; idx < 32; idx++)
2158                                 inb(ES_REG(ensoniq, UART_DATA));
2159                         ensoniq->uartc |= ES_RXINTEN;
2160                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2161                 }
2162         } else {
2163                 if (ensoniq->uartc & ES_RXINTEN) {
2164                         ensoniq->uartc &= ~ES_RXINTEN;
2165                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2166                 }
2167         }
2168         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2169 }
2170
2171 static void snd_ensoniq_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2172 {
2173         unsigned long flags;
2174         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, substream->rmidi->private_data, return);
2175         unsigned char byte;
2176
2177         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2178         if (up) {
2179                 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2180                         ensoniq->uartc |= ES_TXINTENO(1);
2181                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2182                         while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2183                                (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2184                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2185                                         ensoniq->uartc &= ~ES_TXINTENM;
2186                                 } else {
2187                                         outb(byte, ES_REG(ensoniq, UART_DATA));
2188                                 }
2189                         }
2190                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2191                 }
2192         } else {
2193                 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2194                         ensoniq->uartc &= ~ES_TXINTENM;
2195                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2196                 }
2197         }
2198         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2199 }
2200
2201 static snd_rawmidi_ops_t snd_ensoniq_midi_output =
2202 {
2203         .open =         snd_ensoniq_midi_output_open,
2204         .close =        snd_ensoniq_midi_output_close,
2205         .trigger =      snd_ensoniq_midi_output_trigger,
2206 };
2207
2208 static snd_rawmidi_ops_t snd_ensoniq_midi_input =
2209 {
2210         .open =         snd_ensoniq_midi_input_open,
2211         .close =        snd_ensoniq_midi_input_close,
2212         .trigger =      snd_ensoniq_midi_input_trigger,
2213 };
2214
2215 static int __devinit snd_ensoniq_midi(ensoniq_t * ensoniq, int device, snd_rawmidi_t **rrawmidi)
2216 {
2217         snd_rawmidi_t *rmidi;
2218         int err;
2219
2220         if (rrawmidi)
2221                 *rrawmidi = NULL;
2222         if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2223                 return err;
2224 #ifdef CHIP1370
2225         strcpy(rmidi->name, "ES1370");
2226 #else
2227         strcpy(rmidi->name, "ES1371");
2228 #endif
2229         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2230         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2231         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2232         rmidi->private_data = ensoniq;
2233         ensoniq->rmidi = rmidi;
2234         if (rrawmidi)
2235                 *rrawmidi = rmidi;
2236         return 0;
2237 }
2238
2239 /*
2240  *  Interrupt handler
2241  */
2242
2243 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2244 {
2245         ensoniq_t *ensoniq = snd_magic_cast(ensoniq_t, dev_id, return IRQ_NONE);
2246         unsigned int status, sctrl;
2247
2248         if (ensoniq == NULL)
2249                 return IRQ_NONE;
2250
2251         status = inl(ES_REG(ensoniq, STATUS));
2252         if (!(status & ES_INTR))
2253                 return IRQ_NONE;
2254
2255         spin_lock(&ensoniq->reg_lock);
2256         sctrl = ensoniq->sctrl;
2257         if (status & ES_DAC1)
2258                 sctrl &= ~ES_P1_INT_EN;
2259         if (status & ES_DAC2)
2260                 sctrl &= ~ES_P2_INT_EN;
2261         if (status & ES_ADC)
2262                 sctrl &= ~ES_R1_INT_EN;
2263         outl(sctrl, ES_REG(ensoniq, SERIAL));
2264         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2265         spin_unlock(&ensoniq->reg_lock);
2266
2267         if (status & ES_UART)
2268                 snd_ensoniq_midi_interrupt(ensoniq);
2269         if ((status & ES_DAC2) && ensoniq->playback2_substream)
2270                 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2271         if ((status & ES_ADC) && ensoniq->capture_substream)
2272                 snd_pcm_period_elapsed(ensoniq->capture_substream);
2273         if ((status & ES_DAC1) && ensoniq->playback1_substream)
2274                 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2275         return IRQ_HANDLED;
2276 }
2277
2278 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2279                                         const struct pci_device_id *pci_id)
2280 {
2281         static int dev;
2282         snd_card_t *card;
2283         ensoniq_t *ensoniq;
2284         int err, pcm_devs[2];
2285
2286         if (dev >= SNDRV_CARDS)
2287                 return -ENODEV;
2288         if (!enable[dev]) {
2289                 dev++;
2290                 return -ENOENT;
2291         }
2292
2293         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2294         if (card == NULL)
2295                 return -ENOMEM;
2296
2297         if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2298                 snd_card_free(card);
2299                 return err;
2300         }
2301
2302         pcm_devs[0] = 0; pcm_devs[1] = 1;
2303 #ifdef CHIP1370
2304         if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2305                 snd_card_free(card);
2306                 return err;
2307         }
2308 #endif
2309 #ifdef CHIP1371
2310         if ((err = snd_ensoniq_1371_mixer(ensoniq)) < 0) {
2311                 snd_card_free(card);
2312                 return err;
2313         }
2314 #endif
2315         if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2316                 snd_card_free(card);
2317                 return err;
2318         }
2319         if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2320                 snd_card_free(card);
2321                 return err;
2322         }
2323         if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2324                 snd_card_free(card);
2325                 return err;
2326         }
2327 #ifdef CHIP1370
2328         strcpy(card->driver, "ENS1370");
2329 #endif
2330 #ifdef CHIP1371
2331         strcpy(card->driver, "ENS1371");
2332 #endif
2333         strcpy(card->shortname, "Ensoniq AudioPCI");
2334         sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2335                 card->shortname,
2336                 card->driver,
2337                 ensoniq->port,
2338                 ensoniq->irq);
2339
2340         if ((err = snd_card_register(card)) < 0) {
2341                 snd_card_free(card);
2342                 return err;
2343         }
2344
2345         pci_set_drvdata(pci, card);
2346         dev++;
2347         return 0;
2348 }
2349
2350 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2351 {
2352         snd_card_free(pci_get_drvdata(pci));
2353         pci_set_drvdata(pci, NULL);
2354 }
2355
2356 static struct pci_driver driver = {
2357         .name = "Ensoniq AudioPCI",
2358         .id_table = snd_audiopci_ids,
2359         .probe = snd_audiopci_probe,
2360         .remove = __devexit_p(snd_audiopci_remove),
2361 };
2362
2363 static int __init alsa_card_ens137x_init(void)
2364 {
2365         int err;
2366
2367         if ((err = pci_module_init(&driver)) < 0) {
2368 #ifdef MODULE
2369                 printk(KERN_ERR "Ensoniq AudioPCI soundcard not found or device busy\n");
2370 #endif
2371                 return err;
2372         }
2373         return 0;
2374 }
2375
2376 static void __exit alsa_card_ens137x_exit(void)
2377 {
2378         pci_unregister_driver(&driver);
2379 }
2380
2381 module_init(alsa_card_ens137x_init)
2382 module_exit(alsa_card_ens137x_exit)
2383
2384 #ifndef MODULE
2385
2386 /* format is: snd-ens1370=enable,index,id */
2387
2388 static int __init alsa_card_ens137x_setup(char *str)
2389 {
2390         static unsigned __initdata nr_dev = 0;
2391
2392         if (nr_dev >= SNDRV_CARDS)
2393                 return 0;
2394         (void)(get_option(&str,&enable[nr_dev]) == 2 &&
2395                get_option(&str,&index[nr_dev]) == 2 &&
2396                get_id(&str,&id[nr_dev]) == 2);
2397         nr_dev++;
2398         return 1;
2399 }
2400
2401 #if defined(CHIP1370)
2402 __setup("snd-ens1370=", alsa_card_ens137x_setup);
2403 #elif defined(CHIP1371)
2404 __setup("snd-ens1371=", alsa_card_ens137x_setup);
2405 #endif
2406
2407 #endif /* ifndef MODULE */