2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
7 * Copyright (C) 1999 by Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
10 * Some useful macros for MIPS assembler code
12 * Some of the routines below contain useless nops that will be optimized
13 * away by gas in -O mode. These nops are however required to fill delay
14 * slots in noreorder mode.
19 #include <linux/config.h>
20 #include <asm/sgidefs.h>
24 #define __CAT(str1,str2) str1##str2
26 #define __CAT(str1,str2) str1/**/str2
28 #define CAT(str1,str2) __CAT(str1,str2)
32 * PIC specific declarations
33 * Not used for the kernel but here seems to be the right place.
36 #define CPRESTORE(register) \
38 #define CPADD(register) \
40 #define CPLOAD(register) \
43 #define CPRESTORE(register)
44 #define CPADD(register)
45 #define CPLOAD(register)
49 * LEAF - declare leaf routine
51 #define LEAF(symbol) \
54 .type symbol,@function; \
56 symbol: .frame sp,0,ra
59 * NESTED - declare nested routine entry point
61 #define NESTED(symbol, framesize, rpc) \
64 .type symbol,@function; \
66 symbol: .frame sp, framesize, rpc
69 * END - mark end of function
71 #define END(function) \
73 .size function,.-function
76 * EXPORT - export definition of symbol
78 #define EXPORT(symbol) \
83 * FEXPORT - export definition of a function symbol
85 #define FEXPORT(symbol) \
87 .type symbol,@function; \
91 * ABS - export absolute symbol
93 #define ABS(symbol,value) \
107 * Print formatted string
109 #define PRINT(string) \
118 .pushsection .data; \
125 #define TTABLE(string) \
126 .pushsection .text; \
129 .pushsection .data; \
134 * MIPS IV pref instruction.
135 * Use with .set noreorder only!
137 * MIPS IV implementations are free to treat this as a nop. The R5000
138 * is one of them. So we should have an option not to use this instruction.
140 #ifdef CONFIG_CPU_HAS_PREFETCH
142 #define PREF(hint,addr) \
148 #define PREFX(hint,addr) \
154 #else /* !CONFIG_CPU_HAS_PREFETCH */
156 #define PREF(hint,addr)
157 #define PREFX(hint,addr)
159 #endif /* !CONFIG_CPU_HAS_PREFETCH */
162 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
164 #if (_MIPS_ISA == _MIPS_ISA_MIPS1)
165 #define MOVN(rd,rs,rt) \
172 #define MOVZ(rd,rs,rt) \
179 #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
180 #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
181 #define MOVN(rd,rs,rt) \
188 #define MOVZ(rd,rs,rt) \
195 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
196 #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
197 (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
198 #define MOVN(rd,rs,rt) \
200 #define MOVZ(rd,rs,rt) \
202 #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
207 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
208 (_MIPS_ISA == _MIPS_ISA_MIPS32)
212 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
213 (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
219 * Macros to handle different pointer/register sizes for 32/64-bit code
232 * Use the following macros in assemblercode to load/store registers,
235 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
236 (_MIPS_ISA == _MIPS_ISA_MIPS32)
239 #define REG_SUBU subu
240 #define REG_ADDU addu
242 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
243 (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
246 #define REG_SUBU dsubu
247 #define REG_ADDU daddu
251 * How to add/sub/load/store/shift C int variables.
253 #if (_MIPS_SZINT == 32)
255 #define INT_ADDU addu
256 #define INT_ADDI addi
257 #define INT_ADDIU addiu
259 #define INT_SUBU subu
263 #define INT_SLLV sllv
265 #define INT_SRLV srlv
267 #define INT_SRAV srav
270 #if (_MIPS_SZINT == 64)
272 #define INT_ADDU daddu
273 #define INT_ADDI daddi
274 #define INT_ADDIU daddiu
276 #define INT_SUBU dsubu
280 #define INT_SLLV dsllv
282 #define INT_SRLV dsrlv
284 #define INT_SRAV dsrav
288 * How to add/sub/load/store/shift C long variables.
290 #if (_MIPS_SZLONG == 32)
292 #define LONG_ADDU addu
293 #define LONG_ADDI addi
294 #define LONG_ADDIU addiu
296 #define LONG_SUBU subu
300 #define LONG_SLLV sllv
302 #define LONG_SRLV srlv
304 #define LONG_SRAV srav
312 #if (_MIPS_SZLONG == 64)
313 #define LONG_ADD dadd
314 #define LONG_ADDU daddu
315 #define LONG_ADDI daddi
316 #define LONG_ADDIU daddiu
317 #define LONG_SUB dsub
318 #define LONG_SUBU dsubu
321 #define LONG_SLL dsll
322 #define LONG_SLLV dsllv
323 #define LONG_SRL dsrl
324 #define LONG_SRLV dsrlv
325 #define LONG_SRA dsra
326 #define LONG_SRAV dsrav
335 * How to add/sub/load/store/shift pointers.
337 #if (_MIPS_SZPTR == 32)
339 #define PTR_ADDU addu
340 #define PTR_ADDI addi
341 #define PTR_ADDIU addiu
343 #define PTR_SUBU subu
348 #define PTR_SLLV sllv
350 #define PTR_SRLV srlv
352 #define PTR_SRAV srav
354 #define PTR_SCALESHIFT 2
361 #if (_MIPS_SZPTR == 64)
363 #define PTR_ADDU daddu
364 #define PTR_ADDI daddi
365 #define PTR_ADDIU daddiu
367 #define PTR_SUBU dsubu
372 #define PTR_SLLV dsllv
374 #define PTR_SRLV dsrlv
376 #define PTR_SRAV dsrav
378 #define PTR_SCALESHIFT 3
386 * Some cp0 registers were extended to 64bit for MIPS III.
388 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
389 (_MIPS_ISA == _MIPS_ISA_MIPS32)
393 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
394 (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
399 #define SSNOP sll zero,zero,1
401 #endif /* _ASM_ASM_H */