drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/sched.h>
  20 #include <linux/string.h>
  21 #include <linux/kernel.h>
  22 #include <linux/slab.h>
  23 #include <linux/tty.h>
  24 #include <linux/serial.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/8250_pci.h>
  27
  28 #include <asm/bitops.h>
  29 #include <asm/byteorder.h>
  30 #include <asm/serial.h>
  31 #include <asm/io.h>
  32
  33 #include "8250.h"
  34
  35 /*
  36  * Definitions for PCI support.
  37  */
  38 #define FL_BASE_MASK            0x0007
  39 #define FL_BASE0                0x0000
  40 #define FL_BASE1                0x0001
  41 #define FL_BASE2                0x0002
  42 #define FL_BASE3                0x0003
  43 #define FL_BASE4                0x0004
  44 #define FL_GET_BASE(x)          (x & FL_BASE_MASK)
  45
  46 #define FL_IRQ_MASK             (0x0007 << 4)
  47 #define FL_IRQBASE0             (0x0000 << 4)
  48 #define FL_IRQBASE1             (0x0001 << 4)
  49 #define FL_IRQBASE2             (0x0002 << 4)
  50 #define FL_IRQBASE3             (0x0003 << 4)
  51 #define FL_IRQBASE4             (0x0004 << 4)
  52 #define FL_GET_IRQBASE(x)       ((x & FL_IRQ_MASK) >> 4)
  53
  54 /* Use successive BARs (PCI base address registers),
  55    else use offset into some specified BAR */
  56 #define FL_BASE_BARS            0x0008
  57
  58 /* Use the irq resource table instead of dev->irq */
  59 #define FL_IRQRESOURCE          0x0080
  60
  61 /* Use the Base address register size to cap number of ports */
  62 #define FL_REGION_SZ_CAP        0x0100
  63
  64 struct pci_board {
  65         unsigned int flags;
  66         unsigned int num_ports;
  67         unsigned int base_baud;
  68         unsigned int uart_offset;
  69         unsigned int reg_shift;
  70         unsigned int first_offset;
  71 };
  72
  73 /*
  74  * init function returns:
  75  *  > 0 - number of ports
  76  *  = 0 - use board->num_ports
  77  *  < 0 - error
  78  */
  79 struct pci_serial_quirk {
  80         u32     vendor;
  81         u32     device;
  82         u32     subvendor;
  83         u32     subdevice;
  84         int     (*init)(struct pci_dev *dev);
  85         int     (*setup)(struct pci_dev *dev, struct pci_board *board,
  86                          struct serial_struct *req, int idx);
  87         void    (*exit)(struct pci_dev *dev);
  88 };
  89
  90 #define PCI_NUM_BAR_RESOURCES   6
  91
  92 struct serial_private {
  93         unsigned int            nr;
  94         void                    *remapped_bar[PCI_NUM_BAR_RESOURCES];
  95         struct pci_serial_quirk *quirk;
  96         int                     line[0];
  97 };
  98
  99 static void moan_device(const char *str, struct pci_dev *dev)
 100 {
 101         printk(KERN_WARNING "%s: %s\n"
 102                KERN_WARNING "Please send the output of lspci -vv, this\n"
 103                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
 104                KERN_WARNING "manufacturer and name of serial board or\n"
 105                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
 106                pci_name(dev), str, dev->vendor, dev->device,
 107                dev->subsystem_vendor, dev->subsystem_device);
 108 }
 109
 110 static int
 111 setup_port(struct pci_dev *dev, struct serial_struct *req,
 112            int bar, int offset, int regshift)
 113 {
 114         struct serial_private *priv = pci_get_drvdata(dev);
 115         unsigned long port, len;
 116
 117         if (bar >= PCI_NUM_BAR_RESOURCES)
 118                 return -EINVAL;
 119
 120         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
 121                 port = pci_resource_start(dev, bar);
 122                 len =  pci_resource_len(dev, bar);
 123
 124                 if (!priv->remapped_bar[bar])
 125                         priv->remapped_bar[bar] = ioremap(port, len);
 126                 if (!priv->remapped_bar[bar])
 127                         return -ENOMEM;
 128
 129                 req->io_type = UPIO_MEM;
 130                 req->iomap_base = port + offset;
 131                 req->iomem_base = priv->remapped_bar[bar] + offset;
 132                 req->iomem_reg_shift = regshift;
 133         } else {
 134                 port = pci_resource_start(dev, bar) + offset;
 135                 req->io_type = UPIO_PORT;
 136                 req->port = port;
 137                 if (HIGH_BITS_OFFSET)
 138                         req->port_high = port >> HIGH_BITS_OFFSET;
 139         }
 140         return 0;
 141 }
 142
 143 /*
 144  * AFAVLAB uses a different mixture of BARs and offsets
 145  * Not that ugly ;) -- HW
 146  */
 147 static int
 148 afavlab_setup(struct pci_dev *dev, struct pci_board *board,
 149               struct serial_struct *req, int idx)
 150 {
 151         unsigned int bar, offset = board->first_offset;
 152
 153         bar = FL_GET_BASE(board->flags);
 154         if (idx < 4)
 155                 bar += idx;
 156         else
 157                 offset += (idx - 4) * board->uart_offset;
 158
 159         return setup_port(dev, req, bar, offset, board->reg_shift);
 160 }
 161
 162 /*
 163  * HP's Remote Management Console.  The Diva chip came in several
 164  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 165  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 166  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 167  * one Diva chip, but it has been expanded to 5 UARTs.
 168  */
 169 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
 170 {
 171         int rc = 0;
 172
 173         switch (dev->subsystem_device) {
 174         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 175         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 176         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 177         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 178                 rc = 3;
 179                 break;
 180         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 181                 rc = 2;
 182                 break;
 183         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 184                 rc = 4;
 185                 break;
 186         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 187                 rc = 1;
 188                 break;
 189         }
 190
 191         return rc;
 192 }
 193
 194 /*
 195  * HP's Diva chip puts the 4th/5th serial port further out, and
 196  * some serial ports are supposed to be hidden on certain models.
 197  */
 198 static int
 199 pci_hp_diva_setup(struct pci_dev *dev, struct pci_board *board,
 200               struct serial_struct *req, int idx)
 201 {
 202         unsigned int offset = board->first_offset;
 203         unsigned int bar = FL_GET_BASE(board->flags);
 204
 205         switch (dev->subsystem_device) {
 206         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 207                 if (idx == 3)
 208                         idx++;
 209                 break;
 210         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 211                 if (idx > 0)
 212                         idx++;
 213                 if (idx > 2)
 214                         idx++;
 215                 break;
 216         }
 217         if (idx > 2)
 218                 offset = 0x18;
 219
 220         offset += idx * board->uart_offset;
 221
 222         return setup_port(dev, req, bar, offset, board->reg_shift);
 223 }
 224
 225 /*
 226  * Added for EKF Intel i960 serial boards
 227  */
 228 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
 229 {
 230         unsigned long oldval;
 231
 232         if (!(dev->subsystem_device & 0x1000))
 233                 return -ENODEV;
 234
 235         /* is firmware started? */
 236         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 237         if (oldval == 0x00001000L) { /* RESET value */
 238                 printk(KERN_DEBUG "Local i960 firmware missing");
 239                 return -ENODEV;
 240         }
 241         return 0;
 242 }
 243
 244 /*
 245  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 246  * that the card interrupt be explicitly enabled or disabled.  This
 247  * seems to be mainly needed on card using the PLX which also use I/O
 248  * mapped memory.
 249  */
 250 static int __devinit pci_plx9050_init(struct pci_dev *dev)
 251 {
 252         u8 *p, irq_config;
 253
 254         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 255                 moan_device("no memory in bar 0", dev);
 256                 return 0;
 257         }
 258
 259         irq_config = 0x41;
 260         if (dev->vendor == PCI_VENDOR_ID_PANACOM)
 261                 irq_config = 0x43;
 262         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 263             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 264                 /*
 265                  * As the megawolf cards have the int pins active
 266                  * high, and have 2 UART chips, both ints must be
 267                  * enabled on the 9050. Also, the UARTS are set in
 268                  * 16450 mode by default, so we have to enable the
 269                  * 16C950 'enhanced' mode so that we can use the
 270                  * deep FIFOs
 271                  */
 272                 irq_config = 0x5b;
 273         }
 274
 275         /*
 276          * enable/disable interrupts
 277          */
 278         p = ioremap(pci_resource_start(dev, 0), 0x80);
 279         if (p == NULL)
 280                 return -ENOMEM;
 281         writel(irq_config, (unsigned long)p + 0x4c);
 282
 283         /*
 284          * Read the register back to ensure that it took effect.
 285          */
 286         readl((unsigned long)p + 0x4c);
 287         iounmap(p);
 288
 289         return 0;
 290 }
 291
 292 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 293 {
 294         u8 *p;
 295
 296         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 297                 return;
 298
 299         /*
 300          * disable interrupts
 301          */
 302         p = ioremap(pci_resource_start(dev, 0), 0x80);
 303         if (p != NULL) {
 304                 writel(0, p + 0x4c);
 305
 306                 /*
 307                  * Read the register back to ensure that it took effect.
 308                  */
 309                 readl(p + 0x4c);
 310                 iounmap(p);
 311         }
 312 }
 313
 314 /*
 315  * SIIG serial cards have an PCI interface chip which also controls
 316  * the UART clocking frequency. Each UART can be clocked independently
 317  * (except cards equiped with 4 UARTs) and initial clocking settings
 318  * are stored in the EEPROM chip. It can cause problems because this
 319  * version of serial driver doesn't support differently clocked UART's
 320  * on single PCI card. To prevent this, initialization functions set
 321  * high frequency clocking for all UART's on given card. It is safe (I
 322  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 323  * with other OSes (like M$ DOS).
 324  *
 325  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 326  *
 327  * There is two family of SIIG serial cards with different PCI
 328  * interface chip and different configuration methods:
 329  *     - 10x cards have control registers in IO and/or memory space;
 330  *     - 20x cards have control registers in standard PCI configuration space.
 331  *
 332  * Note: some SIIG cards are probed by the parport_serial object.
 333  */
 334
 335 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 336 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 337
 338 static int pci_siig10x_init(struct pci_dev *dev)
 339 {
 340         u16 data, *p;
 341
 342         switch (dev->device & 0xfff8) {
 343         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 344                 data = 0xffdf;
 345                 break;
 346         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 347                 data = 0xf7ff;
 348                 break;
 349         default:                        /* 1S1P, 4S */
 350                 data = 0xfffb;
 351                 break;
 352         }
 353
 354         p = ioremap(pci_resource_start(dev, 0), 0x80);
 355         if (p == NULL)
 356                 return -ENOMEM;
 357
 358         writew(readw((unsigned long) p + 0x28) & data, (unsigned long) p + 0x28);
 359         readw((unsigned long)p + 0x28);
 360         iounmap(p);
 361         return 0;
 362 }
 363
 364 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 365 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 366
 367 static int pci_siig20x_init(struct pci_dev *dev)
 368 {
 369         u8 data;
 370
 371         /* Change clock frequency for the first UART. */
 372         pci_read_config_byte(dev, 0x6f, &data);
 373         pci_write_config_byte(dev, 0x6f, data & 0xef);
 374
 375         /* If this card has 2 UART, we have to do the same with second UART. */
 376         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 377             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 378                 pci_read_config_byte(dev, 0x73, &data);
 379                 pci_write_config_byte(dev, 0x73, data & 0xef);
 380         }
 381         return 0;
 382 }
 383
 384 int pci_siig10x_fn(struct pci_dev *dev, int enable)
 385 {
 386         int ret = 0;
 387         if (enable)
 388                 ret = pci_siig10x_init(dev);
 389         return ret;
 390 }
 391
 392 int pci_siig20x_fn(struct pci_dev *dev, int enable)
 393 {
 394         int ret = 0;
 395         if (enable)
 396                 ret = pci_siig20x_init(dev);
 397         return ret;
 398 }
 399
 400 EXPORT_SYMBOL(pci_siig10x_fn);
 401 EXPORT_SYMBOL(pci_siig20x_fn);
 402
 403 /*
 404  * Timedia has an explosion of boards, and to avoid the PCI table from
 405  * growing *huge*, we use this function to collapse some 70 entries
 406  * in the PCI table into one, for sanity's and compactness's sake.
 407  */
 408 static unsigned short timedia_single_port[] = {
 409         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 410 };
 411
 412 static unsigned short timedia_dual_port[] = {
 413         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 414         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 415         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 416         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 417         0xD079, 0
 418 };
 419
 420 static unsigned short timedia_quad_port[] = {
 421         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 422         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 423         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 424         0xB157, 0
 425 };
 426
 427 static unsigned short timedia_eight_port[] = {
 428         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 429         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 430 };
 431
 432 static struct timedia_struct {
 433         int num;
 434         unsigned short *ids;
 435 } timedia_data[] = {
 436         { 1, timedia_single_port },
 437         { 2, timedia_dual_port },
 438         { 4, timedia_quad_port },
 439         { 8, timedia_eight_port },
 440         { 0, 0 }
 441 };
 442
 443 static int __devinit pci_timedia_init(struct pci_dev *dev)
 444 {
 445         unsigned short *ids;
 446         int i, j;
 447
 448         for (i = 0; timedia_data[i].num; i++) {
 449                 ids = timedia_data[i].ids;
 450                 for (j = 0; ids[j]; j++)
 451                         if (dev->subsystem_device == ids[j])
 452                                 return timedia_data[i].num;
 453         }
 454         return 0;
 455 }
 456
 457 /*
 458  * Timedia/SUNIX uses a mixture of BARs and offsets
 459  * Ugh, this is ugly as all hell --- TYT
 460  */
 461 static int
 462 pci_timedia_setup(struct pci_dev *dev, struct pci_board *board,
 463                   struct serial_struct *req, int idx)
 464 {
 465         unsigned int bar = 0, offset = board->first_offset;
 466
 467         switch (idx) {
 468         case 0:
 469                 bar = 0;
 470                 break;
 471         case 1:
 472                 offset = board->uart_offset;
 473                 bar = 0;
 474                 break;
 475         case 2:
 476                 bar = 1;
 477                 break;
 478         case 3:
 479                 offset = board->uart_offset;
 480                 bar = 1;
 481         case 4: /* BAR 2 */
 482         case 5: /* BAR 3 */
 483         case 6: /* BAR 4 */
 484         case 7: /* BAR 5 */
 485                 bar = idx - 2;
 486         }
 487
 488         return setup_port(dev, req, bar, offset, board->reg_shift);
 489 }
 490
 491 /*
 492  * Some Titan cards are also a little weird
 493  */
 494 static int
 495 titan_400l_800l_setup(struct pci_dev *dev, struct pci_board *board,
 496                       struct serial_struct *req, int idx)
 497 {
 498         unsigned int bar, offset = board->first_offset;
 499
 500         switch (idx) {
 501         case 0:
 502                 bar = 1;
 503                 break;
 504         case 1:
 505                 bar = 2;
 506                 break;
 507         default:
 508                 bar = 4;
 509                 offset = (idx - 2) * board->uart_offset;
 510         }
 511
 512         return setup_port(dev, req, bar, offset, board->reg_shift);
 513 }
 514
 515 static int __devinit pci_xircom_init(struct pci_dev *dev)
 516 {
 517         __set_current_state(TASK_UNINTERRUPTIBLE);
 518         schedule_timeout(HZ/10);
 519         return 0;
 520 }
 521
 522 static int
 523 pci_default_setup(struct pci_dev *dev, struct pci_board *board,
 524                   struct serial_struct *req, int idx)
 525 {
 526         unsigned int bar, offset = board->first_offset, maxnr;
 527
 528         bar = FL_GET_BASE(board->flags);
 529         if (board->flags & FL_BASE_BARS)
 530                 bar += idx;
 531         else
 532                 offset += idx * board->uart_offset;
 533
 534         maxnr = (pci_resource_len(dev, bar) - board->uart_offset) /
 535                 (8 << board->reg_shift);
 536
 537         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 538                 return 1;
 539
 540         return setup_port(dev, req, bar, offset, board->reg_shift);
 541 }
 542
 543 /*
 544  * Master list of serial port init/setup/exit quirks.
 545  * This does not describe the general nature of the port.
 546  * (ie, baud base, number and location of ports, etc)
 547  *
 548  * This list is ordered alphabetically by vendor then device.
 549  * Specific entries must come before more generic entries.
 550  */
 551 static struct pci_serial_quirk pci_serial_quirks[] = {
 552         /*
 553          * AFAVLAB cards.
 554          *  It is not clear whether this applies to all products.
 555          */
 556         {
 557                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 558                 .device         = PCI_ANY_ID,
 559                 .subvendor      = PCI_ANY_ID,
 560                 .subdevice      = PCI_ANY_ID,
 561                 .setup          = afavlab_setup,
 562         },
 563         /*
 564          * HP Diva
 565          */
 566         {
 567                 .vendor         = PCI_VENDOR_ID_HP,
 568                 .device         = PCI_DEVICE_ID_HP_DIVA,
 569                 .subvendor      = PCI_ANY_ID,
 570                 .subdevice      = PCI_ANY_ID,
 571                 .init           = pci_hp_diva_init,
 572                 .setup          = pci_hp_diva_setup,
 573         },
 574         /*
 575          * Intel
 576          */
 577         {
 578                 .vendor         = PCI_VENDOR_ID_INTEL,
 579                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 580                 .subvendor      = 0xe4bf,
 581                 .subdevice      = PCI_ANY_ID,
 582                 .init           = pci_inteli960ni_init,
 583                 .setup          = pci_default_setup,
 584         },
 585         /*
 586          * Panacom
 587          */
 588         {
 589                 .vendor         = PCI_VENDOR_ID_PANACOM,
 590                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 591                 .subvendor      = PCI_ANY_ID,
 592                 .subdevice      = PCI_ANY_ID,
 593                 .init           = pci_plx9050_init,
 594                 .setup          = pci_default_setup,
 595                 .exit           = __devexit_p(pci_plx9050_exit),
 596         },
 597         {
 598                 .vendor         = PCI_VENDOR_ID_PANACOM,
 599                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 600                 .subvendor      = PCI_ANY_ID,
 601                 .subdevice      = PCI_ANY_ID,
 602                 .init           = pci_plx9050_init,
 603                 .setup          = pci_default_setup,
 604                 .exit           = __devexit_p(pci_plx9050_exit),
 605         },
 606         /*
 607          * PLX
 608          */
 609         {
 610                 .vendor         = PCI_VENDOR_ID_PLX,
 611                 .device         = PCI_DEVICE_ID_PLX_9050,
 612                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 613                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 614                 .init           = pci_plx9050_init,
 615                 .setup          = pci_default_setup,
 616                 .exit           = __devexit_p(pci_plx9050_exit),
 617         },
 618         {
 619                 .vendor         = PCI_VENDOR_ID_PLX,
 620                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 621                 .subvendor      = PCI_VENDOR_ID_PLX,
 622                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 623                 .init           = pci_plx9050_init,
 624                 .setup          = pci_default_setup,
 625                 .exit           = __devexit_p(pci_plx9050_exit),
 626         },
 627         /*
 628          * SIIG cards.
 629          *  It is not clear whether these could be collapsed.
 630          */
 631         {
 632                 .vendor         = PCI_VENDOR_ID_SIIG,
 633                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_550,
 634                 .subvendor      = PCI_ANY_ID,
 635                 .subdevice      = PCI_ANY_ID,
 636                 .init           = pci_siig10x_init,
 637                 .setup          = pci_default_setup,
 638         },
 639         {
 640                 .vendor         = PCI_VENDOR_ID_SIIG,
 641                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_650,
 642                 .subvendor      = PCI_ANY_ID,
 643                 .subdevice      = PCI_ANY_ID,
 644                 .init           = pci_siig10x_init,
 645                 .setup          = pci_default_setup,
 646         },
 647         {
 648                 .vendor         = PCI_VENDOR_ID_SIIG,
 649                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_850,
 650                 .subvendor      = PCI_ANY_ID,
 651                 .subdevice      = PCI_ANY_ID,
 652                 .init           = pci_siig10x_init,
 653                 .setup          = pci_default_setup,
 654         },
 655         {
 656                 .vendor         = PCI_VENDOR_ID_SIIG,
 657                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_550,
 658                 .subvendor      = PCI_ANY_ID,
 659                 .subdevice      = PCI_ANY_ID,
 660                 .init           = pci_siig10x_init,
 661                 .setup          = pci_default_setup,
 662         },
 663         {
 664                 .vendor         = PCI_VENDOR_ID_SIIG,
 665                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_650,
 666                 .subvendor      = PCI_ANY_ID,
 667                 .subdevice      = PCI_ANY_ID,
 668                 .init           = pci_siig10x_init,
 669                 .setup          = pci_default_setup,
 670         },
 671         {
 672                 .vendor         = PCI_VENDOR_ID_SIIG,
 673                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_850,
 674                 .subvendor      = PCI_ANY_ID,
 675                 .subdevice      = PCI_ANY_ID,
 676                 .init           = pci_siig10x_init,
 677                 .setup          = pci_default_setup,
 678         },
 679         {
 680                 .vendor         = PCI_VENDOR_ID_SIIG,
 681                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_550,
 682                 .subvendor      = PCI_ANY_ID,
 683                 .subdevice      = PCI_ANY_ID,
 684                 .init           = pci_siig10x_init,
 685                 .setup          = pci_default_setup,
 686         },
 687         {
 688                 .vendor         = PCI_VENDOR_ID_SIIG,
 689                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_650,
 690                 .subvendor      = PCI_ANY_ID,
 691                 .subdevice      = PCI_ANY_ID,
 692                 .init           = pci_siig10x_init,
 693                 .setup          = pci_default_setup,
 694         },
 695         {
 696                 .vendor         = PCI_VENDOR_ID_SIIG,
 697                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_850,
 698                 .subvendor      = PCI_ANY_ID,
 699                 .subdevice      = PCI_ANY_ID,
 700                 .init           = pci_siig10x_init,
 701                 .setup          = pci_default_setup,
 702         },
 703         {
 704                 .vendor         = PCI_VENDOR_ID_SIIG,
 705                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_550,
 706                 .subvendor      = PCI_ANY_ID,
 707                 .subdevice      = PCI_ANY_ID,
 708                 .init           = pci_siig20x_init,
 709                 .setup          = pci_default_setup,
 710         },
 711         {
 712                 .vendor         = PCI_VENDOR_ID_SIIG,
 713                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_650,
 714                 .subvendor      = PCI_ANY_ID,
 715                 .subdevice      = PCI_ANY_ID,
 716                 .init           = pci_siig20x_init,
 717                 .setup          = pci_default_setup,
 718         },
 719         {
 720                 .vendor         = PCI_VENDOR_ID_SIIG,
 721                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_850,
 722                 .subvendor      = PCI_ANY_ID,
 723                 .subdevice      = PCI_ANY_ID,
 724                 .init           = pci_siig20x_init,
 725                 .setup          = pci_default_setup,
 726         },
 727         {
 728                 .vendor         = PCI_VENDOR_ID_SIIG,
 729                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_550,
 730                 .subvendor      = PCI_ANY_ID,
 731                 .subdevice      = PCI_ANY_ID,
 732                 .init           = pci_siig20x_init,
 733                 .setup          = pci_default_setup,
 734         },
 735         {       .vendor         = PCI_VENDOR_ID_SIIG,
 736                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_650,
 737                 .subvendor      = PCI_ANY_ID,
 738                 .subdevice      = PCI_ANY_ID,
 739                 .init           = pci_siig20x_init,
 740                 .setup          = pci_default_setup,
 741         },
 742         {
 743                 .vendor         = PCI_VENDOR_ID_SIIG,
 744                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_850,
 745                 .subvendor      = PCI_ANY_ID,
 746                 .subdevice      = PCI_ANY_ID,
 747                 .init           = pci_siig20x_init,
 748                 .setup          = pci_default_setup,
 749         },
 750         {
 751                 .vendor         = PCI_VENDOR_ID_SIIG,
 752                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_550,
 753                 .subvendor      = PCI_ANY_ID,
 754                 .subdevice      = PCI_ANY_ID,
 755                 .init           = pci_siig20x_init,
 756                 .setup          = pci_default_setup,
 757         },
 758         {
 759                 .vendor         = PCI_VENDOR_ID_SIIG,
 760                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_650,
 761                 .subvendor      = PCI_ANY_ID,
 762                 .subdevice      = PCI_ANY_ID,
 763                 .init           = pci_siig20x_init,
 764                 .setup          = pci_default_setup,
 765         },
 766         {
 767                 .vendor         = PCI_VENDOR_ID_SIIG,
 768                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_850,
 769                 .subvendor      = PCI_ANY_ID,
 770                 .subdevice      = PCI_ANY_ID,
 771                 .init           = pci_siig20x_init,
 772                 .setup          = pci_default_setup,
 773         },
 774         /*
 775          * Titan cards
 776          */
 777         {
 778                 .vendor         = PCI_VENDOR_ID_TITAN,
 779                 .device         = PCI_DEVICE_ID_TITAN_400L,
 780                 .subvendor      = PCI_ANY_ID,
 781                 .subdevice      = PCI_ANY_ID,
 782                 .setup          = titan_400l_800l_setup,
 783         },
 784         {
 785                 .vendor         = PCI_VENDOR_ID_TITAN,
 786                 .device         = PCI_DEVICE_ID_TITAN_800L,
 787                 .subvendor      = PCI_ANY_ID,
 788                 .subdevice      = PCI_ANY_ID,
 789                 .setup          = titan_400l_800l_setup,
 790         },
 791         /*
 792          * Timedia cards
 793          */
 794         {
 795                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 796                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 797                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 798                 .subdevice      = PCI_ANY_ID,
 799                 .init           = pci_timedia_init,
 800                 .setup          = pci_timedia_setup,
 801         },
 802         {
 803                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 804                 .device         = PCI_ANY_ID,
 805                 .subvendor      = PCI_ANY_ID,
 806                 .subdevice      = PCI_ANY_ID,
 807                 .setup          = pci_timedia_setup,
 808         },
 809         /*
 810          * Xircom cards
 811          */
 812         {
 813                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 814                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 815                 .subvendor      = PCI_ANY_ID,
 816                 .subdevice      = PCI_ANY_ID,
 817                 .init           = pci_xircom_init,
 818                 .setup          = pci_default_setup,
 819         },
 820         /*
 821          * Default "match everything" terminator entry
 822          */
 823         {
 824                 .vendor         = PCI_ANY_ID,
 825                 .device         = PCI_ANY_ID,
 826                 .subvendor      = PCI_ANY_ID,
 827                 .subdevice      = PCI_ANY_ID,
 828                 .setup          = pci_default_setup,
 829         }
 830 };
 831
 832 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
 833 {
 834         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
 835 }
 836
 837 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
 838 {
 839         struct pci_serial_quirk *quirk;
 840
 841         for (quirk = pci_serial_quirks; ; quirk++)
 842                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
 843                     quirk_id_matches(quirk->device, dev->device) &&
 844                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
 845                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
 846                         break;
 847         return quirk;
 848 }
 849
 850 static _INLINE_ int
 851 get_pci_irq(struct pci_dev *dev, struct pci_board *board, int idx)
 852 {
 853         int base_idx;
 854
 855         if ((board->flags & FL_IRQRESOURCE) == 0)
 856                 return dev->irq;
 857
 858         base_idx = FL_GET_IRQBASE(board->flags);
 859
 860         if (base_idx > DEVICE_COUNT_IRQ)
 861                 return 0;
 862
 863         return dev->irq_resource[base_idx].start;
 864 }
 865
 866 /*
 867  * This is the configuration table for all of the PCI serial boards
 868  * which we support.  It is directly indexed by the pci_board_num_t enum
 869  * value, which is encoded in the pci_device_id PCI probe table's
 870  * driver_data member.
 871  *
 872  * The makeup of these names are:
 873  *  pbn_bn{_bt}_n_baud
 874  *
 875  *  bn   = PCI BAR number
 876  *  bt   = Index using PCI BARs
 877  *  n    = number of serial ports
 878  *  baud = baud rate
 879  *
 880  * Please note: in theory if n = 1, _bt infix should make no difference.
 881  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
 882  */
 883 enum pci_board_num_t {
 884         pbn_default = 0,
 885
 886         pbn_b0_1_115200,
 887         pbn_b0_2_115200,
 888         pbn_b0_4_115200,
 889         pbn_b0_5_115200,
 890
 891         pbn_b0_1_921600,
 892         pbn_b0_2_921600,
 893         pbn_b0_4_921600,
 894
 895         pbn_b0_bt_1_115200,
 896         pbn_b0_bt_2_115200,
 897         pbn_b0_bt_8_115200,
 898
 899         pbn_b0_bt_1_460800,
 900         pbn_b0_bt_2_460800,
 901         pbn_b0_bt_4_460800,
 902
 903         pbn_b0_bt_1_921600,
 904         pbn_b0_bt_2_921600,
 905         pbn_b0_bt_4_921600,
 906         pbn_b0_bt_8_921600,
 907
 908         pbn_b1_1_115200,
 909         pbn_b1_2_115200,
 910         pbn_b1_4_115200,
 911         pbn_b1_8_115200,
 912
 913         pbn_b1_1_921600,
 914         pbn_b1_2_921600,
 915         pbn_b1_4_921600,
 916         pbn_b1_8_921600,
 917
 918         pbn_b1_bt_2_921600,
 919
 920         pbn_b1_2_1382400,
 921         pbn_b1_4_1382400,
 922         pbn_b1_8_1382400,
 923
 924         pbn_b2_1_115200,
 925         pbn_b2_8_115200,
 926
 927         pbn_b2_1_460800,
 928         pbn_b2_4_460800,
 929         pbn_b2_8_460800,
 930         pbn_b2_16_460800,
 931
 932         pbn_b2_1_921600,
 933         pbn_b2_4_921600,
 934         pbn_b2_8_921600,
 935
 936         pbn_b2_bt_1_115200,
 937         pbn_b2_bt_2_115200,
 938         pbn_b2_bt_4_115200,
 939
 940         pbn_b2_bt_2_921600,
 941         pbn_b2_bt_4_921600,
 942
 943         pbn_b3_4_115200,
 944         pbn_b3_8_115200,
 945
 946         /*
 947          * Board-specific versions.
 948          */
 949         pbn_panacom,
 950         pbn_panacom2,
 951         pbn_panacom4,
 952         pbn_plx_romulus,
 953         pbn_oxsemi,
 954         pbn_intel_i960,
 955         pbn_sgi_ioc3,
 956         pbn_nec_nile4,
 957         pbn_computone_4,
 958         pbn_computone_6,
 959         pbn_computone_8,
 960 };
 961
 962 static struct pci_board pci_boards[] __devinitdata = {
 963         [pbn_default] = {
 964                 .flags          = FL_BASE0,
 965                 .num_ports      = 1,
 966                 .base_baud      = 115200,
 967                 .uart_offset    = 8,
 968         },
 969         [pbn_b0_1_115200] = {
 970                 .flags          = FL_BASE0,
 971                 .num_ports      = 1,
 972                 .base_baud      = 115200,
 973                 .uart_offset    = 8,
 974         },
 975         [pbn_b0_2_115200] = {
 976                 .flags          = FL_BASE0,
 977                 .num_ports      = 2,
 978                 .base_baud      = 115200,
 979                 .uart_offset    = 8,
 980         },
 981         [pbn_b0_4_115200] = {
 982                 .flags          = FL_BASE0,
 983                 .num_ports      = 4,
 984                 .base_baud      = 115200,
 985                 .uart_offset    = 8,
 986         },
 987         [pbn_b0_5_115200] = {
 988                 .flags          = FL_BASE0,
 989                 .num_ports      = 5,
 990                 .base_baud      = 115200,
 991                 .uart_offset    = 8,
 992         },
 993
 994         [pbn_b0_1_921600] = {
 995                 .flags          = FL_BASE0,
 996                 .num_ports      = 1,
 997                 .base_baud      = 921600,
 998                 .uart_offset    = 8,
 999         },
1000         [pbn_b0_2_921600] = {
1001                 .flags          = FL_BASE0,
1002                 .num_ports      = 2,
1003                 .base_baud      = 921600,
1004                 .uart_offset    = 8,
1005         },
1006         [pbn_b0_4_921600] = {
1007                 .flags          = FL_BASE0,
1008                 .num_ports      = 4,
1009                 .base_baud      = 921600,
1010                 .uart_offset    = 8,
1011         },
1012
1013         [pbn_b0_bt_1_115200] = {
1014                 .flags          = FL_BASE0|FL_BASE_BARS,
1015                 .num_ports      = 1,
1016                 .base_baud      = 115200,
1017                 .uart_offset    = 8,
1018         },
1019         [pbn_b0_bt_2_115200] = {
1020                 .flags          = FL_BASE0|FL_BASE_BARS,
1021                 .num_ports      = 2,
1022                 .base_baud      = 115200,
1023                 .uart_offset    = 8,
1024         },
1025         [pbn_b0_bt_8_115200] = {
1026                 .flags          = FL_BASE0|FL_BASE_BARS,
1027                 .num_ports      = 8,
1028                 .base_baud      = 115200,
1029                 .uart_offset    = 8,
1030         },
1031
1032         [pbn_b0_bt_1_460800] = {
1033                 .flags          = FL_BASE0|FL_BASE_BARS,
1034                 .num_ports      = 1,
1035                 .base_baud      = 460800,
1036                 .uart_offset    = 8,
1037         },
1038         [pbn_b0_bt_2_460800] = {
1039                 .flags          = FL_BASE0|FL_BASE_BARS,
1040                 .num_ports      = 2,
1041                 .base_baud      = 460800,
1042                 .uart_offset    = 8,
1043         },
1044         [pbn_b0_bt_4_460800] = {
1045                 .flags          = FL_BASE0|FL_BASE_BARS,
1046                 .num_ports      = 4,
1047                 .base_baud      = 460800,
1048                 .uart_offset    = 8,
1049         },
1050
1051         [pbn_b0_bt_1_921600] = {
1052                 .flags          = FL_BASE0|FL_BASE_BARS,
1053                 .num_ports      = 1,
1054                 .base_baud      = 921600,
1055                 .uart_offset    = 8,
1056         },
1057         [pbn_b0_bt_2_921600] = {
1058                 .flags          = FL_BASE0|FL_BASE_BARS,
1059                 .num_ports      = 2,
1060                 .base_baud      = 921600,
1061                 .uart_offset    = 8,
1062         },
1063         [pbn_b0_bt_4_921600] = {
1064                 .flags          = FL_BASE0|FL_BASE_BARS,
1065                 .num_ports      = 4,
1066                 .base_baud      = 921600,
1067                 .uart_offset    = 8,
1068         },
1069         [pbn_b0_bt_8_921600] = {
1070                 .flags          = FL_BASE0|FL_BASE_BARS,
1071                 .num_ports      = 8,
1072                 .base_baud      = 921600,
1073                 .uart_offset    = 8,
1074         },
1075
1076         [pbn_b1_1_115200] = {
1077                 .flags          = FL_BASE1,
1078                 .num_ports      = 1,
1079                 .base_baud      = 115200,
1080                 .uart_offset    = 8,
1081         },
1082         [pbn_b1_2_115200] = {
1083                 .flags          = FL_BASE1,
1084                 .num_ports      = 2,
1085                 .base_baud      = 115200,
1086                 .uart_offset    = 8,
1087         },
1088         [pbn_b1_4_115200] = {
1089                 .flags          = FL_BASE1,
1090                 .num_ports      = 4,
1091                 .base_baud      = 115200,
1092                 .uart_offset    = 8,
1093         },
1094         [pbn_b1_8_115200] = {
1095                 .flags          = FL_BASE1,
1096                 .num_ports      = 8,
1097                 .base_baud      = 115200,
1098                 .uart_offset    = 8,
1099         },
1100
1101         [pbn_b1_1_921600] = {
1102                 .flags          = FL_BASE1,
1103                 .num_ports      = 1,
1104                 .base_baud      = 921600,
1105                 .uart_offset    = 8,
1106         },
1107         [pbn_b1_2_921600] = {
1108                 .flags          = FL_BASE1,
1109                 .num_ports      = 2,
1110                 .base_baud      = 921600,
1111                 .uart_offset    = 8,
1112         },
1113         [pbn_b1_4_921600] = {
1114                 .flags          = FL_BASE1,
1115                 .num_ports      = 4,
1116                 .base_baud      = 921600,
1117                 .uart_offset    = 8,
1118         },
1119         [pbn_b1_8_921600] = {
1120                 .flags          = FL_BASE1,
1121                 .num_ports      = 8,
1122                 .base_baud      = 921600,
1123                 .uart_offset    = 8,
1124         },
1125
1126         [pbn_b1_bt_2_921600] = {
1127                 .flags          = FL_BASE1|FL_BASE_BARS,
1128                 .num_ports      = 2,
1129                 .base_baud      = 921600,
1130                 .uart_offset    = 8,
1131         },
1132
1133         [pbn_b1_2_1382400] = {
1134                 .flags          = FL_BASE1,
1135                 .num_ports      = 2,
1136                 .base_baud      = 1382400,
1137                 .uart_offset    = 8,
1138         },
1139         [pbn_b1_4_1382400] = {
1140                 .flags          = FL_BASE1,
1141                 .num_ports      = 4,
1142                 .base_baud      = 1382400,
1143                 .uart_offset    = 8,
1144         },
1145         [pbn_b1_8_1382400] = {
1146                 .flags          = FL_BASE1,
1147                 .num_ports      = 8,
1148                 .base_baud      = 1382400,
1149                 .uart_offset    = 8,
1150         },
1151
1152         [pbn_b2_1_115200] = {
1153                 .flags          = FL_BASE2,
1154                 .num_ports      = 1,
1155                 .base_baud      = 115200,
1156                 .uart_offset    = 8,
1157         },
1158         [pbn_b2_8_115200] = {
1159                 .flags          = FL_BASE2,
1160                 .num_ports      = 8,
1161                 .base_baud      = 115200,
1162                 .uart_offset    = 8,
1163         },
1164
1165         [pbn_b2_1_460800] = {
1166                 .flags          = FL_BASE2,
1167                 .num_ports      = 1,
1168                 .base_baud      = 460800,
1169                 .uart_offset    = 8,
1170         },
1171         [pbn_b2_4_460800] = {
1172                 .flags          = FL_BASE2,
1173                 .num_ports      = 4,
1174                 .base_baud      = 460800,
1175                 .uart_offset    = 8,
1176         },
1177         [pbn_b2_8_460800] = {
1178                 .flags          = FL_BASE2,
1179                 .num_ports      = 8,
1180                 .base_baud      = 460800,
1181                 .uart_offset    = 8,
1182         },
1183         [pbn_b2_16_460800] = {
1184                 .flags          = FL_BASE2,
1185                 .num_ports      = 16,
1186                 .base_baud      = 460800,
1187                 .uart_offset    = 8,
1188          },
1189
1190         [pbn_b2_1_921600] = {
1191                 .flags          = FL_BASE2,
1192                 .num_ports      = 1,
1193                 .base_baud      = 921600,
1194                 .uart_offset    = 8,
1195         },
1196         [pbn_b2_4_921600] = {
1197                 .flags          = FL_BASE2,
1198                 .num_ports      = 4,
1199                 .base_baud      = 921600,
1200                 .uart_offset    = 8,
1201         },
1202         [pbn_b2_8_921600] = {
1203                 .flags          = FL_BASE2,
1204                 .num_ports      = 8,
1205                 .base_baud      = 921600,
1206                 .uart_offset    = 8,
1207         },
1208
1209         [pbn_b2_bt_1_115200] = {
1210                 .flags          = FL_BASE2|FL_BASE_BARS,
1211                 .num_ports      = 1,
1212                 .base_baud      = 115200,
1213                 .uart_offset    = 8,
1214         },
1215         [pbn_b2_bt_2_115200] = {
1216                 .flags          = FL_BASE2|FL_BASE_BARS,
1217                 .num_ports      = 2,
1218                 .base_baud      = 115200,
1219                 .uart_offset    = 8,
1220         },
1221         [pbn_b2_bt_4_115200] = {
1222                 .flags          = FL_BASE2|FL_BASE_BARS,
1223                 .num_ports      = 4,
1224                 .base_baud      = 115200,
1225                 .uart_offset    = 8,
1226         },
1227
1228         [pbn_b2_bt_2_921600] = {
1229                 .flags          = FL_BASE2|FL_BASE_BARS,
1230                 .num_ports      = 2,
1231                 .base_baud      = 921600,
1232                 .uart_offset    = 8,
1233         },
1234         [pbn_b2_bt_4_921600] = {
1235                 .flags          = FL_BASE2|FL_BASE_BARS,
1236                 .num_ports      = 4,
1237                 .base_baud      = 921600,
1238                 .uart_offset    = 8,
1239         },
1240
1241         [pbn_b3_4_115200] = {
1242                 .flags          = FL_BASE3,
1243                 .num_ports      = 4,
1244                 .base_baud      = 115200,
1245                 .uart_offset    = 8,
1246         },
1247         [pbn_b3_8_115200] = {
1248                 .flags          = FL_BASE3,
1249                 .num_ports      = 8,
1250                 .base_baud      = 115200,
1251                 .uart_offset    = 8,
1252         },
1253
1254         /*
1255          * Entries following this are board-specific.
1256          */
1257
1258         /*
1259          * Panacom - IOMEM
1260          */
1261         [pbn_panacom] = {
1262                 .flags          = FL_BASE2,
1263                 .num_ports      = 2,
1264                 .base_baud      = 921600,
1265                 .uart_offset    = 0x400,
1266                 .reg_shift      = 7,
1267         },
1268         [pbn_panacom2] = {
1269                 .flags          = FL_BASE2|FL_BASE_BARS,
1270                 .num_ports      = 2,
1271                 .base_baud      = 921600,
1272                 .uart_offset    = 0x400,
1273                 .reg_shift      = 7,
1274         },
1275         [pbn_panacom4] = {
1276                 .flags          = FL_BASE2|FL_BASE_BARS,
1277                 .num_ports      = 4,
1278                 .base_baud      = 921600,
1279                 .uart_offset    = 0x400,
1280                 .reg_shift      = 7,
1281         },
1282
1283         /* I think this entry is broken - the first_offset looks wrong --rmk */
1284         [pbn_plx_romulus] = {
1285                 .flags          = FL_BASE2,
1286                 .num_ports      = 4,
1287                 .base_baud      = 921600,
1288                 .uart_offset    = 8 << 2,
1289                 .reg_shift      = 2,
1290                 .first_offset   = 0x03,
1291         },
1292
1293         /*
1294          * This board uses the size of PCI Base region 0 to
1295          * signal now many ports are available
1296          */
1297         [pbn_oxsemi] = {
1298                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1299                 .num_ports      = 32,
1300                 .base_baud      = 115200,
1301                 .uart_offset    = 8,
1302         },
1303
1304         /*
1305          * EKF addition for i960 Boards form EKF with serial port.
1306          * Max 256 ports.
1307          */
1308         [pbn_intel_i960] = {
1309                 .flags          = FL_BASE0,
1310                 .num_ports      = 32,
1311                 .base_baud      = 921600,
1312                 .uart_offset    = 8 << 2,
1313                 .reg_shift      = 2,
1314                 .first_offset   = 0x10000,
1315         },
1316         [pbn_sgi_ioc3] = {
1317                 .flags          = FL_BASE0|FL_IRQRESOURCE,
1318                 .num_ports      = 1,
1319                 .base_baud      = 458333,
1320                 .uart_offset    = 8,
1321                 .reg_shift      = 0,
1322                 .first_offset   = 0x20178,
1323         },
1324
1325         /*
1326          * NEC Vrc-5074 (Nile 4) builtin UART.
1327          */
1328         [pbn_nec_nile4] = {
1329                 .flags          = FL_BASE0,
1330                 .num_ports      = 1,
1331                 .base_baud      = 520833,
1332                 .uart_offset    = 8 << 3,
1333                 .reg_shift      = 3,
1334                 .first_offset   = 0x300,
1335         },
1336
1337         /*
1338          * Computone - uses IOMEM.
1339          */
1340         [pbn_computone_4] = {
1341                 .flags          = FL_BASE0,
1342                 .num_ports      = 4,
1343                 .base_baud      = 921600,
1344                 .uart_offset    = 0x40,
1345                 .reg_shift      = 2,
1346                 .first_offset   = 0x200,
1347         },
1348         [pbn_computone_6] = {
1349                 .flags          = FL_BASE0,
1350                 .num_ports      = 6,
1351                 .base_baud      = 921600,
1352                 .uart_offset    = 0x40,
1353                 .reg_shift      = 2,
1354                 .first_offset   = 0x200,
1355         },
1356         [pbn_computone_8] = {
1357                 .flags          = FL_BASE0,
1358                 .num_ports      = 8,
1359                 .base_baud      = 921600,
1360                 .uart_offset    = 0x40,
1361                 .reg_shift      = 2,
1362                 .first_offset   = 0x200,
1363         },
1364 };
1365
1366 /*
1367  * Given a complete unknown PCI device, try to use some heuristics to
1368  * guess what the configuration might be, based on the pitiful PCI
1369  * serial specs.  Returns 0 on success, 1 on failure.
1370  */
1371 static int __devinit
1372 serial_pci_guess_board(struct pci_dev *dev, struct pci_board *board)
1373 {
1374         int num_iomem, num_port, first_port = -1, i;
1375
1376         /*
1377          * If it is not a communications device or the programming
1378          * interface is greater than 6, give up.
1379          *
1380          * (Should we try to make guesses for multiport serial devices
1381          * later?)
1382          */
1383         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1384              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1385             (dev->class & 0xff) > 6)
1386                 return -ENODEV;
1387
1388         num_iomem = num_port = 0;
1389         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1390                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1391                         num_port++;
1392                         if (first_port == -1)
1393                                 first_port = i;
1394                 }
1395                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1396                         num_iomem++;
1397         }
1398
1399         /*
1400          * If there is 1 or 0 iomem regions, and exactly one port,
1401          * use it.  We guess the number of ports based on the IO
1402          * region size.
1403          */
1404         if (num_iomem <= 1 && num_port == 1) {
1405                 board->flags = first_port;
1406                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1407                 return 0;
1408         }
1409
1410         /*
1411          * Now guess if we've got a board which indexes by BARs.
1412          * Each IO BAR should be 8 bytes, and they should follow
1413          * consecutively.
1414          */
1415         first_port = -1;
1416         num_port = 0;
1417         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1418                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1419                     pci_resource_len(dev, i) == 8 &&
1420                     (first_port == -1 || (first_port + num_port) == i)) {
1421                         num_port++;
1422                         if (first_port == -1)
1423                                 first_port = i;
1424                 }
1425         }
1426
1427         if (num_port > 1) {
1428                 board->flags = first_port | FL_BASE_BARS;
1429                 board->num_ports = num_port;
1430                 return 0;
1431         }
1432
1433         return -ENODEV;
1434 }
1435
1436 static inline int
1437 serial_pci_matches(struct pci_board *board, struct pci_board *guessed)
1438 {
1439         return
1440             board->num_ports == guessed->num_ports &&
1441             board->base_baud == guessed->base_baud &&
1442             board->uart_offset == guessed->uart_offset &&
1443             board->reg_shift == guessed->reg_shift &&
1444             board->first_offset == guessed->first_offset;
1445 }
1446
1447 /*
1448  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1449  * to the arrangement of serial ports on a PCI card.
1450  */
1451 static int __devinit
1452 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1453 {
1454         struct serial_private *priv;
1455         struct pci_board *board, tmp;
1456         struct pci_serial_quirk *quirk;
1457         struct serial_struct serial_req;
1458         int base_baud, rc, nr_ports, i;
1459
1460         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1461                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1462                         ent->driver_data);
1463                 return -EINVAL;
1464         }
1465
1466         board = &pci_boards[ent->driver_data];
1467
1468         rc = pci_enable_device(dev);
1469         if (rc)
1470                 return rc;
1471
1472         if (ent->driver_data == pbn_default) {
1473                 /*
1474                  * Use a copy of the pci_board entry for this;
1475                  * avoid changing entries in the table.
1476                  */
1477                 memcpy(&tmp, board, sizeof(struct pci_board));
1478                 board = &tmp;
1479
1480                 /*
1481                  * We matched one of our class entries.  Try to
1482                  * determine the parameters of this board.
1483                  */
1484                 rc = serial_pci_guess_board(dev, board);
1485                 if (rc)
1486                         goto disable;
1487         } else {
1488                 /*
1489                  * We matched an explicit entry.  If we are able to
1490                  * detect this boards settings with our heuristic,
1491                  * then we no longer need this entry.
1492                  */
1493                 memcpy(&tmp, &pci_boards[pbn_default], sizeof(struct pci_board));
1494                 rc = serial_pci_guess_board(dev, &tmp);
1495                 if (rc == 0 && serial_pci_matches(board, &tmp))
1496                         moan_device("Redundant entry in serial pci_table.",
1497                                     dev);
1498         }
1499
1500         nr_ports = board->num_ports;
1501
1502         /*
1503          * Find an init and setup quirks.
1504          */
1505         quirk = find_quirk(dev);
1506
1507         /*
1508          * Run the new-style initialization function.
1509          * The initialization function returns:
1510          *  <0  - error
1511          *   0  - use board->num_ports
1512          *  >0  - number of ports
1513          */
1514         if (quirk->init) {
1515                 rc = quirk->init(dev);
1516                 if (rc < 0)
1517                         goto disable;
1518                 if (rc)
1519                         nr_ports = rc;
1520         }
1521
1522         priv = kmalloc(sizeof(struct serial_private) +
1523                        sizeof(unsigned int) * nr_ports,
1524                        GFP_KERNEL);
1525         if (!priv) {
1526                 rc = -ENOMEM;
1527                 goto deinit;
1528         }
1529
1530         memset(priv, 0, sizeof(struct serial_private) +
1531                         sizeof(unsigned int) * nr_ports);
1532
1533         priv->quirk = quirk;
1534         pci_set_drvdata(dev, priv);
1535
1536         base_baud = board->base_baud;
1537         if (!base_baud) {
1538                 moan_device("Board entry does not specify baud rate.", dev);
1539                 base_baud = BASE_BAUD;
1540         }
1541         for (i = 0; i < nr_ports; i++) {
1542                 memset(&serial_req, 0, sizeof(serial_req));
1543                 serial_req.flags = UPF_SKIP_TEST | UPF_AUTOPROBE |
1544                                    UPF_RESOURCES | UPF_SHARE_IRQ;
1545                 serial_req.baud_base = base_baud;
1546                 serial_req.irq = get_pci_irq(dev, board, i);
1547                 if (quirk->setup(dev, board, &serial_req, i))
1548                         break;
1549 #ifdef SERIAL_DEBUG_PCI
1550                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1551                        serial_req.port, serial_req.irq, serial_req.io_type);
1552 #endif
1553
1554                 priv->line[i] = register_serial(&serial_req);
1555                 if (priv->line[i] < 0)
1556                         break;
1557         }
1558
1559         priv->nr = i;
1560
1561         return 0;
1562
1563  deinit:
1564         if (quirk->exit)
1565                 quirk->exit(dev);
1566  disable:
1567         pci_disable_device(dev);
1568         return rc;
1569 }
1570
1571 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1572 {
1573         struct serial_private *priv = pci_get_drvdata(dev);
1574
1575         pci_set_drvdata(dev, NULL);
1576
1577         if (priv) {
1578                 struct pci_serial_quirk *quirk;
1579                 int i;
1580
1581                 for (i = 0; i < priv->nr; i++)
1582                         unregister_serial(priv->line[i]);
1583
1584                 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1585                         if (priv->remapped_bar[i])
1586                                 iounmap(priv->remapped_bar[i]);
1587                         priv->remapped_bar[i] = NULL;
1588                 }
1589
1590                 /*
1591                  * Find the exit quirks.
1592                  */
1593                 quirk = find_quirk(dev);
1594                 if (quirk->exit)
1595                         quirk->exit(dev);
1596
1597                 pci_disable_device(dev);
1598
1599                 kfree(priv);
1600         }
1601 }
1602
1603 static int pciserial_save_state_one(struct pci_dev *dev, u32 state)
1604 {
1605         struct serial_private *priv = pci_get_drvdata(dev);
1606
1607         if (priv) {
1608                 int i;
1609
1610                 for (i = 0; i < priv->nr; i++)
1611                         serial8250_suspend_port(priv->line[i], SUSPEND_SAVE_STATE);
1612         }
1613         return 0;
1614 }
1615
1616 static int pciserial_suspend_one(struct pci_dev *dev, u32 state)
1617 {
1618         struct serial_private *priv = pci_get_drvdata(dev);
1619
1620         if (priv) {
1621                 int i;
1622
1623                 for (i = 0; i < priv->nr; i++)
1624                         serial8250_suspend_port(priv->line[i], SUSPEND_POWER_DOWN);
1625         }
1626         return 0;
1627 }
1628
1629 static int pciserial_resume_one(struct pci_dev *dev)
1630 {
1631         struct serial_private *priv = pci_get_drvdata(dev);
1632
1633         if (priv) {
1634                 int i;
1635
1636                 /*
1637                  * Ensure that the board is correctly configured.
1638                  */
1639                 if (priv->quirk->init)
1640                         priv->quirk->init(dev);
1641
1642                 for (i = 0; i < priv->nr; i++) {
1643                         serial8250_resume_port(priv->line[i], RESUME_POWER_ON);
1644                         serial8250_resume_port(priv->line[i], RESUME_RESTORE_STATE);
1645                 }
1646         }
1647         return 0;
1648 }
1649
1650 static struct pci_device_id serial_pci_tbl[] = {
1651         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1652                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1653                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1654                 pbn_b1_8_1382400 },
1655         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1656                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1657                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1658                 pbn_b1_4_1382400 },
1659         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1660                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1661                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1662                 pbn_b1_2_1382400 },
1663         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1664                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1665                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1666                 pbn_b1_8_1382400 },
1667         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1668                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1669                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1670                 pbn_b1_4_1382400 },
1671         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1672                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1673                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1674                 pbn_b1_2_1382400 },
1675         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1676                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1677                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1678                 pbn_b1_8_921600 },
1679         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1680                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1681                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1682                 pbn_b1_8_921600 },
1683         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1684                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1685                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1686                 pbn_b1_4_921600 },
1687         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1688                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1689                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1690                 pbn_b1_4_921600 },
1691         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1692                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1693                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1694                 pbn_b1_2_921600 },
1695         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1696                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1697                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1698                 pbn_b1_8_921600 },
1699         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1700                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1701                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1702                 pbn_b1_8_921600 },
1703         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1704                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1705                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1706                 pbn_b1_4_921600 },
1707
1708         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1709                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1710                 pbn_b2_bt_1_115200 },
1711         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1712                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1713                 pbn_b2_bt_2_115200 },
1714         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1715                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1716                 pbn_b2_bt_4_115200 },
1717         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1718                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1719                 pbn_b2_bt_2_115200 },
1720         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1721                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1722                 pbn_b2_bt_4_115200 },
1723         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1724                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1725                 pbn_b2_8_115200 },
1726
1727         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1728                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1729                 pbn_b2_bt_2_115200 },
1730         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1731                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1732                 pbn_b2_bt_2_921600 },
1733         /*
1734          * VScom SPCOM800, from sl@s.pl
1735          */
1736         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1737                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1738                 pbn_b2_8_921600 },
1739         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1740                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1741                 pbn_b2_4_921600 },
1742         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1743                 PCI_SUBVENDOR_ID_KEYSPAN,
1744                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1745                 pbn_panacom },
1746         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1747                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1748                 pbn_panacom4 },
1749         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1750                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1751                 pbn_panacom2 },
1752         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1753                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1754                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1755                 pbn_b2_4_460800 },
1756         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1757                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1758                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1759                 pbn_b2_8_460800 },
1760         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1761                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1762                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1763                 pbn_b2_16_460800 },
1764         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1765                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1766                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1767                 pbn_b2_16_460800 },
1768         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1769                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1770                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1771                 pbn_b2_4_460800 },
1772         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1773                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1774                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1775                 pbn_b2_8_460800 },
1776         /*
1777          * Megawolf Romulus PCI Serial Card, from Mike Hudson
1778          * (Exoray@isys.ca)
1779          */
1780         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1781                 0x10b5, 0x106a, 0, 0,
1782                 pbn_plx_romulus },
1783         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1784                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1785                 pbn_b1_4_115200 },
1786         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1787                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1788                 pbn_b1_2_115200 },
1789         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1790                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1791                 pbn_b1_8_115200 },
1792         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1793                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1794                 pbn_b1_8_115200 },
1795         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1796                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1797                 pbn_b0_4_921600 },
1798         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1799                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1800                 pbn_b0_4_115200 },
1801         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1802                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1803                 pbn_b0_2_115200 },
1804
1805         /*
1806          * Digitan DS560-558, from jimd@esoft.com
1807          */
1808         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
1809                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1810                 pbn_b1_1_115200 },
1811
1812         /*
1813          * Titan Electronic cards
1814          *  The 400L and 800L have a custom setup quirk.
1815          */
1816         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
1817                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1818                 pbn_b0_1_921600 },
1819         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
1820                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1821                 pbn_b0_2_921600 },
1822         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
1823                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1824                 pbn_b0_4_921600 },
1825         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
1826                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1827                 pbn_b0_4_921600 },
1828         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
1829                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1830                 pbn_b1_1_921600 },
1831         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
1832                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1833                 pbn_b1_bt_2_921600 },
1834         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
1835                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1836                 pbn_b0_bt_4_921600 },
1837         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
1838                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1839                 pbn_b0_bt_8_921600 },
1840
1841         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
1842                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1843                 pbn_b2_1_460800 },
1844         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
1845                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1846                 pbn_b2_1_460800 },
1847         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
1848                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1849                 pbn_b2_1_460800 },
1850         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
1851                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1852                 pbn_b2_bt_2_921600 },
1853         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
1854                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1855                 pbn_b2_bt_2_921600 },
1856         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
1857                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1858                 pbn_b2_bt_2_921600 },
1859         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
1860                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1861                 pbn_b2_bt_4_921600 },
1862         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
1863                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1864                 pbn_b2_bt_4_921600 },
1865         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
1866                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1867                 pbn_b2_bt_4_921600 },
1868         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
1869                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1870                 pbn_b0_1_921600 },
1871         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
1872                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1873                 pbn_b0_1_921600 },
1874         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
1875                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1876                 pbn_b0_1_921600 },
1877         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
1878                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1879                 pbn_b0_bt_2_921600 },
1880         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
1881                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1882                 pbn_b0_bt_2_921600 },
1883         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
1884                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1885                 pbn_b0_bt_2_921600 },
1886         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
1887                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1888                 pbn_b0_bt_4_921600 },
1889         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
1890                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1891                 pbn_b0_bt_4_921600 },
1892         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
1893                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1894                 pbn_b0_bt_4_921600 },
1895
1896         /*
1897          * Computone devices submitted by Doug McNash dmcnash@computone.com
1898          */
1899         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
1900                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
1901                 0, 0, pbn_computone_4 },
1902         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
1903                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
1904                 0, 0, pbn_computone_8 },
1905         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
1906                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
1907                 0, 0, pbn_computone_6 },
1908
1909         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
1910                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1911                 pbn_oxsemi },
1912         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
1913                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
1914                 pbn_b0_bt_1_921600 },
1915
1916         /*
1917          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
1918          */
1919         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
1920                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1921                 pbn_b0_bt_8_115200 },
1922
1923         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
1924                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1925                 pbn_b0_bt_2_115200 },
1926         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
1927                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1928                 pbn_b0_bt_2_115200 },
1929         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
1930                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1931                 pbn_b0_bt_2_115200 },
1932         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
1933                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1934                 pbn_b0_bt_4_460800 },
1935         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
1936                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1937                 pbn_b0_bt_4_460800 },
1938         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
1939                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1940                 pbn_b0_bt_2_460800 },
1941         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
1942                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1943                 pbn_b0_bt_2_460800 },
1944         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
1945                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1946                 pbn_b0_bt_2_460800 },
1947         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
1948                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1949                 pbn_b0_bt_1_115200 },
1950         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
1951                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1952                 pbn_b0_bt_1_460800 },
1953
1954         /*
1955          * RAStel 2 port modem, gerg@moreton.com.au
1956          */
1957         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
1958                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1959                 pbn_b2_bt_2_115200 },
1960
1961         /*
1962          * EKF addition for i960 Boards form EKF with serial port
1963          */
1964         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
1965                 0xE4BF, PCI_ANY_ID, 0, 0,
1966                 pbn_intel_i960 },
1967
1968         /*
1969          * Xircom Cardbus/Ethernet combos
1970          */
1971         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1972                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1973                 pbn_b0_1_115200 },
1974         /*
1975          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
1976          */
1977         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
1978                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1979                 pbn_b0_1_115200 },
1980
1981         /*
1982          * Untested PCI modems, sent in from various folks...
1983          */
1984
1985         /*
1986          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
1987          */
1988         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
1989                 0x1048, 0x1500, 0, 0,
1990                 pbn_b1_1_115200 },
1991
1992         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
1993                 0xFF00, 0, 0, 0,
1994                 pbn_sgi_ioc3 },
1995
1996         /*
1997          * HP Diva card
1998          */
1999         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2000                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2001                 pbn_b0_5_115200 },
2002         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2003                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2004                 pbn_b2_1_115200 },
2005
2006         /*
2007          * NEC Vrc-5074 (Nile 4) builtin UART.
2008          */
2009         {       PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2010                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2011                 pbn_nec_nile4 },
2012
2013         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2014                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2015                 pbn_b3_4_115200 },
2016         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2017                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2018                 pbn_b3_8_115200 },
2019
2020         /*
2021          * These entries match devices with class COMMUNICATION_SERIAL,
2022          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2023          */
2024         {       PCI_ANY_ID, PCI_ANY_ID,
2025                 PCI_ANY_ID, PCI_ANY_ID,
2026                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2027                 0xffff00, pbn_default },
2028         {       PCI_ANY_ID, PCI_ANY_ID,
2029                 PCI_ANY_ID, PCI_ANY_ID,
2030                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2031                 0xffff00, pbn_default },
2032         {       PCI_ANY_ID, PCI_ANY_ID,
2033                 PCI_ANY_ID, PCI_ANY_ID,
2034                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2035                 0xffff00, pbn_default },
2036         { 0, }
2037 };
2038
2039 static struct pci_driver serial_pci_driver = {
2040         .name           = "serial",
2041         .probe          = pciserial_init_one,
2042         .remove         = __devexit_p(pciserial_remove_one),
2043         .save_state     = pciserial_save_state_one,
2044         .suspend        = pciserial_suspend_one,
2045         .resume         = pciserial_resume_one,
2046         .id_table       = serial_pci_tbl,
2047 };
2048
2049 static int __init serial8250_pci_init(void)
2050 {
2051         return pci_module_init(&serial_pci_driver);
2052 }
2053
2054 static void __exit serial8250_pci_exit(void)
2055 {
2056         pci_unregister_driver(&serial_pci_driver);
2057 }
2058
2059 module_init(serial8250_pci_init);
2060 module_exit(serial8250_pci_exit);
2061
2062 MODULE_LICENSE("GPL");
2063 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2064 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);