drivers/media/dvb/b2c2/skystar2.c

   1 /*
   2  * skystar2.c - driver for the Technisat SkyStar2 PCI DVB card
   3  *              based on the FlexCopII by B2C2,Inc.
   4  *
   5  * Copyright (C) 2003  V.C. , skystar@moldova.cc
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public License
   9  * as published by the Free Software Foundation; either version 2.1
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  20  */
  21 #include <linux/module.h>
  22 #include <linux/delay.h>
  23 #include <linux/pci.h>
  24 #include <linux/init.h>
  25
  26 #include <asm/io.h>
  27
  28 #include "dvb_i2c.h"
  29 #include "dvb_frontend.h"
  30 #include "dvb_functions.h"
  31
  32 #include <linux/dvb/frontend.h>
  33 #include <linux/dvb/dmx.h>
  34 #include "dvb_demux.h"
  35 #include "dmxdev.h"
  36 #include "dvb_filter.h"
  37 #include "dvbdev.h"
  38 #include "demux.h"
  39 #include "dvb_net.h"
  40
  41 static int debug = 0;
  42 #define dprintk(x...) do { if (debug) printk(x); } while (0)
  43
  44 #define SizeOfBufDMA1   0x3AC00
  45 #define SizeOfBufDMA2   0x758
  46
  47 struct dmaq {
  48
  49         u32 bus_addr;
  50         u32 head;
  51         u32 tail;
  52         u32 buffer_size;
  53         u8 *buffer;
  54 };
  55
  56 struct packet_header {
  57
  58         u32 sync_byte;
  59         u32 transport_error_indicator;
  60         u32 payload_unit_start_indicator;
  61         u32 transport_priority;
  62         u32 pid;
  63         u32 transport_scrambling_control;
  64         u32 adaptation_field_control;
  65         u32 continuity_counter;
  66 };
  67
  68 struct adapter {
  69
  70         struct pci_dev *pdev;
  71
  72         u8 card_revision;
  73         u32 b2c2_revision;
  74         u32 PidFilterMax;
  75         u32 MacFilterMax;
  76         u32 irq;
  77         unsigned long io_mem;
  78         unsigned long io_port;
  79         u8 mac_addr[8];
  80         u32 dwSramType;
  81
  82         struct dvb_adapter *dvb_adapter;
  83         struct dvb_demux demux;
  84         struct dmxdev dmxdev;
  85         struct dmx_frontend hw_frontend;
  86         struct dmx_frontend mem_frontend;
  87         struct dvb_i2c_bus *i2c_bus;
  88         struct dvb_net dvbnet;
  89
  90         struct semaphore i2c_sem;
  91
  92         struct dmaq dmaq1;
  93         struct dmaq dmaq2;
  94
  95         u32 dma_ctrl;
  96         u32 dma_status;
  97
  98         u32 capturing;
  99
 100         spinlock_t lock;
 101
 102         u16 pids[0x27];
 103         u32 mac_filter;
 104 };
 105
 106 #define WriteRegDW(adapter,reg,value) writel(value, adapter->io_mem + reg)
 107 #define ReadRegDW(adapter,reg) readl(adapter->io_mem + reg)
 108
 109 static void WriteRegOp(struct adapter *adapter, u32 reg, u32 operation, u32 andvalue, u32 orvalue)
 110 {
 111         u32 tmp;
 112
 113         tmp = ReadRegDW(adapter, reg);
 114
 115         if (operation == 1)
 116                 tmp = tmp | orvalue;
 117         if (operation == 2)
 118                 tmp = tmp & andvalue;
 119         if (operation == 3)
 120                 tmp = (tmp & andvalue) | orvalue;
 121
 122         WriteRegDW(adapter, reg, tmp);
 123 }
 124
 125 /* i2c functions */
 126 static int i2cMainWriteForFlex2(struct adapter * adapter, u32 command, u8 * buf, u32 retries)
 127 {
 128         u32 i;
 129         u32 value;
 130
 131         WriteRegDW(adapter, 0x100, 0);
 132         WriteRegDW(adapter, 0x100, command);
 133
 134         for (i = 0; i < retries; i++) {
 135                 value = ReadRegDW(adapter, 0x100);
 136
 137                 if ((value & 0x40000000) == 0) {
 138                         if ((value & 0x81000000) == 0x80000000) {
 139                                 if (buf != 0)
 140                                         *buf = (value >> 0x10) & 0xff;
 141
 142                                 return 1;
 143                         }
 144
 145                 } else {
 146
 147                         WriteRegDW(adapter, 0x100, 0);
 148                         WriteRegDW(adapter, 0x100, command);
 149                 }
 150         }
 151
 152         return 0;
 153 }
 154
 155 /* device = 0x10000000 for tuner, 0x20000000 for eeprom */
 156 static void i2cMainSetup(u32 device, u32 chip_addr, u8 op, u8 addr, u32 value, u32 len, u32 *command)
 157 {
 158         *command = device | ((len - 1) << 26) | (value << 16) | (addr << 8) | chip_addr;
 159
 160         if (op != 0)
 161                 *command = *command | 0x03000000;
 162         else
 163                 *command = *command | 0x01000000;
 164 }
 165
 166 static int FlexI2cRead4(struct adapter * adapter, u32 device, u32 chip_addr, u16 addr, u8 * buf, u8 len)
 167 {
 168         u32 command;
 169         u32 value;
 170
 171         int result, i;
 172
 173         i2cMainSetup(device, chip_addr, 1, addr, 0, len, &command);
 174
 175         result = i2cMainWriteForFlex2(adapter, command, buf, 100000);
 176
 177         if ((result & 0xff) != 0) {
 178                 if (len > 1) {
 179                         value = ReadRegDW(adapter, 0x104);
 180
 181                         for (i = 1; i < len; i++) {
 182                                 buf[i] = value & 0xff;
 183                                 value = value >> 8;
 184                         }
 185                 }
 186         }
 187
 188         return result;
 189 }
 190
 191 static int FlexI2cWrite4(struct adapter * adapter, u32 device, u32 chip_addr, u32 addr, u8 * buf, u8 len)
 192 {
 193         u32 command;
 194         u32 value;
 195         int i;
 196
 197         if (len > 1) {
 198                 value = 0;
 199
 200                 for (i = len; i > 1; i--) {
 201                         value = value << 8;
 202                         value = value | buf[i - 1];
 203                 }
 204
 205                 WriteRegDW(adapter, 0x104, value);
 206         }
 207
 208         i2cMainSetup(device, chip_addr, 0, addr, buf[0], len, &command);
 209
 210         return i2cMainWriteForFlex2(adapter, command, 0, 100000);
 211 }
 212
 213 static void fixchipaddr(u32 device, u32 bus, u32 addr, u32 *ret)
 214 {
 215         if (device == 0x20000000)
 216                 *ret = bus | ((addr >> 8) & 3);
 217
 218         *ret = bus;
 219 }
 220
 221 static u32 FLEXI2C_read(struct adapter * adapter, u32 device, u32 bus, u32 addr, u8 * buf, u32 len)
 222 {
 223         u32 chipaddr;
 224         u32 bytes_to_transfer;
 225         u8 *start;
 226
 227 //  dprintk("%s:\n", __FUNCTION__);
 228
 229         start = buf;
 230
 231         while (len != 0) {
 232                 bytes_to_transfer = len;
 233
 234                 if (bytes_to_transfer > 4)
 235                         bytes_to_transfer = 4;
 236
 237                 fixchipaddr(device, bus, addr, &chipaddr);
 238
 239                 if (FlexI2cRead4(adapter, device, chipaddr, addr, buf, bytes_to_transfer) == 0)
 240                         return buf - start;
 241
 242                 buf = buf + bytes_to_transfer;
 243                 addr = addr + bytes_to_transfer;
 244                 len = len - bytes_to_transfer;
 245         };
 246
 247         return buf - start;
 248 }
 249
 250 static u32 FLEXI2C_write(struct adapter * adapter, u32 device, u32 bus, u32 addr, u8 * buf, u32 len)
 251 {
 252         u32 chipaddr;
 253         u32 bytes_to_transfer;
 254         u8 *start;
 255
 256 //  dprintk("%s:\n", __FUNCTION__);
 257
 258         start = buf;
 259
 260         while (len != 0) {
 261                 bytes_to_transfer = len;
 262
 263                 if (bytes_to_transfer > 4)
 264                         bytes_to_transfer = 4;
 265
 266                 fixchipaddr(device, bus, addr, &chipaddr);
 267
 268                 if (FlexI2cWrite4(adapter, device, chipaddr, addr, buf, bytes_to_transfer) == 0)
 269                         return buf - start;
 270
 271                 buf = buf + bytes_to_transfer;
 272                 addr = addr + bytes_to_transfer;
 273                 len = len - bytes_to_transfer;
 274         }
 275
 276         return buf - start;
 277 }
 278
 279 static int master_xfer(struct dvb_i2c_bus *i2c, const struct i2c_msg *msgs, int num)
 280 {
 281         struct adapter *tmp = i2c->data;
 282         int i, ret = 0;
 283
 284         if (down_interruptible(&tmp->i2c_sem))
 285                 return -ERESTARTSYS;
 286
 287         if (0) {
 288                 dprintk("%s:\n", __FUNCTION__);
 289
 290                 for (i = 0; i < num; i++) {
 291                         printk("message %d: flags=%x, addr=0x%04x, buf=%p, len=%d \n", i, msgs[i].flags, msgs[i].addr, msgs[i].buf, msgs[i].len);
 292                 }
 293         }
 294
 295         /* allow only the vp310 frontend to access the bus */
 296         if ((msgs[0].addr != 0x0E) && (msgs[0].addr != 0x61)) {
 297                 up(&tmp->i2c_sem);
 298
 299                 return -EREMOTEIO;
 300         }
 301
 302         if ((num == 1) && (msgs[0].buf != NULL)) {
 303                 if (msgs[0].flags == I2C_M_RD) {
 304                         ret = -EINVAL;
 305
 306                 } else {
 307
 308                         // single writes do have the reg addr in buf[0] and data in buf[1] to buf[n]
 309                         ret = FLEXI2C_write(tmp, 0x10000000, msgs[0].addr, msgs[0].buf[0], &msgs[0].buf[1], msgs[0].len - 1);
 310
 311                         if (ret != msgs[0].len - 1)
 312                                 ret = -EREMOTEIO;
 313                         else
 314                                 ret = num;
 315                 }
 316
 317         } else if ((num == 2) && (msgs[1].buf != NULL)) {
 318
 319                 // i2c reads consist of a reg addr _write_ followed by a data read, so msg[1].flags has to be examined
 320                 if (msgs[1].flags == I2C_M_RD) {
 321                         ret = FLEXI2C_read(tmp, 0x10000000, msgs[0].addr, msgs[0].buf[0], msgs[1].buf, msgs[1].len);
 322
 323                 } else {
 324
 325                         ret = FLEXI2C_write(tmp, 0x10000000, msgs[0].addr, msgs[0].buf[0], msgs[1].buf, msgs[1].len);
 326                 }
 327
 328                 if (ret != msgs[1].len)
 329                         ret = -EREMOTEIO;
 330                 else
 331                         ret = num;
 332         }
 333
 334         up(&tmp->i2c_sem);
 335
 336         /* master xfer functions always return the number of successfully
 337            transmitted messages, not the number of transmitted bytes.
 338            return -EREMOTEIO in case of failure. */
 339         return ret;
 340 }
 341
 342 /* SRAM (Skystar2 rev2.3 has one "ISSI IS61LV256" chip on board,
 343    but it seems that FlexCopII can work with more than one chip) */
 344 static void SRAMSetNetDest(struct adapter * adapter, u8 dest)
 345 {
 346         u32 tmp;
 347
 348         udelay(1000);
 349
 350         tmp = (ReadRegDW(adapter, 0x714) & 0xFFFFFFFC) | (dest & 3);
 351
 352         udelay(1000);
 353
 354         WriteRegDW(adapter, 0x714, tmp);
 355         WriteRegDW(adapter, 0x714, tmp);
 356
 357         udelay(1000);
 358
 359         /* return value is never used? */
 360 /*      return tmp; */
 361 }
 362
 363 static void SRAMSetCaiDest(struct adapter * adapter, u8 dest)
 364 {
 365         u32 tmp;
 366
 367         udelay(1000);
 368
 369         tmp = (ReadRegDW(adapter, 0x714) & 0xFFFFFFF3) | ((dest & 3) << 2);
 370
 371         udelay(1000);
 372         udelay(1000);
 373
 374         WriteRegDW(adapter, 0x714, tmp);
 375         WriteRegDW(adapter, 0x714, tmp);
 376
 377         udelay(1000);
 378
 379         /* return value is never used? */
 380 /*      return tmp; */
 381 }
 382
 383 static void SRAMSetCaoDest(struct adapter * adapter, u8 dest)
 384 {
 385         u32 tmp;
 386
 387         udelay(1000);
 388
 389         tmp = (ReadRegDW(adapter, 0x714) & 0xFFFFFFCF) | ((dest & 3) << 4);
 390
 391         udelay(1000);
 392         udelay(1000);
 393
 394         WriteRegDW(adapter, 0x714, tmp);
 395         WriteRegDW(adapter, 0x714, tmp);
 396
 397         udelay(1000);
 398
 399         /* return value is never used? */
 400 /*      return tmp; */
 401 }
 402
 403 static void SRAMSetMediaDest(struct adapter * adapter, u8 dest)
 404 {
 405         u32 tmp;
 406
 407         udelay(1000);
 408
 409         tmp = (ReadRegDW(adapter, 0x714) & 0xFFFFFF3F) | ((dest & 3) << 6);
 410
 411         udelay(1000);
 412         udelay(1000);
 413
 414         WriteRegDW(adapter, 0x714, tmp);
 415         WriteRegDW(adapter, 0x714, tmp);
 416
 417         udelay(1000);
 418
 419         /* return value is never used? */
 420 /*      return tmp; */
 421 }
 422
 423 /* SRAM memory is accessed through a buffer register in the FlexCop
 424    chip (0x700). This register has the following structure:
 425     bits 0-14  : address
 426     bit  15    : read/write flag
 427     bits 16-23 : 8-bit word to write
 428     bits 24-27 : = 4
 429     bits 28-29 : memory bank selector
 430     bit  31    : busy flag
 431 */
 432 static void FlexSramWrite(struct adapter *adapter, u32 bank, u32 addr, u8 * buf, u32 len)
 433 {
 434         u32 i, command, retries;
 435
 436         for (i = 0; i < len; i++) {
 437                 command = bank | addr | 0x04000000 | (*buf << 0x10);
 438
 439                 retries = 2;
 440
 441                 while (((ReadRegDW(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
 442                         mdelay(1);
 443                         retries--;
 444                 };
 445
 446                 if (retries == 0)
 447                         printk("%s: SRAM timeout\n", __FUNCTION__);
 448
 449                 WriteRegDW(adapter, 0x700, command);
 450
 451                 buf++;
 452                 addr++;
 453         }
 454 }
 455
 456 static void FlexSramRead(struct adapter *adapter, u32 bank, u32 addr, u8 * buf, u32 len)
 457 {
 458         u32 i, command, value, retries;
 459
 460         for (i = 0; i < len; i++) {
 461                 command = bank | addr | 0x04008000;
 462
 463                 retries = 10000;
 464
 465                 while (((ReadRegDW(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
 466                         mdelay(1);
 467                         retries--;
 468                 };
 469
 470                 if (retries == 0)
 471                         printk("%s: SRAM timeout\n", __FUNCTION__);
 472
 473                 WriteRegDW(adapter, 0x700, command);
 474
 475                 retries = 10000;
 476
 477                 while (((ReadRegDW(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
 478                         mdelay(1);
 479                         retries--;
 480                 };
 481
 482                 if (retries == 0)
 483                         printk("%s: SRAM timeout\n", __FUNCTION__);
 484
 485                 value = ReadRegDW(adapter, 0x700) >> 0x10;
 486
 487                 *buf = (value & 0xff);
 488
 489                 addr++;
 490                 buf++;
 491         }
 492 }
 493
 494 static void SRAM_writeChunk(struct adapter *adapter, u32 addr, u8 * buf, u16 len)
 495 {
 496         u32 bank;
 497
 498         bank = 0;
 499
 500         if (adapter->dwSramType == 0x20000) {
 501                 bank = (addr & 0x18000) << 0x0D;
 502         }
 503
 504         if (adapter->dwSramType == 0x00000) {
 505                 if ((addr >> 0x0F) == 0)
 506                         bank = 0x20000000;
 507                 else
 508                         bank = 0x10000000;
 509         }
 510
 511         FlexSramWrite(adapter, bank, addr & 0x7FFF, buf, len);
 512 }
 513
 514 static void SRAM_readChunk(struct adapter *adapter, u32 addr, u8 * buf, u16 len)
 515 {
 516         u32 bank;
 517
 518         bank = 0;
 519
 520         if (adapter->dwSramType == 0x20000) {
 521                 bank = (addr & 0x18000) << 0x0D;
 522         }
 523
 524         if (adapter->dwSramType == 0x00000) {
 525                 if ((addr >> 0x0F) == 0)
 526                         bank = 0x20000000;
 527                 else
 528                         bank = 0x10000000;
 529         }
 530
 531         FlexSramRead(adapter, bank, addr & 0x7FFF, buf, len);
 532 }
 533
 534 static void SRAM_read(struct adapter *adapter, u32 addr, u8 * buf, u32 len)
 535 {
 536         u32 length;
 537
 538         while (len != 0) {
 539                 length = len;
 540
 541                 // check if the address range belongs to the same
 542                 // 32K memory chip. If not, the data is read from
 543                 // one chip at a time.
 544                 if ((addr >> 0x0F) != ((addr + len - 1) >> 0x0F)) {
 545                         length = (((addr >> 0x0F) + 1) << 0x0F) - addr;
 546                 }
 547
 548                 SRAM_readChunk(adapter, addr, buf, length);
 549
 550                 addr = addr + length;
 551                 buf = buf + length;
 552                 len = len - length;
 553         }
 554 }
 555
 556 static void SRAM_write(struct adapter *adapter, u32 addr, u8 * buf, u32 len)
 557 {
 558         u32 length;
 559
 560         while (len != 0) {
 561                 length = len;
 562
 563                 // check if the address range belongs to the same
 564                 // 32K memory chip. If not, the data is written to
 565                 // one chip at a time.
 566                 if ((addr >> 0x0F) != ((addr + len - 1) >> 0x0F)) {
 567                         length = (((addr >> 0x0F) + 1) << 0x0F) - addr;
 568                 }
 569
 570                 SRAM_writeChunk(adapter, addr, buf, length);
 571
 572                 addr = addr + length;
 573                 buf = buf + length;
 574                 len = len - length;
 575         }
 576 }
 577
 578 static void SRAM_setSize(struct adapter *adapter, u32 mask)
 579 {
 580         WriteRegDW(adapter, 0x71C, (mask | (~0x30000 & ReadRegDW(adapter, 0x71C))));
 581 }
 582
 583 static void SRAM_init(struct adapter *adapter)
 584 {
 585         u32 tmp;
 586
 587         tmp = ReadRegDW(adapter, 0x71C);
 588
 589         WriteRegDW(adapter, 0x71C, 1);
 590
 591         if (ReadRegDW(adapter, 0x71C) != 0) {
 592                 WriteRegDW(adapter, 0x71C, tmp);
 593
 594                 adapter->dwSramType = tmp & 0x30000;
 595
 596                 dprintk("%s: dwSramType = %x\n", __FUNCTION__, adapter->dwSramType);
 597
 598         } else {
 599
 600                 adapter->dwSramType = 0x10000;
 601
 602                 dprintk("%s: dwSramType = %x\n", __FUNCTION__, adapter->dwSramType);
 603         }
 604
 605         /* return value is never used? */
 606 /*      return adapter->dwSramType; */
 607 }
 608
 609 static int SRAM_testLocation(struct adapter *adapter, u32 mask, u32 addr)
 610 {
 611         u8 tmp1, tmp2;
 612
 613         dprintk("%s: mask = %x, addr = %x\n", __FUNCTION__, mask, addr);
 614
 615         SRAM_setSize(adapter, mask);
 616         SRAM_init(adapter);
 617
 618         tmp2 = 0xA5;
 619         tmp1 = 0x4F;
 620
 621         SRAM_write(adapter, addr, &tmp2, 1);
 622         SRAM_write(adapter, addr + 4, &tmp1, 1);
 623
 624         tmp2 = 0;
 625
 626         mdelay(20);
 627
 628         SRAM_read(adapter, addr, &tmp2, 1);
 629         SRAM_read(adapter, addr, &tmp2, 1);
 630
 631         dprintk("%s: wrote 0xA5, read 0x%2x\n", __FUNCTION__, tmp2);
 632
 633         if (tmp2 != 0xA5)
 634                 return 0;
 635
 636         tmp2 = 0x5A;
 637         tmp1 = 0xF4;
 638
 639         SRAM_write(adapter, addr, &tmp2, 1);
 640         SRAM_write(adapter, addr + 4, &tmp1, 1);
 641
 642         tmp2 = 0;
 643
 644         mdelay(20);
 645
 646         SRAM_read(adapter, addr, &tmp2, 1);
 647         SRAM_read(adapter, addr, &tmp2, 1);
 648
 649         dprintk("%s: wrote 0x5A, read 0x%2x\n", __FUNCTION__, tmp2);
 650
 651         if (tmp2 != 0x5A)
 652                 return 0;
 653
 654         return 1;
 655 }
 656
 657 static u32 SRAM_length(struct adapter * adapter)
 658 {
 659         if (adapter->dwSramType == 0x10000)
 660                 return 32768;   //  32K
 661         if (adapter->dwSramType == 0x00000)
 662                 return 65536;   //  64K
 663         if (adapter->dwSramType == 0x20000)
 664                 return 131072;  // 128K
 665
 666         return 32768;           // 32K
 667 }
 668
 669 /* FlexcopII can work with 32K, 64K or 128K of external SRAM memory.
 670     - for 128K there are 4x32K chips at bank 0,1,2,3.
 671     - for  64K there are 2x32K chips at bank 1,2.
 672     - for  32K there is one 32K chip at bank 0.
 673
 674    FlexCop works only with one bank at a time. The bank is selected
 675    by bits 28-29 of the 0x700 register.
 676
 677    bank 0 covers addresses 0x00000-0x07FFF
 678    bank 1 covers addresses 0x08000-0x0FFFF
 679    bank 2 covers addresses 0x10000-0x17FFF
 680    bank 3 covers addresses 0x18000-0x1FFFF
 681 */
 682 static int SramDetectForFlex2(struct adapter *adapter)
 683 {
 684         u32 tmp, tmp2, tmp3;
 685
 686         dprintk("%s:\n", __FUNCTION__);
 687
 688         tmp = ReadRegDW(adapter, 0x208);
 689         WriteRegDW(adapter, 0x208, 0);
 690
 691         tmp2 = ReadRegDW(adapter, 0x71C);
 692
 693         dprintk("%s: tmp2 = %x\n", __FUNCTION__, tmp2);
 694
 695         WriteRegDW(adapter, 0x71C, 1);
 696
 697         tmp3 = ReadRegDW(adapter, 0x71C);
 698
 699         dprintk("%s: tmp3 = %x\n", __FUNCTION__, tmp3);
 700
 701         WriteRegDW(adapter, 0x71C, tmp2);
 702
 703         // check for internal SRAM ???
 704         tmp3--;
 705         if (tmp3 != 0) {
 706                 SRAM_setSize(adapter, 0x10000);
 707                 SRAM_init(adapter);
 708                 WriteRegDW(adapter, 0x208, tmp);
 709
 710                 dprintk("%s: sram size = 32K\n", __FUNCTION__);
 711
 712                 return 32;
 713         }
 714
 715         if (SRAM_testLocation(adapter, 0x20000, 0x18000) != 0) {
 716                 SRAM_setSize(adapter, 0x20000);
 717                 SRAM_init(adapter);
 718                 WriteRegDW(adapter, 0x208, tmp);
 719
 720                 dprintk("%s: sram size = 128K\n", __FUNCTION__);
 721
 722                 return 128;
 723         }
 724
 725         if (SRAM_testLocation(adapter, 0x00000, 0x10000) != 0) {
 726                 SRAM_setSize(adapter, 0x00000);
 727                 SRAM_init(adapter);
 728                 WriteRegDW(adapter, 0x208, tmp);
 729
 730                 dprintk("%s: sram size = 64K\n", __FUNCTION__);
 731
 732                 return 64;
 733         }
 734
 735         if (SRAM_testLocation(adapter, 0x10000, 0x00000) != 0) {
 736                 SRAM_setSize(adapter, 0x10000);
 737                 SRAM_init(adapter);
 738                 WriteRegDW(adapter, 0x208, tmp);
 739
 740                 dprintk("%s: sram size = 32K\n", __FUNCTION__);
 741
 742                 return 32;
 743         }
 744
 745         SRAM_setSize(adapter, 0x10000);
 746         SRAM_init(adapter);
 747         WriteRegDW(adapter, 0x208, tmp);
 748
 749         dprintk("%s: SRAM detection failed. Set to 32K \n", __FUNCTION__);
 750
 751         return 0;
 752 }
 753
 754 static void SLL_detectSramSize(struct adapter *adapter)
 755 {
 756         SramDetectForFlex2(adapter);
 757 }
 758 /* EEPROM (Skystar2 has one "24LC08B" chip on board) */
 759 /*
 760 static int EEPROM_write(struct adapter *adapter, u16 addr, u8 * buf, u16 len)
 761 {
 762         return FLEXI2C_write(adapter, 0x20000000, 0x50, addr, buf, len);
 763 }
 764 */
 765
 766 static int EEPROM_read(struct adapter *adapter, u16 addr, u8 * buf, u16 len)
 767 {
 768         return FLEXI2C_read(adapter, 0x20000000, 0x50, addr, buf, len);
 769 }
 770
 771 u8 calc_LRC(u8 * buf, u32 len)
 772 {
 773         u32 i;
 774         u8 sum;
 775
 776         sum = 0;
 777
 778         for (i = 0; i < len; i++)
 779                 sum = sum ^ buf[i];
 780
 781         return sum;
 782 }
 783
 784 static int EEPROM_LRC_read(struct adapter *adapter, u32 addr, u32 len, u8 * buf, u32 retries)
 785 {
 786         int i;
 787
 788         for (i = 0; i < retries; i++) {
 789                 if (EEPROM_read(adapter, addr, buf, len) == len) {
 790                         if (calc_LRC(buf, len - 1) == buf[len - 1])
 791                                 return 1;
 792                 }
 793         }
 794
 795         return 0;
 796 }
 797
 798 /*
 799 static int EEPROM_LRC_write(struct adapter *adapter, u32 addr, u32 len, u8 * wbuf, u8 * rbuf, u32 retries)
 800 {
 801         int i;
 802
 803         for (i = 0; i < retries; i++) {
 804                 if (EEPROM_write(adapter, addr, wbuf, len) == len) {
 805                         if (EEPROM_LRC_read(adapter, addr, len, rbuf, retries) == 1)
 806                                 return 1;
 807                 }
 808         }
 809
 810         return 0;
 811 }
 812 */
 813
 814 /* These functions could be called from the initialization routine
 815    to unlock SkyStar2 cards, locked by "Europe On Line".
 816
 817    in cards from "Europe On Line" the key is:
 818
 819        u8 key[20] = {
 820             0xB2, 0x01, 0x00, 0x00,
 821             0x00, 0x00, 0x00, 0x00,
 822             0x00, 0x00, 0x00, 0x00,
 823             0x00, 0x00, 0x00, 0x00,
 824        };
 825
 826        LRC = 0xB3;
 827
 828   in unlocked cards the key is:
 829
 830        u8 key[20] = {
 831             0xB2, 0x00, 0x00, 0x00,
 832             0x00, 0x00, 0x00, 0x00,
 833             0x00, 0x00, 0x00, 0x00,
 834             0x00, 0x00, 0x00, 0x00,
 835        };
 836
 837       LRC = 0xB2;
 838 */
 839 /*
 840 static int EEPROM_writeKey(struct adapter *adapter, u8 * key, u32 len)
 841 {
 842         u8 rbuf[20];
 843         u8 wbuf[20];
 844
 845         if (len != 16)
 846                 return 0;
 847
 848         memcpy(wbuf, key, len);
 849
 850         wbuf[16] = 0;
 851         wbuf[17] = 0;
 852         wbuf[18] = 0;
 853         wbuf[19] = calc_LRC(wbuf, 19);
 854
 855         return EEPROM_LRC_write(adapter, 0x3E4, 20, wbuf, rbuf, 4);
 856 }
 857 */
 858 static int EEPROM_readKey(struct adapter *adapter, u8 * key, u32 len)
 859 {
 860         u8 buf[20];
 861
 862         if (len != 16)
 863                 return 0;
 864
 865         if (EEPROM_LRC_read(adapter, 0x3E4, 20, buf, 4) == 0)
 866                 return 0;
 867
 868         memcpy(key, buf, len);
 869
 870         return 1;
 871 }
 872
 873 static int EEPROM_getMacAddr(struct adapter *adapter, char type, u8 * mac)
 874 {
 875         u8 tmp[8];
 876
 877         if (EEPROM_LRC_read(adapter, 0x3F8, 8, tmp, 4) != 0) {
 878                 if (type != 0) {
 879                         mac[0] = tmp[0];
 880                         mac[1] = tmp[1];
 881                         mac[2] = tmp[2];
 882                         mac[3] = 0xFE;
 883                         mac[4] = 0xFF;
 884                         mac[5] = tmp[3];
 885                         mac[6] = tmp[4];
 886                         mac[7] = tmp[5];
 887
 888                 } else {
 889
 890                         mac[0] = tmp[0];
 891                         mac[1] = tmp[1];
 892                         mac[2] = tmp[2];
 893                         mac[3] = tmp[3];
 894                         mac[4] = tmp[4];
 895                         mac[5] = tmp[5];
 896                 }
 897
 898                 return 1;
 899
 900         } else {
 901
 902                 if (type == 0) {
 903                         memset(mac, 0, 6);
 904
 905                 } else {
 906
 907                         memset(mac, 0, 8);
 908                 }
 909
 910                 return 0;
 911         }
 912 }
 913
 914 /*
 915 static char EEPROM_setMacAddr(struct adapter *adapter, char type, u8 * mac)
 916 {
 917         u8 tmp[8];
 918
 919         if (type != 0) {
 920                 tmp[0] = mac[0];
 921                 tmp[1] = mac[1];
 922                 tmp[2] = mac[2];
 923                 tmp[3] = mac[5];
 924                 tmp[4] = mac[6];
 925                 tmp[5] = mac[7];
 926
 927         } else {
 928
 929                 tmp[0] = mac[0];
 930                 tmp[1] = mac[1];
 931                 tmp[2] = mac[2];
 932                 tmp[3] = mac[3];
 933                 tmp[4] = mac[4];
 934                 tmp[5] = mac[5];
 935         }
 936
 937         tmp[6] = 0;
 938         tmp[7] = calc_LRC(tmp, 7);
 939
 940         if (EEPROM_write(adapter, 0x3F8, tmp, 8) == 8)
 941                 return 1;
 942
 943         return 0;
 944 }
 945 */
 946
 947 /* PID filter */
 948 static void FilterEnableStream1Filter(struct adapter *adapter, u32 op)
 949 {
 950         dprintk("%s: op=%x\n", __FUNCTION__, op);
 951
 952         if (op == 0) {
 953                 WriteRegOp(adapter, 0x208, 2, ~0x00000001, 0);
 954
 955         } else {
 956
 957                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000001);
 958         }
 959 }
 960
 961 static void FilterEnableStream2Filter(struct adapter *adapter, u32 op)
 962 {
 963         dprintk("%s: op=%x\n", __FUNCTION__, op);
 964
 965         if (op == 0) {
 966                 WriteRegOp(adapter, 0x208, 2, ~0x00000002, 0);
 967
 968         } else {
 969
 970                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000002);
 971         }
 972 }
 973
 974 static void FilterEnablePcrFilter(struct adapter *adapter, u32 op)
 975 {
 976         dprintk("%s: op=%x\n", __FUNCTION__, op);
 977
 978         if (op == 0) {
 979                 WriteRegOp(adapter, 0x208, 2, ~0x00000004, 0);
 980
 981         } else {
 982
 983                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000004);
 984         }
 985 }
 986
 987 static void FilterEnablePmtFilter(struct adapter *adapter, u32 op)
 988 {
 989         dprintk("%s: op=%x\n", __FUNCTION__, op);
 990
 991         if (op == 0) {
 992                 WriteRegOp(adapter, 0x208, 2, ~0x00000008, 0);
 993
 994         } else {
 995
 996                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000008);
 997         }
 998 }
 999
1000 static void FilterEnableEmmFilter(struct adapter *adapter, u32 op)
1001 {
1002         dprintk("%s: op=%x\n", __FUNCTION__, op);
1003
1004         if (op == 0) {
1005                 WriteRegOp(adapter, 0x208, 2, ~0x00000010, 0);
1006
1007         } else {
1008
1009                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000010);
1010         }
1011 }
1012
1013 static void FilterEnableEcmFilter(struct adapter *adapter, u32 op)
1014 {
1015         dprintk("%s: op=%x\n", __FUNCTION__, op);
1016
1017         if (op == 0) {
1018                 WriteRegOp(adapter, 0x208, 2, ~0x00000020, 0);
1019
1020         } else {
1021
1022                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000020);
1023         }
1024 }
1025
1026 /*
1027 static void FilterEnableNullFilter(struct adapter *adapter, u32 op)
1028 {
1029         dprintk("%s: op=%x\n", __FUNCTION__, op);
1030
1031         if (op == 0) {
1032                 WriteRegOp(adapter, 0x208, 2, ~0x00000040, 0);
1033
1034         } else {
1035
1036                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000040);
1037         }
1038 }
1039 */
1040
1041 static void FilterEnableMaskFilter(struct adapter *adapter, u32 op)
1042 {
1043         dprintk("%s: op=%x\n", __FUNCTION__, op);
1044
1045         if (op == 0) {
1046                 WriteRegOp(adapter, 0x208, 2, ~0x00000080, 0);
1047
1048         } else {
1049
1050                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000080);
1051         }
1052 }
1053
1054
1055 static void CtrlEnableMAC(struct adapter *adapter, u32 op)
1056 {
1057         if (op == 0) {
1058                 WriteRegOp(adapter, 0x208, 2, ~0x00004000, 0);
1059
1060         } else {
1061
1062                 WriteRegOp(adapter, 0x208, 1, 0, 0x00004000);
1063         }
1064 }
1065
1066 static int CASetMacDstAddrFilter(struct adapter *adapter, u8 * mac)
1067 {
1068         u32 tmp1, tmp2;
1069
1070         tmp1 = (mac[3] << 0x18) | (mac[2] << 0x10) | (mac[1] << 0x08) | mac[0];
1071         tmp2 = (mac[5] << 0x08) | mac[4];
1072
1073         WriteRegDW(adapter, 0x418, tmp1);
1074         WriteRegDW(adapter, 0x41C, tmp2);
1075
1076         return 0;
1077 }
1078
1079 /*
1080 static void SetIgnoreMACFilter(struct adapter *adapter, u8 op)
1081 {
1082         if (op != 0) {
1083                 WriteRegOp(adapter, 0x208, 2, ~0x00004000, 0);
1084
1085                 adapter->mac_filter = 1;
1086
1087         } else {
1088
1089                 if (adapter->mac_filter != 0) {
1090                         adapter->mac_filter = 0;
1091
1092                         WriteRegOp(adapter, 0x208, 1, 0, 0x00004000);
1093                 }
1094         }
1095 }
1096 */
1097
1098 /*
1099 static void CheckNullFilterEnable(struct adapter *adapter)
1100 {
1101         FilterEnableNullFilter(adapter, 1);
1102         FilterEnableMaskFilter(adapter, 1);
1103 }
1104 */
1105
1106 static void InitPIDsInfo(struct adapter *adapter)
1107 {
1108         int i;
1109
1110         for (i = 0; i < 0x27; i++)
1111                 adapter->pids[i] = 0x1FFF;
1112 }
1113
1114 static int CheckPID(struct adapter *adapter, u16 pid)
1115 {
1116         u32 i;
1117
1118         if (pid == 0x1FFF)
1119                 return 0;
1120
1121         for (i = 0; i < 0x27; i++) {
1122                 if (adapter->pids[i] == pid)
1123                         return 1;
1124         }
1125
1126         return 0;
1127 }
1128
1129 static void PidSetGroupPID(struct adapter * adapter, u32 pid)
1130 {
1131         u32 value;
1132
1133         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1134
1135         value = (pid & 0x3FFF) | (ReadRegDW(adapter, 0x30C) & 0xFFFF0000);
1136
1137         WriteRegDW(adapter, 0x30C, value);
1138
1139         /* return value is never used? */
1140 /*      return value; */
1141 }
1142
1143 static void PidSetGroupMASK(struct adapter * adapter, u32 pid)
1144 {
1145         u32 value;
1146
1147         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1148
1149         value = ((pid & 0x3FFF) << 0x10) | (ReadRegDW(adapter, 0x30C) & 0xFFFF);
1150
1151         WriteRegDW(adapter, 0x30C, value);
1152
1153         /* return value is never used? */
1154 /*      return value; */
1155 }
1156
1157 static void PidSetStream1PID(struct adapter * adapter, u32 pid)
1158 {
1159         u32 value;
1160
1161         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1162
1163         value = (pid & 0x3FFF) | (ReadRegDW(adapter, 0x300) & 0xFFFFC000);
1164
1165         WriteRegDW(adapter, 0x300, value);
1166
1167         /* return value is never used? */
1168 /*      return value; */
1169 }
1170
1171 static void PidSetStream2PID(struct adapter * adapter, u32 pid)
1172 {
1173         u32 value;
1174
1175         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1176
1177         value = ((pid & 0x3FFF) << 0x10) | (ReadRegDW(adapter, 0x300) & 0xFFFF);
1178
1179         WriteRegDW(adapter, 0x300, value);
1180
1181         /* return value is never used? */
1182 /*      return value; */
1183 }
1184
1185 static void PidSetPcrPID(struct adapter * adapter, u32 pid)
1186 {
1187         u32 value;
1188
1189         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1190
1191         value = (pid & 0x3FFF) | (ReadRegDW(adapter, 0x304) & 0xFFFFC000);
1192
1193         WriteRegDW(adapter, 0x304, value);
1194
1195         /* return value is never used? */
1196 /*      return value; */
1197 }
1198
1199 static void PidSetPmtPID(struct adapter * adapter, u32 pid)
1200 {
1201         u32 value;
1202
1203         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1204
1205         value = ((pid & 0x3FFF) << 0x10) | (ReadRegDW(adapter, 0x304) & 0x3FFF);
1206
1207         WriteRegDW(adapter, 0x304, value);
1208
1209         /* return value is never used? */
1210 /*      return value; */
1211 }
1212
1213 static void PidSetEmmPID(struct adapter * adapter, u32 pid)
1214 {
1215         u32 value;
1216
1217         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1218
1219         value = (pid & 0xFFFF) | (ReadRegDW(adapter, 0x308) & 0xFFFF0000);
1220
1221         WriteRegDW(adapter, 0x308, value);
1222
1223         /* return value is never used? */
1224 /*      return value; */
1225 }
1226
1227 static void PidSetEcmPID(struct adapter * adapter, u32 pid)
1228 {
1229         u32 value;
1230
1231         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1232
1233         value = (pid << 0x10) | (ReadRegDW(adapter, 0x308) & 0xFFFF);
1234
1235         WriteRegDW(adapter, 0x308, value);
1236
1237         /* return value is never used? */
1238 /*      return value; */
1239 }
1240
1241 static int PidGetStream1PID(struct adapter * adapter)
1242 {
1243         return ReadRegDW(adapter, 0x300) & 0x00001FFF;
1244 }
1245
1246 static int PidGetStream2PID(struct adapter * adapter)
1247 {
1248         return (ReadRegDW(adapter, 0x300) >> 0x10)& 0x00001FFF;
1249 }
1250
1251 static int PidGetPcrPID(struct adapter * adapter)
1252 {
1253         return ReadRegDW(adapter, 0x304) & 0x00001FFF;
1254 }
1255
1256 static int PidGetPmtPID(struct adapter * adapter)
1257 {
1258         return (ReadRegDW(adapter, 0x304) >> 0x10)& 0x00001FFF;
1259 }
1260
1261 static int PidGetEmmPID(struct adapter * adapter)
1262 {
1263         return ReadRegDW(adapter, 0x308) & 0x00001FFF;
1264 }
1265
1266 static int PidGetEcmPID(struct adapter * adapter)
1267 {
1268         return (ReadRegDW(adapter, 0x308) >> 0x10)& 0x00001FFF;
1269 }
1270
1271 static int PidGetGroupPID(struct adapter * adapter)
1272 {
1273         return ReadRegDW(adapter, 0x30C) & 0x00001FFF;
1274 }
1275
1276 static int PidGetGroupMASK(struct adapter * adapter)
1277 {
1278         return (ReadRegDW(adapter, 0x30C) >> 0x10)& 0x00001FFF;
1279 }
1280
1281 /*
1282 static void ResetHardwarePIDFilter(struct adapter *adapter)
1283 {
1284         PidSetStream1PID(adapter, 0x1FFF);
1285
1286         PidSetStream2PID(adapter, 0x1FFF);
1287         FilterEnableStream2Filter(adapter, 0);
1288
1289         PidSetPcrPID(adapter, 0x1FFF);
1290         FilterEnablePcrFilter(adapter, 0);
1291
1292         PidSetPmtPID(adapter, 0x1FFF);
1293         FilterEnablePmtFilter(adapter, 0);
1294
1295         PidSetEcmPID(adapter, 0x1FFF);
1296         FilterEnableEcmFilter(adapter, 0);
1297
1298         PidSetEmmPID(adapter, 0x1FFF);
1299         FilterEnableEmmFilter(adapter, 0);
1300 }
1301 */
1302
1303 static void OpenWholeBandwidth(struct adapter *adapter)
1304 {
1305         PidSetGroupPID(adapter, 0);
1306
1307         PidSetGroupMASK(adapter, 0);
1308
1309         FilterEnableMaskFilter(adapter, 1);
1310 }
1311
1312 static int AddHwPID(struct adapter *adapter, u32 pid)
1313 {
1314         dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1315
1316         if (pid <= 0x1F)
1317                 return 1;
1318
1319         if ((PidGetGroupMASK(adapter) == 0) && (PidGetGroupPID(adapter) == 0))
1320                 return 0;
1321
1322         if (PidGetStream1PID(adapter) == 0x1FFF) {
1323                 PidSetStream1PID(adapter, pid & 0xFFFF);
1324
1325                 FilterEnableStream1Filter(adapter, 1);
1326
1327                 return 1;
1328         }
1329
1330         if (PidGetStream2PID(adapter) == 0x1FFF) {
1331                 PidSetStream2PID(adapter, (pid & 0xFFFF));
1332
1333                 FilterEnableStream2Filter(adapter, 1);
1334
1335                 return 1;
1336         }
1337
1338         if (PidGetPcrPID(adapter) == 0x1FFF) {
1339                 PidSetPcrPID(adapter, (pid & 0xFFFF));
1340
1341                 FilterEnablePcrFilter(adapter, 1);
1342
1343                 return 1;
1344         }
1345
1346         if ((PidGetPmtPID(adapter) & 0x1FFF) == 0x1FFF) {
1347                 PidSetPmtPID(adapter, (pid & 0xFFFF));
1348
1349                 FilterEnablePmtFilter(adapter, 1);
1350
1351                 return 1;
1352         }
1353
1354         if ((PidGetEmmPID(adapter) & 0x1FFF) == 0x1FFF) {
1355                 PidSetEmmPID(adapter, (pid & 0xFFFF));
1356
1357                 FilterEnableEmmFilter(adapter, 1);
1358
1359                 return 1;
1360         }
1361
1362         if ((PidGetEcmPID(adapter) & 0x1FFF) == 0x1FFF) {
1363                 PidSetEcmPID(adapter, (pid & 0xFFFF));
1364
1365                 FilterEnableEcmFilter(adapter, 1);
1366
1367                 return 1;
1368         }
1369
1370         return -1;
1371 }
1372
1373 static int RemoveHwPID(struct adapter *adapter, u32 pid)
1374 {
1375         dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1376
1377         if (pid <= 0x1F)
1378                 return 1;
1379
1380         if (PidGetStream1PID(adapter) == pid) {
1381                 PidSetStream1PID(adapter, 0x1FFF);
1382
1383                 return 1;
1384         }
1385
1386         if (PidGetStream2PID(adapter) == pid) {
1387                 PidSetStream2PID(adapter, 0x1FFF);
1388
1389                 FilterEnableStream2Filter(adapter, 0);
1390
1391                 return 1;
1392         }
1393
1394         if (PidGetPcrPID(adapter) == pid) {
1395                 PidSetPcrPID(adapter, 0x1FFF);
1396
1397                 FilterEnablePcrFilter(adapter, 0);
1398
1399                 return 1;
1400         }
1401
1402         if (PidGetPmtPID(adapter) == pid) {
1403                 PidSetPmtPID(adapter, 0x1FFF);
1404
1405                 FilterEnablePmtFilter(adapter, 0);
1406
1407                 return 1;
1408         }
1409
1410         if (PidGetEmmPID(adapter) == pid) {
1411                 PidSetEmmPID(adapter, 0x1FFF);
1412
1413                 FilterEnableEmmFilter(adapter, 0);
1414
1415                 return 1;
1416         }
1417
1418         if (PidGetEcmPID(adapter) == pid) {
1419                 PidSetEcmPID(adapter, 0x1FFF);
1420
1421                 FilterEnableEcmFilter(adapter, 0);
1422
1423                 return 1;
1424         }
1425
1426         return -1;
1427 }
1428
1429 static int AddPID(struct adapter *adapter, u32 pid)
1430 {
1431         int i;
1432
1433         dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1434
1435         if (pid > 0x1FFE)
1436                 return -1;
1437
1438         if (CheckPID(adapter, pid) == 1)
1439                 return 1;
1440
1441         for (i = 0; i < 0x27; i++) {
1442                 if (adapter->pids[i] == 0x1FFF) // find free pid filter
1443                 {
1444                         adapter->pids[i] = pid;
1445
1446                         if (AddHwPID(adapter, pid) < 0)
1447                                 OpenWholeBandwidth(adapter);
1448
1449                         return 1;
1450                 }
1451         }
1452
1453         return -1;
1454 }
1455
1456 static int RemovePID(struct adapter *adapter, u32 pid)
1457 {
1458         u32 i;
1459
1460         dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1461
1462         if (pid > 0x1FFE)
1463                 return -1;
1464
1465         for (i = 0; i < 0x27; i++) {
1466                 if (adapter->pids[i] == pid) {
1467                         adapter->pids[i] = 0x1FFF;
1468
1469                         RemoveHwPID(adapter, pid);
1470
1471                         return 1;
1472                 }
1473         }
1474
1475         return -1;
1476 }
1477
1478 /* dma & irq */
1479 static void CtrlEnableSmc(struct adapter *adapter, u32 op)
1480 {
1481         if (op == 0) {
1482                 WriteRegOp(adapter, 0x208, 2, ~0x00000800, 0);
1483
1484         } else {
1485
1486                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000800);
1487         }
1488 }
1489
1490 static void DmaEnableDisableIrq(struct adapter *adapter, u32 flag1, u32 flag2, u32 flag3)
1491 {
1492         adapter->dma_ctrl = adapter->dma_ctrl & 0x000F0000;
1493
1494         if (flag1 == 0) {
1495                 if (flag2 == 0)
1496                         adapter->dma_ctrl = adapter->dma_ctrl & ~0x00010000;
1497                 else
1498                         adapter->dma_ctrl = adapter->dma_ctrl | 0x00010000;
1499
1500                 if (flag3 == 0)
1501                         adapter->dma_ctrl = adapter->dma_ctrl & ~0x00020000;
1502                 else
1503                         adapter->dma_ctrl = adapter->dma_ctrl | 0x00020000;
1504
1505         } else {
1506
1507                 if (flag2 == 0)
1508                         adapter->dma_ctrl = adapter->dma_ctrl & ~0x00040000;
1509                 else
1510                         adapter->dma_ctrl = adapter->dma_ctrl | 0x00040000;
1511
1512                 if (flag3 == 0)
1513                         adapter->dma_ctrl = adapter->dma_ctrl & ~0x00080000;
1514                 else
1515                         adapter->dma_ctrl = adapter->dma_ctrl | 0x00080000;
1516         }
1517 }
1518
1519 static void IrqDmaEnableDisableIrq(struct adapter * adapter, u32 op)
1520 {
1521         u32 value;
1522
1523         value = ReadRegDW(adapter, 0x208) & 0xFFF0FFFF;
1524
1525         if (op != 0)
1526                 value = value | (adapter->dma_ctrl & 0x000F0000);
1527
1528         WriteRegDW(adapter, 0x208, value);
1529 }
1530
1531 /* FlexCopII has 2 dma channels. DMA1 is used to transfer TS data to
1532    system memory.
1533
1534    The DMA1 buffer is divided in 2 subbuffers of equal size.
1535    FlexCopII will transfer TS data to one subbuffer, signal an interrupt
1536    when the subbuffer is full and continue fillig the second subbuffer.
1537
1538    For DMA1:
1539        subbuffer size in 32-bit words is stored in the first 24 bits of
1540        register 0x004. The last 8 bits of register 0x004 contain the number
1541        of subbuffers.
1542
1543        the first 30 bits of register 0x000 contain the address of the first
1544        subbuffer. The last 2 bits contain 0, when dma1 is disabled and 1,
1545        when dma1 is enabled.
1546
1547        the first 30 bits of register 0x00C contain the address of the second
1548        subbuffer. the last 2 bits contain 1.
1549
1550        register 0x008 will contain the address of the subbuffer that was filled
1551        with TS data, when FlexCopII will generate an interrupt.
1552
1553    For DMA2:
1554        subbuffer size in 32-bit words is stored in the first 24 bits of
1555        register 0x014. The last 8 bits of register 0x014 contain the number
1556        of subbuffers.
1557
1558        the first 30 bits of register 0x010 contain the address of the first
1559        subbuffer.  The last 2 bits contain 0, when dma1 is disabled and 1,
1560        when dma1 is enabled.
1561
1562        the first 30 bits of register 0x01C contain the address of the second
1563        subbuffer. the last 2 bits contain 1.
1564
1565        register 0x018 contains the address of the subbuffer that was filled
1566        with TS data, when FlexCopII generates an interrupt.
1567 */
1568 static int DmaInitDMA(struct adapter *adapter, u32 dma_channel)
1569 {
1570         u32 subbuffers, subbufsize, subbuf0, subbuf1;
1571
1572         if (dma_channel == 0) {
1573                 dprintk("%s: Initializing DMA1 channel\n", __FUNCTION__);
1574
1575                 subbuffers = 2;
1576
1577                 subbufsize = (((adapter->dmaq1.buffer_size / 2) / 4) << 8) | subbuffers;
1578
1579                 subbuf0 = adapter->dmaq1.bus_addr & 0xFFFFFFFC;
1580
1581                 subbuf1 = ((adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) & 0xFFFFFFFC) | 1;
1582
1583                 dprintk("%s: first subbuffer address = 0x%x\n", __FUNCTION__, subbuf0);
1584                 udelay(1000);
1585                 WriteRegDW(adapter, 0x000, subbuf0);
1586
1587                 dprintk("%s: subbuffer size = 0x%x\n", __FUNCTION__, (subbufsize >> 8) * 4);
1588                 udelay(1000);
1589                 WriteRegDW(adapter, 0x004, subbufsize);
1590
1591                 dprintk("%s: second subbuffer address = 0x%x\n", __FUNCTION__, subbuf1);
1592                 udelay(1000);
1593                 WriteRegDW(adapter, 0x00C, subbuf1);
1594
1595                 dprintk("%s: counter = 0x%x\n", __FUNCTION__, adapter->dmaq1.bus_addr & 0xFFFFFFFC);
1596                 WriteRegDW(adapter, 0x008, adapter->dmaq1.bus_addr & 0xFFFFFFFC);
1597                 udelay(1000);
1598
1599                 if (subbuffers == 0)
1600                         DmaEnableDisableIrq(adapter, 0, 1, 0);
1601                 else
1602                         DmaEnableDisableIrq(adapter, 0, 1, 1);
1603
1604                 IrqDmaEnableDisableIrq(adapter, 1);
1605
1606                 SRAMSetMediaDest(adapter, 1);
1607                 SRAMSetNetDest(adapter, 1);
1608                 SRAMSetCaiDest(adapter, 2);
1609                 SRAMSetCaoDest(adapter, 2);
1610         }
1611
1612         if (dma_channel == 1) {
1613                 dprintk("%s: Initializing DMA2 channel\n", __FUNCTION__);
1614
1615                 subbuffers = 2;
1616
1617                 subbufsize = (((adapter->dmaq2.buffer_size / 2) / 4) << 8) | subbuffers;
1618
1619                 subbuf0 = adapter->dmaq2.bus_addr & 0xFFFFFFFC;
1620
1621                 subbuf1 = ((adapter->dmaq2.bus_addr + adapter->dmaq2.buffer_size / 2) & 0xFFFFFFFC) | 1;
1622
1623                 dprintk("%s: first subbuffer address = 0x%x\n", __FUNCTION__, subbuf0);
1624                 udelay(1000);
1625                 WriteRegDW(adapter, 0x010, subbuf0);
1626
1627                 dprintk("%s: subbuffer size = 0x%x\n", __FUNCTION__, (subbufsize >> 8) * 4);
1628                 udelay(1000);
1629                 WriteRegDW(adapter, 0x014, subbufsize);
1630
1631                 dprintk("%s: second buffer address = 0x%x\n", __FUNCTION__, subbuf1);
1632                 udelay(1000);
1633                 WriteRegDW(adapter, 0x01C, subbuf1);
1634
1635                 SRAMSetCaiDest(adapter, 2);
1636         }
1637
1638         return 0;
1639 }
1640
1641 static void CtrlEnableReceiveData(struct adapter *adapter, u32 op)
1642 {
1643         if (op == 0) {
1644                 WriteRegOp(adapter, 0x208, 2, ~0x00008000, 0);
1645
1646                 adapter->dma_status = adapter->dma_status & ~0x00000004;
1647
1648         } else {
1649
1650                 WriteRegOp(adapter, 0x208, 1, 0, 0x00008000);
1651
1652                 adapter->dma_status = adapter->dma_status | 0x00000004;
1653         }
1654 }
1655
1656 /* bit 0 of dma_mask is set to 1 if dma1 channel has to be enabled/disabled
1657    bit 1 of dma_mask is set to 1 if dma2 channel has to be enabled/disabled
1658 */
1659 static void DmaStartStop0x2102(struct adapter *adapter, u32 dma_mask, u32 start_stop)
1660 {
1661         u32 dma_enable, dma1_enable, dma2_enable;
1662
1663         dprintk("%s: dma_mask=%x\n", __FUNCTION__, dma_mask);
1664
1665         if (start_stop == 1) {
1666                 dprintk("%s: starting dma\n", __FUNCTION__);
1667
1668                 dma1_enable = 0;
1669                 dma2_enable = 0;
1670
1671                 if (((dma_mask & 1) != 0) && ((adapter->dma_status & 1) == 0) && (adapter->dmaq1.bus_addr != 0)) {
1672                         adapter->dma_status = adapter->dma_status | 1;
1673                         dma1_enable = 1;
1674                 }
1675
1676                 if (((dma_mask & 2) != 0) && ((adapter->dma_status & 2) == 0) && (adapter->dmaq2.bus_addr != 0)) {
1677                         adapter->dma_status = adapter->dma_status | 2;
1678                         dma2_enable = 1;
1679                 }
1680                 // enable dma1 and dma2
1681                 if ((dma1_enable == 1) && (dma2_enable == 1)) {
1682                         WriteRegDW(adapter, 0x000, adapter->dmaq1.bus_addr | 1);
1683                         WriteRegDW(adapter, 0x00C, (adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) | 1);
1684                         WriteRegDW(adapter, 0x010, adapter->dmaq2.bus_addr | 1);
1685
1686                         CtrlEnableReceiveData(adapter, 1);
1687
1688                         return;
1689                 }
1690                 // enable dma1
1691                 if ((dma1_enable == 1) && (dma2_enable == 0)) {
1692                         WriteRegDW(adapter, 0x000, adapter->dmaq1.bus_addr | 1);
1693                         WriteRegDW(adapter, 0x00C, (adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) | 1);
1694
1695                         CtrlEnableReceiveData(adapter, 1);
1696
1697                         return;
1698                 }
1699                 // enable dma2
1700                 if ((dma1_enable == 0) && (dma2_enable == 1)) {
1701                         WriteRegDW(adapter, 0x010, adapter->dmaq2.bus_addr | 1);
1702
1703                         CtrlEnableReceiveData(adapter, 1);
1704
1705                         return;
1706                 }
1707                 // start dma
1708                 if ((dma1_enable == 0) && (dma2_enable == 0)) {
1709                         CtrlEnableReceiveData(adapter, 1);
1710
1711                         return;
1712                 }
1713
1714         } else {
1715
1716                 dprintk("%s: stoping dma\n", __FUNCTION__);
1717
1718                 dma_enable = adapter->dma_status & 0x00000003;
1719
1720                 if (((dma_mask & 1) != 0) && ((adapter->dma_status & 1) != 0)) {
1721                         dma_enable = dma_enable & 0xFFFFFFFE;
1722                 }
1723
1724                 if (((dma_mask & 2) != 0) && ((adapter->dma_status & 2) != 0)) {
1725                         dma_enable = dma_enable & 0xFFFFFFFD;
1726                 }
1727                 //stop dma
1728                 if ((dma_enable == 0) && ((adapter->dma_status & 4) != 0)) {
1729                         CtrlEnableReceiveData(adapter, 0);
1730
1731                         udelay(3000);
1732                 }
1733                 //disable dma1
1734                 if (((dma_mask & 1) != 0) && ((adapter->dma_status & 1) != 0) && (adapter->dmaq1.bus_addr != 0)) {
1735                         WriteRegDW(adapter, 0x000, adapter->dmaq1.bus_addr);
1736                         WriteRegDW(adapter, 0x00C, (adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) | 1);
1737
1738                         adapter->dma_status = adapter->dma_status & ~0x00000001;
1739                 }
1740                 //disable dma2
1741                 if (((dma_mask & 2) != 0) && ((adapter->dma_status & 2) != 0) && (adapter->dmaq2.bus_addr != 0)) {
1742                         WriteRegDW(adapter, 0x010, adapter->dmaq2.bus_addr);
1743
1744                         adapter->dma_status = adapter->dma_status & ~0x00000002;
1745                 }
1746         }
1747 }
1748
1749 static void OpenStream(struct adapter *adapter, u32 pid)
1750 {
1751         u32 dma_mask;
1752
1753         if (adapter->capturing == 0)
1754                 adapter->capturing = 1;
1755
1756         FilterEnableMaskFilter(adapter, 1);
1757
1758         AddPID(adapter, pid);
1759
1760         dprintk("%s: adapter->dma_status=%x\n", __FUNCTION__, adapter->dma_status);
1761
1762         if ((adapter->dma_status & 7) != 7) {
1763                 dma_mask = 0;
1764
1765                 if (((adapter->dma_status & 0x10000000) != 0) && ((adapter->dma_status & 1) == 0)) {
1766                         dma_mask = dma_mask | 1;
1767
1768                         adapter->dmaq1.head = 0;
1769                         adapter->dmaq1.tail = 0;
1770
1771                         memset(adapter->dmaq1.buffer, 0, adapter->dmaq1.buffer_size);
1772                 }
1773
1774                 if (((adapter->dma_status & 0x20000000) != 0) && ((adapter->dma_status & 2) == 0)) {
1775                         dma_mask = dma_mask | 2;
1776
1777                         adapter->dmaq2.head = 0;
1778                         adapter->dmaq2.tail = 0;
1779                 }
1780
1781                 if (dma_mask != 0) {
1782                         IrqDmaEnableDisableIrq(adapter, 1);
1783
1784                         DmaStartStop0x2102(adapter, dma_mask, 1);
1785                 }
1786         }
1787 }
1788
1789 static void CloseStream(struct adapter *adapter, u32 pid)
1790 {
1791         u32 dma_mask;
1792
1793         if (adapter->capturing != 0)
1794                 adapter->capturing = 0;
1795
1796         dprintk("%s: dma_status=%x\n", __FUNCTION__, adapter->dma_status);
1797
1798         dma_mask = 0;
1799
1800         if ((adapter->dma_status & 1) != 0)
1801                 dma_mask = dma_mask | 0x00000001;
1802         if ((adapter->dma_status & 2) != 0)
1803                 dma_mask = dma_mask | 0x00000002;
1804
1805         if (dma_mask != 0) {
1806                 DmaStartStop0x2102(adapter, dma_mask, 0);
1807         }
1808
1809         RemovePID(adapter, pid);
1810 }
1811
1812 static void InterruptServiceDMA1(struct adapter *adapter)
1813 {
1814         struct dvb_demux *dvbdmx = &adapter->demux;
1815         struct packet_header packet_header;
1816
1817         int nCurDmaCounter;
1818         u32 nNumBytesParsed;
1819         u32 nNumNewBytesTransferred;
1820         u32 dwDefaultPacketSize = 188;
1821         u8 gbTmpBuffer[188];
1822         u8 *pbDMABufCurPos;
1823
1824         nCurDmaCounter = readl(adapter->io_mem + 0x008) - adapter->dmaq1.bus_addr;
1825         nCurDmaCounter = (nCurDmaCounter / dwDefaultPacketSize) * dwDefaultPacketSize;
1826
1827         if ((nCurDmaCounter < 0) || (nCurDmaCounter > adapter->dmaq1.buffer_size)) {
1828                 dprintk("%s: dma counter outside dma buffer\n", __FUNCTION__);
1829                 return;
1830         }
1831
1832         adapter->dmaq1.head = nCurDmaCounter;
1833
1834         if (adapter->dmaq1.tail <= nCurDmaCounter) {
1835                 nNumNewBytesTransferred = nCurDmaCounter - adapter->dmaq1.tail;
1836
1837         } else {
1838
1839                 nNumNewBytesTransferred = (adapter->dmaq1.buffer_size - adapter->dmaq1.tail) + nCurDmaCounter;
1840         }
1841
1842 //  dprintk("%s: nCurDmaCounter   = %d\n" , __FUNCTION__, nCurDmaCounter);
1843 //      dprintk("%s: dmaq1.tail       = %d\n" , __FUNCTION__, adapter->dmaq1.tail):
1844 //  dprintk("%s: BytesTransferred = %d\n" , __FUNCTION__, nNumNewBytesTransferred);
1845
1846         if (nNumNewBytesTransferred < dwDefaultPacketSize)
1847                 return;
1848
1849         nNumBytesParsed = 0;
1850
1851         while (nNumBytesParsed < nNumNewBytesTransferred) {
1852                 pbDMABufCurPos = adapter->dmaq1.buffer + adapter->dmaq1.tail;
1853
1854                 if (adapter->dmaq1.buffer + adapter->dmaq1.buffer_size < adapter->dmaq1.buffer + adapter->dmaq1.tail + 188) {
1855                         memcpy(gbTmpBuffer, adapter->dmaq1.buffer + adapter->dmaq1.tail, adapter->dmaq1.buffer_size - adapter->dmaq1.tail);
1856                         memcpy(gbTmpBuffer + (adapter->dmaq1.buffer_size - adapter->dmaq1.tail), adapter->dmaq1.buffer, (188 - (adapter->dmaq1.buffer_size - adapter->dmaq1.tail)));
1857
1858                         pbDMABufCurPos = gbTmpBuffer;
1859                 }
1860
1861                 if (adapter->capturing != 0) {
1862                         u32 *dq = (u32 *) pbDMABufCurPos;
1863
1864                         packet_header.sync_byte = *dq & 0x000000FF;
1865                         packet_header.transport_error_indicator = *dq & 0x00008000;
1866                         packet_header.payload_unit_start_indicator = *dq & 0x00004000;
1867                         packet_header.transport_priority = *dq & 0x00002000;
1868                         packet_header.pid = ((*dq & 0x00FF0000) >> 0x10) | (*dq & 0x00001F00);
1869                         packet_header.transport_scrambling_control = *dq >> 0x1E;
1870                         packet_header.adaptation_field_control = (*dq & 0x30000000) >> 0x1C;
1871                         packet_header.continuity_counter = (*dq & 0x0F000000) >> 0x18;
1872
1873                         if ((packet_header.sync_byte == 0x47) && (packet_header.transport_error_indicator == 0) && (packet_header.pid != 0x1FFF)) {
1874                                 if (CheckPID(adapter, packet_header.pid & 0x0000FFFF) != 0) {
1875                                         dvb_dmx_swfilter_packets(dvbdmx, pbDMABufCurPos, dwDefaultPacketSize / 188);
1876
1877                                 } else {
1878
1879 //                  dprintk("%s: pid=%x\n", __FUNCTION__, packet_header.pid);
1880                                 }
1881                         }
1882                 }
1883
1884                 nNumBytesParsed = nNumBytesParsed + dwDefaultPacketSize;
1885
1886                 adapter->dmaq1.tail = adapter->dmaq1.tail + dwDefaultPacketSize;
1887
1888                 if (adapter->dmaq1.tail >= adapter->dmaq1.buffer_size)
1889                         adapter->dmaq1.tail = adapter->dmaq1.tail - adapter->dmaq1.buffer_size;
1890         };
1891 }
1892
1893 static void InterruptServiceDMA2(struct adapter *adapter)
1894 {
1895         printk("%s:\n", __FUNCTION__);
1896 }
1897
1898 static irqreturn_t isr(int irq, void *dev_id, struct pt_regs *regs)
1899 {
1900         struct adapter *tmp = dev_id;
1901
1902         u32 value;
1903
1904 //  dprintk("%s:\n", __FUNCTION__);
1905
1906         spin_lock_irq(&tmp->lock);
1907
1908         if (0 == ((value = ReadRegDW(tmp, 0x20C)) & 0x0F)) {
1909                 spin_unlock_irq(&tmp->lock);
1910                 return IRQ_NONE;
1911         }
1912
1913         while (value != 0) {
1914                 if ((value & 0x03) != 0)
1915                         InterruptServiceDMA1(tmp);
1916                 if ((value & 0x0C) != 0)
1917                         InterruptServiceDMA2(tmp);
1918                 value = ReadRegDW(tmp, 0x20C) & 0x0F;
1919         }
1920
1921         spin_unlock_irq(&tmp->lock);
1922         return IRQ_HANDLED;
1923 }
1924
1925 static void Initdmaqueue(struct adapter *adapter)
1926 {
1927         dma_addr_t dma_addr;
1928
1929         if (adapter->dmaq1.buffer != 0)
1930                 return;
1931
1932         adapter->dmaq1.head = 0;
1933         adapter->dmaq1.tail = 0;
1934         adapter->dmaq1.buffer = 0;
1935
1936         adapter->dmaq1.buffer = pci_alloc_consistent(adapter->pdev, SizeOfBufDMA1 + 0x80, &dma_addr);
1937
1938         if (adapter->dmaq1.buffer != 0) {
1939                 memset(adapter->dmaq1.buffer, 0, SizeOfBufDMA1);
1940
1941                 adapter->dmaq1.bus_addr = dma_addr;
1942                 adapter->dmaq1.buffer_size = SizeOfBufDMA1;
1943
1944                 DmaInitDMA(adapter, 0);
1945
1946                 adapter->dma_status = adapter->dma_status | 0x10000000;
1947
1948                 dprintk("%s: allocated dma buffer at 0x%p, length=%d\n", __FUNCTION__, adapter->dmaq1.buffer, SizeOfBufDMA1);
1949
1950         } else {
1951
1952                 adapter->dma_status = adapter->dma_status & ~0x10000000;
1953         }
1954
1955         if (adapter->dmaq2.buffer != 0)
1956                 return;
1957
1958         adapter->dmaq2.head = 0;
1959         adapter->dmaq2.tail = 0;
1960         adapter->dmaq2.buffer = 0;
1961
1962         adapter->dmaq2.buffer = pci_alloc_consistent(adapter->pdev, SizeOfBufDMA2 + 0x80, &dma_addr);
1963
1964         if (adapter->dmaq2.buffer != 0) {
1965                 memset(adapter->dmaq2.buffer, 0, SizeOfBufDMA2);
1966
1967                 adapter->dmaq2.bus_addr = dma_addr;
1968                 adapter->dmaq2.buffer_size = SizeOfBufDMA2;
1969
1970                 DmaInitDMA(adapter, 1);
1971
1972                 adapter->dma_status = adapter->dma_status | 0x20000000;
1973
1974                 dprintk("%s: allocated dma buffer at 0x%p, length=%d\n", __FUNCTION__, adapter->dmaq2.buffer, (int) SizeOfBufDMA2);
1975
1976         } else {
1977
1978                 adapter->dma_status = adapter->dma_status & ~0x20000000;
1979         }
1980 }
1981
1982 static void Freedmaqueue(struct adapter *adapter)
1983 {
1984         if (adapter->dmaq1.buffer != 0) {
1985                 pci_free_consistent(adapter->pdev, SizeOfBufDMA1 + 0x80, adapter->dmaq1.buffer, adapter->dmaq1.bus_addr);
1986
1987                 adapter->dmaq1.bus_addr = 0;
1988                 adapter->dmaq1.head = 0;
1989                 adapter->dmaq1.tail = 0;
1990                 adapter->dmaq1.buffer_size = 0;
1991                 adapter->dmaq1.buffer = 0;
1992         }
1993
1994         if (adapter->dmaq2.buffer != 0) {
1995                 pci_free_consistent(adapter->pdev, SizeOfBufDMA2 + 0x80, adapter->dmaq2.buffer, adapter->dmaq2.bus_addr);
1996
1997                 adapter->dmaq2.bus_addr = 0;
1998                 adapter->dmaq2.head = 0;
1999                 adapter->dmaq2.tail = 0;
2000                 adapter->dmaq2.buffer_size = 0;
2001                 adapter->dmaq2.buffer = 0;
2002         }
2003 }
2004
2005 static void FreeAdapterObject(struct adapter *adapter)
2006 {
2007         dprintk("%s:\n", __FUNCTION__);
2008
2009         CloseStream(adapter, 0);
2010
2011         if (adapter->irq != 0)
2012                 free_irq(adapter->irq, adapter);
2013
2014         Freedmaqueue(adapter);
2015
2016         if (adapter->io_mem != 0)
2017                 iounmap((void *) adapter->io_mem);
2018
2019         if (adapter != 0)
2020                 kfree(adapter);
2021 }
2022
2023 static struct pci_driver skystar2_pci_driver;
2024
2025 static int ClaimAdapter(struct adapter *adapter)
2026 {
2027         struct pci_dev *pdev = adapter->pdev;
2028
2029         u16 var;
2030
2031         if (!request_region(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1), skystar2_pci_driver.name))
2032                 return -EBUSY;
2033
2034         if (!request_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0), skystar2_pci_driver.name))
2035                 return -EBUSY;
2036
2037         pci_read_config_byte(pdev, PCI_CLASS_REVISION, &adapter->card_revision);
2038
2039         dprintk("%s: card revision %x \n", __FUNCTION__, adapter->card_revision);
2040
2041         if (pci_enable_device(pdev))
2042                 return -EIO;
2043
2044         pci_read_config_word(pdev, 4, &var);
2045
2046         if ((var & 4) == 0)
2047                 pci_set_master(pdev);
2048
2049         adapter->io_port = pdev->resource[1].start;
2050
2051         adapter->io_mem = (unsigned long) ioremap(pdev->resource[0].start, 0x800);
2052
2053         if (adapter->io_mem == 0) {
2054                 dprintk("%s: can not map io memory\n", __FUNCTION__);
2055
2056                 return 2;
2057         }
2058
2059         dprintk("%s: io memory maped at %lx\n", __FUNCTION__, adapter->io_mem);
2060
2061         return 1;
2062 }
2063
2064 /*
2065 static int SLL_reset_FlexCOP(struct adapter *adapter)
2066 {
2067         WriteRegDW(adapter, 0x208, 0);
2068         WriteRegDW(adapter, 0x210, 0xB2FF);
2069
2070         return 0;
2071 }
2072 */
2073
2074 static int DriverInitialize(struct pci_dev * pdev)
2075 {
2076         struct adapter *adapter;
2077         u32 tmp;
2078         u8 key[16];
2079
2080         if (!(adapter = kmalloc(sizeof(struct adapter), GFP_KERNEL))) {
2081                 dprintk("%s: out of memory!\n", __FUNCTION__);
2082
2083                 return -ENOMEM;
2084         }
2085
2086         memset(adapter, 0, sizeof(struct adapter));
2087
2088         pci_set_drvdata(pdev,adapter);
2089
2090         adapter->pdev = pdev;
2091         adapter->irq = pdev->irq;
2092
2093         if ((ClaimAdapter(adapter)) != 1) {
2094                 FreeAdapterObject(adapter);
2095
2096                 return -ENODEV;
2097         }
2098
2099         IrqDmaEnableDisableIrq(adapter, 0);
2100
2101         if (request_irq(pdev->irq, isr, 0x4000000, "Skystar2", adapter) != 0) {
2102                 dprintk("%s: unable to allocate irq=%d !\n", __FUNCTION__, pdev->irq);
2103
2104                 FreeAdapterObject(adapter);
2105
2106                 return -ENODEV;
2107         }
2108
2109         ReadRegDW(adapter, 0x208);
2110         WriteRegDW(adapter, 0x208, 0);
2111         WriteRegDW(adapter, 0x210, 0xB2FF);
2112         WriteRegDW(adapter, 0x208, 0x40);
2113
2114         InitPIDsInfo(adapter);
2115
2116         PidSetGroupPID(adapter, 0);
2117         PidSetGroupMASK(adapter, 0x1FE0);
2118         PidSetStream1PID(adapter, 0x1FFF);
2119         PidSetStream2PID(adapter, 0x1FFF);
2120         PidSetPmtPID(adapter, 0x1FFF);
2121         PidSetPcrPID(adapter, 0x1FFF);
2122         PidSetEcmPID(adapter, 0x1FFF);
2123         PidSetEmmPID(adapter, 0x1FFF);
2124
2125         Initdmaqueue(adapter);
2126
2127         if ((adapter->dma_status & 0x30000000) == 0) {
2128                 FreeAdapterObject(adapter);
2129
2130                 return -ENODEV;
2131         }
2132
2133         adapter->b2c2_revision = (ReadRegDW(adapter, 0x204) >> 0x18);
2134
2135         if ((adapter->b2c2_revision != 0x82) && (adapter->b2c2_revision != 0xC3))
2136                 if (adapter->b2c2_revision != 0x82) {
2137                         dprintk("%s: The revision of the FlexCopII chip on your card is - %d\n", __FUNCTION__, adapter->b2c2_revision);
2138                         dprintk("%s: This driver works now only with FlexCopII(rev.130) and FlexCopIIB(rev.195).\n", __FUNCTION__);
2139
2140                         FreeAdapterObject(adapter);
2141
2142                         return -ENODEV;
2143                 }
2144
2145         tmp = ReadRegDW(adapter, 0x204);
2146
2147         WriteRegDW(adapter, 0x204, 0);
2148         mdelay(20);
2149
2150         WriteRegDW(adapter, 0x204, tmp);
2151         mdelay(10);
2152
2153         tmp = ReadRegDW(adapter, 0x308);
2154         WriteRegDW(adapter, 0x308, 0x4000 | tmp);
2155
2156         adapter->dwSramType = 0x10000;
2157
2158         SLL_detectSramSize(adapter);
2159
2160         dprintk("%s sram length = %d, sram type= %x\n", __FUNCTION__, SRAM_length(adapter), adapter->dwSramType);
2161
2162         SRAMSetMediaDest(adapter, 1);
2163         SRAMSetNetDest(adapter, 1);
2164
2165         CtrlEnableSmc(adapter, 0);
2166
2167         SRAMSetCaiDest(adapter, 2);
2168         SRAMSetCaoDest(adapter, 2);
2169
2170         DmaEnableDisableIrq(adapter, 1, 0, 0);
2171
2172         if (EEPROM_getMacAddr(adapter, 0, adapter->mac_addr) != 0) {
2173                 printk("%s MAC address = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x \n", __FUNCTION__, adapter->mac_addr[0], adapter->mac_addr[1], adapter->mac_addr[2], adapter->mac_addr[3], adapter->mac_addr[4], adapter->mac_addr[5], adapter->mac_addr[6], adapter->mac_addr[7]
2174                     );
2175
2176                 CASetMacDstAddrFilter(adapter, adapter->mac_addr);
2177                 CtrlEnableMAC(adapter, 1);
2178         }
2179
2180         EEPROM_readKey(adapter, key, 16);
2181
2182         printk("%s key = \n %02x %02x %02x %02x \n %02x %02x %02x %02x \n %02x %02x %02x %02x \n %02x %02x %02x %02x \n", __FUNCTION__, key[0], key[1], key[2], key[3], key[4], key[5], key[6], key[7], key[8], key[9], key[10], key[11], key[12], key[13], key[14], key[15]);
2183
2184         adapter->lock = SPIN_LOCK_UNLOCKED;
2185
2186         return 0;
2187 }
2188
2189 static void DriverHalt(struct pci_dev *pdev)
2190 {
2191         struct adapter *adapter;
2192
2193         adapter = pci_get_drvdata(pdev);
2194
2195         IrqDmaEnableDisableIrq(adapter, 0);
2196
2197         CtrlEnableReceiveData(adapter, 0);
2198
2199         FreeAdapterObject(adapter);
2200
2201         pci_set_drvdata(pdev, NULL);
2202
2203         release_region(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
2204
2205         release_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
2206 }
2207
2208 static int dvb_start_feed(struct dvb_demux_feed *dvbdmxfeed)
2209 {
2210         struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
2211         struct adapter *adapter = (struct adapter *) dvbdmx->priv;
2212
2213         dprintk("%s: PID=%d, type=%d\n", __FUNCTION__, dvbdmxfeed->pid, dvbdmxfeed->type);
2214
2215         OpenStream(adapter, dvbdmxfeed->pid);
2216
2217         return 0;
2218 }
2219
2220 static int dvb_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
2221 {
2222         struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
2223         struct adapter *adapter = (struct adapter *) dvbdmx->priv;
2224
2225         dprintk("%s: PID=%d, type=%d\n", __FUNCTION__, dvbdmxfeed->pid, dvbdmxfeed->type);
2226
2227         CloseStream(adapter, dvbdmxfeed->pid);
2228
2229         return 0;
2230 }
2231
2232 /* lnb control */
2233 static void set_tuner_tone(struct adapter *adapter, u8 tone)
2234 {
2235         u16 wzHalfPeriodFor45MHz[] = { 0x01FF, 0x0154, 0x00FF, 0x00CC };
2236         u16 ax;
2237
2238         dprintk("%s: %u\n", __FUNCTION__, tone);
2239
2240         switch (tone) {
2241         case 1:
2242                 ax = wzHalfPeriodFor45MHz[0];
2243                 break;
2244         case 2:
2245                 ax = wzHalfPeriodFor45MHz[1];
2246                 break;
2247         case 3:
2248                 ax = wzHalfPeriodFor45MHz[2];
2249                 break;
2250         case 4:
2251                 ax = wzHalfPeriodFor45MHz[3];
2252                 break;
2253
2254         default:
2255                 ax = 0;
2256         }
2257
2258         if (ax != 0) {
2259                 WriteRegDW(adapter, 0x200, ((ax << 0x0F) + (ax & 0x7FFF)) | 0x40000000);
2260
2261         } else {
2262
2263                 WriteRegDW(adapter, 0x200, 0x40FF8000);
2264         }
2265 }
2266
2267 static void set_tuner_polarity(struct adapter *adapter, u8 polarity)
2268 {
2269         u32 var;
2270
2271         dprintk("%s : polarity = %u \n", __FUNCTION__, polarity);
2272
2273         var = ReadRegDW(adapter, 0x204);
2274
2275         if (polarity == 0) {
2276                 dprintk("%s: LNB power off\n", __FUNCTION__);
2277                 var = var | 1;
2278         };
2279
2280         if (polarity == 1) {
2281                 var = var & ~1;
2282                 var = var & ~4;
2283         };
2284
2285         if (polarity == 2) {
2286                 var = var & ~1;
2287                 var = var | 4;
2288         }
2289
2290         WriteRegDW(adapter, 0x204, var);
2291 }
2292
2293 static int flexcop_diseqc_ioctl(struct dvb_frontend *fe, unsigned int cmd, void *arg)
2294 {
2295         struct adapter *adapter = fe->before_after_data;
2296
2297         switch (cmd) {
2298         case FE_SLEEP:
2299                 {
2300                         printk("%s: FE_SLEEP\n", __FUNCTION__);
2301
2302                         set_tuner_polarity(adapter, 0);
2303
2304                         // return -EOPNOTSUPP, to make DVB core also send "FE_SLEEP" command to frontend.
2305                         return -EOPNOTSUPP;
2306                 }
2307
2308         case FE_SET_VOLTAGE:
2309                 {
2310                         dprintk("%s: FE_SET_VOLTAGE\n", __FUNCTION__);
2311
2312                         switch ((fe_sec_voltage_t) arg) {
2313                         case SEC_VOLTAGE_13:
2314
2315                                 printk("%s: SEC_VOLTAGE_13, %x\n", __FUNCTION__, SEC_VOLTAGE_13);
2316
2317                                 set_tuner_polarity(adapter, 1);
2318
2319                                 break;
2320
2321                         case SEC_VOLTAGE_18:
2322
2323                                 printk("%s: SEC_VOLTAGE_18, %x\n", __FUNCTION__, SEC_VOLTAGE_18);
2324
2325                                 set_tuner_polarity(adapter, 2);
2326
2327                                 break;
2328
2329                         default:
2330
2331                                 return -EINVAL;
2332                         };
2333
2334                         break;
2335                 }
2336
2337         case FE_SET_TONE:
2338                 {
2339                         dprintk("%s: FE_SET_TONE\n", __FUNCTION__);
2340
2341                         switch ((fe_sec_tone_mode_t) arg) {
2342                         case SEC_TONE_ON:
2343
2344                                 printk("%s: SEC_TONE_ON, %x\n", __FUNCTION__, SEC_TONE_ON);
2345
2346                                 set_tuner_tone(adapter, 1);
2347
2348                                 break;
2349
2350                         case SEC_TONE_OFF:
2351
2352                                 printk("%s: SEC_TONE_OFF, %x\n", __FUNCTION__, SEC_TONE_OFF);
2353
2354                                 set_tuner_tone(adapter, 0);
2355
2356                                 break;
2357
2358                         default:
2359
2360                                 return -EINVAL;
2361                         };
2362
2363                         break;
2364                 }
2365
2366         default:
2367
2368                 return -EOPNOTSUPP;
2369         };
2370
2371         return 0;
2372 }
2373
2374 static int skystar2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2375 {
2376         struct adapter *adapter;
2377         struct dvb_adapter *dvb_adapter;
2378         struct dvb_demux *dvbdemux;
2379
2380         int ret;
2381
2382         if (pdev == NULL)
2383                 return -ENODEV;
2384
2385         if (DriverInitialize(pdev) != 0)
2386                 return -ENODEV;
2387
2388         dvb_register_adapter(&dvb_adapter, skystar2_pci_driver.name);
2389
2390         if (dvb_adapter == NULL) {
2391                 printk("%s: Error registering DVB adapter\n", __FUNCTION__);
2392
2393                 DriverHalt(pdev);
2394
2395                 return -ENODEV;
2396         }
2397
2398         adapter = (struct adapter *) pci_get_drvdata(pdev);
2399
2400         adapter->dvb_adapter = dvb_adapter;
2401
2402         init_MUTEX(&adapter->i2c_sem);
2403
2404         adapter->i2c_bus = dvb_register_i2c_bus(master_xfer, adapter, adapter->dvb_adapter, 0);
2405
2406         if (!adapter->i2c_bus)
2407                 return -ENOMEM;
2408
2409         dvb_add_frontend_ioctls(adapter->dvb_adapter, flexcop_diseqc_ioctl, NULL, adapter);
2410
2411         dvbdemux = &adapter->demux;
2412
2413         dvbdemux->priv = (void *) adapter;
2414         dvbdemux->filternum = 32;
2415         dvbdemux->feednum = 32;
2416         dvbdemux->start_feed = dvb_start_feed;
2417         dvbdemux->stop_feed = dvb_stop_feed;
2418         dvbdemux->write_to_decoder = 0;
2419         dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING);
2420
2421         dvb_dmx_init(&adapter->demux);
2422
2423         adapter->hw_frontend.source = DMX_FRONTEND_0;
2424
2425         adapter->dmxdev.filternum = 32;
2426         adapter->dmxdev.demux = &dvbdemux->dmx;
2427         adapter->dmxdev.capabilities = 0;
2428
2429         dvb_dmxdev_init(&adapter->dmxdev, adapter->dvb_adapter);
2430
2431         ret = dvbdemux->dmx.add_frontend(&dvbdemux->dmx, &adapter->hw_frontend);
2432         if (ret < 0)
2433                 return ret;
2434
2435         adapter->mem_frontend.source = DMX_MEMORY_FE;
2436
2437         ret = dvbdemux->dmx.add_frontend(&dvbdemux->dmx, &adapter->mem_frontend);
2438         if (ret < 0)
2439                 return ret;
2440
2441         ret = dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, &adapter->hw_frontend);
2442         if (ret < 0)
2443                 return ret;
2444
2445         dvb_net_init(adapter->dvb_adapter, &adapter->dvbnet, &dvbdemux->dmx);
2446         return 0;
2447 }
2448
2449 static void skystar2_remove(struct pci_dev *pdev)
2450 {
2451         struct adapter *adapter;
2452         struct dvb_demux *dvbdemux;
2453
2454         if (pdev == NULL)
2455                 return;
2456
2457         adapter = pci_get_drvdata(pdev);
2458
2459         if (adapter != NULL) {
2460                 dvb_net_release(&adapter->dvbnet);
2461                 dvbdemux = &adapter->demux;
2462
2463                 dvbdemux->dmx.close(&dvbdemux->dmx);
2464                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &adapter->hw_frontend);
2465                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &adapter->mem_frontend);
2466
2467                 dvb_dmxdev_release(&adapter->dmxdev);
2468                 dvb_dmx_release(&adapter->demux);
2469
2470                 if (adapter->dvb_adapter != NULL) {
2471                         dvb_remove_frontend_ioctls(adapter->dvb_adapter, flexcop_diseqc_ioctl, NULL);
2472
2473                         if (adapter->i2c_bus != NULL)
2474                                 dvb_unregister_i2c_bus(master_xfer, adapter->i2c_bus->adapter, adapter->i2c_bus->id);
2475
2476                         dvb_unregister_adapter(adapter->dvb_adapter);
2477                 }
2478
2479                 DriverHalt(pdev);
2480         }
2481 }
2482
2483 static struct pci_device_id skystar2_pci_tbl[] = {
2484         {0x000013D0, 0x00002103, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000},
2485         {0,},
2486 };
2487
2488 static struct pci_driver skystar2_pci_driver = {
2489         .name = "Technisat SkyStar2 driver",
2490         .id_table = skystar2_pci_tbl,
2491         .probe = skystar2_probe,
2492         .remove = skystar2_remove,
2493 };
2494
2495 static int skystar2_init(void)
2496 {
2497         return pci_module_init(&skystar2_pci_driver);
2498 }
2499
2500 static void skystar2_cleanup(void)
2501 {
2502         pci_unregister_driver(&skystar2_pci_driver);
2503 }
2504
2505 module_init(skystar2_init);
2506 module_exit(skystar2_cleanup);
2507
2508 MODULE_DESCRIPTION("Technisat SkyStar2 DVB PCI Driver");
2509 MODULE_LICENSE("GPL");