drivers/ide/pci/serverworks.c

   1 /*
   2  * linux/drivers/ide/pci/serverworks.c          Version 0.8      25 Ebr 2003
   3  *
   4  * Copyright (C) 1998-2000 Michel Aubry
   5  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
   6  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   7  * Portions copyright (c) 2001 Sun Microsystems
   8  *
   9  *
  10  * RCC/ServerWorks IDE driver for Linux
  11  *
  12  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
  13  *         supports UDMA mode 2 (33 MB/s)
  14  *
  15  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
  16  *         all revisions support UDMA mode 4 (66 MB/s)
  17  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
  18  *
  19  *         *** The CSB5 does not provide ANY register ***
  20  *         *** to detect 80-conductor cable presence. ***
  21  *
  22  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  23  *
  24  * Documentation:
  25  *      Available under NDA only. Errata info very hard to get.
  26  *
  27  */
  28
  29 #include <linux/config.h>
  30 #include <linux/types.h>
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/ioport.h>
  34 #include <linux/pci.h>
  35 #include <linux/hdreg.h>
  36 #include <linux/ide.h>
  37 #include <linux/init.h>
  38 #include <linux/delay.h>
  39
  40 #include <asm/io.h>
  41
  42 #include "ide_modes.h"
  43 #include "serverworks.h"
  44
  45 static u8 svwks_revision = 0;
  46 static struct pci_dev *isa_dev;
  47
  48 #if defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS)
  49 #include <linux/stat.h>
  50 #include <linux/proc_fs.h>
  51
  52 static u8 svwks_proc = 0;
  53 #define SVWKS_MAX_DEVS          2
  54 static struct pci_dev *svwks_devs[SVWKS_MAX_DEVS];
  55 static int n_svwks_devs;
  56
  57 static int svwks_get_info (char *buffer, char **addr, off_t offset, int count)
  58 {
  59         char *p = buffer;
  60         int i, len;
  61
  62         p += sprintf(p, "\n                             "
  63                         "ServerWorks OSB4/CSB5/CSB6\n");
  64
  65         for (i = 0; i < n_svwks_devs; i++) {
  66                 struct pci_dev *dev = svwks_devs[i];
  67                 unsigned long bibma = pci_resource_start(dev, 4);
  68                 u32 reg40, reg44;
  69                 u16 reg48, reg56;
  70                 u8  reg54, c0=0, c1=0;
  71
  72                 pci_read_config_dword(dev, 0x40, &reg40);
  73                 pci_read_config_dword(dev, 0x44, &reg44);
  74                 pci_read_config_word(dev, 0x48, &reg48);
  75                 pci_read_config_byte(dev, 0x54, &reg54);
  76                 pci_read_config_word(dev, 0x56, &reg56);
  77
  78                 /*
  79                  * at that point bibma+0x2 et bibma+0xa are byte registers
  80                  * to investigate:
  81                  */
  82                 c0 = inb_p(bibma + 0x02);
  83                 c1 = inb_p(bibma + 0x0a);
  84
  85                 p += sprintf(p, "\n                            ServerWorks ");
  86                 switch(dev->device) {
  87                         case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
  88                         case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
  89                                 p += sprintf(p, "CSB6 ");
  90                                 break;
  91                         case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
  92                                 p += sprintf(p, "CSB5 ");
  93                                 break;
  94                         case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
  95                                 p += sprintf(p, "OSB4 ");
  96                                 break;
  97                         default:
  98                                 p += sprintf(p, "%04x ", dev->device);
  99                                 break;
 100                 }
 101                 p += sprintf(p, "Chipset (rev %02x)\n", svwks_revision);
 102
 103                 p += sprintf(p, "------------------------------- "
 104                                 "General Status "
 105                                 "---------------------------------\n");
 106                 p += sprintf(p, "--------------- Primary Channel "
 107                                 "---------------- Secondary Channel "
 108                                 "-------------\n");
 109                 p += sprintf(p, "                %sabled"
 110                                 "                         %sabled\n",
 111                                 (c0&0x80) ? "dis" : " en",
 112                                 (c1&0x80) ? "dis" : " en");
 113                 p += sprintf(p, "--------------- drive0 --------- drive1 "
 114                                 "-------- drive0 ---------- drive1 ------\n");
 115                 p += sprintf(p, "DMA enabled:    %s              %s"
 116                                 "             %s               %s\n",
 117                         (c0&0x20) ? "yes" : "no ",
 118                         (c0&0x40) ? "yes" : "no ",
 119                         (c1&0x20) ? "yes" : "no ",
 120                         (c1&0x40) ? "yes" : "no " );
 121                 p += sprintf(p, "UDMA enabled:   %s              %s"
 122                                 "             %s               %s\n",
 123                         (reg54 & 0x01) ? "yes" : "no ",
 124                         (reg54 & 0x02) ? "yes" : "no ",
 125                         (reg54 & 0x04) ? "yes" : "no ",
 126                         (reg54 & 0x08) ? "yes" : "no " );
 127                 p += sprintf(p, "UDMA enabled:   %s                %s"
 128                                 "               %s                 %s\n",
 129                         ((reg56&0x0005)==0x0005)?"5":
 130                                 ((reg56&0x0004)==0x0004)?"4":
 131                                 ((reg56&0x0003)==0x0003)?"3":
 132                                 ((reg56&0x0002)==0x0002)?"2":
 133                                 ((reg56&0x0001)==0x0001)?"1":
 134                                 ((reg56&0x000F))?"?":"0",
 135                         ((reg56&0x0050)==0x0050)?"5":
 136                                 ((reg56&0x0040)==0x0040)?"4":
 137                                 ((reg56&0x0030)==0x0030)?"3":
 138                                 ((reg56&0x0020)==0x0020)?"2":
 139                                 ((reg56&0x0010)==0x0010)?"1":
 140                                 ((reg56&0x00F0))?"?":"0",
 141                         ((reg56&0x0500)==0x0500)?"5":
 142                                 ((reg56&0x0400)==0x0400)?"4":
 143                                 ((reg56&0x0300)==0x0300)?"3":
 144                                 ((reg56&0x0200)==0x0200)?"2":
 145                                 ((reg56&0x0100)==0x0100)?"1":
 146                                 ((reg56&0x0F00))?"?":"0",
 147                         ((reg56&0x5000)==0x5000)?"5":
 148                                 ((reg56&0x4000)==0x4000)?"4":
 149                                 ((reg56&0x3000)==0x3000)?"3":
 150                                 ((reg56&0x2000)==0x2000)?"2":
 151                                 ((reg56&0x1000)==0x1000)?"1":
 152                                 ((reg56&0xF000))?"?":"0");
 153                 p += sprintf(p, "DMA enabled:    %s                %s"
 154                                 "               %s                 %s\n",
 155                         ((reg44&0x00002000)==0x00002000)?"2":
 156                                 ((reg44&0x00002100)==0x00002100)?"1":
 157                                 ((reg44&0x00007700)==0x00007700)?"0":
 158                                 ((reg44&0x0000FF00)==0x0000FF00)?"X":"?",
 159                         ((reg44&0x00000020)==0x00000020)?"2":
 160                                 ((reg44&0x00000021)==0x00000021)?"1":
 161                                 ((reg44&0x00000077)==0x00000077)?"0":
 162                                 ((reg44&0x000000FF)==0x000000FF)?"X":"?",
 163                         ((reg44&0x20000000)==0x20000000)?"2":
 164                                 ((reg44&0x21000000)==0x21000000)?"1":
 165                                 ((reg44&0x77000000)==0x77000000)?"0":
 166                                 ((reg44&0xFF000000)==0xFF000000)?"X":"?",
 167                         ((reg44&0x00200000)==0x00200000)?"2":
 168                                 ((reg44&0x00210000)==0x00210000)?"1":
 169                                 ((reg44&0x00770000)==0x00770000)?"0":
 170                                 ((reg44&0x00FF0000)==0x00FF0000)?"X":"?");
 171
 172                 p += sprintf(p, "PIO  enabled:   %s                %s"
 173                                 "               %s                 %s\n",
 174                         ((reg40&0x00002000)==0x00002000)?"4":
 175                                 ((reg40&0x00002200)==0x00002200)?"3":
 176                                 ((reg40&0x00003400)==0x00003400)?"2":
 177                                 ((reg40&0x00004700)==0x00004700)?"1":
 178                                 ((reg40&0x00005D00)==0x00005D00)?"0":"?",
 179                         ((reg40&0x00000020)==0x00000020)?"4":
 180                                 ((reg40&0x00000022)==0x00000022)?"3":
 181                                 ((reg40&0x00000034)==0x00000034)?"2":
 182                                 ((reg40&0x00000047)==0x00000047)?"1":
 183                                 ((reg40&0x0000005D)==0x0000005D)?"0":"?",
 184                         ((reg40&0x20000000)==0x20000000)?"4":
 185                                 ((reg40&0x22000000)==0x22000000)?"3":
 186                                 ((reg40&0x34000000)==0x34000000)?"2":
 187                                 ((reg40&0x47000000)==0x47000000)?"1":
 188                                 ((reg40&0x5D000000)==0x5D000000)?"0":"?",
 189                         ((reg40&0x00200000)==0x00200000)?"4":
 190                                 ((reg40&0x00220000)==0x00220000)?"3":
 191                                 ((reg40&0x00340000)==0x00340000)?"2":
 192                                 ((reg40&0x00470000)==0x00470000)?"1":
 193                                 ((reg40&0x005D0000)==0x005D0000)?"0":"?");
 194
 195         }
 196         p += sprintf(p, "\n");
 197
 198         /* p - buffer must be less than 4k! */
 199         len = (p - buffer) - offset;
 200         *addr = buffer + offset;
 201
 202         return len > count ? count : len;
 203 }
 204 #endif  /* defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS) */
 205
 206 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 207 {
 208         while (*list)
 209                 if (!strcmp(*list++, drive->id->model))
 210                         return 1;
 211         return 0;
 212 }
 213
 214 static u8 svwks_ratemask (ide_drive_t *drive)
 215 {
 216         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 217         u8 mode;
 218
 219         if (!svwks_revision)
 220                 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
 221
 222         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 223                 u32 reg = 0;
 224                 if (isa_dev)
 225                         pci_read_config_dword(isa_dev, 0x64, &reg);
 226
 227                 /*
 228                  *      Don't enable UDMA on disk devices for the moment
 229                  */
 230                 if(drive->media == ide_disk)
 231                         return 0;
 232                 /* Check the OSB4 DMA33 enable bit */
 233                 return ((reg & 0x00004000) == 0x00004000) ? 1 : 0;
 234         } else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
 235                 return 1;
 236         } else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
 237                 u8 btr = 0;
 238                 pci_read_config_byte(dev, 0x5A, &btr);
 239                 mode = btr & 0x3;
 240                 if (!eighty_ninty_three(drive))
 241                         mode = min(mode, (u8)1);
 242                 /* If someone decides to do UDMA133 on CSB5 the same
 243                    issue will bite so be inclusive */
 244                 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
 245                         mode = 2;
 246         }
 247         if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 248              (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 249             (!(PCI_FUNC(dev->devfn) & 1)))
 250                 mode = 2;
 251         return mode;
 252 }
 253
 254 static u8 svwks_csb_check (struct pci_dev *dev)
 255 {
 256         switch (dev->device) {
 257                 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 258                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 259                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 260                         return 1;
 261                 default:
 262                         break;
 263         }
 264         return 0;
 265 }
 266 static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 267 {
 268         u8 udma_modes[]         = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
 269         u8 dma_modes[]          = { 0x77, 0x21, 0x20 };
 270         u8 pio_modes[]          = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
 271         u8 drive_pci[]          = { 0x41, 0x40, 0x43, 0x42 };
 272         u8 drive_pci2[]         = { 0x45, 0x44, 0x47, 0x46 };
 273
 274         ide_hwif_t *hwif        = HWIF(drive);
 275         struct pci_dev *dev     = hwif->pci_dev;
 276         u8 speed                = ide_rate_filter(svwks_ratemask(drive), xferspeed);
 277         u8 pio                  = ide_get_best_pio_mode(drive, 255, 5, NULL);
 278         u8 unit                 = (drive->select.b.unit & 0x01);
 279         u8 csb5                 = svwks_csb_check(dev);
 280         u8 ultra_enable         = 0, ultra_timing = 0;
 281         u8 dma_timing           = 0, pio_timing = 0;
 282         u16 csb5_pio            = 0;
 283
 284         /* If we are about to put a disk into UDMA mode we screwed up.
 285            Our code assumes we never _ever_ do this on an OSB4 */
 286
 287         if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
 288                 drive->media == ide_disk && speed >= XFER_UDMA_0)
 289                         BUG();
 290
 291         pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
 292         pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
 293         pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
 294         pci_read_config_word(dev, 0x4A, &csb5_pio);
 295         pci_read_config_byte(dev, 0x54, &ultra_enable);
 296
 297         /* Per Specified Design by OEM, and ASIC Architect */
 298         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 299             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 300                 if (!drive->init_speed) {
 301                         u8 dma_stat = hwif->INB(hwif->dma_status);
 302
 303 dma_pio:
 304                         if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
 305                             ((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
 306                                 drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
 307                                 return 0;
 308                         } else if ((dma_timing) &&
 309                                    ((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
 310                                 u8 dmaspeed = dma_timing;
 311
 312                                 dma_timing &= ~0xFF;
 313                                 if ((dmaspeed & 0x20) == 0x20)
 314                                         dmaspeed = XFER_MW_DMA_2;
 315                                 else if ((dmaspeed & 0x21) == 0x21)
 316                                         dmaspeed = XFER_MW_DMA_1;
 317                                 else if ((dmaspeed & 0x77) == 0x77)
 318                                         dmaspeed = XFER_MW_DMA_0;
 319                                 else
 320                                         goto dma_pio;
 321                                 drive->current_speed = drive->init_speed = dmaspeed;
 322                                 return 0;
 323                         } else if (pio_timing) {
 324                                 u8 piospeed = pio_timing;
 325
 326                                 pio_timing &= ~0xFF;
 327                                 if ((piospeed & 0x20) == 0x20)
 328                                         piospeed = XFER_PIO_4;
 329                                 else if ((piospeed & 0x22) == 0x22)
 330                                         piospeed = XFER_PIO_3;
 331                                 else if ((piospeed & 0x34) == 0x34)
 332                                         piospeed = XFER_PIO_2;
 333                                 else if ((piospeed & 0x47) == 0x47)
 334                                         piospeed = XFER_PIO_1;
 335                                 else if ((piospeed & 0x5d) == 0x5d)
 336                                         piospeed = XFER_PIO_0;
 337                                 else
 338                                         goto oem_setup_failed;
 339                                 drive->current_speed = drive->init_speed = piospeed;
 340                                 return 0;
 341                         }
 342                 }
 343         }
 344
 345 oem_setup_failed:
 346
 347         pio_timing      &= ~0xFF;
 348         dma_timing      &= ~0xFF;
 349         ultra_timing    &= ~(0x0F << (4*unit));
 350         ultra_enable    &= ~(0x01 << drive->dn);
 351         csb5_pio        &= ~(0x0F << (4*drive->dn));
 352
 353         switch(speed) {
 354                 case XFER_PIO_4:
 355                 case XFER_PIO_3:
 356                 case XFER_PIO_2:
 357                 case XFER_PIO_1:
 358                 case XFER_PIO_0:
 359                         pio_timing |= pio_modes[speed - XFER_PIO_0];
 360                         csb5_pio   |= ((speed - XFER_PIO_0) << (4*drive->dn));
 361                         break;
 362
 363                 case XFER_MW_DMA_2:
 364                 case XFER_MW_DMA_1:
 365                 case XFER_MW_DMA_0:
 366                         pio_timing |= pio_modes[pio];
 367                         csb5_pio   |= (pio << (4*drive->dn));
 368                         dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
 369                         break;
 370
 371                 case XFER_UDMA_5:
 372                 case XFER_UDMA_4:
 373                 case XFER_UDMA_3:
 374                 case XFER_UDMA_2:
 375                 case XFER_UDMA_1:
 376                 case XFER_UDMA_0:
 377                         pio_timing   |= pio_modes[pio];
 378                         csb5_pio     |= (pio << (4*drive->dn));
 379                         dma_timing   |= dma_modes[2];
 380                         ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
 381                         ultra_enable |= (0x01 << drive->dn);
 382                 default:
 383                         break;
 384         }
 385
 386         pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
 387         if (csb5)
 388                 pci_write_config_word(dev, 0x4A, csb5_pio);
 389
 390         pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
 391         pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
 392         pci_write_config_byte(dev, 0x54, ultra_enable);
 393
 394         return (ide_config_drive_speed(drive, speed));
 395 }
 396
 397 static void config_chipset_for_pio (ide_drive_t *drive)
 398 {
 399         u16 eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
 400         u16 xfer_pio = drive->id->eide_pio_modes;
 401         u8 timing, speed, pio;
 402
 403         pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
 404
 405         if (xfer_pio > 4)
 406                 xfer_pio = 0;
 407
 408         if (drive->id->eide_pio_iordy > 0)
 409                 for (xfer_pio = 5;
 410                         xfer_pio>0 &&
 411                         drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
 412                         xfer_pio--);
 413         else
 414                 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
 415                            (drive->id->eide_pio_modes & 2) ? 0x04 :
 416                            (drive->id->eide_pio_modes & 1) ? 0x03 :
 417                            (drive->id->tPIO & 2) ? 0x02 :
 418                            (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
 419
 420         timing = (xfer_pio >= pio) ? xfer_pio : pio;
 421
 422         switch(timing) {
 423                 case 4: speed = XFER_PIO_4;break;
 424                 case 3: speed = XFER_PIO_3;break;
 425                 case 2: speed = XFER_PIO_2;break;
 426                 case 1: speed = XFER_PIO_1;break;
 427                 default:
 428                         speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
 429                         break;
 430         }
 431         (void) svwks_tune_chipset(drive, speed);
 432         drive->current_speed = speed;
 433 }
 434
 435 static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
 436 {
 437         if(pio == 255)
 438                 (void) svwks_tune_chipset(drive, 255);
 439         else
 440                 (void) svwks_tune_chipset(drive, (XFER_PIO_0 + pio));
 441 }
 442
 443 static int config_chipset_for_dma (ide_drive_t *drive)
 444 {
 445         u8 speed = ide_dma_speed(drive, svwks_ratemask(drive));
 446
 447         if (!(speed))
 448                 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
 449
 450         (void) svwks_tune_chipset(drive, speed);
 451         return ide_dma_enable(drive);
 452 }
 453
 454 static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
 455 {
 456         ide_hwif_t *hwif        = HWIF(drive);
 457         struct hd_driveid *id   = drive->id;
 458
 459         drive->init_speed = 0;
 460
 461         if ((id->capability & 1) && drive->autodma) {
 462                 /* Consult the list of known "bad" drives */
 463                 if (hwif->ide_dma_bad_drive(drive))
 464                         goto fast_ata_pio;
 465                 if (id->field_valid & 4) {
 466                         if (id->dma_ultra & hwif->ultra_mask) {
 467                                 /* Force if Capable UltraDMA */
 468                                 int dma = config_chipset_for_dma(drive);
 469                                 if ((id->field_valid & 2) && !dma)
 470                                         goto try_dma_modes;
 471                         }
 472                 } else if (id->field_valid & 2) {
 473 try_dma_modes:
 474                         if ((id->dma_mword & hwif->mwdma_mask) ||
 475                             (id->dma_1word & hwif->swdma_mask)) {
 476                                 /* Force if Capable regular DMA modes */
 477                                 if (!config_chipset_for_dma(drive))
 478                                         goto no_dma_set;
 479                         }
 480                 } else if (hwif->ide_dma_good_drive(drive) &&
 481                            (id->eide_dma_time < 150)) {
 482                         /* Consult the list of known "good" drives */
 483                         if (!config_chipset_for_dma(drive))
 484                                 goto no_dma_set;
 485                 } else {
 486                         goto no_dma_set;
 487                 }
 488         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 489 fast_ata_pio:
 490 no_dma_set:
 491                 config_chipset_for_pio(drive);
 492                 //      hwif->tuneproc(drive, 5);
 493                 return hwif->ide_dma_off_quietly(drive);
 494         }
 495         return hwif->ide_dma_on(drive);
 496 }
 497
 498 /* This can go soon */
 499
 500 static int svwks_ide_dma_end (ide_drive_t *drive)
 501 {
 502         return __ide_dma_end(drive);
 503 }
 504
 505 static unsigned int __init init_chipset_svwks (struct pci_dev *dev, const char *name)
 506 {
 507         unsigned int reg;
 508         u8 btr;
 509
 510         /* save revision id to determine DMA capability */
 511         pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
 512
 513         /* force Master Latency Timer value to 64 PCICLKs */
 514         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
 515
 516         /* OSB4 : South Bridge and IDE */
 517         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 518                 isa_dev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
 519                           PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
 520                 if (isa_dev) {
 521                         pci_read_config_dword(isa_dev, 0x64, &reg);
 522                         reg &= ~0x00002000; /* disable 600ns interrupt mask */
 523                         if(!(reg & 0x00004000))
 524                                 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
 525                         reg |=  0x00004000; /* enable UDMA/33 support */
 526                         pci_write_config_dword(isa_dev, 0x64, reg);
 527                 }
 528         }
 529
 530         /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
 531         else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
 532                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 533                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 534 //              u32 pioreg = 0, dmareg = 0;
 535
 536                 /* Third Channel Test */
 537                 if (!(PCI_FUNC(dev->devfn) & 1)) {
 538 #if 1
 539                         struct pci_dev * findev = NULL;
 540                         u32 reg4c = 0;
 541                         findev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
 542                                 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
 543                         if (findev) {
 544                                 pci_read_config_dword(findev, 0x4C, &reg4c);
 545                                 reg4c &= ~0x000007FF;
 546                                 reg4c |=  0x00000040;
 547                                 reg4c |=  0x00000020;
 548                                 pci_write_config_dword(findev, 0x4C, reg4c);
 549                         }
 550 #endif
 551                         outb_p(0x06, 0x0c00);
 552                         dev->irq = inb_p(0x0c01);
 553 #if 0
 554                         /* WE need to figure out how to get the correct one */
 555                         printk("%s: interrupt %d\n", name, dev->irq);
 556                         if (dev->irq != 0x0B)
 557                                 dev->irq = 0x0B;
 558 #endif
 559 #if 0
 560                         printk("%s: device class (0x%04x)\n",
 561                                 name, dev->class);
 562 #else
 563                         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 564                                 dev->class &= ~0x000F0F00;
 565                 //              dev->class |= ~0x00000400;
 566                                 dev->class |= ~0x00010100;
 567                                 /**/
 568                         }
 569 #endif
 570                 } else {
 571                         struct pci_dev * findev = NULL;
 572                         u8 reg41 = 0;
 573
 574                         findev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
 575                                         PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
 576                         if (findev) {
 577                                 pci_read_config_byte(findev, 0x41, &reg41);
 578                                 reg41 &= ~0x40;
 579                                 pci_write_config_byte(findev, 0x41, reg41);
 580                         }
 581                         /*
 582                          * This is a device pin issue on CSB6.
 583                          * Since there will be a future raid mode,
 584                          * early versions of the chipset require the
 585                          * interrupt pin to be set, and it is a compatibility
 586                          * mode issue.
 587                          */
 588                         dev->irq = 0;
 589                 }
 590 //              pci_read_config_dword(dev, 0x40, &pioreg)
 591 //              pci_write_config_dword(dev, 0x40, 0x99999999);
 592 //              pci_read_config_dword(dev, 0x44, &dmareg);
 593 //              pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
 594                 /* setup the UDMA Control register
 595                  *
 596                  * 1. clear bit 6 to enable DMA
 597                  * 2. enable DMA modes with bits 0-1
 598                  *      00 : legacy
 599                  *      01 : udma2
 600                  *      10 : udma2/udma4
 601                  *      11 : udma2/udma4/udma5
 602                  */
 603                 pci_read_config_byte(dev, 0x5A, &btr);
 604                 btr &= ~0x40;
 605                 if (!(PCI_FUNC(dev->devfn) & 1))
 606                         btr |= 0x2;
 607                 else
 608                         btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
 609                 pci_write_config_byte(dev, 0x5A, btr);
 610         }
 611
 612
 613 #if defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS)
 614         svwks_devs[n_svwks_devs++] = dev;
 615
 616         if (!svwks_proc) {
 617                 svwks_proc = 1;
 618                 ide_pci_register_host_proc(&svwks_procs[0]);
 619         }
 620 #endif /* DISPLAY_SVWKS_TIMINGS && CONFIG_PROC_FS */
 621
 622         return (dev->irq) ? dev->irq : 0;
 623 }
 624
 625 static unsigned int __init ata66_svwks_svwks (ide_hwif_t *hwif)
 626 {
 627         return 1;
 628 }
 629
 630 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 631  * of the subsystem device ID indicate presence of an 80-pin cable.
 632  * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 633  * Bit 15 set   = secondary IDE channel has 80-pin cable.
 634  * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 635  * Bit 14 set   = primary IDE channel has 80-pin cable.
 636  */
 637 static unsigned int __init ata66_svwks_dell (ide_hwif_t *hwif)
 638 {
 639         struct pci_dev *dev = hwif->pci_dev;
 640         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
 641             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 642             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
 643              dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
 644                 return ((1 << (hwif->channel + 14)) &
 645                         dev->subsystem_device) ? 1 : 0;
 646         return 0;
 647 }
 648
 649 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
 650  * detect issue by attaching the drives directly to the board.
 651  * This check follows the Dell precedent (how scary is that?!)
 652  *
 653  * WARNING: this only works on Alpine hardware!
 654  */
 655 static unsigned int __init ata66_svwks_cobalt (ide_hwif_t *hwif)
 656 {
 657         struct pci_dev *dev = hwif->pci_dev;
 658         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
 659             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 660             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
 661                 return ((1 << (hwif->channel + 14)) &
 662                         dev->subsystem_device) ? 1 : 0;
 663         return 0;
 664 }
 665
 666 static unsigned int __init ata66_svwks (ide_hwif_t *hwif)
 667 {
 668         struct pci_dev *dev = hwif->pci_dev;
 669
 670         /* Per Specified Design by OEM, and ASIC Architect */
 671         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 672             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
 673                 return 1;
 674
 675         /* Server Works */
 676         if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
 677                 return ata66_svwks_svwks (hwif);
 678
 679         /* Dell PowerEdge */
 680         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
 681                 return ata66_svwks_dell (hwif);
 682
 683         /* Cobalt Alpine */
 684         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
 685                 return ata66_svwks_cobalt (hwif);
 686
 687         return 0;
 688 }
 689
 690 #undef CAN_SW_DMA
 691 static void __init init_hwif_svwks (ide_hwif_t *hwif)
 692 {
 693         u8 dma_stat = 0;
 694
 695         if (!hwif->irq)
 696                 hwif->irq = hwif->channel ? 15 : 14;
 697
 698         hwif->tuneproc = &svwks_tune_drive;
 699         hwif->speedproc = &svwks_tune_chipset;
 700
 701         hwif->atapi_dma = 1;
 702
 703         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
 704                 hwif->ultra_mask = 0x3f;
 705
 706         hwif->mwdma_mask = 0x07;
 707 #ifdef CAN_SW_DMA
 708         hwif->swdma_mask = 0x07;
 709 #endif /* CAN_SW_DMA */
 710
 711         hwif->autodma = 0;
 712
 713         if (!hwif->dma_base) {
 714                 hwif->drives[0].autotune = 1;
 715                 hwif->drives[1].autotune = 1;
 716                 return;
 717         }
 718
 719         hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
 720         if (hwif->pci_dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
 721                 hwif->ide_dma_end = &svwks_ide_dma_end;
 722         else if (!(hwif->udma_four))
 723                 hwif->udma_four = ata66_svwks(hwif);
 724         if (!noautodma)
 725                 hwif->autodma = 1;
 726
 727         dma_stat = hwif->INB(hwif->dma_status);
 728         hwif->drives[0].autodma = (dma_stat & 0x20);
 729         hwif->drives[1].autodma = (dma_stat & 0x40);
 730         hwif->drives[0].autotune = (!(dma_stat & 0x20));
 731         hwif->drives[1].autotune = (!(dma_stat & 0x40));
 732 //      hwif->drives[0].autodma = hwif->autodma;
 733 //      hwif->drives[1].autodma = hwif->autodma;
 734 }
 735
 736 /*
 737  * We allow the BM-DMA driver to only work on enabled interfaces.
 738  */
 739 static void __init init_dma_svwks (ide_hwif_t *hwif, unsigned long dmabase)
 740 {
 741         struct pci_dev *dev = hwif->pci_dev;
 742
 743         if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 744              (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 745             (!(PCI_FUNC(dev->devfn) & 1)) && (hwif->channel))
 746                 return;
 747
 748         ide_setup_dma(hwif, dmabase, 8);
 749 }
 750
 751 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
 752
 753 static void __init init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
 754 {
 755         ide_setup_pci_device(dev, d);
 756 }
 757
 758 static void __init init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
 759 {
 760         if (!(PCI_FUNC(dev->devfn) & 1)) {
 761                 d->bootable = NEVER_BOARD;
 762                 if (dev->resource[0].start == 0x01f1)
 763                         d->bootable = ON_BOARD;
 764         } else {
 765                 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
 766                         return;
 767         }
 768 #if 0
 769         if ((IDE_PCI_DEVID_EQ(d->devid, DEVID_CSB6) &&
 770              (!(PCI_FUNC(dev->devfn) & 1)))
 771                 d->autodma = AUTODMA;
 772 #endif
 773
 774         d->channels = (((d->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 775                         (d->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 776                        (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
 777
 778         ide_setup_pci_device(dev, d);
 779 }
 780
 781
 782 /**
 783  *      svwks_init_one  -       called when a OSB/CSB is found
 784  *      @dev: the svwks device
 785  *      @id: the matching pci id
 786  *
 787  *      Called when the PCI registration layer (or the IDE initialization)
 788  *      finds a device matching our IDE device tables.
 789  */
 790
 791 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 792 {
 793         ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
 794
 795         if (dev->device != d->device)
 796                 BUG();
 797         d->init_setup(dev, d);
 798         MOD_INC_USE_COUNT;
 799         return 0;
 800 }
 801
 802 static struct pci_device_id svwks_pci_tbl[] = {
 803         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 804         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 805         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 806         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 807         { 0, },
 808 };
 809
 810 static struct pci_driver driver = {
 811         .name           = "Serverworks IDE",
 812         .id_table       = svwks_pci_tbl,
 813         .probe          = svwks_init_one,
 814 #if 0   /* FIXME: implement */
 815         .suspend        = ,
 816         .resume         = ,
 817 #endif
 818 };
 819
 820 static int svwks_ide_init(void)
 821 {
 822         return ide_pci_register_driver(&driver);
 823 }
 824
 825 static void svwks_ide_exit(void)
 826 {
 827         ide_pci_unregister_driver(&driver);
 828 }
 829
 830 module_init(svwks_ide_init);
 831 module_exit(svwks_ide_exit);
 832
 833 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
 834 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
 835 MODULE_LICENSE("GPL");