2 * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
8 * 00:12.0 Unknown mass storage controller:
9 * Triones Technologies, Inc.
10 * Unknown device 0003 (rev 01)
12 * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
13 * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
14 * hde: DMA 2 (0x0000 0x0002) (0x0000 0x0010)
15 * hdf: DMA 2 (0x0002 0x0012) (0x0010 0x0030)
16 * hdg: DMA 1 (0x0012 0x0052) (0x0030 0x0070)
17 * hdh: DMA 1 (0x0052 0x0252) (0x0070 0x00f0)
21 * Since there are two cards that report almost identically,
22 * the only discernable difference is the values reported in pcicmd.
23 * Booting-BIOS card or HPT363 :: pcicmd == 0x07
24 * Non-bootable card or HPT343 :: pcicmd == 0x05
27 #include <linux/config.h>
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/kernel.h>
31 #include <linux/delay.h>
32 #include <linux/timer.h>
34 #include <linux/ioport.h>
35 #include <linux/blkdev.h>
36 #include <linux/hdreg.h>
37 #include <linux/interrupt.h>
38 #include <linux/pci.h>
39 #include <linux/init.h>
40 #include <linux/ide.h>
45 #include "ide_modes.h"
48 #if defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS)
49 #include <linux/stat.h>
50 #include <linux/proc_fs.h>
52 static u8 hpt34x_proc = 0;
54 #define HPT34X_MAX_DEVS 8
55 static struct pci_dev *hpt34x_devs[HPT34X_MAX_DEVS];
56 static int n_hpt34x_devs;
58 static int hpt34x_get_info (char *buffer, char **addr, off_t offset, int count)
65 for (i = 0; i < n_hpt34x_devs; i++) {
66 struct pci_dev *dev = hpt34x_devs[i];
67 unsigned long bibma = pci_resource_start(dev, 4);
71 * at that point bibma+0x2 et bibma+0xa are byte registers
74 c0 = inb_p((u16)bibma + 0x02);
75 c1 = inb_p((u16)bibma + 0x0a);
76 p += sprintf(p, "\nController: %d\n", i);
77 p += sprintf(p, "--------------- Primary Channel "
78 "---------------- Secondary Channel "
80 p += sprintf(p, " %sabled "
82 (c0&0x80) ? "dis" : " en",
83 (c1&0x80) ? "dis" : " en");
84 p += sprintf(p, "--------------- drive0 --------- drive1 "
85 "-------- drive0 ---------- drive1 ------\n");
86 p += sprintf(p, "DMA enabled: %s %s"
88 (c0&0x20) ? "yes" : "no ",
89 (c0&0x40) ? "yes" : "no ",
90 (c1&0x20) ? "yes" : "no ",
91 (c1&0x40) ? "yes" : "no " );
93 p += sprintf(p, "UDMA\n");
94 p += sprintf(p, "DMA\n");
95 p += sprintf(p, "PIO\n");
97 p += sprintf(p, "\n");
99 /* p - buffer must be less than 4k! */
100 len = (p - buffer) - offset;
101 *addr = buffer + offset;
103 return len > count ? count : len;
105 #endif /* defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS) */
107 static u8 hpt34x_ratemask (ide_drive_t *drive)
112 static void hpt34x_clear_chipset (ide_drive_t *drive)
114 struct pci_dev *dev = HWIF(drive)->pci_dev;
115 u32 reg1 = 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
117 pci_read_config_dword(dev, 0x44, ®1);
118 pci_read_config_dword(dev, 0x48, ®2);
119 tmp1 = ((0x00 << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
120 tmp2 = (reg2 & ~(0x11 << drive->dn));
121 pci_write_config_dword(dev, 0x44, tmp1);
122 pci_write_config_dword(dev, 0x48, tmp2);
125 static int hpt34x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
127 struct pci_dev *dev = HWIF(drive)->pci_dev;
128 u8 speed = ide_rate_filter(hpt34x_ratemask(drive), xferspeed);
129 u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
130 u8 hi_speed, lo_speed;
132 SPLIT_BYTE(speed, hi_speed, lo_speed);
135 hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
141 pci_read_config_dword(dev, 0x44, ®1);
142 pci_read_config_dword(dev, 0x48, ®2);
143 tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
144 tmp2 = ((hi_speed << drive->dn) | reg2);
145 pci_write_config_dword(dev, 0x44, tmp1);
146 pci_write_config_dword(dev, 0x48, tmp2);
148 #if HPT343_DEBUG_DRIVE_INFO
149 printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
150 " (0x%02x 0x%02x)\n",
151 drive->name, ide_xfer_verbose(speed),
152 drive->dn, reg1, tmp1, reg2, tmp2,
154 #endif /* HPT343_DEBUG_DRIVE_INFO */
156 return(ide_config_drive_speed(drive, speed));
159 static void hpt34x_tune_drive (ide_drive_t *drive, u8 pio)
161 pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
162 hpt34x_clear_chipset(drive);
163 (void) hpt34x_tune_chipset(drive, (XFER_PIO_0 + pio));
167 * This allows the configuration of ide_pci chipset registers
168 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
169 * after the drive is reported by the OS. Initially for designed for
170 * HPT343 UDMA chipset by HighPoint|Triones Technologies, Inc.
173 static int config_chipset_for_dma (ide_drive_t *drive)
175 u8 speed = ide_dma_speed(drive, hpt34x_ratemask(drive));
180 hpt34x_clear_chipset(drive);
181 (void) hpt34x_tune_chipset(drive, speed);
182 return ide_dma_enable(drive);
185 static int hpt34x_config_drive_xfer_rate (ide_drive_t *drive)
187 ide_hwif_t *hwif = HWIF(drive);
188 struct hd_driveid *id = drive->id;
190 drive->init_speed = 0;
192 if (id && (id->capability & 1) && drive->autodma) {
193 /* Consult the list of known "bad" drives */
194 if (hwif->ide_dma_bad_drive(drive))
196 if (id->field_valid & 4) {
197 if (id->dma_ultra & hwif->ultra_mask) {
198 /* Force if Capable UltraDMA */
199 int dma = config_chipset_for_dma(drive);
200 if ((id->field_valid & 2) && dma)
203 } else if (id->field_valid & 2) {
205 if ((id->dma_mword & hwif->mwdma_mask) ||
206 (id->dma_1word & hwif->swdma_mask)) {
207 /* Force if Capable regular DMA modes */
208 if (!config_chipset_for_dma(drive))
211 } else if (hwif->ide_dma_good_drive(drive) &&
212 (id->eide_dma_time < 150)) {
213 /* Consult the list of known "good" drives */
214 if (!config_chipset_for_dma(drive))
219 } else if ((id->capability & 8) || (id->field_valid & 2)) {
222 hpt34x_tune_drive(drive, 255);
223 return hwif->ide_dma_off_quietly(drive);
226 #ifndef CONFIG_HPT34X_AUTODMA
227 return hwif->ide_dma_off_quietly(drive);
228 #endif /* CONFIG_HPT34X_AUTODMA */
229 return hwif->ide_dma_on(drive);
233 * If the BIOS does not set the IO base addaress to XX00, 343 will fail.
235 #define HPT34X_PCI_INIT_REG 0x80
237 static unsigned int __init init_chipset_hpt34x (struct pci_dev *dev, const char *name)
240 unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
241 unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
242 unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
246 local_irq_save(flags);
248 pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
249 pci_read_config_word(dev, PCI_COMMAND, &cmd);
251 if (cmd & PCI_COMMAND_MEMORY) {
252 if (pci_resource_start(dev, PCI_ROM_RESOURCE)) {
253 pci_write_config_byte(dev, PCI_ROM_ADDRESS,
254 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
255 printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n",
256 dev->resource[PCI_ROM_RESOURCE].start);
258 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
260 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
264 * Since 20-23 can be assigned and are R/W, we correct them.
266 pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
268 dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
269 dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
270 dev->resource[i].flags = IORESOURCE_IO;
271 pci_write_config_dword(dev,
272 (PCI_BASE_ADDRESS_0 + (i * 4)),
273 dev->resource[i].start);
275 pci_write_config_word(dev, PCI_COMMAND, cmd);
277 local_irq_restore(flags);
279 #if defined(DISPLAY_HPT34X_TIMINGS) && defined(CONFIG_PROC_FS)
280 hpt34x_devs[n_hpt34x_devs++] = dev;
284 ide_pci_register_host_proc(&hpt34x_procs[0]);
286 #endif /* DISPLAY_HPT34X_TIMINGS && CONFIG_PROC_FS */
291 static void __init init_hwif_hpt34x (ide_hwif_t *hwif)
297 hwif->tuneproc = &hpt34x_tune_drive;
298 hwif->speedproc = &hpt34x_tune_chipset;
300 hwif->drives[0].autotune = 1;
301 hwif->drives[1].autotune = 1;
303 pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd);
308 hwif->ultra_mask = 0x07;
309 hwif->mwdma_mask = 0x07;
310 hwif->swdma_mask = 0x07;
312 hwif->ide_dma_check = &hpt34x_config_drive_xfer_rate;
314 hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0;
315 hwif->drives[0].autodma = hwif->autodma;
316 hwif->drives[1].autodma = hwif->autodma;
319 static void __init init_dma_hpt34x (ide_hwif_t *hwif, unsigned long dmabase)
321 ide_setup_dma(hwif, dmabase, 8);
324 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
326 static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
328 ide_pci_device_t *d = &hpt34x_chipsets[id->driver_data];
329 static char *chipset_names[] = {"HPT343", "HPT345"};
332 pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
334 d->name = chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
335 d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;
337 ide_setup_pci_device(dev, d);
342 static struct pci_device_id hpt34x_pci_tbl[] = {
343 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
347 static struct pci_driver driver = {
348 .name = "HPT34x IDE",
349 .id_table = hpt34x_pci_tbl,
350 .probe = hpt34x_init_one,
353 static int hpt34x_ide_init(void)
355 return ide_pci_register_driver(&driver);
358 static void hpt34x_ide_exit(void)
360 ide_pci_unregister_driver(&driver);
363 module_init(hpt34x_ide_init);
364 module_exit(hpt34x_ide_exit);
366 MODULE_AUTHOR("Andre Hedrick");
367 MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
368 MODULE_LICENSE("GPL");