2 * linux/drivers/ide/pci/cs5530.c Version 0.7 Sept 10, 2002
4 * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
5 * Ditto of GNU General Public License.
7 * Copyright (C) 2000 Mark Lord <mlord@pobox.com>
8 * May be copied or modified under the terms of the GNU General Public License
10 * Development of this chipset driver was funded
11 * by the nice folks at National Semiconductor.
14 * CS5530 documentation available from National Semiconductor.
17 #include <linux/config.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/timer.h>
24 #include <linux/ioport.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/ide.h>
34 #include "ide_modes.h"
37 #if defined(DISPLAY_CS5530_TIMINGS) && defined(CONFIG_PROC_FS)
38 #include <linux/stat.h>
39 #include <linux/proc_fs.h>
41 static u8 cs5530_proc = 0;
43 static struct pci_dev *bmide_dev;
45 static int cs5530_get_info (char *buffer, char **addr, off_t offset, int count)
48 unsigned long bibma = pci_resource_start(bmide_dev, 4);
52 * at that point bibma+0x2 et bibma+0xa are byte registers
56 c0 = inb_p((u16)bibma + 0x02);
57 c1 = inb_p((u16)bibma + 0x0a);
60 "Cyrix 5530 Chipset.\n");
61 p += sprintf(p, "--------------- Primary Channel "
62 "---------------- Secondary Channel "
64 p += sprintf(p, " %sabled "
66 (c0&0x80) ? "dis" : " en",
67 (c1&0x80) ? "dis" : " en");
68 p += sprintf(p, "--------------- drive0 --------- drive1 "
69 "-------- drive0 ---------- drive1 ------\n");
70 p += sprintf(p, "DMA enabled: %s %s "
72 (c0&0x20) ? "yes" : "no ",
73 (c0&0x40) ? "yes" : "no ",
74 (c1&0x20) ? "yes" : "no ",
75 (c1&0x40) ? "yes" : "no " );
77 p += sprintf(p, "UDMA\n");
78 p += sprintf(p, "DMA\n");
79 p += sprintf(p, "PIO\n");
83 #endif /* DISPLAY_CS5530_TIMINGS && CONFIG_PROC_FS */
86 * cs5530_xfer_set_mode - set a new transfer mode at the drive
87 * @drive: drive to tune
90 * Logging wrapper to the IDE driver speed configuration. This can
91 * probably go away now.
94 static int cs5530_set_xfer_mode (ide_drive_t *drive, u8 mode)
96 printk(KERN_DEBUG "%s: cs5530_set_xfer_mode(%s)\n",
97 drive->name, ide_xfer_verbose(mode));
98 return (ide_config_drive_speed(drive, mode));
102 * Here are the standard PIO mode 0-4 timings for each "format".
103 * Format-0 uses fast data reg timings, with slower command reg timings.
104 * Format-1 uses fast timings for all registers, but won't work with all drives.
106 static unsigned int cs5530_pio_timings[2][5] = {
107 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
108 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
112 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
114 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
115 #define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
118 * cs5530_tuneproc - select/set PIO modes
120 * cs5530_tuneproc() handles selection/setting of PIO modes
121 * for both the chipset and drive.
123 * The ide_init_cs5530() routine guarantees that all drives
124 * will have valid default PIO timings set up before we get here.
127 static void cs5530_tuneproc (ide_drive_t *drive, u8 pio) /* pio=255 means "autotune" */
129 ide_hwif_t *hwif = HWIF(drive);
131 unsigned long basereg = CS5530_BASEREG(hwif);
132 static u8 modes[5] = { XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, XFER_PIO_4};
134 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
135 if (!cs5530_set_xfer_mode(drive, modes[pio])) {
136 format = (hwif->INL(basereg+4) >> 31) & 1;
137 hwif->OUTL(cs5530_pio_timings[format][pio],
138 basereg+(drive->select.b.unit<<3));
143 * cs5530_config_dma - select/set DMA and UDMA modes
144 * @drive: drive to tune
146 * cs5530_config_dma() handles selection/setting of DMA/UDMA modes
147 * for both the chipset and drive. The CS5530 has limitations about
148 * mixing DMA/UDMA on the same cable.
151 static int cs5530_config_dma (ide_drive_t *drive)
153 int udma_ok = 1, mode = 0;
154 ide_hwif_t *hwif = HWIF(drive);
155 int unit = drive->select.b.unit;
156 ide_drive_t *mate = &hwif->drives[unit^1];
157 struct hd_driveid *id = drive->id;
158 unsigned int reg, timings;
159 unsigned long basereg;
162 * Default to DMA-off in case we run into trouble here.
164 hwif->ide_dma_off_quietly(drive);
165 /* turn off DMA while we fiddle */
166 hwif->ide_dma_host_off(drive);
167 /* clear DMA_capable bit */
170 * The CS5530 specifies that two drives sharing a cable cannot
171 * mix UDMA/MDMA. It has to be one or the other, for the pair,
172 * though different timings can still be chosen for each drive.
173 * We could set the appropriate timing bits on the fly,
174 * but that might be a bit confusing. So, for now we statically
175 * handle this requirement by looking at our mate drive to see
176 * what it is capable of, before choosing a mode for our own drive.
178 * Note: This relies on the fact we never fail from UDMA to MWDMA_2
179 * but instead drop to PIO
182 struct hd_driveid *mateid = mate->id;
183 if (mateid && (mateid->capability & 1) &&
184 !hwif->ide_dma_bad_drive(mate)) {
185 if ((mateid->field_valid & 4) &&
186 (mateid->dma_ultra & 7))
188 else if ((mateid->field_valid & 2) &&
189 (mateid->dma_mword & 7))
197 * Now see what the current drive is capable of,
198 * selecting UDMA only if the mate said it was ok.
200 if (id && (id->capability & 1) && drive->autodma &&
201 !hwif->ide_dma_bad_drive(drive)) {
202 if (udma_ok && (id->field_valid & 4) && (id->dma_ultra & 7)) {
203 if (id->dma_ultra & 4)
205 else if (id->dma_ultra & 2)
207 else if (id->dma_ultra & 1)
210 if (!mode && (id->field_valid & 2) && (id->dma_mword & 7)) {
211 if (id->dma_mword & 4)
212 mode = XFER_MW_DMA_2;
213 else if (id->dma_mword & 2)
214 mode = XFER_MW_DMA_1;
215 else if (id->dma_mword & 1)
216 mode = XFER_MW_DMA_0;
221 * Tell the drive to switch to the new mode; abort on failure.
223 if (!mode || cs5530_set_xfer_mode(drive, mode))
224 return 1; /* failure */
227 * Now tune the chipset to match the drive:
230 case XFER_UDMA_0: timings = 0x00921250; break;
231 case XFER_UDMA_1: timings = 0x00911140; break;
232 case XFER_UDMA_2: timings = 0x00911030; break;
233 case XFER_MW_DMA_0: timings = 0x00077771; break;
234 case XFER_MW_DMA_1: timings = 0x00012121; break;
235 case XFER_MW_DMA_2: timings = 0x00002020; break;
237 printk(KERN_ERR "%s: cs5530_config_dma: huh? mode=%02x\n",
239 return 1; /* failure */
241 basereg = CS5530_BASEREG(hwif);
242 reg = hwif->INL(basereg+4); /* get drive0 config register */
243 timings |= reg & 0x80000000; /* preserve PIO format bit */
244 if (unit == 0) { /* are we configuring drive0? */
245 hwif->OUTL(timings, basereg+4); /* write drive0 config register */
247 if (timings & 0x00100000)
248 reg |= 0x00100000; /* enable UDMA timings for both drives */
250 reg &= ~0x00100000; /* disable UDMA timings for both drives */
251 hwif->OUTL(reg, basereg+4); /* write drive0 config register */
252 hwif->OUTL(timings, basereg+12); /* write drive1 config register */
254 (void) hwif->ide_dma_host_on(drive);
255 /* set DMA_capable bit */
258 * Finally, turn DMA on in software, and exit.
260 return hwif->ide_dma_on(drive); /* success */
264 * init_chipset_5530 - set up 5530 bridge
268 * Initialize the cs5530 bridge for reliable IDE DMA operation.
271 static unsigned int __init init_chipset_cs5530 (struct pci_dev *dev, const char *name)
273 struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
276 #if defined(DISPLAY_CS5530_TIMINGS) && defined(CONFIG_PROC_FS)
280 ide_pci_register_host_proc(&cs5530_procs[0]);
282 #endif /* DISPLAY_CS5530_TIMINGS && CONFIG_PROC_FS */
285 while ((dev = pci_find_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
286 switch (dev->device) {
287 case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
290 case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
296 printk(KERN_ERR "%s: unable to locate PCI MASTER function\n", name);
300 printk(KERN_ERR "%s: unable to locate CS5530 LEGACY function\n", name);
304 spin_lock_irqsave(&ide_lock, flags);
305 /* all CPUs (there should only be one CPU with this chipset) */
308 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
309 * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
312 pci_set_master(cs5530_0);
313 pci_set_mwi(cs5530_0);
316 * Set PCI CacheLineSize to 16-bytes:
317 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
320 pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
323 * Disable trapping of UDMA register accesses (Win98 hack):
324 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
327 pci_write_config_word(cs5530_0, 0xd0, 0x5006);
330 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
331 * The other settings are what is necessary to get the register
332 * into a sane state for IDE DMA operation.
335 pci_write_config_byte(master_0, 0x40, 0x1e);
338 * Set max PCI burst size (16-bytes seems to work best):
339 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
340 * all others: clear bit-1 at 0x41, and do:
341 * 128bytes: OR 0x00 at 0x41
342 * 256bytes: OR 0x04 at 0x41
343 * 512bytes: OR 0x08 at 0x41
344 * 1024bytes: OR 0x0c at 0x41
347 pci_write_config_byte(master_0, 0x41, 0x14);
350 * These settings are necessary to get the chip
351 * into a sane state for IDE DMA operation.
354 pci_write_config_byte(master_0, 0x42, 0x00);
355 pci_write_config_byte(master_0, 0x43, 0xc1);
357 spin_unlock_irqrestore(&ide_lock, flags);
363 * init_hwif_cs5530 - initialise an IDE channel
364 * @hwif: IDE to initialize
366 * This gets invoked by the IDE driver once for each channel. It
367 * performs channel-specific pre-initialization before drive probing.
370 static void __init init_hwif_cs5530 (ide_hwif_t *hwif)
372 unsigned long basereg;
377 hwif->serialized = hwif->mate->serialized = 1;
379 hwif->tuneproc = &cs5530_tuneproc;
380 basereg = CS5530_BASEREG(hwif);
381 d0_timings = hwif->INL(basereg+0);
382 if (CS5530_BAD_PIO(d0_timings)) {
383 /* PIO timings not initialized? */
384 hwif->OUTL(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+0);
385 if (!hwif->drives[0].autotune)
386 hwif->drives[0].autotune = 1;
387 /* needs autotuning later */
389 if (CS5530_BAD_PIO(hwif->INL(basereg+8))) {
390 /* PIO timings not initialized? */
391 hwif->OUTL(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+8);
392 if (!hwif->drives[1].autotune)
393 hwif->drives[1].autotune = 1;
394 /* needs autotuning later */
398 hwif->ultra_mask = 0x07;
399 hwif->mwdma_mask = 0x07;
401 hwif->ide_dma_check = &cs5530_config_dma;
404 hwif->drives[0].autodma = hwif->autodma;
405 hwif->drives[1].autodma = hwif->autodma;
409 * init_dma_cs5530 - set up for DMA
411 * @dmabase: DMA base address
413 * FIXME: this can go away
416 static void __init init_dma_cs5530 (ide_hwif_t *hwif, unsigned long dmabase)
418 ide_setup_dma(hwif, dmabase, 8);
421 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
424 static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
426 ide_pci_device_t *d = &cs5530_chipsets[id->driver_data];
427 if (dev->device != d->device)
429 ide_setup_pci_device(dev, d);
434 static struct pci_device_id cs5530_pci_tbl[] = {
435 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
439 static struct pci_driver driver = {
440 .name = "CS5530 IDE",
441 .id_table = cs5530_pci_tbl,
442 .probe = cs5530_init_one,
445 static int cs5530_ide_init(void)
447 return ide_pci_register_driver(&driver);
450 static void cs5530_ide_exit(void)
452 ide_pci_unregister_driver(&driver);
455 module_init(cs5530_ide_init);
456 module_exit(cs5530_ide_exit);
458 MODULE_AUTHOR("Mark Lord");
459 MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
460 MODULE_LICENSE("GPL");