drivers/char/agp/amd-k7-agp.c

   1 /*
   2  * AMD K7 AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/agp_backend.h>
   9 #include <linux/gfp.h>
  10 #include <linux/page-flags.h>
  11 #include <linux/mm.h>
  12 #include "agp.h"
  13
  14 static int agp_try_unsupported __initdata = 0;
  15
  16 struct amd_page_map {
  17         unsigned long *real;
  18         unsigned long *remapped;
  19 };
  20
  21 static struct _amd_irongate_private {
  22         volatile u8 *registers;
  23         struct amd_page_map **gatt_pages;
  24         int num_tables;
  25 } amd_irongate_private;
  26
  27 static int amd_create_page_map(struct amd_page_map *page_map)
  28 {
  29         int i;
  30
  31         page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
  32         if (page_map->real == NULL)
  33                 return -ENOMEM;
  34
  35         SetPageReserved(virt_to_page(page_map->real));
  36         global_cache_flush();
  37         page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real),
  38                                             PAGE_SIZE);
  39         if (page_map->remapped == NULL) {
  40                 ClearPageReserved(virt_to_page(page_map->real));
  41                 free_page((unsigned long) page_map->real);
  42                 page_map->real = NULL;
  43                 return -ENOMEM;
  44         }
  45         global_cache_flush();
  46
  47         for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
  48                 page_map->remapped[i] = agp_bridge->scratch_page;
  49
  50         return 0;
  51 }
  52
  53 static void amd_free_page_map(struct amd_page_map *page_map)
  54 {
  55         iounmap(page_map->remapped);
  56         ClearPageReserved(virt_to_page(page_map->real));
  57         free_page((unsigned long) page_map->real);
  58 }
  59
  60 static void amd_free_gatt_pages(void)
  61 {
  62         int i;
  63         struct amd_page_map **tables;
  64         struct amd_page_map *entry;
  65
  66         tables = amd_irongate_private.gatt_pages;
  67         for (i = 0; i < amd_irongate_private.num_tables; i++) {
  68                 entry = tables[i];
  69                 if (entry != NULL) {
  70                         if (entry->real != NULL)
  71                                 amd_free_page_map(entry);
  72                         kfree(entry);
  73                 }
  74         }
  75         kfree(tables);
  76         amd_irongate_private.gatt_pages = NULL;
  77 }
  78
  79 static int amd_create_gatt_pages(int nr_tables)
  80 {
  81         struct amd_page_map **tables;
  82         struct amd_page_map *entry;
  83         int retval = 0;
  84         int i;
  85
  86         tables = kmalloc((nr_tables + 1) * sizeof(struct amd_page_map *),
  87                          GFP_KERNEL);
  88         if (tables == NULL)
  89                 return -ENOMEM;
  90
  91         memset (tables, 0, sizeof(struct amd_page_map *) * (nr_tables + 1));
  92         for (i = 0; i < nr_tables; i++) {
  93                 entry = kmalloc(sizeof(struct amd_page_map), GFP_KERNEL);
  94                 if (entry == NULL) {
  95                         retval = -ENOMEM;
  96                         break;
  97                 }
  98                 memset (entry, 0, sizeof(struct amd_page_map));
  99                 tables[i] = entry;
 100                 retval = amd_create_page_map(entry);
 101                 if (retval != 0)
 102                         break;
 103         }
 104         amd_irongate_private.num_tables = nr_tables;
 105         amd_irongate_private.gatt_pages = tables;
 106
 107         if (retval != 0)
 108                 amd_free_gatt_pages();
 109
 110         return retval;
 111 }
 112
 113 /* Since we don't need contigious memory we just try
 114  * to get the gatt table once
 115  */
 116
 117 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
 118 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
 119         GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
 120 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
 121 #define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
 122         GET_PAGE_DIR_IDX(addr)]->remapped)
 123
 124 static int amd_create_gatt_table(void)
 125 {
 126         struct aper_size_info_lvl2 *value;
 127         struct amd_page_map page_dir;
 128         unsigned long addr;
 129         int retval;
 130         u32 temp;
 131         int i;
 132
 133         value = A_SIZE_LVL2(agp_bridge->current_size);
 134         retval = amd_create_page_map(&page_dir);
 135         if (retval != 0)
 136                 return retval;
 137
 138         retval = amd_create_gatt_pages(value->num_entries / 1024);
 139         if (retval != 0) {
 140                 amd_free_page_map(&page_dir);
 141                 return retval;
 142         }
 143
 144         agp_bridge->gatt_table_real = (u32 *)page_dir.real;
 145         agp_bridge->gatt_table = (u32 *)page_dir.remapped;
 146         agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
 147
 148         /* Get the address for the gart region.
 149          * This is a bus address even on the alpha, b/c its
 150          * used to program the agp master not the cpu
 151          */
 152
 153         pci_read_config_dword(agp_bridge->dev, AMD_APBASE, &temp);
 154         addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 155         agp_bridge->gart_bus_addr = addr;
 156
 157         /* Calculate the agp offset */
 158         for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
 159                 page_dir.remapped[GET_PAGE_DIR_OFF(addr)] =
 160                         virt_to_phys(amd_irongate_private.gatt_pages[i]->real);
 161                 page_dir.remapped[GET_PAGE_DIR_OFF(addr)] |= 0x00000001;
 162         }
 163
 164         return 0;
 165 }
 166
 167 static int amd_free_gatt_table(void)
 168 {
 169         struct amd_page_map page_dir;
 170
 171         page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
 172         page_dir.remapped = (unsigned long *)agp_bridge->gatt_table;
 173
 174         amd_free_gatt_pages();
 175         amd_free_page_map(&page_dir);
 176         return 0;
 177 }
 178
 179 static int amd_irongate_fetch_size(void)
 180 {
 181         int i;
 182         u32 temp;
 183         struct aper_size_info_lvl2 *values;
 184
 185         pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
 186         temp = (temp & 0x0000000e);
 187         values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
 188         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 189                 if (temp == values[i].size_value) {
 190                         agp_bridge->previous_size =
 191                             agp_bridge->current_size = (void *) (values + i);
 192
 193                         agp_bridge->aperture_size_idx = i;
 194                         return values[i].size;
 195                 }
 196         }
 197
 198         return 0;
 199 }
 200
 201 static int amd_irongate_configure(void)
 202 {
 203         struct aper_size_info_lvl2 *current_size;
 204         u32 temp;
 205         u16 enable_reg;
 206
 207         current_size = A_SIZE_LVL2(agp_bridge->current_size);
 208
 209         /* Get the memory mapped registers */
 210         pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
 211         temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 212         amd_irongate_private.registers = (volatile u8 *) ioremap(temp, 4096);
 213
 214         /* Write out the address of the gatt table */
 215         OUTREG32(amd_irongate_private.registers, AMD_ATTBASE,
 216                  agp_bridge->gatt_bus_addr);
 217
 218         /* Write the Sync register */
 219         pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
 220
 221         /* Set indexing mode */
 222         pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
 223
 224         /* Write the enable register */
 225         enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
 226         enable_reg = (enable_reg | 0x0004);
 227         OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
 228
 229         /* Write out the size register */
 230         pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
 231         temp = (((temp & ~(0x0000000e)) | current_size->size_value)
 232                 | 0x00000001);
 233         pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
 234
 235         /* Flush the tlb */
 236         OUTREG32(amd_irongate_private.registers, AMD_TLBFLUSH, 0x00000001);
 237
 238         return 0;
 239 }
 240
 241 static void amd_irongate_cleanup(void)
 242 {
 243         struct aper_size_info_lvl2 *previous_size;
 244         u32 temp;
 245         u16 enable_reg;
 246
 247         previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
 248
 249         enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
 250         enable_reg = (enable_reg & ~(0x0004));
 251         OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
 252
 253         /* Write back the previous size and disable gart translation */
 254         pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
 255         temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
 256         pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
 257         iounmap((void *) amd_irongate_private.registers);
 258 }
 259
 260 /*
 261  * This routine could be implemented by taking the addresses
 262  * written to the GATT, and flushing them individually.  However
 263  * currently it just flushes the whole table.  Which is probably
 264  * more efficent, since agp_memory blocks can be a large number of
 265  * entries.
 266  */
 267
 268 static void amd_irongate_tlbflush(struct agp_memory *temp)
 269 {
 270         OUTREG32(amd_irongate_private.registers, AMD_TLBFLUSH, 0x00000001);
 271 }
 272
 273 static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
 274 {
 275         int i, j, num_entries;
 276         unsigned long *cur_gatt;
 277         unsigned long addr;
 278
 279         num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
 280
 281         if (type != 0 || mem->type != 0)
 282                 return -EINVAL;
 283
 284         if ((pg_start + mem->page_count) > num_entries)
 285                 return -EINVAL;
 286
 287         j = pg_start;
 288         while (j < (pg_start + mem->page_count)) {
 289                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 290                 cur_gatt = GET_GATT(addr);
 291                 if (!PGE_EMPTY(agp_bridge, cur_gatt[GET_GATT_OFF(addr)]))
 292                         return -EBUSY;
 293                 j++;
 294         }
 295
 296         if (mem->is_flushed == FALSE) {
 297                 global_cache_flush();
 298                 mem->is_flushed = TRUE;
 299         }
 300
 301         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 302                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 303                 cur_gatt = GET_GATT(addr);
 304                 cur_gatt[GET_GATT_OFF(addr)] =
 305                         agp_generic_mask_memory(mem->memory[i], mem->type);
 306         }
 307         amd_irongate_tlbflush(mem);
 308         return 0;
 309 }
 310
 311 static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
 312 {
 313         int i;
 314         unsigned long *cur_gatt;
 315         unsigned long addr;
 316
 317         if (type != 0 || mem->type != 0)
 318                 return -EINVAL;
 319
 320         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 321                 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 322                 cur_gatt = GET_GATT(addr);
 323                 cur_gatt[GET_GATT_OFF(addr)] =
 324                         (unsigned long) agp_bridge->scratch_page;
 325         }
 326
 327         amd_irongate_tlbflush(mem);
 328         return 0;
 329 }
 330
 331 static struct aper_size_info_lvl2 amd_irongate_sizes[7] =
 332 {
 333         {2048, 524288, 0x0000000c},
 334         {1024, 262144, 0x0000000a},
 335         {512, 131072, 0x00000008},
 336         {256, 65536, 0x00000006},
 337         {128, 32768, 0x00000004},
 338         {64, 16384, 0x00000002},
 339         {32, 8192, 0x00000000}
 340 };
 341
 342 static struct gatt_mask amd_irongate_masks[] =
 343 {
 344         {.mask = 1, .type = 0}
 345 };
 346
 347 struct agp_bridge_driver amd_irongate_driver = {
 348         .owner                  = THIS_MODULE,
 349         .aperture_sizes         = amd_irongate_sizes,
 350         .size_type              = LVL2_APER_SIZE,
 351         .num_aperture_sizes     = 7,
 352         .configure              = amd_irongate_configure,
 353         .fetch_size             = amd_irongate_fetch_size,
 354         .cleanup                = amd_irongate_cleanup,
 355         .tlb_flush              = amd_irongate_tlbflush,
 356         .mask_memory            = agp_generic_mask_memory,
 357         .masks                  = amd_irongate_masks,
 358         .agp_enable             = agp_generic_enable,
 359         .cache_flush            = global_cache_flush,
 360         .create_gatt_table      = amd_create_gatt_table,
 361         .free_gatt_table        = amd_free_gatt_table,
 362         .insert_memory          = amd_insert_memory,
 363         .remove_memory          = amd_remove_memory,
 364         .alloc_by_type          = agp_generic_alloc_by_type,
 365         .free_by_type           = agp_generic_free_by_type,
 366         .agp_alloc_page         = agp_generic_alloc_page,
 367         .agp_destroy_page       = agp_generic_destroy_page,
 368 };
 369
 370 struct agp_device_ids amd_agp_device_ids[] __initdata =
 371 {
 372         {
 373                 .device_id      = PCI_DEVICE_ID_AMD_FE_GATE_7006,
 374                 .chipset_name   = "Irongate",
 375         },
 376         {
 377                 .device_id      = PCI_DEVICE_ID_AMD_FE_GATE_700E,
 378                 .chipset_name   = "761",
 379         },
 380         {
 381                 .device_id      = PCI_DEVICE_ID_AMD_FE_GATE_700C,
 382                 .chipset_name   = "760MP",
 383         },
 384         { }, /* dummy final entry, always present */
 385 };
 386
 387 static int __init agp_amdk7_probe(struct pci_dev *pdev,
 388                                   const struct pci_device_id *ent)
 389 {
 390         struct agp_device_ids *devs = amd_agp_device_ids;
 391         struct agp_bridge_data *bridge;
 392         u8 cap_ptr;
 393         int j;
 394
 395         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 396         if (!cap_ptr)
 397                 return -ENODEV;
 398
 399         for (j = 0; devs[j].chipset_name; j++) {
 400                 if (pdev->device == devs[j].device_id) {
 401                         printk (KERN_INFO PFX "Detected AMD %s chipset\n",
 402                                         devs[j].chipset_name);
 403                         goto found;
 404                 }
 405         }
 406
 407         if (!agp_try_unsupported) {
 408                 printk(KERN_ERR PFX
 409                     "Unsupported AMD chipset (device id: %04x),"
 410                     " you might want to try agp_try_unsupported=1.\n",
 411                     pdev->device);
 412                 return -ENODEV;
 413         }
 414
 415         printk(KERN_WARNING PFX "Trying generic AMD routines"
 416                " for device id: %04x\n", pdev->device);
 417
 418 found:
 419         bridge = agp_alloc_bridge();
 420         if (!bridge)
 421                 return -ENOMEM;
 422
 423         bridge->driver = &amd_irongate_driver;
 424         bridge->dev_private_data = &amd_irongate_private,
 425         bridge->dev = pdev;
 426         bridge->capndx = cap_ptr;
 427
 428         /* Fill in the mode register */
 429         pci_read_config_dword(pdev,
 430                         bridge->capndx+PCI_AGP_STATUS,
 431                         &bridge->mode);
 432
 433         pci_set_drvdata(pdev, bridge);
 434         return agp_add_bridge(bridge);
 435 }
 436
 437 static void __devexit agp_amdk7_remove(struct pci_dev *pdev)
 438 {
 439         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 440
 441         agp_remove_bridge(bridge);
 442         agp_put_bridge(bridge);
 443 }
 444
 445 static struct pci_device_id agp_amdk7_pci_table[] = {
 446         {
 447         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 448         .class_mask     = ~0,
 449         .vendor         = PCI_VENDOR_ID_AMD,
 450         .device         = PCI_ANY_ID,
 451         .subvendor      = PCI_ANY_ID,
 452         .subdevice      = PCI_ANY_ID,
 453         },
 454         { }
 455 };
 456
 457 MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table);
 458
 459 static struct pci_driver agp_amdk7_pci_driver = {
 460         .name           = "agpgart-amdk7",
 461         .id_table       = agp_amdk7_pci_table,
 462         .probe          = agp_amdk7_probe,
 463         .remove         = agp_amdk7_remove,
 464 };
 465
 466 static int __init agp_amdk7_init(void)
 467 {
 468         return pci_module_init(&agp_amdk7_pci_driver);
 469 }
 470
 471 static void __exit agp_amdk7_cleanup(void)
 472 {
 473         pci_unregister_driver(&agp_amdk7_pci_driver);
 474 }
 475
 476 module_init(agp_amdk7_init);
 477 module_exit(agp_amdk7_cleanup);
 478
 479 MODULE_PARM(agp_try_unsupported, "1i");
 480 MODULE_LICENSE("GPL and additional rights");