1 /* arch/sh/kernel/pci.c
2 * $Id: pci.c,v 1.4 2003/05/25 01:29:24 lethal Exp $
4 * Copyright (c) 2002 M. R. Brown <mrbrown@linux-sh.org>
7 * These functions are collected here to reduce duplication of common
8 * code amongst the many platform-specific PCI support code files.
10 * These routines require the following board-specific routines:
11 * void pcibios_fixup();
12 * void pcibios_fixup_irqs();
14 * See include/asm-sh/pci.h for more information.
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
21 static int __init pcibios_init(void)
23 struct pci_channel *p;
27 #ifdef CONFIG_PCI_AUTO
28 /* assign resources */
30 for (p = board_pci_channels; p->pci_ops != NULL; p++) {
31 busno = pciauto_assign_resources(busno, p) + 1;
37 for (p= board_pci_channels; p->pci_ops != NULL; p++) {
38 bus = pci_scan_bus(busno, p->pci_ops, p);
39 busno = bus->subordinate+1;
42 /* board-specific fixups */
49 subsys_initcall(pcibios_init);
52 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
53 struct resource *res, int resource)
58 new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
60 reg = PCI_BASE_ADDRESS_0 + 4*resource;
61 } else if (resource == PCI_ROM_RESOURCE) {
62 res->flags |= PCI_ROM_ADDRESS_ENABLE;
63 new |= PCI_ROM_ADDRESS_ENABLE;
64 reg = dev->rom_base_reg;
66 /* Somebody might have asked allocation of a non-standard resource */
70 pci_write_config_dword(dev, reg, new);
71 pci_read_config_dword(dev, reg, &check);
72 if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
73 printk(KERN_ERR "PCI: Error while updating region "
74 "%s/%d (%08x != %08x)\n", pci_name(dev), resource,
79 void pcibios_align_resource(void *data, struct resource *res,
80 unsigned long size, unsigned long align)
81 __attribute__ ((weak));
84 * We need to avoid collisions with `mirrored' VGA ports
85 * and other strange ISA hardware, so we always want the
86 * addresses to be allocated in the 0x000-0x0ff region
89 void pcibios_align_resource(void *data, struct resource *res,
90 unsigned long size, unsigned long align)
92 if (res->flags & IORESOURCE_IO) {
93 unsigned long start = res->start;
96 start = (start + 0x3ff) & ~0x3ff;
102 int pcibios_enable_device(struct pci_dev *dev, int mask)
108 pci_read_config_word(dev, PCI_COMMAND, &cmd);
110 for(idx=0; idx<6; idx++) {
111 r = &dev->resource[idx];
112 if (!r->start && r->end) {
113 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
116 if (r->flags & IORESOURCE_IO)
117 cmd |= PCI_COMMAND_IO;
118 if (r->flags & IORESOURCE_MEM)
119 cmd |= PCI_COMMAND_MEMORY;
121 if (dev->resource[PCI_ROM_RESOURCE].start)
122 cmd |= PCI_COMMAND_MEMORY;
123 if (cmd != old_cmd) {
124 printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n", dev->dev.name, old_cmd, cmd);
125 pci_write_config_word(dev, PCI_COMMAND, cmd);
131 * If we set up a device for bus mastering, we need to check and set
132 * the latency timer as it may not be properly set.
134 unsigned int pcibios_max_latency = 255;
136 void pcibios_set_master(struct pci_dev *dev)
139 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
141 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
142 else if (lat > pcibios_max_latency)
143 lat = pcibios_max_latency;
146 printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n", dev->dev.name, lat);
147 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
150 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
152 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);