arch/mips/math-emu/cp1emu.c

   1 /*
   2  * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
   3  *
   4  * MIPS floating point support
   5  * Copyright (C) 1994-2000 Algorithmics Ltd.  All rights reserved.
   6  * http://www.algor.co.uk
   7  *
   8  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   9  * Copyright (C) 2000  MIPS Technologies, Inc.
  10  *
  11  *  This program is free software; you can distribute it and/or modify it
  12  *  under the terms of the GNU General Public License (Version 2) as
  13  *  published by the Free Software Foundation.
  14  *
  15  *  This program is distributed in the hope it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  18  *  for more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License along
  21  *  with this program; if not, write to the Free Software Foundation, Inc.,
  22  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  23  *
  24  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  25  * required for #float(switch) or #float(trap), where it catches all
  26  * COP1 instructions via the "CoProcessor Unusable" exception.
  27  *
  28  * More surprisingly it is also required for #float(ieee), to help out
  29  * the hardware fpu at the boundaries of the IEEE-754 representation
  30  * (denormalised values, infinities, underflow, etc).  It is made
  31  * quite nasty because emulation of some non-COP1 instructions is
  32  * required, e.g. in branch delay slots.
  33  *
  34  * Note if you know that you won't have an fpu, then you'll get much
  35  * better performance by compiling with -msoft-float!
  36  */
  37 #include <linux/sched.h>
  38
  39 #include <asm/inst.h>
  40 #include <asm/bootinfo.h>
  41 #include <asm/cpu.h>
  42 #include <asm/processor.h>
  43 #include <asm/ptrace.h>
  44 #include <asm/signal.h>
  45 #include <asm/mipsregs.h>
  46 #include <asm/fpu_emulator.h>
  47 #include <asm/uaccess.h>
  48 #include <asm/branch.h>
  49
  50 #include "ieee754.h"
  51 #include "dsemul.h"
  52
  53 /* Strap kernel emulator for full MIPS IV emulation */
  54
  55 #ifdef __mips
  56 #undef __mips
  57 #endif
  58 #define __mips 4
  59
  60 /* Function which emulates a floating point instruction. */
  61
  62 static int fpu_emu(struct pt_regs *, struct mips_fpu_soft_struct *,
  63         mips_instruction);
  64
  65 #if __mips >= 4 && __mips != 32
  66 static int fpux_emu(struct pt_regs *,
  67         struct mips_fpu_soft_struct *, mips_instruction);
  68 #endif
  69
  70 /* Further private data for which no space exists in mips_fpu_soft_struct */
  71
  72 struct mips_fpu_emulator_private fpuemuprivate;
  73
  74 /* Control registers */
  75
  76 #define FPCREG_RID      0       /* $0  = revision id */
  77 #define FPCREG_CSR      31      /* $31 = csr */
  78
  79 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
  80 static const unsigned char ieee_rm[4] = {
  81         IEEE754_RN, IEEE754_RZ, IEEE754_RU, IEEE754_RD
  82 };
  83
  84 #if __mips >= 4
  85 /* convert condition code register number to csr bit */
  86 static const unsigned int fpucondbit[8] = {
  87         FPU_CSR_COND0,
  88         FPU_CSR_COND1,
  89         FPU_CSR_COND2,
  90         FPU_CSR_COND3,
  91         FPU_CSR_COND4,
  92         FPU_CSR_COND5,
  93         FPU_CSR_COND6,
  94         FPU_CSR_COND7
  95 };
  96 #endif
  97
  98
  99 /*
 100  * Redundant with logic already in kernel/branch.c,
 101  * embedded in compute_return_epc.  At some point,
 102  * a single subroutine should be used across both
 103  * modules.
 104  */
 105 static int isBranchInstr(mips_instruction * i)
 106 {
 107         switch (MIPSInst_OPCODE(*i)) {
 108         case spec_op:
 109                 switch (MIPSInst_FUNC(*i)) {
 110                 case jalr_op:
 111                 case jr_op:
 112                         return 1;
 113                 }
 114                 break;
 115
 116         case bcond_op:
 117                 switch (MIPSInst_RT(*i)) {
 118                 case bltz_op:
 119                 case bgez_op:
 120                 case bltzl_op:
 121                 case bgezl_op:
 122                 case bltzal_op:
 123                 case bgezal_op:
 124                 case bltzall_op:
 125                 case bgezall_op:
 126                         return 1;
 127                 }
 128                 break;
 129
 130         case j_op:
 131         case jal_op:
 132         case jalx_op:
 133         case beq_op:
 134         case bne_op:
 135         case blez_op:
 136         case bgtz_op:
 137         case beql_op:
 138         case bnel_op:
 139         case blezl_op:
 140         case bgtzl_op:
 141                 return 1;
 142
 143         case cop0_op:
 144         case cop1_op:
 145         case cop2_op:
 146         case cop1x_op:
 147                 if (MIPSInst_RS(*i) == bc_op)
 148                         return 1;
 149                 break;
 150         }
 151
 152         return 0;
 153 }
 154
 155 /*
 156  * In the Linux kernel, we support selection of FPR format on the
 157  * basis of the Status.FR bit.  This does imply that, if a full 32
 158  * FPRs are desired, there needs to be a flip-flop that can be written
 159  * to one at that bit position.  In any case, O32 MIPS ABI uses
 160  * only the even FPRs (Status.FR = 0).
 161  */
 162
 163 #define CP0_STATUS_FR_SUPPORT
 164
 165 #ifdef CP0_STATUS_FR_SUPPORT
 166 #define FR_BIT ST0_FR
 167 #else
 168 #define FR_BIT 0
 169 #endif
 170
 171 #define SIFROMREG(si,x) ((si) = \
 172                         (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
 173                         (int)ctx->fpr[x] : \
 174                         (int)(ctx->fpr[x & ~1] >> 32 ))
 175 #define SITOREG(si,x)   (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \
 176                         (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
 177                         ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
 178                         ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
 179
 180 #define DIFROMREG(di,x) ((di) = \
 181                         ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)])
 182 #define DITOREG(di,x)   (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] \
 183                         = (di))
 184
 185 #define SPFROMREG(sp,x) SIFROMREG((sp).bits,x)
 186 #define SPTOREG(sp,x)   SITOREG((sp).bits,x)
 187 #define DPFROMREG(dp,x) DIFROMREG((dp).bits,x)
 188 #define DPTOREG(dp,x)   DITOREG((dp).bits,x)
 189
 190 /*
 191  * Emulate the single floating point instruction pointed at by EPC.
 192  * Two instructions if the instruction is in a branch delay slot.
 193  */
 194
 195 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
 196 {
 197         mips_instruction ir;
 198         vaddr_t emulpc, contpc;
 199         unsigned int cond;
 200
 201         if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) {
 202                 fpuemuprivate.stats.errors++;
 203                 return SIGBUS;
 204         }
 205
 206         /* XXX NEC Vr54xx bug workaround */
 207         if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir))
 208                 xcp->cp0_cause &= ~CAUSEF_BD;
 209
 210         if (xcp->cp0_cause & CAUSEF_BD) {
 211                 /*
 212                  * The instruction to be emulated is in a branch delay slot
 213                  * which means that we have to  emulate the branch instruction
 214                  * BEFORE we do the cop1 instruction.
 215                  *
 216                  * This branch could be a COP1 branch, but in that case we
 217                  * would have had a trap for that instruction, and would not
 218                  * come through this route.
 219                  *
 220                  * Linux MIPS branch emulator operates on context, updating the
 221                  * cp0_epc.
 222                  */
 223                 emulpc = REG_TO_VA(xcp->cp0_epc + 4);   /* Snapshot emulation target */
 224
 225                 if (__compute_return_epc(xcp)) {
 226 #ifdef CP1DBG
 227                         printk("failed to emulate branch at %p\n",
 228                                 REG_TO_VA(xcp->cp0_epc));
 229 #endif
 230                         return SIGILL;
 231                 }
 232                 if (get_user(ir, (mips_instruction *) emulpc)) {
 233                         fpuemuprivate.stats.errors++;
 234                         return SIGBUS;
 235                 }
 236                 /* __computer_return_epc() will have updated cp0_epc */
 237                 contpc = REG_TO_VA xcp->cp0_epc;
 238                 /* In order not to confuse ptrace() et al, tweak context */
 239                 xcp->cp0_epc = VA_TO_REG emulpc - 4;
 240         }
 241         else {
 242                 emulpc = REG_TO_VA xcp->cp0_epc;
 243                 contpc = REG_TO_VA(xcp->cp0_epc + 4);
 244         }
 245
 246       emul:
 247         fpuemuprivate.stats.emulated++;
 248         switch (MIPSInst_OPCODE(ir)) {
 249 #ifndef SINGLE_ONLY_FPU
 250         case ldc1_op:{
 251                 u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
 252                         MIPSInst_SIMM(ir));
 253                 u64 val;
 254
 255                 fpuemuprivate.stats.loads++;
 256                 if (get_user(val, va)) {
 257                         fpuemuprivate.stats.errors++;
 258                         return SIGBUS;
 259                 }
 260                 DITOREG(val, MIPSInst_RT(ir));
 261                 break;
 262         }
 263
 264         case sdc1_op:{
 265                 u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
 266                         MIPSInst_SIMM(ir));
 267                 u64 val;
 268
 269                 fpuemuprivate.stats.stores++;
 270                 DIFROMREG(val, MIPSInst_RT(ir));
 271                 if (put_user(val, va)) {
 272                         fpuemuprivate.stats.errors++;
 273                         return SIGBUS;
 274                 }
 275                 break;
 276         }
 277 #endif
 278
 279         case lwc1_op:{
 280                 u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
 281                         MIPSInst_SIMM(ir));
 282                 u32 val;
 283
 284                 fpuemuprivate.stats.loads++;
 285                 if (get_user(val, va)) {
 286                         fpuemuprivate.stats.errors++;
 287                         return SIGBUS;
 288                 }
 289 #ifdef SINGLE_ONLY_FPU
 290                 if (MIPSInst_RT(ir) & 1) {
 291                         /* illegal register in single-float mode */
 292                         return SIGILL;
 293                 }
 294 #endif
 295                 SITOREG(val, MIPSInst_RT(ir));
 296                 break;
 297         }
 298
 299         case swc1_op:{
 300                 u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
 301                         MIPSInst_SIMM(ir));
 302                 u32 val;
 303
 304                 fpuemuprivate.stats.stores++;
 305 #ifdef SINGLE_ONLY_FPU
 306                 if (MIPSInst_RT(ir) & 1) {
 307                         /* illegal register in single-float mode */
 308                         return SIGILL;
 309                 }
 310 #endif
 311                 SIFROMREG(val, MIPSInst_RT(ir));
 312                 if (put_user(val, va)) {
 313                         fpuemuprivate.stats.errors++;
 314                         return SIGBUS;
 315                 }
 316                 break;
 317         }
 318
 319         case cop1_op:
 320                 switch (MIPSInst_RS(ir)) {
 321
 322 #if __mips64 && !defined(SINGLE_ONLY_FPU)
 323                 case dmfc_op:
 324                         /* copregister fs -> gpr[rt] */
 325                         if (MIPSInst_RT(ir) != 0) {
 326                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
 327                                         MIPSInst_RD(ir));
 328                         }
 329                         break;
 330
 331                 case dmtc_op:
 332                         /* copregister fs <- rt */
 333                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 334                         break;
 335 #endif
 336
 337                 case mfc_op:
 338                         /* copregister rd -> gpr[rt] */
 339 #ifdef SINGLE_ONLY_FPU
 340                         if (MIPSInst_RD(ir) & 1) {
 341                                 /* illegal register in single-float mode */
 342                                 return SIGILL;
 343                         }
 344 #endif
 345                         if (MIPSInst_RT(ir) != 0) {
 346                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
 347                                         MIPSInst_RD(ir));
 348                         }
 349                         break;
 350
 351                 case mtc_op:
 352                         /* copregister rd <- rt */
 353 #ifdef SINGLE_ONLY_FPU
 354                         if (MIPSInst_RD(ir) & 1) {
 355                                 /* illegal register in single-float mode */
 356                                 return SIGILL;
 357                         }
 358 #endif
 359                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 360                         break;
 361
 362                 case cfc_op:{
 363                         /* cop control register rd -> gpr[rt] */
 364                         u32 value;
 365
 366                         if (ir == CP1UNDEF) {
 367                                 return do_dsemulret(xcp);
 368                         }
 369                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
 370                                 value = ctx->fcr31;
 371 #ifdef CSRTRACE
 372                                 printk("%p gpr[%d]<-csr=%08x\n",
 373                                         REG_TO_VA(xcp->cp0_epc),
 374                                         MIPSInst_RT(ir), value);
 375 #endif
 376                         }
 377                         else if (MIPSInst_RD(ir) == FPCREG_RID)
 378                                 value = 0;
 379                         else
 380                                 value = 0;
 381                         if (MIPSInst_RT(ir))
 382                                 xcp->regs[MIPSInst_RT(ir)] = value;
 383                         break;
 384                 }
 385
 386                 case ctc_op:{
 387                         /* copregister rd <- rt */
 388                         u32 value;
 389
 390                         if (MIPSInst_RT(ir) == 0)
 391                                 value = 0;
 392                         else
 393                                 value = xcp->regs[MIPSInst_RT(ir)];
 394
 395                         /* we only have one writable control reg
 396                          */
 397                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
 398 #ifdef CSRTRACE
 399                                 printk("%p gpr[%d]->csr=%08x\n",
 400                                         REG_TO_VA(xcp->cp0_epc),
 401                                         MIPSInst_RT(ir), value);
 402 #endif
 403                                 ctx->fcr31 = value;
 404                                 /* copy new rounding mode and
 405                                    flush bit to ieee library state! */
 406                                 ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0;
 407                                 ieee754_csr.rm = ieee_rm[value & 0x3];
 408                         }
 409                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
 410                                 return SIGFPE;
 411                         }
 412                         break;
 413                 }
 414
 415                 case bc_op:{
 416                         int likely = 0;
 417
 418                         if (xcp->cp0_cause & CAUSEF_BD)
 419                                 return SIGILL;
 420
 421 #if __mips >= 4
 422                         cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
 423 #else
 424                         cond = ctx->fcr31 & FPU_CSR_COND;
 425 #endif
 426                         switch (MIPSInst_RT(ir) & 3) {
 427                         case bcfl_op:
 428                                 likely = 1;
 429                         case bcf_op:
 430                                 cond = !cond;
 431                                 break;
 432                         case bctl_op:
 433                                 likely = 1;
 434                         case bct_op:
 435                                 break;
 436                         default:
 437                                 /* thats an illegal instruction */
 438                                 return SIGILL;
 439                         }
 440
 441                         xcp->cp0_cause |= CAUSEF_BD;
 442                         if (cond) {
 443                                 /* branch taken: emulate dslot
 444                                  * instruction
 445                                  */
 446                                 xcp->cp0_epc += 4;
 447                                 contpc = REG_TO_VA
 448                                         (xcp->cp0_epc +
 449                                         (MIPSInst_SIMM(ir) << 2));
 450
 451                                 if (get_user(ir, (mips_instruction *)
 452                                                 REG_TO_VA xcp->cp0_epc)) {
 453                                         fpuemuprivate.stats.errors++;
 454                                         return SIGBUS;
 455                                 }
 456
 457                                 switch (MIPSInst_OPCODE(ir)) {
 458                                 case lwc1_op:
 459                                 case swc1_op:
 460 #if (__mips >= 2 || __mips64) && !defined(SINGLE_ONLY_FPU)
 461                                 case ldc1_op:
 462                                 case sdc1_op:
 463 #endif
 464                                 case cop1_op:
 465 #if __mips >= 4 && __mips != 32
 466                                 case cop1x_op:
 467 #endif
 468                                         /* its one of ours */
 469                                         goto emul;
 470 #if __mips >= 4
 471                                 case spec_op:
 472                                         if (MIPSInst_FUNC(ir) == movc_op)
 473                                                 goto emul;
 474                                         break;
 475 #endif
 476                                 }
 477
 478                                 /*
 479                                  * Single step the non-cp1
 480                                  * instruction in the dslot
 481                                  */
 482                                 return mips_dsemul(xcp, ir, VA_TO_REG contpc);
 483                         }
 484                         else {
 485                                 /* branch not taken */
 486                                 if (likely) {
 487                                         /*
 488                                          * branch likely nullifies
 489                                          * dslot if not taken
 490                                          */
 491                                         xcp->cp0_epc += 4;
 492                                         contpc += 4;
 493                                         /*
 494                                          * else continue & execute
 495                                          * dslot as normal insn
 496                                          */
 497                                 }
 498                         }
 499                         break;
 500                 }
 501
 502                 default:
 503                         if (!(MIPSInst_RS(ir) & 0x10))
 504                                 return SIGILL;
 505                         {
 506                                 int sig;
 507
 508                                 /* a real fpu computation instruction */
 509                                 if ((sig = fpu_emu(xcp, ctx, ir)))
 510                                         return sig;
 511                         }
 512                 }
 513                 break;
 514
 515 #if __mips >= 4 && __mips != 32
 516         case cop1x_op:{
 517                 int sig;
 518
 519                 if ((sig = fpux_emu(xcp, ctx, ir)))
 520                         return sig;
 521                 break;
 522         }
 523 #endif
 524
 525 #if __mips >= 4
 526         case spec_op:
 527                 if (MIPSInst_FUNC(ir) != movc_op)
 528                         return SIGILL;
 529                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
 530                 if (((ctx->fcr31 & cond) != 0) != ((MIPSInst_RT(ir) & 1) != 0))
 531                         return 0;
 532                 xcp->regs[MIPSInst_RD(ir)] = xcp->regs[MIPSInst_RS(ir)];
 533                 break;
 534 #endif
 535
 536         default:
 537                 return SIGILL;
 538         }
 539
 540         /* we did it !! */
 541         xcp->cp0_epc = VA_TO_REG(contpc);
 542         xcp->cp0_cause &= ~CAUSEF_BD;
 543         return 0;
 544 }
 545
 546 /*
 547  * Conversion table from MIPS compare ops 48-63
 548  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
 549  */
 550 static const unsigned char cmptab[8] = {
 551         0,                      /* cmp_0 (sig) cmp_sf */
 552         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
 553         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
 554         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
 555         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
 556         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
 557         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
 558         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
 559 };
 560
 561
 562 #if __mips >= 4 && __mips != 32
 563
 564 /*
 565  * Additional MIPS4 instructions
 566  */
 567
 568 #define DEF3OP(name, p, f1, f2, f3) \
 569 static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \
 570     ieee754##p t) \
 571 { \
 572         struct ieee754_csr ieee754_csr_save; \
 573         s = f1 (s, t); \
 574         ieee754_csr_save = ieee754_csr; \
 575         s = f2 (s, r); \
 576         ieee754_csr_save.cx |= ieee754_csr.cx; \
 577         ieee754_csr_save.sx |= ieee754_csr.sx; \
 578         s = f3 (s); \
 579         ieee754_csr.cx |= ieee754_csr_save.cx; \
 580         ieee754_csr.sx |= ieee754_csr_save.sx; \
 581         return s; \
 582 }
 583
 584 static ieee754dp fpemu_dp_recip(ieee754dp d)
 585 {
 586         return ieee754dp_div(ieee754dp_one(0), d);
 587 }
 588
 589 static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
 590 {
 591         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
 592 }
 593
 594 static ieee754sp fpemu_sp_recip(ieee754sp s)
 595 {
 596         return ieee754sp_div(ieee754sp_one(0), s);
 597 }
 598
 599 static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
 600 {
 601         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
 602 }
 603
 604 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add,);
 605 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub,);
 606 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
 607 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
 608 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add,);
 609 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub,);
 610 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
 611 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
 612
 613 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
 614         mips_instruction ir)
 615 {
 616         unsigned rcsr = 0;      /* resulting csr */
 617
 618         fpuemuprivate.stats.cp1xops++;
 619
 620         switch (MIPSInst_FMA_FFMT(ir)) {
 621         case s_fmt:{            /* 0 */
 622
 623                 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
 624                 ieee754sp fd, fr, fs, ft;
 625                 u32 *va;
 626                 u32 val;
 627
 628                 switch (MIPSInst_FUNC(ir)) {
 629                 case lwxc1_op:
 630                         va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
 631                                 xcp->regs[MIPSInst_FT(ir)]);
 632
 633                         fpuemuprivate.stats.loads++;
 634                         if (get_user(val, va)) {
 635                                 fpuemuprivate.stats.errors++;
 636                                 return SIGBUS;
 637                         }
 638 #ifdef SINGLE_ONLY_FPU
 639                         if (MIPSInst_FD(ir) & 1) {
 640                                 /* illegal register in single-float
 641                                  * mode
 642                                  */
 643                                 return SIGILL;
 644                         }
 645 #endif
 646                         SITOREG(val, MIPSInst_FD(ir));
 647                         break;
 648
 649                 case swxc1_op:
 650                         va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
 651                                 xcp->regs[MIPSInst_FT(ir)]);
 652
 653                         fpuemuprivate.stats.stores++;
 654 #ifdef SINGLE_ONLY_FPU
 655                         if (MIPSInst_FS(ir) & 1) {
 656                                 /* illegal register in single-float
 657                                  * mode
 658                                  */
 659                                 return SIGILL;
 660                         }
 661 #endif
 662
 663                         SIFROMREG(val, MIPSInst_FS(ir));
 664                         if (put_user(val, va)) {
 665                                 fpuemuprivate.stats.errors++;
 666                                 return SIGBUS;
 667                         }
 668                         break;
 669
 670                 case madd_s_op:
 671                         handler = fpemu_sp_madd;
 672                         goto scoptop;
 673                 case msub_s_op:
 674                         handler = fpemu_sp_msub;
 675                         goto scoptop;
 676                 case nmadd_s_op:
 677                         handler = fpemu_sp_nmadd;
 678                         goto scoptop;
 679                 case nmsub_s_op:
 680                         handler = fpemu_sp_nmsub;
 681                         goto scoptop;
 682
 683                       scoptop:
 684                         SPFROMREG(fr, MIPSInst_FR(ir));
 685                         SPFROMREG(fs, MIPSInst_FS(ir));
 686                         SPFROMREG(ft, MIPSInst_FT(ir));
 687                         fd = (*handler) (fr, fs, ft);
 688                         SPTOREG(fd, MIPSInst_FD(ir));
 689
 690                       copcsr:
 691                         if (ieee754_cxtest(IEEE754_INEXACT))
 692                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
 693                         if (ieee754_cxtest(IEEE754_UNDERFLOW))
 694                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
 695                         if (ieee754_cxtest(IEEE754_OVERFLOW))
 696                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
 697                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
 698                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
 699
 700                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
 701                         if (ieee754_csr.nod)
 702                                 ctx->fcr31 |= 0x1000000;
 703                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
 704                                 /*printk ("SIGFPE: fpu csr = %08x\n",
 705                                    ctx->fcr31); */
 706                                 return SIGFPE;
 707                         }
 708
 709                         break;
 710
 711                 default:
 712                         return SIGILL;
 713                 }
 714                 break;
 715         }
 716
 717 #ifndef SINGLE_ONLY_FPU
 718         case d_fmt:{            /* 1 */
 719                 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
 720                 ieee754dp fd, fr, fs, ft;
 721                 u64 *va;
 722                 u64 val;
 723
 724                 switch (MIPSInst_FUNC(ir)) {
 725                 case ldxc1_op:
 726                         va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
 727                                 xcp->regs[MIPSInst_FT(ir)]);
 728
 729                         fpuemuprivate.stats.loads++;
 730                         if (get_user(val, va)) {
 731                                 fpuemuprivate.stats.errors++;
 732                                 return SIGBUS;
 733                         }
 734                         DITOREG(val, MIPSInst_FD(ir));
 735                         break;
 736
 737                 case sdxc1_op:
 738                         va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
 739                                 xcp->regs[MIPSInst_FT(ir)]);
 740
 741                         fpuemuprivate.stats.stores++;
 742                         DIFROMREG(val, MIPSInst_FS(ir));
 743                         if (put_user(val, va)) {
 744                                 fpuemuprivate.stats.errors++;
 745                                 return SIGBUS;
 746                         }
 747                         break;
 748
 749                 case madd_d_op:
 750                         handler = fpemu_dp_madd;
 751                         goto dcoptop;
 752                 case msub_d_op:
 753                         handler = fpemu_dp_msub;
 754                         goto dcoptop;
 755                 case nmadd_d_op:
 756                         handler = fpemu_dp_nmadd;
 757                         goto dcoptop;
 758                 case nmsub_d_op:
 759                         handler = fpemu_dp_nmsub;
 760                         goto dcoptop;
 761
 762                       dcoptop:
 763                         DPFROMREG(fr, MIPSInst_FR(ir));
 764                         DPFROMREG(fs, MIPSInst_FS(ir));
 765                         DPFROMREG(ft, MIPSInst_FT(ir));
 766                         fd = (*handler) (fr, fs, ft);
 767                         DPTOREG(fd, MIPSInst_FD(ir));
 768                         goto copcsr;
 769
 770                 default:
 771                         return SIGILL;
 772                 }
 773                 break;
 774         }
 775 #endif
 776
 777         case 0x7:               /* 7 */
 778                 if (MIPSInst_FUNC(ir) != pfetch_op) {
 779                         return SIGILL;
 780                 }
 781                 /* ignore prefx operation */
 782                 break;
 783
 784         default:
 785                 return SIGILL;
 786         }
 787
 788         return 0;
 789 }
 790 #endif
 791
 792
 793
 794 /*
 795  * Emulate a single COP1 arithmetic instruction.
 796  */
 797 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
 798         mips_instruction ir)
 799 {
 800         int rfmt;               /* resulting format */
 801         unsigned rcsr = 0;      /* resulting csr */
 802         unsigned cond;
 803         union {
 804                 ieee754dp d;
 805                 ieee754sp s;
 806                 int w;
 807 #if __mips64
 808                 s64 l;
 809 #endif
 810         } rv;                   /* resulting value */
 811
 812         fpuemuprivate.stats.cp1ops++;
 813         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
 814         case s_fmt:{            /* 0 */
 815                 union {
 816                         ieee754sp(*b) (ieee754sp, ieee754sp);
 817                         ieee754sp(*u) (ieee754sp);
 818                 } handler;
 819
 820                 switch (MIPSInst_FUNC(ir)) {
 821                         /* binary ops */
 822                 case fadd_op:
 823                         handler.b = ieee754sp_add;
 824                         goto scopbop;
 825                 case fsub_op:
 826                         handler.b = ieee754sp_sub;
 827                         goto scopbop;
 828                 case fmul_op:
 829                         handler.b = ieee754sp_mul;
 830                         goto scopbop;
 831                 case fdiv_op:
 832                         handler.b = ieee754sp_div;
 833                         goto scopbop;
 834
 835                         /* unary  ops */
 836 #if __mips >= 2 || __mips64
 837                 case fsqrt_op:
 838                         handler.u = ieee754sp_sqrt;
 839                         goto scopuop;
 840 #endif
 841 #if __mips >= 4 && __mips != 32
 842                 case frsqrt_op:
 843                         handler.u = fpemu_sp_rsqrt;
 844                         goto scopuop;
 845                 case frecip_op:
 846                         handler.u = fpemu_sp_recip;
 847                         goto scopuop;
 848 #endif
 849 #if __mips >= 4
 850                 case fmovc_op:
 851                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
 852                         if (((ctx->fcr31 & cond) != 0) !=
 853                                 ((MIPSInst_FT(ir) & 1) != 0))
 854                                 return 0;
 855                         SPFROMREG(rv.s, MIPSInst_FS(ir));
 856                         break;
 857                 case fmovz_op:
 858                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
 859                                 return 0;
 860                         SPFROMREG(rv.s, MIPSInst_FS(ir));
 861                         break;
 862                 case fmovn_op:
 863                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
 864                                 return 0;
 865                         SPFROMREG(rv.s, MIPSInst_FS(ir));
 866                         break;
 867 #endif
 868                 case fabs_op:
 869                         handler.u = ieee754sp_abs;
 870                         goto scopuop;
 871                 case fneg_op:
 872                         handler.u = ieee754sp_neg;
 873                         goto scopuop;
 874                 case fmov_op:
 875                         /* an easy one */
 876                         SPFROMREG(rv.s, MIPSInst_FS(ir));
 877                         goto copcsr;
 878
 879                         /* binary op on handler */
 880                       scopbop:
 881                         {
 882                                 ieee754sp fs, ft;
 883
 884                                 SPFROMREG(fs, MIPSInst_FS(ir));
 885                                 SPFROMREG(ft, MIPSInst_FT(ir));
 886
 887                                 rv.s = (*handler.b) (fs, ft);
 888                                 goto copcsr;
 889                         }
 890                       scopuop:
 891                         {
 892                                 ieee754sp fs;
 893
 894                                 SPFROMREG(fs, MIPSInst_FS(ir));
 895                                 rv.s = (*handler.u) (fs);
 896                                 goto copcsr;
 897                         }
 898                       copcsr:
 899                         if (ieee754_cxtest(IEEE754_INEXACT))
 900                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
 901                         if (ieee754_cxtest(IEEE754_UNDERFLOW))
 902                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
 903                         if (ieee754_cxtest(IEEE754_OVERFLOW))
 904                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
 905                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
 906                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
 907                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
 908                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
 909                         break;
 910
 911                         /* unary conv ops */
 912                 case fcvts_op:
 913                         return SIGILL;  /* not defined */
 914                 case fcvtd_op:{
 915 #ifdef SINGLE_ONLY_FPU
 916                         return SIGILL;  /* not defined */
 917 #else
 918                         ieee754sp fs;
 919
 920                         SPFROMREG(fs, MIPSInst_FS(ir));
 921                         rv.d = ieee754dp_fsp(fs);
 922                         rfmt = d_fmt;
 923                         goto copcsr;
 924                 }
 925 #endif
 926                 case fcvtw_op:{
 927                         ieee754sp fs;
 928
 929                         SPFROMREG(fs, MIPSInst_FS(ir));
 930                         rv.w = ieee754sp_tint(fs);
 931                         rfmt = w_fmt;
 932                         goto copcsr;
 933                 }
 934
 935 #if __mips >= 2 || __mips64
 936                 case fround_op:
 937                 case ftrunc_op:
 938                 case fceil_op:
 939                 case ffloor_op:{
 940                         unsigned int oldrm = ieee754_csr.rm;
 941                         ieee754sp fs;
 942
 943                         SPFROMREG(fs, MIPSInst_FS(ir));
 944                         ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
 945                         rv.w = ieee754sp_tint(fs);
 946                         ieee754_csr.rm = oldrm;
 947                         rfmt = w_fmt;
 948                         goto copcsr;
 949                 }
 950 #endif /* __mips >= 2 */
 951
 952 #if __mips64 && !defined(SINGLE_ONLY_FPU)
 953                 case fcvtl_op:{
 954                         ieee754sp fs;
 955
 956                         SPFROMREG(fs, MIPSInst_FS(ir));
 957                         rv.l = ieee754sp_tlong(fs);
 958                         rfmt = l_fmt;
 959                         goto copcsr;
 960                 }
 961
 962                 case froundl_op:
 963                 case ftruncl_op:
 964                 case fceill_op:
 965                 case ffloorl_op:{
 966                         unsigned int oldrm = ieee754_csr.rm;
 967                         ieee754sp fs;
 968
 969                         SPFROMREG(fs, MIPSInst_FS(ir));
 970                         ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
 971                         rv.l = ieee754sp_tlong(fs);
 972                         ieee754_csr.rm = oldrm;
 973                         rfmt = l_fmt;
 974                         goto copcsr;
 975                 }
 976 #endif /* __mips64 && !fpu(single) */
 977
 978                 default:
 979                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
 980                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
 981                                 ieee754sp fs, ft;
 982
 983                                 SPFROMREG(fs, MIPSInst_FS(ir));
 984                                 SPFROMREG(ft, MIPSInst_FT(ir));
 985                                 rv.w = ieee754sp_cmp(fs, ft,
 986                                         cmptab[cmpop & 0x7], cmpop & 0x8);
 987                                 rfmt = -1;
 988                                 if ((cmpop & 0x8) && ieee754_cxtest
 989                                         (IEEE754_INVALID_OPERATION))
 990                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
 991                                 else
 992                                         goto copcsr;
 993
 994                         }
 995                         else {
 996                                 return SIGILL;
 997                         }
 998                         break;
 999                 }
1000                 break;
1001         }
1002
1003 #ifndef SINGLE_ONLY_FPU
1004         case d_fmt:{
1005                 union {
1006                         ieee754dp(*b) (ieee754dp, ieee754dp);
1007                         ieee754dp(*u) (ieee754dp);
1008                 } handler;
1009
1010                 switch (MIPSInst_FUNC(ir)) {
1011                         /* binary ops */
1012                 case fadd_op:
1013                         handler.b = ieee754dp_add;
1014                         goto dcopbop;
1015                 case fsub_op:
1016                         handler.b = ieee754dp_sub;
1017                         goto dcopbop;
1018                 case fmul_op:
1019                         handler.b = ieee754dp_mul;
1020                         goto dcopbop;
1021                 case fdiv_op:
1022                         handler.b = ieee754dp_div;
1023                         goto dcopbop;
1024
1025                         /* unary  ops */
1026 #if __mips >= 2 || __mips64
1027                 case fsqrt_op:
1028                         handler.u = ieee754dp_sqrt;
1029                         goto dcopuop;
1030 #endif
1031 #if __mips >= 4 && __mips != 32
1032                 case frsqrt_op:
1033                         handler.u = fpemu_dp_rsqrt;
1034                         goto dcopuop;
1035                 case frecip_op:
1036                         handler.u = fpemu_dp_recip;
1037                         goto dcopuop;
1038 #endif
1039 #if __mips >= 4
1040                 case fmovc_op:
1041                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1042                         if (((ctx->fcr31 & cond) != 0) !=
1043                                 ((MIPSInst_FT(ir) & 1) != 0))
1044                                 return 0;
1045                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1046                         break;
1047                 case fmovz_op:
1048                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1049                                 return 0;
1050                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1051                         break;
1052                 case fmovn_op:
1053                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1054                                 return 0;
1055                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1056                         break;
1057 #endif
1058                 case fabs_op:
1059                         handler.u = ieee754dp_abs;
1060                         goto dcopuop;
1061
1062                 case fneg_op:
1063                         handler.u = ieee754dp_neg;
1064                         goto dcopuop;
1065
1066                 case fmov_op:
1067                         /* an easy one */
1068                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1069                         goto copcsr;
1070
1071                         /* binary op on handler */
1072                       dcopbop:{
1073                                 ieee754dp fs, ft;
1074
1075                                 DPFROMREG(fs, MIPSInst_FS(ir));
1076                                 DPFROMREG(ft, MIPSInst_FT(ir));
1077
1078                                 rv.d = (*handler.b) (fs, ft);
1079                                 goto copcsr;
1080                         }
1081                       dcopuop:{
1082                                 ieee754dp fs;
1083
1084                                 DPFROMREG(fs, MIPSInst_FS(ir));
1085                                 rv.d = (*handler.u) (fs);
1086                                 goto copcsr;
1087                         }
1088
1089                         /* unary conv ops */
1090                 case fcvts_op:{
1091                         ieee754dp fs;
1092
1093                         DPFROMREG(fs, MIPSInst_FS(ir));
1094                         rv.s = ieee754sp_fdp(fs);
1095                         rfmt = s_fmt;
1096                         goto copcsr;
1097                 }
1098                 case fcvtd_op:
1099                         return SIGILL;  /* not defined */
1100
1101                 case fcvtw_op:{
1102                         ieee754dp fs;
1103
1104                         DPFROMREG(fs, MIPSInst_FS(ir));
1105                         rv.w = ieee754dp_tint(fs);      /* wrong */
1106                         rfmt = w_fmt;
1107                         goto copcsr;
1108                 }
1109
1110 #if __mips >= 2 || __mips64
1111                 case fround_op:
1112                 case ftrunc_op:
1113                 case fceil_op:
1114                 case ffloor_op:{
1115                         unsigned int oldrm = ieee754_csr.rm;
1116                         ieee754dp fs;
1117
1118                         DPFROMREG(fs, MIPSInst_FS(ir));
1119                         ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
1120                         rv.w = ieee754dp_tint(fs);
1121                         ieee754_csr.rm = oldrm;
1122                         rfmt = w_fmt;
1123                         goto copcsr;
1124                 }
1125 #endif
1126
1127 #if __mips64 && !defined(SINGLE_ONLY_FPU)
1128                 case fcvtl_op:{
1129                         ieee754dp fs;
1130
1131                         DPFROMREG(fs, MIPSInst_FS(ir));
1132                         rv.l = ieee754dp_tlong(fs);
1133                         rfmt = l_fmt;
1134                         goto copcsr;
1135                 }
1136
1137                 case froundl_op:
1138                 case ftruncl_op:
1139                 case fceill_op:
1140                 case ffloorl_op:{
1141                         unsigned int oldrm = ieee754_csr.rm;
1142                         ieee754dp fs;
1143
1144                         DPFROMREG(fs, MIPSInst_FS(ir));
1145                         ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
1146                         rv.l = ieee754dp_tlong(fs);
1147                         ieee754_csr.rm = oldrm;
1148                         rfmt = l_fmt;
1149                         goto copcsr;
1150                 }
1151 #endif /* __mips >= 3 && !fpu(single) */
1152
1153                 default:
1154                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1155                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1156                                 ieee754dp fs, ft;
1157
1158                                 DPFROMREG(fs, MIPSInst_FS(ir));
1159                                 DPFROMREG(ft, MIPSInst_FT(ir));
1160                                 rv.w = ieee754dp_cmp(fs, ft,
1161                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1162                                 rfmt = -1;
1163                                 if ((cmpop & 0x8)
1164                                         &&
1165                                         ieee754_cxtest
1166                                         (IEEE754_INVALID_OPERATION))
1167                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1168                                 else
1169                                         goto copcsr;
1170
1171                         }
1172                         else {
1173                                 return SIGILL;
1174                         }
1175                         break;
1176                 }
1177                 break;
1178         }
1179 #endif /* ifndef SINGLE_ONLY_FPU */
1180
1181         case w_fmt:{
1182                 ieee754sp fs;
1183
1184                 switch (MIPSInst_FUNC(ir)) {
1185                 case fcvts_op:
1186                         /* convert word to single precision real */
1187                         SPFROMREG(fs, MIPSInst_FS(ir));
1188                         rv.s = ieee754sp_fint(fs.bits);
1189                         rfmt = s_fmt;
1190                         goto copcsr;
1191 #ifndef SINGLE_ONLY_FPU
1192                 case fcvtd_op:
1193                         /* convert word to double precision real */
1194                         SPFROMREG(fs, MIPSInst_FS(ir));
1195                         rv.d = ieee754dp_fint(fs.bits);
1196                         rfmt = d_fmt;
1197                         goto copcsr;
1198 #endif
1199                 default:
1200                         return SIGILL;
1201                 }
1202                 break;
1203         }
1204
1205 #if __mips64 && !defined(SINGLE_ONLY_FPU)
1206         case l_fmt:{
1207                 switch (MIPSInst_FUNC(ir)) {
1208                 case fcvts_op:
1209                         /* convert long to single precision real */
1210                         rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1211                         rfmt = s_fmt;
1212                         goto copcsr;
1213                 case fcvtd_op:
1214                         /* convert long to double precision real */
1215                         rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1216                         rfmt = d_fmt;
1217                         goto copcsr;
1218                 default:
1219                         return SIGILL;
1220                 }
1221                 break;
1222         }
1223 #endif
1224
1225         default:
1226                 return SIGILL;
1227         }
1228
1229         /*
1230          * Update the fpu CSR register for this operation.
1231          * If an exception is required, generate a tidy SIGFPE exception,
1232          * without updating the result register.
1233          * Note: cause exception bits do not accumulate, they are rewritten
1234          * for each op; only the flag/sticky bits accumulate.
1235          */
1236         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1237         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1238                 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1239                 return SIGFPE;
1240         }
1241
1242         /*
1243          * Now we can safely write the result back to the register file.
1244          */
1245         switch (rfmt) {
1246         case -1:{
1247 #if __mips >= 4
1248                 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
1249 #else
1250                 cond = FPU_CSR_COND;
1251 #endif
1252                 if (rv.w)
1253                         ctx->fcr31 |= cond;
1254                 else
1255                         ctx->fcr31 &= ~cond;
1256                 break;
1257         }
1258 #ifndef SINGLE_ONLY_FPU
1259         case d_fmt:
1260                 DPTOREG(rv.d, MIPSInst_FD(ir));
1261                 break;
1262 #endif
1263         case s_fmt:
1264                 SPTOREG(rv.s, MIPSInst_FD(ir));
1265                 break;
1266         case w_fmt:
1267                 SITOREG(rv.w, MIPSInst_FD(ir));
1268                 break;
1269 #if __mips64 && !defined(SINGLE_ONLY_FPU)
1270         case l_fmt:
1271                 DITOREG(rv.l, MIPSInst_FD(ir));
1272                 break;
1273 #endif
1274         default:
1275                 return SIGILL;
1276         }
1277
1278         return 0;
1279 }
1280
1281 int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
1282         struct mips_fpu_soft_struct *ctx)
1283 {
1284         gpreg_t oldepc, prevepc;
1285         mips_instruction insn;
1286         int sig = 0;
1287
1288         oldepc = xcp->cp0_epc;
1289         do {
1290                 prevepc = xcp->cp0_epc;
1291
1292                 if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) {
1293                         fpuemuprivate.stats.errors++;
1294                         return SIGBUS;
1295                 }
1296                 if (insn == 0)
1297                         xcp->cp0_epc += 4;      /* skip nops */
1298                 else {
1299                         /* Update ieee754_csr. Only relevant if we have a
1300                            h/w FPU */
1301                         ieee754_csr.nod = (ctx->fcr31 & 0x1000000) != 0;
1302                         ieee754_csr.rm = ieee_rm[ctx->fcr31 & 0x3];
1303                         ieee754_csr.cx = (ctx->fcr31 >> 12) & 0x1f;
1304                         sig = cop1Emulate(xcp, ctx);
1305                 }
1306
1307                 if (cpu_has_fpu)
1308                         break;
1309                 if (sig)
1310                         break;
1311
1312                 cond_resched();
1313         } while (xcp->cp0_epc > prevepc);
1314
1315         /* SIGILL indicates a non-fpu instruction */
1316         if (sig == SIGILL && xcp->cp0_epc != oldepc)
1317                 /* but if epc has advanced, then ignore it */
1318                 sig = 0;
1319
1320         return sig;
1321 }