1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <asm/semaphore.h>
6 #include <asm/processor.h>
9 #include <asm/mmu_context.h>
13 static int cachesize_override __initdata = -1;
14 static int disable_x86_fxsr __initdata = 0;
15 static int disable_x86_serial_nr __initdata = 1;
17 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
19 extern void mcheck_init(struct cpuinfo_x86 *c);
21 extern int disable_pse;
23 static void default_init(struct cpuinfo_x86 * c)
25 /* Not much we can do here... */
26 /* Check if at least it has cpuid */
27 if (c->cpuid_level == -1) {
28 /* No cpuid. It must be an ancient CPU */
30 strcpy(c->x86_model_id, "486");
32 strcpy(c->x86_model_id, "386");
36 static struct cpu_dev default_cpu = {
37 .c_init = default_init,
39 static struct cpu_dev * this_cpu = &default_cpu;
41 static int __init cachesize_setup(char *str)
43 get_option (&str, &cachesize_override);
46 __setup("cachesize=", cachesize_setup);
48 int __init get_model_name(struct cpuinfo_x86 *c)
53 if (cpuid_eax(0x80000000) < 0x80000004)
56 v = (unsigned int *) c->x86_model_id;
57 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
58 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
59 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
60 c->x86_model_id[48] = 0;
62 /* Intel chips right-justify this string for some dumb reason;
63 undo that brain damage */
64 p = q = &c->x86_model_id[0];
70 while ( q <= &c->x86_model_id[48] )
71 *q++ = '\0'; /* Zero-pad the rest */
78 void __init display_cacheinfo(struct cpuinfo_x86 *c)
80 unsigned int n, dummy, ecx, edx, l2size;
82 n = cpuid_eax(0x80000000);
84 if (n >= 0x80000005) {
85 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
86 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
87 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
88 c->x86_cache_size=(ecx>>24)+(edx>>24);
91 if (n < 0x80000006) /* Some chips just has a large L1. */
94 ecx = cpuid_ecx(0x80000006);
97 /* do processor-specific cache resizing */
98 if (this_cpu->c_size_cache)
99 l2size = this_cpu->c_size_cache(c,l2size);
101 /* Allow user to override all this if necessary. */
102 if (cachesize_override != -1)
103 l2size = cachesize_override;
106 return; /* Again, no L2 cache is possible */
108 c->x86_cache_size = l2size;
110 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
114 /* Naming convention should be: <Name> [(<Codename>)] */
115 /* This table only is used unless init_<vendor>() below doesn't set it; */
116 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
118 /* Look up CPU names by table lookup. */
119 static char __init *table_lookup_model(struct cpuinfo_x86 *c)
121 struct cpu_model_info *info;
123 if ( c->x86_model >= 16 )
124 return NULL; /* Range check */
129 info = this_cpu->c_models;
131 while (info && info->family) {
132 if (info->family == c->x86)
133 return info->model_names[c->x86_model];
136 return NULL; /* Not found */
141 void __init get_cpu_vendor(struct cpuinfo_x86 *c)
143 char *v = c->x86_vendor_id;
146 for (i = 0; i < X86_VENDOR_NUM; i++) {
148 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
149 (cpu_devs[i]->c_ident[1] &&
150 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
152 this_cpu = cpu_devs[i];
160 static int __init x86_fxsr_setup(char * s)
162 disable_x86_fxsr = 1;
165 __setup("nofxsr", x86_fxsr_setup);
168 /* Standard macro to see if a specific flag is changeable */
169 static inline int flag_is_changeable_p(u32 flag)
183 : "=&r" (f1), "=&r" (f2)
186 return ((f1^f2) & flag) != 0;
190 /* Probe for the CPUID instruction */
191 int __init have_cpuid_p(void)
193 return flag_is_changeable_p(X86_EFLAGS_ID);
196 void __init generic_identify(struct cpuinfo_x86 * c)
201 if (have_cpuid_p()) {
202 /* Get vendor name */
203 cpuid(0x00000000, &c->cpuid_level,
204 (int *)&c->x86_vendor_id[0],
205 (int *)&c->x86_vendor_id[8],
206 (int *)&c->x86_vendor_id[4]);
209 /* Initialize the standard set of capabilities */
210 /* Note that the vendor-specific code below might override */
212 /* Intel-defined flags: level 0x00000001 */
213 if ( c->cpuid_level >= 0x00000001 ) {
214 u32 capability, excap;
215 cpuid(0x00000001, &tfms, &junk, &excap, &capability);
216 c->x86_capability[0] = capability;
217 c->x86_capability[4] = excap;
218 c->x86 = (tfms >> 8) & 15;
219 c->x86_model = (tfms >> 4) & 15;
221 c->x86 += (tfms >> 20) & 0xff;
222 c->x86_model += ((tfms >> 16) & 0xF) << 4;
224 c->x86_mask = tfms & 15;
226 /* Have CPUID level 0 only - unheard of */
230 /* AMD-defined flags: level 0x80000001 */
231 xlvl = cpuid_eax(0x80000000);
232 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
233 if ( xlvl >= 0x80000001 )
234 c->x86_capability[1] = cpuid_edx(0x80000001);
235 if ( xlvl >= 0x80000004 )
236 get_model_name(c); /* Default name */
241 static void __init squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
243 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
244 /* Disable processor serial number */
246 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
248 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
249 printk(KERN_NOTICE "CPU serial number disabled.\n");
250 clear_bit(X86_FEATURE_PN, c->x86_capability);
252 /* Disabling the serial number may affect the cpuid level */
253 c->cpuid_level = cpuid_eax(0);
257 static int __init x86_serial_nr_setup(char *s)
259 disable_x86_serial_nr = 0;
262 __setup("serialnumber", x86_serial_nr_setup);
267 * This does the hard work of actually picking apart the CPU stuff...
269 void __init identify_cpu(struct cpuinfo_x86 *c)
273 c->loops_per_jiffy = loops_per_jiffy;
274 c->x86_cache_size = -1;
275 c->x86_vendor = X86_VENDOR_UNKNOWN;
276 c->cpuid_level = -1; /* CPUID not detected */
277 c->x86_model = c->x86_mask = 0; /* So far unknown... */
278 c->x86_vendor_id[0] = '\0'; /* Unset */
279 c->x86_model_id[0] = '\0'; /* Unset */
280 memset(&c->x86_capability, 0, sizeof c->x86_capability);
282 if (!have_cpuid_p()) {
283 /* First of all, decide if this is a 486 or higher */
284 /* It's a 486 if we can modify the AC flag */
285 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
293 printk(KERN_DEBUG "CPU: After generic identify, caps: %08lx %08lx %08lx %08lx\n",
294 c->x86_capability[0],
295 c->x86_capability[1],
296 c->x86_capability[2],
297 c->x86_capability[3]);
299 if (this_cpu->c_identify) {
300 this_cpu->c_identify(c);
302 printk(KERN_DEBUG "CPU: After vendor identify, caps: %08lx %08lx %08lx %08lx\n",
303 c->x86_capability[0],
304 c->x86_capability[1],
305 c->x86_capability[2],
306 c->x86_capability[3]);
310 * Vendor-specific initialization. In this section we
311 * canonicalize the feature flags, meaning if there are
312 * features a certain CPU supports which CPUID doesn't
313 * tell us, CPUID claiming incorrect flags, or other bugs,
314 * we handle them here.
316 * At the end of this section, c->x86_capability better
317 * indicate the features this CPU genuinely supports!
319 if (this_cpu->c_init)
322 /* Disable the PN if appropriate */
323 squash_the_stupid_serial_number(c);
326 * The vendor-specific functions might have changed features. Now
327 * we do "generic changes."
332 clear_bit(X86_FEATURE_TSC, c->x86_capability);
335 if (disable_x86_fxsr) {
336 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
337 clear_bit(X86_FEATURE_XMM, c->x86_capability);
341 clear_bit(X86_FEATURE_PSE, c->x86_capability);
343 /* If the model name is still unset, do table lookup. */
344 if ( !c->x86_model_id[0] ) {
346 p = table_lookup_model(c);
348 strcpy(c->x86_model_id, p);
351 sprintf(c->x86_model_id, "%02x/%02x",
352 c->x86_vendor, c->x86_model);
355 /* Now the feature flags better reflect actual CPU features! */
357 printk(KERN_DEBUG "CPU: After all inits, caps: %08lx %08lx %08lx %08lx\n",
358 c->x86_capability[0],
359 c->x86_capability[1],
360 c->x86_capability[2],
361 c->x86_capability[3]);
364 * On SMP, boot_cpu_data holds the common feature set between
365 * all CPUs; so make sure that we indicate which features are
366 * common between the CPUs. The first time this routine gets
367 * executed, c == &boot_cpu_data.
369 if ( c != &boot_cpu_data ) {
370 /* AND the already accumulated flags with these */
371 for ( i = 0 ; i < NCAPINTS ; i++ )
372 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
375 /* Init Machine Check Exception if available. */
376 #ifdef CONFIG_X86_MCE
381 * Perform early boot up checks for a valid TSC. See arch/i386/kernel/time.c
384 void __init dodgy_tsc(void)
386 get_cpu_vendor(&boot_cpu_data);
387 if (( boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX ) ||
388 ( boot_cpu_data.x86_vendor == X86_VENDOR_NSC ))
389 cpu_devs[X86_VENDOR_CYRIX]->c_init(&boot_cpu_data);
392 void __init print_cpu_info(struct cpuinfo_x86 *c)
396 if (c->x86_vendor < X86_VENDOR_NUM)
397 vendor = this_cpu->c_vendor;
398 else if (c->cpuid_level >= 0)
399 vendor = c->x86_vendor_id;
401 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
402 printk("%s ", vendor);
404 if (!c->x86_model_id[0])
405 printk("%d86", c->x86);
407 printk("%s", c->x86_model_id);
409 if (c->x86_mask || c->cpuid_level >= 0)
410 printk(" stepping %02x\n", c->x86_mask);
415 unsigned long cpu_initialized __initdata = 0;
418 * We're emulating future behavior.
419 * In the future, the cpu-specific init functions will be called implicitly
420 * via the magic of initcalls.
421 * They will insert themselves into the cpu_devs structure.
422 * Then, when cpu_init() is called, we can just iterate over that array.
425 extern int intel_cpu_init(void);
426 extern int cyrix_init_cpu(void);
427 extern int nsc_init_cpu(void);
428 extern int amd_init_cpu(void);
429 extern int centaur_init_cpu(void);
430 extern int transmeta_init_cpu(void);
431 extern int rise_init_cpu(void);
432 extern int nexgen_init_cpu(void);
433 extern int umc_init_cpu(void);
435 void __init early_cpu_init(void)
442 transmeta_init_cpu();
447 #ifdef CONFIG_DEBUG_PAGEALLOC
448 /* pse is not compatible with on-the-fly unmapping,
449 * disable it even if the cpus claim to support it.
451 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
456 * cpu_init() initializes state that is per-CPU. Some data is already
457 * initialized (naturally) in the bootstrap process, such as the GDT
458 * and IDT. We reload them nevertheless, this function acts as a
459 * 'CPU state barrier', nothing should get across.
461 void __init cpu_init (void)
463 int cpu = smp_processor_id();
464 struct tss_struct * t = init_tss + cpu;
465 struct thread_struct *thread = ¤t->thread;
467 if (test_and_set_bit(cpu, &cpu_initialized)) {
468 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
469 for (;;) local_irq_enable();
471 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
473 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
474 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
475 if (tsc_disable && cpu_has_tsc) {
476 printk(KERN_NOTICE "Disabling TSC...\n");
477 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
478 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
479 set_in_cr4(X86_CR4_TSD);
483 * Initialize the per-CPU GDT with the boot GDT,
484 * and set up the GDT descriptor:
487 memcpy(cpu_gdt_table[cpu], cpu_gdt_table[0], GDT_SIZE);
488 cpu_gdt_descr[cpu].size = GDT_SIZE - 1;
489 cpu_gdt_descr[cpu].address = (unsigned long)cpu_gdt_table[cpu];
492 * Set up the per-thread TLS descriptor cache:
494 memcpy(thread->tls_array, cpu_gdt_table[cpu], GDT_ENTRY_TLS_ENTRIES * 8);
496 __asm__ __volatile__("lgdt %0": "=m" (cpu_gdt_descr[cpu]));
497 __asm__ __volatile__("lidt %0": "=m" (idt_descr));
502 __asm__("pushfl ; andl $0xffffbfff,(%esp) ; popfl");
505 * Set up and load the per-CPU TSS and LDT
507 atomic_inc(&init_mm.mm_count);
508 current->active_mm = &init_mm;
511 enter_lazy_tlb(&init_mm, current);
513 load_esp0(t, thread->esp0);
515 cpu_gdt_table[cpu][GDT_ENTRY_TSS].b &= 0xfffffdff;
517 load_LDT(&init_mm.context);
519 /* Set up doublefault TSS pointer in the GDT */
520 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
521 cpu_gdt_table[cpu][GDT_ENTRY_DOUBLEFAULT_TSS].b &= 0xfffffdff;
523 /* Clear %fs and %gs. */
524 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
526 /* Clear all 6 debug registers: */
528 #define CD(register) __asm__("movl %0,%%db" #register ::"r"(0) );
530 CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
535 * Force FPU initialization:
537 current_thread_info()->status = 0;
538 current->used_math = 0;