drivers/media/dvb/b2c2/skystar2.c

   1 /*
   2  * skystar2.c - driver for the Technisat SkyStar2 PCI DVB card
   3  *              based on the FlexCopII by B2C2,Inc.
   4  *
   5  * Copyright (C) 2003  V.C. , skystar@moldova.cc
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public License
   9  * as published by the Free Software Foundation; either version 2.1
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  20  */
  21 #include <linux/module.h>
  22 #include <linux/delay.h>
  23 #include <linux/pci.h>
  24
  25 #include "dvb_i2c.h"
  26 #include "dvb_frontend.h"
  27 #include "dvb_functions.h"
  28
  29 #include <linux/dvb/frontend.h>
  30 #include <linux/dvb/dmx.h>
  31 #include "dvb_demux.h"
  32 #include "dmxdev.h"
  33 #include "dvb_filter.h"
  34 #include "dvbdev.h"
  35 #include "demux.h"
  36 #include "dvb_net.h"
  37
  38 static int debug = 0;
  39 #define dprintk(x...) do { if (debug) printk(x); } while (0)
  40
  41 #define SizeOfBufDMA1   0x3AC00
  42 #define SizeOfBufDMA2   0x758
  43
  44 struct dmaq {
  45
  46         u32 bus_addr;
  47         u32 head;
  48         u32 tail;
  49         u32 buffer_size;
  50         u8 *buffer;
  51 };
  52
  53 struct packet_header {
  54
  55         u32 sync_byte;
  56         u32 transport_error_indicator;
  57         u32 payload_unit_start_indicator;
  58         u32 transport_priority;
  59         u32 pid;
  60         u32 transport_scrambling_control;
  61         u32 adaptation_field_control;
  62         u32 continuity_counter;
  63 };
  64
  65 struct adapter {
  66
  67         struct pci_dev *pdev;
  68
  69         u8 card_revision;
  70         u32 b2c2_revision;
  71         u32 PidFilterMax;
  72         u32 MacFilterMax;
  73         u32 irq;
  74         u32 io_mem;
  75         u32 io_port;
  76         u8 mac_addr[8];
  77         u32 dwSramType;
  78
  79         struct dvb_adapter *dvb_adapter;
  80         struct dvb_demux demux;
  81         struct dmxdev dmxdev;
  82         struct dmx_frontend hw_frontend;
  83         struct dmx_frontend mem_frontend;
  84         struct dvb_i2c_bus *i2c_bus;
  85         struct dvb_net dvbnet;
  86
  87         struct semaphore i2c_sem;
  88
  89         struct dmaq dmaq1;
  90         struct dmaq dmaq2;
  91
  92         u32 dma_ctrl;
  93         u32 dma_status;
  94
  95         u32 capturing;
  96
  97         spinlock_t lock;
  98
  99         u16 pids[0x27];
 100         u32 mac_filter;
 101 };
 102
 103 #define WriteRegDW(adapter,reg,value) writel(value, adapter->io_mem + reg)
 104 #define ReadRegDW(adapter,reg) readl(adapter->io_mem + reg)
 105
 106 static void WriteRegOp(struct adapter *adapter, u32 reg, u32 operation, u32 andvalue, u32 orvalue)
 107 {
 108         u32 tmp;
 109
 110         tmp = ReadRegDW(adapter, reg);
 111
 112         if (operation == 1)
 113                 tmp = tmp | orvalue;
 114         if (operation == 2)
 115                 tmp = tmp & andvalue;
 116         if (operation == 3)
 117                 tmp = (tmp & andvalue) | orvalue;
 118
 119         WriteRegDW(adapter, reg, tmp);
 120 }
 121
 122 /* i2c functions */
 123 static int i2cMainWriteForFlex2(struct adapter * adapter, u32 command, u8 * buf, u32 retries)
 124 {
 125         u32 i;
 126         u32 value;
 127
 128         WriteRegDW(adapter, 0x100, 0);
 129         WriteRegDW(adapter, 0x100, command);
 130
 131         for (i = 0; i < retries; i++) {
 132                 value = ReadRegDW(adapter, 0x100);
 133
 134                 if ((value & 0x40000000) == 0) {
 135                         if ((value & 0x81000000) == 0x80000000) {
 136                                 if (buf != 0)
 137                                         *buf = (value >> 0x10) & 0xff;
 138
 139                                 return 1;
 140                         }
 141
 142                 } else {
 143
 144                         WriteRegDW(adapter, 0x100, 0);
 145                         WriteRegDW(adapter, 0x100, command);
 146                 }
 147         }
 148
 149         return 0;
 150 }
 151
 152 /* device = 0x10000000 for tuner, 0x20000000 for eeprom */
 153 static void i2cMainSetup(u32 device, u32 chip_addr, u8 op, u8 addr, u32 value, u32 len, u32 *command)
 154 {
 155         *command = device | ((len - 1) << 26) | (value << 16) | (addr << 8) | chip_addr;
 156
 157         if (op != 0)
 158                 *command = *command | 0x03000000;
 159         else
 160                 *command = *command | 0x01000000;
 161 }
 162
 163 static int FlexI2cRead4(struct adapter * adapter, u32 device, u32 chip_addr, u16 addr, u8 * buf, u8 len)
 164 {
 165         u32 command;
 166         u32 value;
 167
 168         int result, i;
 169
 170         i2cMainSetup(device, chip_addr, 1, addr, 0, len, &command);
 171
 172         result = i2cMainWriteForFlex2(adapter, command, buf, 100000);
 173
 174         if ((result & 0xff) != 0) {
 175                 if (len > 1) {
 176                         value = ReadRegDW(adapter, 0x104);
 177
 178                         for (i = 1; i < len; i++) {
 179                                 buf[i] = value & 0xff;
 180                                 value = value >> 8;
 181                         }
 182                 }
 183         }
 184
 185         return result;
 186 }
 187
 188 static int FlexI2cWrite4(struct adapter * adapter, u32 device, u32 chip_addr, u32 addr, u8 * buf, u8 len)
 189 {
 190         u32 command;
 191         u32 value;
 192         int i;
 193
 194         if (len > 1) {
 195                 value = 0;
 196
 197                 for (i = len; i > 1; i--) {
 198                         value = value << 8;
 199                         value = value | buf[i - 1];
 200                 }
 201
 202                 WriteRegDW(adapter, 0x104, value);
 203         }
 204
 205         i2cMainSetup(device, chip_addr, 0, addr, buf[0], len, &command);
 206
 207         return i2cMainWriteForFlex2(adapter, command, 0, 100000);
 208 }
 209
 210 static void fixchipaddr(u32 device, u32 bus, u32 addr, u32 *ret)
 211 {
 212         if (device == 0x20000000)
 213                 *ret = bus | ((addr >> 8) & 3);
 214
 215         *ret = bus;
 216 }
 217
 218 static u32 FLEXI2C_read(struct adapter * adapter, u32 device, u32 bus, u32 addr, u8 * buf, u32 len)
 219 {
 220         u32 chipaddr;
 221         u32 bytes_to_transfer;
 222         u8 *start;
 223
 224 //  dprintk("%s:\n", __FUNCTION__);
 225
 226         start = buf;
 227
 228         while (len != 0) {
 229                 bytes_to_transfer = len;
 230
 231                 if (bytes_to_transfer > 4)
 232                         bytes_to_transfer = 4;
 233
 234                 fixchipaddr(device, bus, addr, &chipaddr);
 235
 236                 if (FlexI2cRead4(adapter, device, chipaddr, addr, buf, bytes_to_transfer) == 0)
 237                         return buf - start;
 238
 239                 buf = buf + bytes_to_transfer;
 240                 addr = addr + bytes_to_transfer;
 241                 len = len - bytes_to_transfer;
 242         };
 243
 244         return buf - start;
 245 }
 246
 247 static u32 FLEXI2C_write(struct adapter * adapter, u32 device, u32 bus, u32 addr, u8 * buf, u32 len)
 248 {
 249         u32 chipaddr;
 250         u32 bytes_to_transfer;
 251         u8 *start;
 252
 253 //  dprintk("%s:\n", __FUNCTION__);
 254
 255         start = buf;
 256
 257         while (len != 0) {
 258                 bytes_to_transfer = len;
 259
 260                 if (bytes_to_transfer > 4)
 261                         bytes_to_transfer = 4;
 262
 263                 fixchipaddr(device, bus, addr, &chipaddr);
 264
 265                 if (FlexI2cWrite4(adapter, device, chipaddr, addr, buf, bytes_to_transfer) == 0)
 266                         return buf - start;
 267
 268                 buf = buf + bytes_to_transfer;
 269                 addr = addr + bytes_to_transfer;
 270                 len = len - bytes_to_transfer;
 271         }
 272
 273         return buf - start;
 274 }
 275
 276 static int master_xfer(struct dvb_i2c_bus *i2c, const struct i2c_msg *msgs, int num)
 277 {
 278         struct adapter *tmp = i2c->data;
 279         int i, ret = 0;
 280
 281         if (down_interruptible(&tmp->i2c_sem))
 282                 return -ERESTARTSYS;
 283
 284         if (0) {
 285                 dprintk("%s:\n", __FUNCTION__);
 286
 287                 for (i = 0; i < num; i++) {
 288                         printk("message %d: flags=%x, addr=0x%04x, buf=%x, len=%d \n", i, msgs[i].flags, msgs[i].addr, (u32) msgs[i].buf, msgs[i].len);
 289                 }
 290         }
 291
 292         /* allow only the vp310 frontend to access the bus */
 293         if ((msgs[0].addr != 0x0E) && (msgs[0].addr != 0x61)) {
 294                 up(&tmp->i2c_sem);
 295
 296                 return -EREMOTEIO;
 297         }
 298
 299         if ((num == 1) && (msgs[0].buf != NULL)) {
 300                 if (msgs[0].flags == I2C_M_RD) {
 301                         ret = -EINVAL;
 302
 303                 } else {
 304
 305                         // single writes do have the reg addr in buf[0] and data in buf[1] to buf[n]
 306                         ret = FLEXI2C_write(tmp, 0x10000000, msgs[0].addr, msgs[0].buf[0], &msgs[0].buf[1], msgs[0].len - 1);
 307
 308                         if (ret != msgs[0].len - 1)
 309                                 ret = -EREMOTEIO;
 310                         else
 311                                 ret = num;
 312                 }
 313
 314         } else if ((num == 2) && (msgs[1].buf != NULL)) {
 315
 316                 // i2c reads consist of a reg addr _write_ followed by a data read, so msg[1].flags has to be examined
 317                 if (msgs[1].flags == I2C_M_RD) {
 318                         ret = FLEXI2C_read(tmp, 0x10000000, msgs[0].addr, msgs[0].buf[0], msgs[1].buf, msgs[1].len);
 319
 320                 } else {
 321
 322                         ret = FLEXI2C_write(tmp, 0x10000000, msgs[0].addr, msgs[0].buf[0], msgs[1].buf, msgs[1].len);
 323                 }
 324
 325                 if (ret != msgs[1].len)
 326                         ret = -EREMOTEIO;
 327                 else
 328                         ret = num;
 329         }
 330
 331         up(&tmp->i2c_sem);
 332
 333         /* master xfer functions always return the number of successfully
 334            transmitted messages, not the number of transmitted bytes.
 335            return -EREMOTEIO in case of failure. */
 336         return ret;
 337 }
 338
 339 /* SRAM (Skystar2 rev2.3 has one "ISSI IS61LV256" chip on board,
 340    but it seems that FlexCopII can work with more than one chip) */
 341 static void SRAMSetNetDest(struct adapter * adapter, u8 dest)
 342 {
 343         u32 tmp;
 344
 345         udelay(1000);
 346
 347         tmp = (ReadRegDW(adapter, 0x714) & 0xFFFFFFFC) | (dest & 3);
 348
 349         udelay(1000);
 350
 351         WriteRegDW(adapter, 0x714, tmp);
 352         WriteRegDW(adapter, 0x714, tmp);
 353
 354         udelay(1000);
 355
 356         /* return value is never used? */
 357 /*      return tmp; */
 358 }
 359
 360 static void SRAMSetCaiDest(struct adapter * adapter, u8 dest)
 361 {
 362         u32 tmp;
 363
 364         udelay(1000);
 365
 366         tmp = (ReadRegDW(adapter, 0x714) & 0xFFFFFFF3) | ((dest & 3) << 2);
 367
 368         udelay(1000);
 369         udelay(1000);
 370
 371         WriteRegDW(adapter, 0x714, tmp);
 372         WriteRegDW(adapter, 0x714, tmp);
 373
 374         udelay(1000);
 375
 376         /* return value is never used? */
 377 /*      return tmp; */
 378 }
 379
 380 static void SRAMSetCaoDest(struct adapter * adapter, u8 dest)
 381 {
 382         u32 tmp;
 383
 384         udelay(1000);
 385
 386         tmp = (ReadRegDW(adapter, 0x714) & 0xFFFFFFCF) | ((dest & 3) << 4);
 387
 388         udelay(1000);
 389         udelay(1000);
 390
 391         WriteRegDW(adapter, 0x714, tmp);
 392         WriteRegDW(adapter, 0x714, tmp);
 393
 394         udelay(1000);
 395
 396         /* return value is never used? */
 397 /*      return tmp; */
 398 }
 399
 400 static void SRAMSetMediaDest(struct adapter * adapter, u8 dest)
 401 {
 402         u32 tmp;
 403
 404         udelay(1000);
 405
 406         tmp = (ReadRegDW(adapter, 0x714) & 0xFFFFFF3F) | ((dest & 3) << 6);
 407
 408         udelay(1000);
 409         udelay(1000);
 410
 411         WriteRegDW(adapter, 0x714, tmp);
 412         WriteRegDW(adapter, 0x714, tmp);
 413
 414         udelay(1000);
 415
 416         /* return value is never used? */
 417 /*      return tmp; */
 418 }
 419
 420 /* SRAM memory is accessed through a buffer register in the FlexCop
 421    chip (0x700). This register has the following structure:
 422     bits 0-14  : address
 423     bit  15    : read/write flag
 424     bits 16-23 : 8-bit word to write
 425     bits 24-27 : = 4
 426     bits 28-29 : memory bank selector
 427     bit  31    : busy flag
 428 */
 429 static void FlexSramWrite(struct adapter *adapter, u32 bank, u32 addr, u8 * buf, u32 len)
 430 {
 431         u32 i, command, retries;
 432
 433         for (i = 0; i < len; i++) {
 434                 command = bank | addr | 0x04000000 | (*buf << 0x10);
 435
 436                 retries = 2;
 437
 438                 while (((ReadRegDW(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
 439                         mdelay(1);
 440                         retries--;
 441                 };
 442
 443                 if (retries == 0)
 444                         printk("%s: SRAM timeout\n", __FUNCTION__);
 445
 446                 WriteRegDW(adapter, 0x700, command);
 447
 448                 buf++;
 449                 addr++;
 450         }
 451 }
 452
 453 static void FlexSramRead(struct adapter *adapter, u32 bank, u32 addr, u8 * buf, u32 len)
 454 {
 455         u32 i, command, value, retries;
 456
 457         for (i = 0; i < len; i++) {
 458                 command = bank | addr | 0x04008000;
 459
 460                 retries = 10000;
 461
 462                 while (((ReadRegDW(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
 463                         mdelay(1);
 464                         retries--;
 465                 };
 466
 467                 if (retries == 0)
 468                         printk("%s: SRAM timeout\n", __FUNCTION__);
 469
 470                 WriteRegDW(adapter, 0x700, command);
 471
 472                 retries = 10000;
 473
 474                 while (((ReadRegDW(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
 475                         mdelay(1);
 476                         retries--;
 477                 };
 478
 479                 if (retries == 0)
 480                         printk("%s: SRAM timeout\n", __FUNCTION__);
 481
 482                 value = ReadRegDW(adapter, 0x700) >> 0x10;
 483
 484                 *buf = (value & 0xff);
 485
 486                 addr++;
 487                 buf++;
 488         }
 489 }
 490
 491 static void SRAM_writeChunk(struct adapter *adapter, u32 addr, u8 * buf, u16 len)
 492 {
 493         u32 bank;
 494
 495         bank = 0;
 496
 497         if (adapter->dwSramType == 0x20000) {
 498                 bank = (addr & 0x18000) << 0x0D;
 499         }
 500
 501         if (adapter->dwSramType == 0x00000) {
 502                 if ((addr >> 0x0F) == 0)
 503                         bank = 0x20000000;
 504                 else
 505                         bank = 0x10000000;
 506         }
 507
 508         FlexSramWrite(adapter, bank, addr & 0x7FFF, buf, len);
 509 }
 510
 511 static void SRAM_readChunk(struct adapter *adapter, u32 addr, u8 * buf, u16 len)
 512 {
 513         u32 bank;
 514
 515         bank = 0;
 516
 517         if (adapter->dwSramType == 0x20000) {
 518                 bank = (addr & 0x18000) << 0x0D;
 519         }
 520
 521         if (adapter->dwSramType == 0x00000) {
 522                 if ((addr >> 0x0F) == 0)
 523                         bank = 0x20000000;
 524                 else
 525                         bank = 0x10000000;
 526         }
 527
 528         FlexSramRead(adapter, bank, addr & 0x7FFF, buf, len);
 529 }
 530
 531 static void SRAM_read(struct adapter *adapter, u32 addr, u8 * buf, u32 len)
 532 {
 533         u32 length;
 534
 535         while (len != 0) {
 536                 length = len;
 537
 538                 // check if the address range belongs to the same
 539                 // 32K memory chip. If not, the data is read from
 540                 // one chip at a time.
 541                 if ((addr >> 0x0F) != ((addr + len - 1) >> 0x0F)) {
 542                         length = (((addr >> 0x0F) + 1) << 0x0F) - addr;
 543                 }
 544
 545                 SRAM_readChunk(adapter, addr, buf, length);
 546
 547                 addr = addr + length;
 548                 buf = buf + length;
 549                 len = len - length;
 550         }
 551 }
 552
 553 static void SRAM_write(struct adapter *adapter, u32 addr, u8 * buf, u32 len)
 554 {
 555         u32 length;
 556
 557         while (len != 0) {
 558                 length = len;
 559
 560                 // check if the address range belongs to the same
 561                 // 32K memory chip. If not, the data is written to
 562                 // one chip at a time.
 563                 if ((addr >> 0x0F) != ((addr + len - 1) >> 0x0F)) {
 564                         length = (((addr >> 0x0F) + 1) << 0x0F) - addr;
 565                 }
 566
 567                 SRAM_writeChunk(adapter, addr, buf, length);
 568
 569                 addr = addr + length;
 570                 buf = buf + length;
 571                 len = len - length;
 572         }
 573 }
 574
 575 static void SRAM_setSize(struct adapter *adapter, u32 mask)
 576 {
 577         WriteRegDW(adapter, 0x71C, (mask | (~0x30000 & ReadRegDW(adapter, 0x71C))));
 578 }
 579
 580 static void SRAM_init(struct adapter *adapter)
 581 {
 582         u32 tmp;
 583
 584         tmp = ReadRegDW(adapter, 0x71C);
 585
 586         WriteRegDW(adapter, 0x71C, 1);
 587
 588         if (ReadRegDW(adapter, 0x71C) != 0) {
 589                 WriteRegDW(adapter, 0x71C, tmp);
 590
 591                 adapter->dwSramType = tmp & 0x30000;
 592
 593                 dprintk("%s: dwSramType = %x\n", __FUNCTION__, adapter->dwSramType);
 594
 595         } else {
 596
 597                 adapter->dwSramType = 0x10000;
 598
 599                 dprintk("%s: dwSramType = %x\n", __FUNCTION__, adapter->dwSramType);
 600         }
 601
 602         /* return value is never used? */
 603 /*      return adapter->dwSramType; */
 604 }
 605
 606 static int SRAM_testLocation(struct adapter *adapter, u32 mask, u32 addr)
 607 {
 608         u8 tmp1, tmp2;
 609
 610         dprintk("%s: mask = %x, addr = %x\n", __FUNCTION__, mask, addr);
 611
 612         SRAM_setSize(adapter, mask);
 613         SRAM_init(adapter);
 614
 615         tmp2 = 0xA5;
 616         tmp1 = 0x4F;
 617
 618         SRAM_write(adapter, addr, &tmp2, 1);
 619         SRAM_write(adapter, addr + 4, &tmp1, 1);
 620
 621         tmp2 = 0;
 622
 623         mdelay(20);
 624
 625         SRAM_read(adapter, addr, &tmp2, 1);
 626         SRAM_read(adapter, addr, &tmp2, 1);
 627
 628         dprintk("%s: wrote 0xA5, read 0x%2x\n", __FUNCTION__, tmp2);
 629
 630         if (tmp2 != 0xA5)
 631                 return 0;
 632
 633         tmp2 = 0x5A;
 634         tmp1 = 0xF4;
 635
 636         SRAM_write(adapter, addr, &tmp2, 1);
 637         SRAM_write(adapter, addr + 4, &tmp1, 1);
 638
 639         tmp2 = 0;
 640
 641         mdelay(20);
 642
 643         SRAM_read(adapter, addr, &tmp2, 1);
 644         SRAM_read(adapter, addr, &tmp2, 1);
 645
 646         dprintk("%s: wrote 0x5A, read 0x%2x\n", __FUNCTION__, tmp2);
 647
 648         if (tmp2 != 0x5A)
 649                 return 0;
 650
 651         return 1;
 652 }
 653
 654 static u32 SRAM_length(struct adapter * adapter)
 655 {
 656         if (adapter->dwSramType == 0x10000)
 657                 return 32768;   //  32K
 658         if (adapter->dwSramType == 0x00000)
 659                 return 65536;   //  64K
 660         if (adapter->dwSramType == 0x20000)
 661                 return 131072;  // 128K
 662
 663         return 32768;           // 32K
 664 }
 665
 666 /* FlexcopII can work with 32K, 64K or 128K of external SRAM memory.
 667     - for 128K there are 4x32K chips at bank 0,1,2,3.
 668     - for  64K there are 2x32K chips at bank 1,2.
 669     - for  32K there is one 32K chip at bank 0.
 670
 671    FlexCop works only with one bank at a time. The bank is selected
 672    by bits 28-29 of the 0x700 register.
 673
 674    bank 0 covers addresses 0x00000-0x07FFF
 675    bank 1 covers addresses 0x08000-0x0FFFF
 676    bank 2 covers addresses 0x10000-0x17FFF
 677    bank 3 covers addresses 0x18000-0x1FFFF
 678 */
 679 static int SramDetectForFlex2(struct adapter *adapter)
 680 {
 681         u32 tmp, tmp2, tmp3;
 682
 683         dprintk("%s:\n", __FUNCTION__);
 684
 685         tmp = ReadRegDW(adapter, 0x208);
 686         WriteRegDW(adapter, 0x208, 0);
 687
 688         tmp2 = ReadRegDW(adapter, 0x71C);
 689
 690         dprintk("%s: tmp2 = %x\n", __FUNCTION__, tmp2);
 691
 692         WriteRegDW(adapter, 0x71C, 1);
 693
 694         tmp3 = ReadRegDW(adapter, 0x71C);
 695
 696         dprintk("%s: tmp3 = %x\n", __FUNCTION__, tmp3);
 697
 698         WriteRegDW(adapter, 0x71C, tmp2);
 699
 700         // check for internal SRAM ???
 701         tmp3--;
 702         if (tmp3 != 0) {
 703                 SRAM_setSize(adapter, 0x10000);
 704                 SRAM_init(adapter);
 705                 WriteRegDW(adapter, 0x208, tmp);
 706
 707                 dprintk("%s: sram size = 32K\n", __FUNCTION__);
 708
 709                 return 32;
 710         }
 711
 712         if (SRAM_testLocation(adapter, 0x20000, 0x18000) != 0) {
 713                 SRAM_setSize(adapter, 0x20000);
 714                 SRAM_init(adapter);
 715                 WriteRegDW(adapter, 0x208, tmp);
 716
 717                 dprintk("%s: sram size = 128K\n", __FUNCTION__);
 718
 719                 return 128;
 720         }
 721
 722         if (SRAM_testLocation(adapter, 0x00000, 0x10000) != 0) {
 723                 SRAM_setSize(adapter, 0x00000);
 724                 SRAM_init(adapter);
 725                 WriteRegDW(adapter, 0x208, tmp);
 726
 727                 dprintk("%s: sram size = 64K\n", __FUNCTION__);
 728
 729                 return 64;
 730         }
 731
 732         if (SRAM_testLocation(adapter, 0x10000, 0x00000) != 0) {
 733                 SRAM_setSize(adapter, 0x10000);
 734                 SRAM_init(adapter);
 735                 WriteRegDW(adapter, 0x208, tmp);
 736
 737                 dprintk("%s: sram size = 32K\n", __FUNCTION__);
 738
 739                 return 32;
 740         }
 741
 742         SRAM_setSize(adapter, 0x10000);
 743         SRAM_init(adapter);
 744         WriteRegDW(adapter, 0x208, tmp);
 745
 746         dprintk("%s: SRAM detection failed. Set to 32K \n", __FUNCTION__);
 747
 748         return 0;
 749 }
 750
 751 static void SLL_detectSramSize(struct adapter *adapter)
 752 {
 753         SramDetectForFlex2(adapter);
 754 }
 755 /* EEPROM (Skystar2 has one "24LC08B" chip on board) */
 756 /*
 757 static int EEPROM_write(struct adapter *adapter, u16 addr, u8 * buf, u16 len)
 758 {
 759         return FLEXI2C_write(adapter, 0x20000000, 0x50, addr, buf, len);
 760 }
 761 */
 762
 763 static int EEPROM_read(struct adapter *adapter, u16 addr, u8 * buf, u16 len)
 764 {
 765         return FLEXI2C_read(adapter, 0x20000000, 0x50, addr, buf, len);
 766 }
 767
 768 u8 calc_LRC(u8 * buf, u32 len)
 769 {
 770         u32 i;
 771         u8 sum;
 772
 773         sum = 0;
 774
 775         for (i = 0; i < len; i++)
 776                 sum = sum ^ buf[i];
 777
 778         return sum;
 779 }
 780
 781 static int EEPROM_LRC_read(struct adapter *adapter, u32 addr, u32 len, u8 * buf, u32 retries)
 782 {
 783         int i;
 784
 785         for (i = 0; i < retries; i++) {
 786                 if (EEPROM_read(adapter, addr, buf, len) == len) {
 787                         if (calc_LRC(buf, len - 1) == buf[len - 1])
 788                                 return 1;
 789                 }
 790         }
 791
 792         return 0;
 793 }
 794
 795 /*
 796 static int EEPROM_LRC_write(struct adapter *adapter, u32 addr, u32 len, u8 * wbuf, u8 * rbuf, u32 retries)
 797 {
 798         int i;
 799
 800         for (i = 0; i < retries; i++) {
 801                 if (EEPROM_write(adapter, addr, wbuf, len) == len) {
 802                         if (EEPROM_LRC_read(adapter, addr, len, rbuf, retries) == 1)
 803                                 return 1;
 804                 }
 805         }
 806
 807         return 0;
 808 }
 809 */
 810
 811 /* These functions could be called from the initialization routine
 812    to unlock SkyStar2 cards, locked by "Europe On Line".
 813
 814    in cards from "Europe On Line" the key is:
 815
 816        u8 key[20] = {
 817             0xB2, 0x01, 0x00, 0x00,
 818             0x00, 0x00, 0x00, 0x00,
 819             0x00, 0x00, 0x00, 0x00,
 820             0x00, 0x00, 0x00, 0x00,
 821        };
 822
 823        LRC = 0xB3;
 824
 825   in unlocked cards the key is:
 826
 827        u8 key[20] = {
 828             0xB2, 0x00, 0x00, 0x00,
 829             0x00, 0x00, 0x00, 0x00,
 830             0x00, 0x00, 0x00, 0x00,
 831             0x00, 0x00, 0x00, 0x00,
 832        };
 833
 834       LRC = 0xB2;
 835 */
 836 /*
 837 static int EEPROM_writeKey(struct adapter *adapter, u8 * key, u32 len)
 838 {
 839         u8 rbuf[20];
 840         u8 wbuf[20];
 841
 842         if (len != 16)
 843                 return 0;
 844
 845         memcpy(wbuf, key, len);
 846
 847         wbuf[16] = 0;
 848         wbuf[17] = 0;
 849         wbuf[18] = 0;
 850         wbuf[19] = calc_LRC(wbuf, 19);
 851
 852         return EEPROM_LRC_write(adapter, 0x3E4, 20, wbuf, rbuf, 4);
 853 }
 854 */
 855 static int EEPROM_readKey(struct adapter *adapter, u8 * key, u32 len)
 856 {
 857         u8 buf[20];
 858
 859         if (len != 16)
 860                 return 0;
 861
 862         if (EEPROM_LRC_read(adapter, 0x3E4, 20, buf, 4) == 0)
 863                 return 0;
 864
 865         memcpy(key, buf, len);
 866
 867         return 1;
 868 }
 869
 870 static int EEPROM_getMacAddr(struct adapter *adapter, char type, u8 * mac)
 871 {
 872         u8 tmp[8];
 873
 874         if (EEPROM_LRC_read(adapter, 0x3F8, 8, tmp, 4) != 0) {
 875                 if (type != 0) {
 876                         mac[0] = tmp[0];
 877                         mac[1] = tmp[1];
 878                         mac[2] = tmp[2];
 879                         mac[3] = 0xFE;
 880                         mac[4] = 0xFF;
 881                         mac[5] = tmp[3];
 882                         mac[6] = tmp[4];
 883                         mac[7] = tmp[5];
 884
 885                 } else {
 886
 887                         mac[0] = tmp[0];
 888                         mac[1] = tmp[1];
 889                         mac[2] = tmp[2];
 890                         mac[3] = tmp[3];
 891                         mac[4] = tmp[4];
 892                         mac[5] = tmp[5];
 893                 }
 894
 895                 return 1;
 896
 897         } else {
 898
 899                 if (type == 0) {
 900                         memset(mac, 0, 6);
 901
 902                 } else {
 903
 904                         memset(mac, 0, 8);
 905                 }
 906
 907                 return 0;
 908         }
 909 }
 910
 911 /*
 912 static char EEPROM_setMacAddr(struct adapter *adapter, char type, u8 * mac)
 913 {
 914         u8 tmp[8];
 915
 916         if (type != 0) {
 917                 tmp[0] = mac[0];
 918                 tmp[1] = mac[1];
 919                 tmp[2] = mac[2];
 920                 tmp[3] = mac[5];
 921                 tmp[4] = mac[6];
 922                 tmp[5] = mac[7];
 923
 924         } else {
 925
 926                 tmp[0] = mac[0];
 927                 tmp[1] = mac[1];
 928                 tmp[2] = mac[2];
 929                 tmp[3] = mac[3];
 930                 tmp[4] = mac[4];
 931                 tmp[5] = mac[5];
 932         }
 933
 934         tmp[6] = 0;
 935         tmp[7] = calc_LRC(tmp, 7);
 936
 937         if (EEPROM_write(adapter, 0x3F8, tmp, 8) == 8)
 938                 return 1;
 939
 940         return 0;
 941 }
 942 */
 943
 944 /* PID filter */
 945 static void FilterEnableStream1Filter(struct adapter *adapter, u32 op)
 946 {
 947         dprintk("%s: op=%x\n", __FUNCTION__, op);
 948
 949         if (op == 0) {
 950                 WriteRegOp(adapter, 0x208, 2, ~0x00000001, 0);
 951
 952         } else {
 953
 954                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000001);
 955         }
 956 }
 957
 958 static void FilterEnableStream2Filter(struct adapter *adapter, u32 op)
 959 {
 960         dprintk("%s: op=%x\n", __FUNCTION__, op);
 961
 962         if (op == 0) {
 963                 WriteRegOp(adapter, 0x208, 2, ~0x00000002, 0);
 964
 965         } else {
 966
 967                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000002);
 968         }
 969 }
 970
 971 static void FilterEnablePcrFilter(struct adapter *adapter, u32 op)
 972 {
 973         dprintk("%s: op=%x\n", __FUNCTION__, op);
 974
 975         if (op == 0) {
 976                 WriteRegOp(adapter, 0x208, 2, ~0x00000004, 0);
 977
 978         } else {
 979
 980                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000004);
 981         }
 982 }
 983
 984 static void FilterEnablePmtFilter(struct adapter *adapter, u32 op)
 985 {
 986         dprintk("%s: op=%x\n", __FUNCTION__, op);
 987
 988         if (op == 0) {
 989                 WriteRegOp(adapter, 0x208, 2, ~0x00000008, 0);
 990
 991         } else {
 992
 993                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000008);
 994         }
 995 }
 996
 997 static void FilterEnableEmmFilter(struct adapter *adapter, u32 op)
 998 {
 999         dprintk("%s: op=%x\n", __FUNCTION__, op);
1000
1001         if (op == 0) {
1002                 WriteRegOp(adapter, 0x208, 2, ~0x00000010, 0);
1003
1004         } else {
1005
1006                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000010);
1007         }
1008 }
1009
1010 static void FilterEnableEcmFilter(struct adapter *adapter, u32 op)
1011 {
1012         dprintk("%s: op=%x\n", __FUNCTION__, op);
1013
1014         if (op == 0) {
1015                 WriteRegOp(adapter, 0x208, 2, ~0x00000020, 0);
1016
1017         } else {
1018
1019                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000020);
1020         }
1021 }
1022
1023 /*
1024 static void FilterEnableNullFilter(struct adapter *adapter, u32 op)
1025 {
1026         dprintk("%s: op=%x\n", __FUNCTION__, op);
1027
1028         if (op == 0) {
1029                 WriteRegOp(adapter, 0x208, 2, ~0x00000040, 0);
1030
1031         } else {
1032
1033                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000040);
1034         }
1035 }
1036 */
1037
1038 static void FilterEnableMaskFilter(struct adapter *adapter, u32 op)
1039 {
1040         dprintk("%s: op=%x\n", __FUNCTION__, op);
1041
1042         if (op == 0) {
1043                 WriteRegOp(adapter, 0x208, 2, ~0x00000080, 0);
1044
1045         } else {
1046
1047                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000080);
1048         }
1049 }
1050
1051
1052 static void CtrlEnableMAC(struct adapter *adapter, u32 op)
1053 {
1054         if (op == 0) {
1055                 WriteRegOp(adapter, 0x208, 2, ~0x00004000, 0);
1056
1057         } else {
1058
1059                 WriteRegOp(adapter, 0x208, 1, 0, 0x00004000);
1060         }
1061 }
1062
1063 static int CASetMacDstAddrFilter(struct adapter *adapter, u8 * mac)
1064 {
1065         u32 tmp1, tmp2;
1066
1067         tmp1 = (mac[3] << 0x18) | (mac[2] << 0x10) | (mac[1] << 0x08) | mac[0];
1068         tmp2 = (mac[5] << 0x08) | mac[4];
1069
1070         WriteRegDW(adapter, 0x418, tmp1);
1071         WriteRegDW(adapter, 0x41C, tmp2);
1072
1073         return 0;
1074 }
1075
1076 /*
1077 static void SetIgnoreMACFilter(struct adapter *adapter, u8 op)
1078 {
1079         if (op != 0) {
1080                 WriteRegOp(adapter, 0x208, 2, ~0x00004000, 0);
1081
1082                 adapter->mac_filter = 1;
1083
1084         } else {
1085
1086                 if (adapter->mac_filter != 0) {
1087                         adapter->mac_filter = 0;
1088
1089                         WriteRegOp(adapter, 0x208, 1, 0, 0x00004000);
1090                 }
1091         }
1092 }
1093 */
1094
1095 /*
1096 static void CheckNullFilterEnable(struct adapter *adapter)
1097 {
1098         FilterEnableNullFilter(adapter, 1);
1099         FilterEnableMaskFilter(adapter, 1);
1100 }
1101 */
1102
1103 static void InitPIDsInfo(struct adapter *adapter)
1104 {
1105         int i;
1106
1107         for (i = 0; i < 0x27; i++)
1108                 adapter->pids[i] = 0x1FFF;
1109 }
1110
1111 static int CheckPID(struct adapter *adapter, u16 pid)
1112 {
1113         u32 i;
1114
1115         if (pid == 0x1FFF)
1116                 return 0;
1117
1118         for (i = 0; i < 0x27; i++) {
1119                 if (adapter->pids[i] == pid)
1120                         return 1;
1121         }
1122
1123         return 0;
1124 }
1125
1126 static void PidSetGroupPID(struct adapter * adapter, u32 pid)
1127 {
1128         u32 value;
1129
1130         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1131
1132         value = (pid & 0x3FFF) | (ReadRegDW(adapter, 0x30C) & 0xFFFF0000);
1133
1134         WriteRegDW(adapter, 0x30C, value);
1135
1136         /* return value is never used? */
1137 /*      return value; */
1138 }
1139
1140 static void PidSetGroupMASK(struct adapter * adapter, u32 pid)
1141 {
1142         u32 value;
1143
1144         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1145
1146         value = ((pid & 0x3FFF) << 0x10) | (ReadRegDW(adapter, 0x30C) & 0xFFFF);
1147
1148         WriteRegDW(adapter, 0x30C, value);
1149
1150         /* return value is never used? */
1151 /*      return value; */
1152 }
1153
1154 static void PidSetStream1PID(struct adapter * adapter, u32 pid)
1155 {
1156         u32 value;
1157
1158         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1159
1160         value = (pid & 0x3FFF) | (ReadRegDW(adapter, 0x300) & 0xFFFFC000);
1161
1162         WriteRegDW(adapter, 0x300, value);
1163
1164         /* return value is never used? */
1165 /*      return value; */
1166 }
1167
1168 static void PidSetStream2PID(struct adapter * adapter, u32 pid)
1169 {
1170         u32 value;
1171
1172         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1173
1174         value = ((pid & 0x3FFF) << 0x10) | (ReadRegDW(adapter, 0x300) & 0xFFFF);
1175
1176         WriteRegDW(adapter, 0x300, value);
1177
1178         /* return value is never used? */
1179 /*      return value; */
1180 }
1181
1182 static void PidSetPcrPID(struct adapter * adapter, u32 pid)
1183 {
1184         u32 value;
1185
1186         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1187
1188         value = (pid & 0x3FFF) | (ReadRegDW(adapter, 0x304) & 0xFFFFC000);
1189
1190         WriteRegDW(adapter, 0x304, value);
1191
1192         /* return value is never used? */
1193 /*      return value; */
1194 }
1195
1196 static void PidSetPmtPID(struct adapter * adapter, u32 pid)
1197 {
1198         u32 value;
1199
1200         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1201
1202         value = ((pid & 0x3FFF) << 0x10) | (ReadRegDW(adapter, 0x304) & 0x3FFF);
1203
1204         WriteRegDW(adapter, 0x304, value);
1205
1206         /* return value is never used? */
1207 /*      return value; */
1208 }
1209
1210 static void PidSetEmmPID(struct adapter * adapter, u32 pid)
1211 {
1212         u32 value;
1213
1214         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1215
1216         value = (pid & 0xFFFF) | (ReadRegDW(adapter, 0x308) & 0xFFFF0000);
1217
1218         WriteRegDW(adapter, 0x308, value);
1219
1220         /* return value is never used? */
1221 /*      return value; */
1222 }
1223
1224 static void PidSetEcmPID(struct adapter * adapter, u32 pid)
1225 {
1226         u32 value;
1227
1228         dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1229
1230         value = (pid << 0x10) | (ReadRegDW(adapter, 0x308) & 0xFFFF);
1231
1232         WriteRegDW(adapter, 0x308, value);
1233
1234         /* return value is never used? */
1235 /*      return value; */
1236 }
1237
1238 static int PidGetStream1PID(struct adapter * adapter)
1239 {
1240         return ReadRegDW(adapter, 0x300) & 0x00001FFF;
1241 }
1242
1243 static int PidGetStream2PID(struct adapter * adapter)
1244 {
1245         return (ReadRegDW(adapter, 0x300) >> 0x10)& 0x00001FFF;
1246 }
1247
1248 static int PidGetPcrPID(struct adapter * adapter)
1249 {
1250         return ReadRegDW(adapter, 0x304) & 0x00001FFF;
1251 }
1252
1253 static int PidGetPmtPID(struct adapter * adapter)
1254 {
1255         return (ReadRegDW(adapter, 0x304) >> 0x10)& 0x00001FFF;
1256 }
1257
1258 static int PidGetEmmPID(struct adapter * adapter)
1259 {
1260         return ReadRegDW(adapter, 0x308) & 0x00001FFF;
1261 }
1262
1263 static int PidGetEcmPID(struct adapter * adapter)
1264 {
1265         return (ReadRegDW(adapter, 0x308) >> 0x10)& 0x00001FFF;
1266 }
1267
1268 static int PidGetGroupPID(struct adapter * adapter)
1269 {
1270         return ReadRegDW(adapter, 0x30C) & 0x00001FFF;
1271 }
1272
1273 static int PidGetGroupMASK(struct adapter * adapter)
1274 {
1275         return (ReadRegDW(adapter, 0x30C) >> 0x10)& 0x00001FFF;
1276 }
1277
1278 /*
1279 static void ResetHardwarePIDFilter(struct adapter *adapter)
1280 {
1281         PidSetStream1PID(adapter, 0x1FFF);
1282
1283         PidSetStream2PID(adapter, 0x1FFF);
1284         FilterEnableStream2Filter(adapter, 0);
1285
1286         PidSetPcrPID(adapter, 0x1FFF);
1287         FilterEnablePcrFilter(adapter, 0);
1288
1289         PidSetPmtPID(adapter, 0x1FFF);
1290         FilterEnablePmtFilter(adapter, 0);
1291
1292         PidSetEcmPID(adapter, 0x1FFF);
1293         FilterEnableEcmFilter(adapter, 0);
1294
1295         PidSetEmmPID(adapter, 0x1FFF);
1296         FilterEnableEmmFilter(adapter, 0);
1297 }
1298 */
1299
1300 static void OpenWholeBandwidth(struct adapter *adapter)
1301 {
1302         PidSetGroupPID(adapter, 0);
1303
1304         PidSetGroupMASK(adapter, 0);
1305
1306         FilterEnableMaskFilter(adapter, 1);
1307 }
1308
1309 static int AddHwPID(struct adapter *adapter, u32 pid)
1310 {
1311         dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1312
1313         if (pid <= 0x1F)
1314                 return 1;
1315
1316         if ((PidGetGroupMASK(adapter) == 0) && (PidGetGroupPID(adapter) == 0))
1317                 return 0;
1318
1319         if (PidGetStream1PID(adapter) == 0x1FFF) {
1320                 PidSetStream1PID(adapter, pid & 0xFFFF);
1321
1322                 FilterEnableStream1Filter(adapter, 1);
1323
1324                 return 1;
1325         }
1326
1327         if (PidGetStream2PID(adapter) == 0x1FFF) {
1328                 PidSetStream2PID(adapter, (pid & 0xFFFF));
1329
1330                 FilterEnableStream2Filter(adapter, 1);
1331
1332                 return 1;
1333         }
1334
1335         if (PidGetPcrPID(adapter) == 0x1FFF) {
1336                 PidSetPcrPID(adapter, (pid & 0xFFFF));
1337
1338                 FilterEnablePcrFilter(adapter, 1);
1339
1340                 return 1;
1341         }
1342
1343         if ((PidGetPmtPID(adapter) & 0x1FFF) == 0x1FFF) {
1344                 PidSetPmtPID(adapter, (pid & 0xFFFF));
1345
1346                 FilterEnablePmtFilter(adapter, 1);
1347
1348                 return 1;
1349         }
1350
1351         if ((PidGetEmmPID(adapter) & 0x1FFF) == 0x1FFF) {
1352                 PidSetEmmPID(adapter, (pid & 0xFFFF));
1353
1354                 FilterEnableEmmFilter(adapter, 1);
1355
1356                 return 1;
1357         }
1358
1359         if ((PidGetEcmPID(adapter) & 0x1FFF) == 0x1FFF) {
1360                 PidSetEcmPID(adapter, (pid & 0xFFFF));
1361
1362                 FilterEnableEcmFilter(adapter, 1);
1363
1364                 return 1;
1365         }
1366
1367         return -1;
1368 }
1369
1370 static int RemoveHwPID(struct adapter *adapter, u32 pid)
1371 {
1372         dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1373
1374         if (pid <= 0x1F)
1375                 return 1;
1376
1377         if (PidGetStream1PID(adapter) == pid) {
1378                 PidSetStream1PID(adapter, 0x1FFF);
1379
1380                 return 1;
1381         }
1382
1383         if (PidGetStream2PID(adapter) == pid) {
1384                 PidSetStream2PID(adapter, 0x1FFF);
1385
1386                 FilterEnableStream2Filter(adapter, 0);
1387
1388                 return 1;
1389         }
1390
1391         if (PidGetPcrPID(adapter) == pid) {
1392                 PidSetPcrPID(adapter, 0x1FFF);
1393
1394                 FilterEnablePcrFilter(adapter, 0);
1395
1396                 return 1;
1397         }
1398
1399         if (PidGetPmtPID(adapter) == pid) {
1400                 PidSetPmtPID(adapter, 0x1FFF);
1401
1402                 FilterEnablePmtFilter(adapter, 0);
1403
1404                 return 1;
1405         }
1406
1407         if (PidGetEmmPID(adapter) == pid) {
1408                 PidSetEmmPID(adapter, 0x1FFF);
1409
1410                 FilterEnableEmmFilter(adapter, 0);
1411
1412                 return 1;
1413         }
1414
1415         if (PidGetEcmPID(adapter) == pid) {
1416                 PidSetEcmPID(adapter, 0x1FFF);
1417
1418                 FilterEnableEcmFilter(adapter, 0);
1419
1420                 return 1;
1421         }
1422
1423         return -1;
1424 }
1425
1426 static int AddPID(struct adapter *adapter, u32 pid)
1427 {
1428         int i;
1429
1430         dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1431
1432         if (pid > 0x1FFE)
1433                 return -1;
1434
1435         if (CheckPID(adapter, pid) == 1)
1436                 return 1;
1437
1438         for (i = 0; i < 0x27; i++) {
1439                 if (adapter->pids[i] == 0x1FFF) // find free pid filter
1440                 {
1441                         adapter->pids[i] = pid;
1442
1443                         if (AddHwPID(adapter, pid) < 0)
1444                                 OpenWholeBandwidth(adapter);
1445
1446                         return 1;
1447                 }
1448         }
1449
1450         return -1;
1451 }
1452
1453 static int RemovePID(struct adapter *adapter, u32 pid)
1454 {
1455         u32 i;
1456
1457         dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1458
1459         if (pid > 0x1FFE)
1460                 return -1;
1461
1462         for (i = 0; i < 0x27; i++) {
1463                 if (adapter->pids[i] == pid) {
1464                         adapter->pids[i] = 0x1FFF;
1465
1466                         RemoveHwPID(adapter, pid);
1467
1468                         return 1;
1469                 }
1470         }
1471
1472         return -1;
1473 }
1474
1475 /* dma & irq */
1476 static void CtrlEnableSmc(struct adapter *adapter, u32 op)
1477 {
1478         if (op == 0) {
1479                 WriteRegOp(adapter, 0x208, 2, ~0x00000800, 0);
1480
1481         } else {
1482
1483                 WriteRegOp(adapter, 0x208, 1, 0, 0x00000800);
1484         }
1485 }
1486
1487 static void DmaEnableDisableIrq(struct adapter *adapter, u32 flag1, u32 flag2, u32 flag3)
1488 {
1489         adapter->dma_ctrl = adapter->dma_ctrl & 0x000F0000;
1490
1491         if (flag1 == 0) {
1492                 if (flag2 == 0)
1493                         adapter->dma_ctrl = adapter->dma_ctrl & ~0x00010000;
1494                 else
1495                         adapter->dma_ctrl = adapter->dma_ctrl | 0x00010000;
1496
1497                 if (flag3 == 0)
1498                         adapter->dma_ctrl = adapter->dma_ctrl & ~0x00020000;
1499                 else
1500                         adapter->dma_ctrl = adapter->dma_ctrl | 0x00020000;
1501
1502         } else {
1503
1504                 if (flag2 == 0)
1505                         adapter->dma_ctrl = adapter->dma_ctrl & ~0x00040000;
1506                 else
1507                         adapter->dma_ctrl = adapter->dma_ctrl | 0x00040000;
1508
1509                 if (flag3 == 0)
1510                         adapter->dma_ctrl = adapter->dma_ctrl & ~0x00080000;
1511                 else
1512                         adapter->dma_ctrl = adapter->dma_ctrl | 0x00080000;
1513         }
1514 }
1515
1516 static void IrqDmaEnableDisableIrq(struct adapter * adapter, u32 op)
1517 {
1518         u32 value;
1519
1520         value = ReadRegDW(adapter, 0x208) & 0xFFF0FFFF;
1521
1522         if (op != 0)
1523                 value = value | (adapter->dma_ctrl & 0x000F0000);
1524
1525         WriteRegDW(adapter, 0x208, value);
1526 }
1527
1528 /* FlexCopII has 2 dma channels. DMA1 is used to transfer TS data to
1529    system memory.
1530
1531    The DMA1 buffer is divided in 2 subbuffers of equal size.
1532    FlexCopII will transfer TS data to one subbuffer, signal an interrupt
1533    when the subbuffer is full and continue fillig the second subbuffer.
1534
1535    For DMA1:
1536        subbuffer size in 32-bit words is stored in the first 24 bits of
1537        register 0x004. The last 8 bits of register 0x004 contain the number
1538        of subbuffers.
1539
1540        the first 30 bits of register 0x000 contain the address of the first
1541        subbuffer. The last 2 bits contain 0, when dma1 is disabled and 1,
1542        when dma1 is enabled.
1543
1544        the first 30 bits of register 0x00C contain the address of the second
1545        subbuffer. the last 2 bits contain 1.
1546
1547        register 0x008 will contain the address of the subbuffer that was filled
1548        with TS data, when FlexCopII will generate an interrupt.
1549
1550    For DMA2:
1551        subbuffer size in 32-bit words is stored in the first 24 bits of
1552        register 0x014. The last 8 bits of register 0x014 contain the number
1553        of subbuffers.
1554
1555        the first 30 bits of register 0x010 contain the address of the first
1556        subbuffer.  The last 2 bits contain 0, when dma1 is disabled and 1,
1557        when dma1 is enabled.
1558
1559        the first 30 bits of register 0x01C contain the address of the second
1560        subbuffer. the last 2 bits contain 1.
1561
1562        register 0x018 contains the address of the subbuffer that was filled
1563        with TS data, when FlexCopII generates an interrupt.
1564 */
1565 static int DmaInitDMA(struct adapter *adapter, u32 dma_channel)
1566 {
1567         u32 subbuffers, subbufsize, subbuf0, subbuf1;
1568
1569         if (dma_channel == 0) {
1570                 dprintk("%s: Initializing DMA1 channel\n", __FUNCTION__);
1571
1572                 subbuffers = 2;
1573
1574                 subbufsize = (((adapter->dmaq1.buffer_size / 2) / 4) << 8) | subbuffers;
1575
1576                 subbuf0 = adapter->dmaq1.bus_addr & 0xFFFFFFFC;
1577
1578                 subbuf1 = ((adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) & 0xFFFFFFFC) | 1;
1579
1580                 dprintk("%s: first subbuffer address = 0x%x\n", __FUNCTION__, subbuf0);
1581                 udelay(1000);
1582                 WriteRegDW(adapter, 0x000, subbuf0);
1583
1584                 dprintk("%s: subbuffer size = 0x%x\n", __FUNCTION__, (subbufsize >> 8) * 4);
1585                 udelay(1000);
1586                 WriteRegDW(adapter, 0x004, subbufsize);
1587
1588                 dprintk("%s: second subbuffer address = 0x%x\n", __FUNCTION__, subbuf1);
1589                 udelay(1000);
1590                 WriteRegDW(adapter, 0x00C, subbuf1);
1591
1592                 dprintk("%s: counter = 0x%x\n", __FUNCTION__, adapter->dmaq1.bus_addr & 0xFFFFFFFC);
1593                 WriteRegDW(adapter, 0x008, adapter->dmaq1.bus_addr & 0xFFFFFFFC);
1594                 udelay(1000);
1595
1596                 if (subbuffers == 0)
1597                         DmaEnableDisableIrq(adapter, 0, 1, 0);
1598                 else
1599                         DmaEnableDisableIrq(adapter, 0, 1, 1);
1600
1601                 IrqDmaEnableDisableIrq(adapter, 1);
1602
1603                 SRAMSetMediaDest(adapter, 1);
1604                 SRAMSetNetDest(adapter, 1);
1605                 SRAMSetCaiDest(adapter, 2);
1606                 SRAMSetCaoDest(adapter, 2);
1607         }
1608
1609         if (dma_channel == 1) {
1610                 dprintk("%s: Initializing DMA2 channel\n", __FUNCTION__);
1611
1612                 subbuffers = 2;
1613
1614                 subbufsize = (((adapter->dmaq2.buffer_size / 2) / 4) << 8) | subbuffers;
1615
1616                 subbuf0 = adapter->dmaq2.bus_addr & 0xFFFFFFFC;
1617
1618                 subbuf1 = ((adapter->dmaq2.bus_addr + adapter->dmaq2.buffer_size / 2) & 0xFFFFFFFC) | 1;
1619
1620                 dprintk("%s: first subbuffer address = 0x%x\n", __FUNCTION__, subbuf0);
1621                 udelay(1000);
1622                 WriteRegDW(adapter, 0x010, subbuf0);
1623
1624                 dprintk("%s: subbuffer size = 0x%x\n", __FUNCTION__, (subbufsize >> 8) * 4);
1625                 udelay(1000);
1626                 WriteRegDW(adapter, 0x014, subbufsize);
1627
1628                 dprintk("%s: second buffer address = 0x%x\n", __FUNCTION__, subbuf1);
1629                 udelay(1000);
1630                 WriteRegDW(adapter, 0x01C, subbuf1);
1631
1632                 SRAMSetCaiDest(adapter, 2);
1633         }
1634
1635         return 0;
1636 }
1637
1638 static void CtrlEnableReceiveData(struct adapter *adapter, u32 op)
1639 {
1640         if (op == 0) {
1641                 WriteRegOp(adapter, 0x208, 2, ~0x00008000, 0);
1642
1643                 adapter->dma_status = adapter->dma_status & ~0x00000004;
1644
1645         } else {
1646
1647                 WriteRegOp(adapter, 0x208, 1, 0, 0x00008000);
1648
1649                 adapter->dma_status = adapter->dma_status | 0x00000004;
1650         }
1651 }
1652
1653 /* bit 0 of dma_mask is set to 1 if dma1 channel has to be enabled/disabled
1654    bit 1 of dma_mask is set to 1 if dma2 channel has to be enabled/disabled
1655 */
1656 static void DmaStartStop0x2102(struct adapter *adapter, u32 dma_mask, u32 start_stop)
1657 {
1658         u32 dma_enable, dma1_enable, dma2_enable;
1659
1660         dprintk("%s: dma_mask=%x\n", __FUNCTION__, dma_mask);
1661
1662         if (start_stop == 1) {
1663                 dprintk("%s: starting dma\n", __FUNCTION__);
1664
1665                 dma1_enable = 0;
1666                 dma2_enable = 0;
1667
1668                 if (((dma_mask & 1) != 0) && ((adapter->dma_status & 1) == 0) && (adapter->dmaq1.bus_addr != 0)) {
1669                         adapter->dma_status = adapter->dma_status | 1;
1670                         dma1_enable = 1;
1671                 }
1672
1673                 if (((dma_mask & 2) != 0) && ((adapter->dma_status & 2) == 0) && (adapter->dmaq2.bus_addr != 0)) {
1674                         adapter->dma_status = adapter->dma_status | 2;
1675                         dma2_enable = 1;
1676                 }
1677                 // enable dma1 and dma2
1678                 if ((dma1_enable == 1) && (dma2_enable == 1)) {
1679                         WriteRegDW(adapter, 0x000, adapter->dmaq1.bus_addr | 1);
1680                         WriteRegDW(adapter, 0x00C, (adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) | 1);
1681                         WriteRegDW(adapter, 0x010, adapter->dmaq2.bus_addr | 1);
1682
1683                         CtrlEnableReceiveData(adapter, 1);
1684
1685                         return;
1686                 }
1687                 // enable dma1
1688                 if ((dma1_enable == 1) && (dma2_enable == 0)) {
1689                         WriteRegDW(adapter, 0x000, adapter->dmaq1.bus_addr | 1);
1690                         WriteRegDW(adapter, 0x00C, (adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) | 1);
1691
1692                         CtrlEnableReceiveData(adapter, 1);
1693
1694                         return;
1695                 }
1696                 // enable dma2
1697                 if ((dma1_enable == 0) && (dma2_enable == 1)) {
1698                         WriteRegDW(adapter, 0x010, adapter->dmaq2.bus_addr | 1);
1699
1700                         CtrlEnableReceiveData(adapter, 1);
1701
1702                         return;
1703                 }
1704                 // start dma
1705                 if ((dma1_enable == 0) && (dma2_enable == 0)) {
1706                         CtrlEnableReceiveData(adapter, 1);
1707
1708                         return;
1709                 }
1710
1711         } else {
1712
1713                 dprintk("%s: stoping dma\n", __FUNCTION__);
1714
1715                 dma_enable = adapter->dma_status & 0x00000003;
1716
1717                 if (((dma_mask & 1) != 0) && ((adapter->dma_status & 1) != 0)) {
1718                         dma_enable = dma_enable & 0xFFFFFFFE;
1719                 }
1720
1721                 if (((dma_mask & 2) != 0) && ((adapter->dma_status & 2) != 0)) {
1722                         dma_enable = dma_enable & 0xFFFFFFFD;
1723                 }
1724                 //stop dma
1725                 if ((dma_enable == 0) && ((adapter->dma_status & 4) != 0)) {
1726                         CtrlEnableReceiveData(adapter, 0);
1727
1728                         udelay(3000);
1729                 }
1730                 //disable dma1
1731                 if (((dma_mask & 1) != 0) && ((adapter->dma_status & 1) != 0) && (adapter->dmaq1.bus_addr != 0)) {
1732                         WriteRegDW(adapter, 0x000, adapter->dmaq1.bus_addr);
1733                         WriteRegDW(adapter, 0x00C, (adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) | 1);
1734
1735                         adapter->dma_status = adapter->dma_status & ~0x00000001;
1736                 }
1737                 //disable dma2
1738                 if (((dma_mask & 2) != 0) && ((adapter->dma_status & 2) != 0) && (adapter->dmaq2.bus_addr != 0)) {
1739                         WriteRegDW(adapter, 0x010, adapter->dmaq2.bus_addr);
1740
1741                         adapter->dma_status = adapter->dma_status & ~0x00000002;
1742                 }
1743         }
1744 }
1745
1746 static void OpenStream(struct adapter *adapter, u32 pid)
1747 {
1748         u32 dma_mask;
1749
1750         if (adapter->capturing == 0)
1751                 adapter->capturing = 1;
1752
1753         FilterEnableMaskFilter(adapter, 1);
1754
1755         AddPID(adapter, pid);
1756
1757         dprintk("%s: adapter->dma_status=%x\n", __FUNCTION__, adapter->dma_status);
1758
1759         if ((adapter->dma_status & 7) != 7) {
1760                 dma_mask = 0;
1761
1762                 if (((adapter->dma_status & 0x10000000) != 0) && ((adapter->dma_status & 1) == 0)) {
1763                         dma_mask = dma_mask | 1;
1764
1765                         adapter->dmaq1.head = 0;
1766                         adapter->dmaq1.tail = 0;
1767
1768                         memset(adapter->dmaq1.buffer, 0, adapter->dmaq1.buffer_size);
1769                 }
1770
1771                 if (((adapter->dma_status & 0x20000000) != 0) && ((adapter->dma_status & 2) == 0)) {
1772                         dma_mask = dma_mask | 2;
1773
1774                         adapter->dmaq2.head = 0;
1775                         adapter->dmaq2.tail = 0;
1776                 }
1777
1778                 if (dma_mask != 0) {
1779                         IrqDmaEnableDisableIrq(adapter, 1);
1780
1781                         DmaStartStop0x2102(adapter, dma_mask, 1);
1782                 }
1783         }
1784 }
1785
1786 static void CloseStream(struct adapter *adapter, u32 pid)
1787 {
1788         u32 dma_mask;
1789
1790         if (adapter->capturing != 0)
1791                 adapter->capturing = 0;
1792
1793         dprintk("%s: dma_status=%x\n", __FUNCTION__, adapter->dma_status);
1794
1795         dma_mask = 0;
1796
1797         if ((adapter->dma_status & 1) != 0)
1798                 dma_mask = dma_mask | 0x00000001;
1799         if ((adapter->dma_status & 2) != 0)
1800                 dma_mask = dma_mask | 0x00000002;
1801
1802         if (dma_mask != 0) {
1803                 DmaStartStop0x2102(adapter, dma_mask, 0);
1804         }
1805
1806         RemovePID(adapter, pid);
1807 }
1808
1809 static void InterruptServiceDMA1(struct adapter *adapter)
1810 {
1811         struct dvb_demux *dvbdmx = &adapter->demux;
1812         struct packet_header packet_header;
1813
1814         int nCurDmaCounter;
1815         u32 nNumBytesParsed;
1816         u32 nNumNewBytesTransferred;
1817         u32 dwDefaultPacketSize = 188;
1818         u8 gbTmpBuffer[188];
1819         u8 *pbDMABufCurPos;
1820
1821         nCurDmaCounter = readl(adapter->io_mem + 0x008) - adapter->dmaq1.bus_addr;
1822         nCurDmaCounter = (nCurDmaCounter / dwDefaultPacketSize) * dwDefaultPacketSize;
1823
1824         if ((nCurDmaCounter < 0) || (nCurDmaCounter > adapter->dmaq1.buffer_size)) {
1825                 dprintk("%s: dma counter outside dma buffer\n", __FUNCTION__);
1826                 return;
1827         }
1828
1829         adapter->dmaq1.head = nCurDmaCounter;
1830
1831         if (adapter->dmaq1.tail <= nCurDmaCounter) {
1832                 nNumNewBytesTransferred = nCurDmaCounter - adapter->dmaq1.tail;
1833
1834         } else {
1835
1836                 nNumNewBytesTransferred = (adapter->dmaq1.buffer_size - adapter->dmaq1.tail) + nCurDmaCounter;
1837         }
1838
1839 //  dprintk("%s: nCurDmaCounter   = %d\n" , __FUNCTION__, nCurDmaCounter);
1840 //      dprintk("%s: dmaq1.tail       = %d\n" , __FUNCTION__, adapter->dmaq1.tail):
1841 //  dprintk("%s: BytesTransferred = %d\n" , __FUNCTION__, nNumNewBytesTransferred);
1842
1843         if (nNumNewBytesTransferred < dwDefaultPacketSize)
1844                 return;
1845
1846         nNumBytesParsed = 0;
1847
1848         while (nNumBytesParsed < nNumNewBytesTransferred) {
1849                 pbDMABufCurPos = adapter->dmaq1.buffer + adapter->dmaq1.tail;
1850
1851                 if (adapter->dmaq1.buffer + adapter->dmaq1.buffer_size < adapter->dmaq1.buffer + adapter->dmaq1.tail + 188) {
1852                         memcpy(gbTmpBuffer, adapter->dmaq1.buffer + adapter->dmaq1.tail, adapter->dmaq1.buffer_size - adapter->dmaq1.tail);
1853                         memcpy(gbTmpBuffer + (adapter->dmaq1.buffer_size - adapter->dmaq1.tail), adapter->dmaq1.buffer, (188 - (adapter->dmaq1.buffer_size - adapter->dmaq1.tail)));
1854
1855                         pbDMABufCurPos = gbTmpBuffer;
1856                 }
1857
1858                 if (adapter->capturing != 0) {
1859                         u32 *dq = (u32 *) pbDMABufCurPos;
1860
1861                         packet_header.sync_byte = *dq & 0x000000FF;
1862                         packet_header.transport_error_indicator = *dq & 0x00008000;
1863                         packet_header.payload_unit_start_indicator = *dq & 0x00004000;
1864                         packet_header.transport_priority = *dq & 0x00002000;
1865                         packet_header.pid = ((*dq & 0x00FF0000) >> 0x10) | (*dq & 0x00001F00);
1866                         packet_header.transport_scrambling_control = *dq >> 0x1E;
1867                         packet_header.adaptation_field_control = (*dq & 0x30000000) >> 0x1C;
1868                         packet_header.continuity_counter = (*dq & 0x0F000000) >> 0x18;
1869
1870                         if ((packet_header.sync_byte == 0x47) && (packet_header.transport_error_indicator == 0) && (packet_header.pid != 0x1FFF)) {
1871                                 if (CheckPID(adapter, packet_header.pid & 0x0000FFFF) != 0) {
1872                                         dvb_dmx_swfilter_packets(dvbdmx, pbDMABufCurPos, dwDefaultPacketSize / 188);
1873
1874                                 } else {
1875
1876 //                  dprintk("%s: pid=%x\n", __FUNCTION__, packet_header.pid);
1877                                 }
1878                         }
1879                 }
1880
1881                 nNumBytesParsed = nNumBytesParsed + dwDefaultPacketSize;
1882
1883                 adapter->dmaq1.tail = adapter->dmaq1.tail + dwDefaultPacketSize;
1884
1885                 if (adapter->dmaq1.tail >= adapter->dmaq1.buffer_size)
1886                         adapter->dmaq1.tail = adapter->dmaq1.tail - adapter->dmaq1.buffer_size;
1887         };
1888 }
1889
1890 static void InterruptServiceDMA2(struct adapter *adapter)
1891 {
1892         printk("%s:\n", __FUNCTION__);
1893 }
1894
1895 static irqreturn_t isr(int irq, void *dev_id, struct pt_regs *regs)
1896 {
1897         struct adapter *tmp = dev_id;
1898
1899         u32 value;
1900
1901 //  dprintk("%s:\n", __FUNCTION__);
1902
1903         spin_lock_irq(&tmp->lock);
1904
1905         if (0 == ((value = ReadRegDW(tmp, 0x20C)) & 0x0F)) {
1906                 spin_unlock_irq(&tmp->lock);
1907                 return IRQ_NONE;
1908         }
1909
1910         while (value != 0) {
1911                 if ((value & 0x03) != 0)
1912                         InterruptServiceDMA1(tmp);
1913                 if ((value & 0x0C) != 0)
1914                         InterruptServiceDMA2(tmp);
1915                 value = ReadRegDW(tmp, 0x20C) & 0x0F;
1916         }
1917
1918         spin_unlock_irq(&tmp->lock);
1919         return IRQ_HANDLED;
1920 }
1921
1922 static void Initdmaqueue(struct adapter *adapter)
1923 {
1924         dma_addr_t dma_addr;
1925
1926         if (adapter->dmaq1.buffer != 0)
1927                 return;
1928
1929         adapter->dmaq1.head = 0;
1930         adapter->dmaq1.tail = 0;
1931         adapter->dmaq1.buffer = 0;
1932
1933         adapter->dmaq1.buffer = pci_alloc_consistent(adapter->pdev, SizeOfBufDMA1 + 0x80, &dma_addr);
1934
1935         if (adapter->dmaq1.buffer != 0) {
1936                 memset(adapter->dmaq1.buffer, 0, SizeOfBufDMA1);
1937
1938                 adapter->dmaq1.bus_addr = dma_addr;
1939                 adapter->dmaq1.buffer_size = SizeOfBufDMA1;
1940
1941                 DmaInitDMA(adapter, 0);
1942
1943                 adapter->dma_status = adapter->dma_status | 0x10000000;
1944
1945                 dprintk("%s: allocated dma buffer at 0x%x, length=%d\n", __FUNCTION__, (int) adapter->dmaq1.buffer, SizeOfBufDMA1);
1946
1947         } else {
1948
1949                 adapter->dma_status = adapter->dma_status & ~0x10000000;
1950         }
1951
1952         if (adapter->dmaq2.buffer != 0)
1953                 return;
1954
1955         adapter->dmaq2.head = 0;
1956         adapter->dmaq2.tail = 0;
1957         adapter->dmaq2.buffer = 0;
1958
1959         adapter->dmaq2.buffer = pci_alloc_consistent(adapter->pdev, SizeOfBufDMA2 + 0x80, &dma_addr);
1960
1961         if (adapter->dmaq2.buffer != 0) {
1962                 memset(adapter->dmaq2.buffer, 0, SizeOfBufDMA2);
1963
1964                 adapter->dmaq2.bus_addr = dma_addr;
1965                 adapter->dmaq2.buffer_size = SizeOfBufDMA2;
1966
1967                 DmaInitDMA(adapter, 1);
1968
1969                 adapter->dma_status = adapter->dma_status | 0x20000000;
1970
1971                 dprintk("%s: allocated dma buffer at 0x%x, length=%d\n", __FUNCTION__, (int) adapter->dmaq2.buffer, (int) SizeOfBufDMA2);
1972
1973         } else {
1974
1975                 adapter->dma_status = adapter->dma_status & ~0x20000000;
1976         }
1977 }
1978
1979 static void Freedmaqueue(struct adapter *adapter)
1980 {
1981         if (adapter->dmaq1.buffer != 0) {
1982                 pci_free_consistent(adapter->pdev, SizeOfBufDMA1 + 0x80, adapter->dmaq1.buffer, adapter->dmaq1.bus_addr);
1983
1984                 adapter->dmaq1.bus_addr = 0;
1985                 adapter->dmaq1.head = 0;
1986                 adapter->dmaq1.tail = 0;
1987                 adapter->dmaq1.buffer_size = 0;
1988                 adapter->dmaq1.buffer = 0;
1989         }
1990
1991         if (adapter->dmaq2.buffer != 0) {
1992                 pci_free_consistent(adapter->pdev, SizeOfBufDMA2 + 0x80, adapter->dmaq2.buffer, adapter->dmaq2.bus_addr);
1993
1994                 adapter->dmaq2.bus_addr = 0;
1995                 adapter->dmaq2.head = 0;
1996                 adapter->dmaq2.tail = 0;
1997                 adapter->dmaq2.buffer_size = 0;
1998                 adapter->dmaq2.buffer = 0;
1999         }
2000 }
2001
2002 static void FreeAdapterObject(struct adapter *adapter)
2003 {
2004         dprintk("%s:\n", __FUNCTION__);
2005
2006         CloseStream(adapter, 0);
2007
2008         if (adapter->irq != 0)
2009                 free_irq(adapter->irq, adapter);
2010
2011         Freedmaqueue(adapter);
2012
2013         if (adapter->io_mem != 0)
2014                 iounmap((void *) adapter->io_mem);
2015
2016         if (adapter != 0)
2017                 kfree(adapter);
2018 }
2019
2020 static struct pci_driver skystar2_pci_driver;
2021
2022 static int ClaimAdapter(struct adapter *adapter)
2023 {
2024         struct pci_dev *pdev = adapter->pdev;
2025
2026         u16 var;
2027
2028         if (!request_region(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1), skystar2_pci_driver.name))
2029                 return -EBUSY;
2030
2031         if (!request_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0), skystar2_pci_driver.name))
2032                 return -EBUSY;
2033
2034         pci_read_config_byte(pdev, PCI_CLASS_REVISION, &adapter->card_revision);
2035
2036         dprintk("%s: card revision %x \n", __FUNCTION__, adapter->card_revision);
2037
2038         if (pci_enable_device(pdev))
2039                 return -EIO;
2040
2041         pci_read_config_word(pdev, 4, &var);
2042
2043         if ((var & 4) == 0)
2044                 pci_set_master(pdev);
2045
2046         adapter->io_port = pdev->resource[1].start;
2047
2048         adapter->io_mem = (u32) ioremap(pdev->resource[0].start, 0x800);
2049
2050         if (adapter->io_mem == 0) {
2051                 dprintk("%s: can not map io memory\n", __FUNCTION__);
2052
2053                 return 2;
2054         }
2055
2056         dprintk("%s: io memory maped at %x\n", __FUNCTION__, adapter->io_mem);
2057
2058         return 1;
2059 }
2060
2061 /*
2062 static int SLL_reset_FlexCOP(struct adapter *adapter)
2063 {
2064         WriteRegDW(adapter, 0x208, 0);
2065         WriteRegDW(adapter, 0x210, 0xB2FF);
2066
2067         return 0;
2068 }
2069 */
2070
2071 static int DriverInitialize(struct pci_dev * pdev)
2072 {
2073         struct adapter *adapter;
2074         u32 tmp;
2075         u8 key[16];
2076
2077         if (!(adapter = kmalloc(sizeof(struct adapter), GFP_KERNEL))) {
2078                 dprintk("%s: out of memory!\n", __FUNCTION__);
2079
2080                 return -ENOMEM;
2081         }
2082
2083         memset(adapter, 0, sizeof(struct adapter));
2084
2085         pci_set_drvdata(pdev,adapter);
2086
2087         adapter->pdev = pdev;
2088         adapter->irq = pdev->irq;
2089
2090         if ((ClaimAdapter(adapter)) != 1) {
2091                 FreeAdapterObject(adapter);
2092
2093                 return -ENODEV;
2094         }
2095
2096         IrqDmaEnableDisableIrq(adapter, 0);
2097
2098         if (request_irq(pdev->irq, isr, 0x4000000, "Skystar2", adapter) != 0) {
2099                 dprintk("%s: unable to allocate irq=%d !\n", __FUNCTION__, pdev->irq);
2100
2101                 FreeAdapterObject(adapter);
2102
2103                 return -ENODEV;
2104         }
2105
2106         ReadRegDW(adapter, 0x208);
2107         WriteRegDW(adapter, 0x208, 0);
2108         WriteRegDW(adapter, 0x210, 0xB2FF);
2109         WriteRegDW(adapter, 0x208, 0x40);
2110
2111         InitPIDsInfo(adapter);
2112
2113         PidSetGroupPID(adapter, 0);
2114         PidSetGroupMASK(adapter, 0x1FE0);
2115         PidSetStream1PID(adapter, 0x1FFF);
2116         PidSetStream2PID(adapter, 0x1FFF);
2117         PidSetPmtPID(adapter, 0x1FFF);
2118         PidSetPcrPID(adapter, 0x1FFF);
2119         PidSetEcmPID(adapter, 0x1FFF);
2120         PidSetEmmPID(adapter, 0x1FFF);
2121
2122         Initdmaqueue(adapter);
2123
2124         if ((adapter->dma_status & 0x30000000) == 0) {
2125                 FreeAdapterObject(adapter);
2126
2127                 return -ENODEV;
2128         }
2129
2130         adapter->b2c2_revision = (ReadRegDW(adapter, 0x204) >> 0x18);
2131
2132         if ((adapter->b2c2_revision != 0x82) && (adapter->b2c2_revision != 0xC3))
2133                 if (adapter->b2c2_revision != 0x82) {
2134                         dprintk("%s: The revision of the FlexCopII chip on your card is - %d\n", __FUNCTION__, adapter->b2c2_revision);
2135                         dprintk("%s: This driver works now only with FlexCopII(rev.130) and FlexCopIIB(rev.195).\n", __FUNCTION__);
2136
2137                         FreeAdapterObject(adapter);
2138
2139                         return -ENODEV;
2140                 }
2141
2142         tmp = ReadRegDW(adapter, 0x204);
2143
2144         WriteRegDW(adapter, 0x204, 0);
2145         mdelay(20);
2146
2147         WriteRegDW(adapter, 0x204, tmp);
2148         mdelay(10);
2149
2150         tmp = ReadRegDW(adapter, 0x308);
2151         WriteRegDW(adapter, 0x308, 0x4000 | tmp);
2152
2153         adapter->dwSramType = 0x10000;
2154
2155         SLL_detectSramSize(adapter);
2156
2157         dprintk("%s sram length = %d, sram type= %x\n", __FUNCTION__, SRAM_length(adapter), adapter->dwSramType);
2158
2159         SRAMSetMediaDest(adapter, 1);
2160         SRAMSetNetDest(adapter, 1);
2161
2162         CtrlEnableSmc(adapter, 0);
2163
2164         SRAMSetCaiDest(adapter, 2);
2165         SRAMSetCaoDest(adapter, 2);
2166
2167         DmaEnableDisableIrq(adapter, 1, 0, 0);
2168
2169         if (EEPROM_getMacAddr(adapter, 0, adapter->mac_addr) != 0) {
2170                 printk("%s MAC address = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x \n", __FUNCTION__, adapter->mac_addr[0], adapter->mac_addr[1], adapter->mac_addr[2], adapter->mac_addr[3], adapter->mac_addr[4], adapter->mac_addr[5], adapter->mac_addr[6], adapter->mac_addr[7]
2171                     );
2172
2173                 CASetMacDstAddrFilter(adapter, adapter->mac_addr);
2174                 CtrlEnableMAC(adapter, 1);
2175         }
2176
2177         EEPROM_readKey(adapter, key, 16);
2178
2179         printk("%s key = \n %02x %02x %02x %02x \n %02x %02x %02x %02x \n %02x %02x %02x %02x \n %02x %02x %02x %02x \n", __FUNCTION__, key[0], key[1], key[2], key[3], key[4], key[5], key[6], key[7], key[8], key[9], key[10], key[11], key[12], key[13], key[14], key[15]);
2180
2181         adapter->lock = SPIN_LOCK_UNLOCKED;
2182
2183         return 0;
2184 }
2185
2186 static void DriverHalt(struct pci_dev *pdev)
2187 {
2188         struct adapter *adapter;
2189
2190         adapter = pci_get_drvdata(pdev);
2191
2192         IrqDmaEnableDisableIrq(adapter, 0);
2193
2194         CtrlEnableReceiveData(adapter, 0);
2195
2196         FreeAdapterObject(adapter);
2197
2198         pci_set_drvdata(pdev, NULL);
2199
2200         release_region(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
2201
2202         release_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
2203 }
2204
2205 static int dvb_start_feed(struct dvb_demux_feed *dvbdmxfeed)
2206 {
2207         struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
2208         struct adapter *adapter = (struct adapter *) dvbdmx->priv;
2209
2210         dprintk("%s: PID=%d, type=%d\n", __FUNCTION__, dvbdmxfeed->pid, dvbdmxfeed->type);
2211
2212         OpenStream(adapter, dvbdmxfeed->pid);
2213
2214         return 0;
2215 }
2216
2217 static int dvb_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
2218 {
2219         struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
2220         struct adapter *adapter = (struct adapter *) dvbdmx->priv;
2221
2222         dprintk("%s: PID=%d, type=%d\n", __FUNCTION__, dvbdmxfeed->pid, dvbdmxfeed->type);
2223
2224         CloseStream(adapter, dvbdmxfeed->pid);
2225
2226         return 0;
2227 }
2228
2229 /* lnb control */
2230 static void set_tuner_tone(struct adapter *adapter, u8 tone)
2231 {
2232         u16 wzHalfPeriodFor45MHz[] = { 0x01FF, 0x0154, 0x00FF, 0x00CC };
2233         u16 ax;
2234
2235         dprintk("%s: %u\n", __FUNCTION__, tone);
2236
2237         switch (tone) {
2238         case 1:
2239                 ax = wzHalfPeriodFor45MHz[0];
2240                 break;
2241         case 2:
2242                 ax = wzHalfPeriodFor45MHz[1];
2243                 break;
2244         case 3:
2245                 ax = wzHalfPeriodFor45MHz[2];
2246                 break;
2247         case 4:
2248                 ax = wzHalfPeriodFor45MHz[3];
2249                 break;
2250
2251         default:
2252                 ax = 0;
2253         }
2254
2255         if (ax != 0) {
2256                 WriteRegDW(adapter, 0x200, ((ax << 0x0F) + (ax & 0x7FFF)) | 0x40000000);
2257
2258         } else {
2259
2260                 WriteRegDW(adapter, 0x200, 0x40FF8000);
2261         }
2262 }
2263
2264 static void set_tuner_polarity(struct adapter *adapter, u8 polarity)
2265 {
2266         u32 var;
2267
2268         dprintk("%s : polarity = %u \n", __FUNCTION__, polarity);
2269
2270         var = ReadRegDW(adapter, 0x204);
2271
2272         if (polarity == 0) {
2273                 dprintk("%s: LNB power off\n", __FUNCTION__);
2274                 var = var | 1;
2275         };
2276
2277         if (polarity == 1) {
2278                 var = var & ~1;
2279                 var = var & ~4;
2280         };
2281
2282         if (polarity == 2) {
2283                 var = var & ~1;
2284                 var = var | 4;
2285         }
2286
2287         WriteRegDW(adapter, 0x204, var);
2288 }
2289
2290 static int flexcop_diseqc_ioctl(struct dvb_frontend *fe, unsigned int cmd, void *arg)
2291 {
2292         struct adapter *adapter = fe->before_after_data;
2293
2294         switch (cmd) {
2295         case FE_SLEEP:
2296                 {
2297                         printk("%s: FE_SLEEP\n", __FUNCTION__);
2298
2299                         set_tuner_polarity(adapter, 0);
2300
2301                         // return -EOPNOTSUPP, to make DVB core also send "FE_SLEEP" command to frontend.
2302                         return -EOPNOTSUPP;
2303                 }
2304
2305         case FE_SET_VOLTAGE:
2306                 {
2307                         dprintk("%s: FE_SET_VOLTAGE\n", __FUNCTION__);
2308
2309                         switch ((fe_sec_voltage_t) arg) {
2310                         case SEC_VOLTAGE_13:
2311
2312                                 printk("%s: SEC_VOLTAGE_13, %x\n", __FUNCTION__, SEC_VOLTAGE_13);
2313
2314                                 set_tuner_polarity(adapter, 1);
2315
2316                                 break;
2317
2318                         case SEC_VOLTAGE_18:
2319
2320                                 printk("%s: SEC_VOLTAGE_18, %x\n", __FUNCTION__, SEC_VOLTAGE_18);
2321
2322                                 set_tuner_polarity(adapter, 2);
2323
2324                                 break;
2325
2326                         default:
2327
2328                                 return -EINVAL;
2329                         };
2330
2331                         break;
2332                 }
2333
2334         case FE_SET_TONE:
2335                 {
2336                         dprintk("%s: FE_SET_TONE\n", __FUNCTION__);
2337
2338                         switch ((fe_sec_tone_mode_t) arg) {
2339                         case SEC_TONE_ON:
2340
2341                                 printk("%s: SEC_TONE_ON, %x\n", __FUNCTION__, SEC_TONE_ON);
2342
2343                                 set_tuner_tone(adapter, 1);
2344
2345                                 break;
2346
2347                         case SEC_TONE_OFF:
2348
2349                                 printk("%s: SEC_TONE_OFF, %x\n", __FUNCTION__, SEC_TONE_OFF);
2350
2351                                 set_tuner_tone(adapter, 0);
2352
2353                                 break;
2354
2355                         default:
2356
2357                                 return -EINVAL;
2358                         };
2359
2360                         break;
2361                 }
2362
2363         default:
2364
2365                 return -EOPNOTSUPP;
2366         };
2367
2368         return 0;
2369 }
2370
2371 static int skystar2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2372 {
2373         struct adapter *adapter;
2374         struct dvb_adapter *dvb_adapter;
2375         struct dvb_demux *dvbdemux;
2376
2377         int ret;
2378
2379         if (pdev == NULL)
2380                 return -ENODEV;
2381
2382         if (DriverInitialize(pdev) != 0)
2383                 return -ENODEV;
2384
2385         dvb_register_adapter(&dvb_adapter, skystar2_pci_driver.name);
2386
2387         if (dvb_adapter == NULL) {
2388                 printk("%s: Error registering DVB adapter\n", __FUNCTION__);
2389
2390                 DriverHalt(pdev);
2391
2392                 return -ENODEV;
2393         }
2394
2395         adapter = (struct adapter *) pci_get_drvdata(pdev);
2396
2397         adapter->dvb_adapter = dvb_adapter;
2398
2399         init_MUTEX(&adapter->i2c_sem);
2400
2401         adapter->i2c_bus = dvb_register_i2c_bus(master_xfer, adapter, adapter->dvb_adapter, 0);
2402
2403         if (!adapter->i2c_bus)
2404                 return -ENOMEM;
2405
2406         dvb_add_frontend_ioctls(adapter->dvb_adapter, flexcop_diseqc_ioctl, NULL, adapter);
2407
2408         dvbdemux = &adapter->demux;
2409
2410         dvbdemux->priv = (void *) adapter;
2411         dvbdemux->filternum = 32;
2412         dvbdemux->feednum = 32;
2413         dvbdemux->start_feed = dvb_start_feed;
2414         dvbdemux->stop_feed = dvb_stop_feed;
2415         dvbdemux->write_to_decoder = 0;
2416         dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING);
2417
2418         dvb_dmx_init(&adapter->demux);
2419
2420         adapter->hw_frontend.source = DMX_FRONTEND_0;
2421
2422         adapter->dmxdev.filternum = 32;
2423         adapter->dmxdev.demux = &dvbdemux->dmx;
2424         adapter->dmxdev.capabilities = 0;
2425
2426         dvb_dmxdev_init(&adapter->dmxdev, adapter->dvb_adapter);
2427
2428         ret = dvbdemux->dmx.add_frontend(&dvbdemux->dmx, &adapter->hw_frontend);
2429         if (ret < 0)
2430                 return ret;
2431
2432         adapter->mem_frontend.source = DMX_MEMORY_FE;
2433
2434         ret = dvbdemux->dmx.add_frontend(&dvbdemux->dmx, &adapter->mem_frontend);
2435         if (ret < 0)
2436                 return ret;
2437
2438         ret = dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, &adapter->hw_frontend);
2439         if (ret < 0)
2440                 return ret;
2441
2442         dvb_net_init(adapter->dvb_adapter, &adapter->dvbnet, &dvbdemux->dmx);
2443         return 0;
2444 }
2445
2446 static void skystar2_remove(struct pci_dev *pdev)
2447 {
2448         struct adapter *adapter;
2449         struct dvb_demux *dvbdemux;
2450
2451         if (pdev == NULL)
2452                 return;
2453
2454         adapter = pci_get_drvdata(pdev);
2455
2456         if (adapter != NULL) {
2457                 dvb_net_release(&adapter->dvbnet);
2458                 dvbdemux = &adapter->demux;
2459
2460                 dvbdemux->dmx.close(&dvbdemux->dmx);
2461                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &adapter->hw_frontend);
2462                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &adapter->mem_frontend);
2463
2464                 dvb_dmxdev_release(&adapter->dmxdev);
2465                 dvb_dmx_release(&adapter->demux);
2466
2467                 if (adapter->dvb_adapter != NULL) {
2468                         dvb_remove_frontend_ioctls(adapter->dvb_adapter, flexcop_diseqc_ioctl, NULL);
2469
2470                         if (adapter->i2c_bus != NULL)
2471                                 dvb_unregister_i2c_bus(master_xfer, adapter->i2c_bus->adapter, adapter->i2c_bus->id);
2472
2473                         dvb_unregister_adapter(adapter->dvb_adapter);
2474                 }
2475
2476                 DriverHalt(pdev);
2477         }
2478 }
2479
2480 static struct pci_device_id skystar2_pci_tbl[] = {
2481         {0x000013D0, 0x00002103, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000},
2482         {0,},
2483 };
2484
2485 static struct pci_driver skystar2_pci_driver = {
2486         .name = "Technisat SkyStar2 driver",
2487         .id_table = skystar2_pci_tbl,
2488         .probe = skystar2_probe,
2489         .remove = skystar2_remove,
2490 };
2491
2492 static int skystar2_init(void)
2493 {
2494         return pci_module_init(&skystar2_pci_driver);
2495 }
2496
2497 static void skystar2_cleanup(void)
2498 {
2499         pci_unregister_driver(&skystar2_pci_driver);
2500 }
2501
2502 module_init(skystar2_init);
2503 module_exit(skystar2_cleanup);
2504
2505 MODULE_DESCRIPTION("Technisat SkyStar2 DVB PCI Driver");
2506 MODULE_LICENSE("GPL");