2 * linux/arch/i386/nmi.c
4 * NMI watchdog support on APIC systems
6 * Started by Ingo Molnar <mingo@redhat.com>
9 * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
10 * Mikael Pettersson : Power Management for local APIC NMI watchdog.
11 * Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog.
13 * Mikael Pettersson : PM converted to driver model. Disable/enable API.
16 #include <linux/config.h>
18 #include <linux/irq.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/smp_lock.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/module.h>
26 #include <linux/nmi.h>
27 #include <linux/sysdev.h>
31 #include <asm/mpspec.h>
34 unsigned int nmi_watchdog = NMI_NONE;
35 static unsigned int nmi_hz = HZ;
36 unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
37 extern void show_registers(struct pt_regs *regs);
40 * +1: the lapic NMI watchdog is active, but can be disabled
41 * 0: the lapic NMI watchdog has not been set up, and cannot
43 * -1: the lapic NMI watchdog is disabled, but can be enabled
45 static int nmi_active;
47 #define K7_EVNTSEL_ENABLE (1 << 22)
48 #define K7_EVNTSEL_INT (1 << 20)
49 #define K7_EVNTSEL_OS (1 << 17)
50 #define K7_EVNTSEL_USR (1 << 16)
51 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
52 #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
54 #define P6_EVNTSEL0_ENABLE (1 << 22)
55 #define P6_EVNTSEL_INT (1 << 20)
56 #define P6_EVNTSEL_OS (1 << 17)
57 #define P6_EVNTSEL_USR (1 << 16)
58 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED 0x79
59 #define P6_NMI_EVENT P6_EVENT_CPU_CLOCKS_NOT_HALTED
61 #define MSR_P4_MISC_ENABLE 0x1A0
62 #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
63 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
64 #define MSR_P4_PERFCTR0 0x300
65 #define MSR_P4_CCCR0 0x360
66 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
67 #define P4_ESCR_OS (1<<3)
68 #define P4_ESCR_USR (1<<2)
69 #define P4_CCCR_OVF_PMI (1<<26)
70 #define P4_CCCR_THRESHOLD(N) ((N)<<20)
71 #define P4_CCCR_COMPLEMENT (1<<19)
72 #define P4_CCCR_COMPARE (1<<18)
73 #define P4_CCCR_REQUIRED (3<<16)
74 #define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
75 #define P4_CCCR_ENABLE (1<<12)
76 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
77 CRU_ESCR0 (with any non-null event selector) through a complemented
78 max threshold. [IA32-Vol3, Section 14.9.9] */
79 #define MSR_P4_IQ_COUNTER0 0x30C
80 #define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
81 #define P4_NMI_IQ_CCCR0 \
82 (P4_CCCR_OVF_PMI|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
83 P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
85 int __init check_nmi_watchdog (void)
87 unsigned int prev_nmi_count[NR_CPUS];
90 printk(KERN_INFO "testing NMI watchdog ... ");
92 for (cpu = 0; cpu < NR_CPUS; cpu++)
93 prev_nmi_count[cpu] = irq_stat[cpu].__nmi_count;
95 mdelay((10*1000)/nmi_hz); // wait 10 ticks
97 /* FIXME: Only boot CPU is online at this stage. Check CPUs
99 for (cpu = 0; cpu < NR_CPUS; cpu++) {
100 if (!cpu_online(cpu))
102 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
103 printk("CPU#%d: NMI appears to be stuck!\n", cpu);
110 /* now that we know it works we can reduce NMI frequency to
111 something more reasonable; makes a difference in some configs */
112 if (nmi_watchdog == NMI_LOCAL_APIC)
118 static int __init setup_nmi_watchdog(char *str)
122 get_option(&str, &nmi);
124 if (nmi >= NMI_INVALID)
129 * If any other x86 CPU has a local APIC, then
130 * please test the NMI stuff there and send me the
131 * missing bits. Right now Intel P6/P4 and AMD K7 only.
133 if ((nmi == NMI_LOCAL_APIC) &&
134 (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
135 (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
137 if ((nmi == NMI_LOCAL_APIC) &&
138 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
139 (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
142 * We can enable the IO-APIC watchdog
145 if (nmi == NMI_IO_APIC) {
152 __setup("nmi_watchdog=", setup_nmi_watchdog);
154 void disable_lapic_nmi_watchdog(void)
158 switch (boot_cpu_data.x86_vendor) {
160 wrmsr(MSR_K7_EVNTSEL0, 0, 0);
162 case X86_VENDOR_INTEL:
163 switch (boot_cpu_data.x86) {
165 if (boot_cpu_data.x86_model > 0xd)
168 wrmsr(MSR_P6_EVNTSEL0, 0, 0);
171 if (boot_cpu_data.x86_model > 0x3)
174 wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
175 wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
181 /* tell do_nmi() and others that we're not active any more */
185 void enable_lapic_nmi_watchdog(void)
187 if (nmi_active < 0) {
188 nmi_watchdog = NMI_LOCAL_APIC;
189 setup_apic_nmi_watchdog();
193 void disable_timer_nmi_watchdog(void)
195 if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
198 unset_nmi_callback();
200 nmi_watchdog = NMI_NONE;
203 void enable_timer_nmi_watchdog(void)
205 if (nmi_active < 0) {
206 nmi_watchdog = NMI_IO_APIC;
207 touch_nmi_watchdog();
214 static int nmi_pm_active; /* nmi_active before suspend */
216 static int lapic_nmi_suspend(struct sys_device *dev, u32 state)
218 nmi_pm_active = nmi_active;
219 disable_lapic_nmi_watchdog();
223 static int lapic_nmi_resume(struct sys_device *dev)
225 if (nmi_pm_active > 0)
226 enable_lapic_nmi_watchdog();
231 static struct sysdev_class nmi_sysclass = {
232 set_kset_name("lapic_nmi"),
233 .resume = lapic_nmi_resume,
234 .suspend = lapic_nmi_suspend,
237 static struct sys_device device_lapic_nmi = {
239 .cls = &nmi_sysclass,
242 static int __init init_lapic_nmi_sysfs(void)
249 error = sysdev_class_register(&nmi_sysclass);
251 error = sys_device_register(&device_lapic_nmi);
254 /* must come after the local APIC's device_initcall() */
255 late_initcall(init_lapic_nmi_sysfs);
257 #endif /* CONFIG_PM */
260 * Activate the NMI watchdog via the local APIC.
261 * Original code written by Keith Owens.
264 static void clear_msr_range(unsigned int base, unsigned int n)
268 for(i = 0; i < n; ++i)
272 static void setup_k7_watchdog(void)
274 unsigned int evntsel;
276 nmi_perfctr_msr = MSR_K7_PERFCTR0;
278 clear_msr_range(MSR_K7_EVNTSEL0, 4);
279 clear_msr_range(MSR_K7_PERFCTR0, 4);
281 evntsel = K7_EVNTSEL_INT
286 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
287 Dprintk("setting K7_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
288 wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1);
289 apic_write(APIC_LVTPC, APIC_DM_NMI);
290 evntsel |= K7_EVNTSEL_ENABLE;
291 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
294 static void setup_p6_watchdog(void)
296 unsigned int evntsel;
298 nmi_perfctr_msr = MSR_P6_PERFCTR0;
300 clear_msr_range(MSR_P6_EVNTSEL0, 2);
301 clear_msr_range(MSR_P6_PERFCTR0, 2);
303 evntsel = P6_EVNTSEL_INT
308 wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
309 Dprintk("setting P6_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
310 wrmsr(MSR_P6_PERFCTR0, -(cpu_khz/nmi_hz*1000), 0);
311 apic_write(APIC_LVTPC, APIC_DM_NMI);
312 evntsel |= P6_EVNTSEL0_ENABLE;
313 wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
316 static int setup_p4_watchdog(void)
318 unsigned int misc_enable, dummy;
320 rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
321 if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
324 nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
326 if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
327 clear_msr_range(0x3F1, 2);
328 /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
329 docs doesn't fully define it, so leave it alone for now. */
330 clear_msr_range(0x3A0, 31);
331 clear_msr_range(0x3C0, 6);
332 clear_msr_range(0x3C8, 6);
333 clear_msr_range(0x3E0, 2);
334 clear_msr_range(MSR_P4_CCCR0, 18);
335 clear_msr_range(MSR_P4_PERFCTR0, 18);
337 wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
338 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
339 Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
340 wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);
341 apic_write(APIC_LVTPC, APIC_DM_NMI);
342 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0);
346 void setup_apic_nmi_watchdog (void)
348 switch (boot_cpu_data.x86_vendor) {
350 if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
354 case X86_VENDOR_INTEL:
355 switch (boot_cpu_data.x86) {
357 if (boot_cpu_data.x86_model > 0xd)
363 if (boot_cpu_data.x86_model > 0x3)
366 if (!setup_p4_watchdog())
379 static spinlock_t nmi_print_lock = SPIN_LOCK_UNLOCKED;
382 * the best way to detect whether a CPU has a 'hard lockup' problem
383 * is to check it's local APIC timer IRQ counts. If they are not
384 * changing then that CPU has some problem.
386 * as these watchdog NMI IRQs are generated on every CPU, we only
387 * have to check the current processor.
389 * since NMIs don't listen to _any_ locks, we have to be extremely
390 * careful not to rely on unsafe variables. The printk might lock
391 * up though, so we have to break up any console locks first ...
392 * [when there will be more tty-related locks, break them up
397 last_irq_sums [NR_CPUS],
398 alert_counter [NR_CPUS];
400 void touch_nmi_watchdog (void)
405 * Just reset the alert counters, (other CPUs might be
406 * spinning on locks we hold):
408 for (i = 0; i < NR_CPUS; i++)
409 alert_counter[i] = 0;
412 void nmi_watchdog_tick (struct pt_regs * regs)
416 * Since current_thread_info()-> is always on the stack, and we
417 * always switch the stack NMI-atomically, it's safe to use
418 * smp_processor_id().
420 int sum, cpu = smp_processor_id();
422 sum = irq_stat[cpu].apic_timer_irqs;
424 if (last_irq_sums[cpu] == sum) {
426 * Ayiee, looks like this CPU is stuck ...
427 * wait a few IRQs (5 seconds) before doing the oops ...
429 alert_counter[cpu]++;
430 if (alert_counter[cpu] == 5*nmi_hz) {
431 spin_lock(&nmi_print_lock);
433 * We are in trouble anyway, lets at least try
434 * to get a message out.
437 printk("NMI Watchdog detected LOCKUP on CPU%d, eip %08lx, registers:\n", cpu, regs->eip);
438 show_registers(regs);
439 printk("console shuts up ...\n");
441 spin_unlock(&nmi_print_lock);
446 last_irq_sums[cpu] = sum;
447 alert_counter[cpu] = 0;
449 if (nmi_perfctr_msr) {
450 if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
453 * - An overflown perfctr will assert its interrupt
454 * until the OVF flag in its CCCR is cleared.
455 * - LVTPC is masked on interrupt and must be
456 * unmasked by the LVTPC handler.
458 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0);
459 apic_write(APIC_LVTPC, APIC_DM_NMI);
461 wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1);
465 EXPORT_SYMBOL(nmi_watchdog);
466 EXPORT_SYMBOL(disable_lapic_nmi_watchdog);
467 EXPORT_SYMBOL(enable_lapic_nmi_watchdog);
468 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
469 EXPORT_SYMBOL(enable_timer_nmi_watchdog);