include/asm-powerpc/spu.h

   1 /*
   2  * SPU core / file system interface and HW structures
   3  *
   4  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
   5  *
   6  * Author: Arnd Bergmann <arndb@de.ibm.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #ifndef _SPU_H
  24 #define _SPU_H
  25 #ifdef __KERNEL__
  26
  27 #include <linux/workqueue.h>
  28 #include <linux/sysdev.h>
  29
  30 #define LS_SIZE (256 * 1024)
  31 #define LS_ADDR_MASK (LS_SIZE - 1)
  32
  33 #define MFC_PUT_CMD             0x20
  34 #define MFC_PUTS_CMD            0x28
  35 #define MFC_PUTR_CMD            0x30
  36 #define MFC_PUTF_CMD            0x22
  37 #define MFC_PUTB_CMD            0x21
  38 #define MFC_PUTFS_CMD           0x2A
  39 #define MFC_PUTBS_CMD           0x29
  40 #define MFC_PUTRF_CMD           0x32
  41 #define MFC_PUTRB_CMD           0x31
  42 #define MFC_PUTL_CMD            0x24
  43 #define MFC_PUTRL_CMD           0x34
  44 #define MFC_PUTLF_CMD           0x26
  45 #define MFC_PUTLB_CMD           0x25
  46 #define MFC_PUTRLF_CMD          0x36
  47 #define MFC_PUTRLB_CMD          0x35
  48
  49 #define MFC_GET_CMD             0x40
  50 #define MFC_GETS_CMD            0x48
  51 #define MFC_GETF_CMD            0x42
  52 #define MFC_GETB_CMD            0x41
  53 #define MFC_GETFS_CMD           0x4A
  54 #define MFC_GETBS_CMD           0x49
  55 #define MFC_GETL_CMD            0x44
  56 #define MFC_GETLF_CMD           0x46
  57 #define MFC_GETLB_CMD           0x45
  58
  59 #define MFC_SDCRT_CMD           0x80
  60 #define MFC_SDCRTST_CMD         0x81
  61 #define MFC_SDCRZ_CMD           0x89
  62 #define MFC_SDCRS_CMD           0x8D
  63 #define MFC_SDCRF_CMD           0x8F
  64
  65 #define MFC_GETLLAR_CMD         0xD0
  66 #define MFC_PUTLLC_CMD          0xB4
  67 #define MFC_PUTLLUC_CMD         0xB0
  68 #define MFC_PUTQLLUC_CMD        0xB8
  69 #define MFC_SNDSIG_CMD          0xA0
  70 #define MFC_SNDSIGB_CMD         0xA1
  71 #define MFC_SNDSIGF_CMD         0xA2
  72 #define MFC_BARRIER_CMD         0xC0
  73 #define MFC_EIEIO_CMD           0xC8
  74 #define MFC_SYNC_CMD            0xCC
  75
  76 #define MFC_MIN_DMA_SIZE_SHIFT  4       /* 16 bytes */
  77 #define MFC_MAX_DMA_SIZE_SHIFT  14      /* 16384 bytes */
  78 #define MFC_MIN_DMA_SIZE        (1 << MFC_MIN_DMA_SIZE_SHIFT)
  79 #define MFC_MAX_DMA_SIZE        (1 << MFC_MAX_DMA_SIZE_SHIFT)
  80 #define MFC_MIN_DMA_SIZE_MASK   (MFC_MIN_DMA_SIZE - 1)
  81 #define MFC_MAX_DMA_SIZE_MASK   (MFC_MAX_DMA_SIZE - 1)
  82 #define MFC_MIN_DMA_LIST_SIZE   0x0008  /*   8 bytes */
  83 #define MFC_MAX_DMA_LIST_SIZE   0x4000  /* 16K bytes */
  84
  85 #define MFC_TAGID_TO_TAGMASK(tag_id)  (1 << (tag_id & 0x1F))
  86
  87 /* Events for Channels 0-2 */
  88 #define MFC_DMA_TAG_STATUS_UPDATE_EVENT     0x00000001
  89 #define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT  0x00000002
  90 #define MFC_DMA_QUEUE_AVAILABLE_EVENT       0x00000008
  91 #define MFC_SPU_MAILBOX_WRITTEN_EVENT       0x00000010
  92 #define MFC_DECREMENTER_EVENT               0x00000020
  93 #define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT  0x00000040
  94 #define MFC_PU_MAILBOX_AVAILABLE_EVENT      0x00000080
  95 #define MFC_SIGNAL_2_EVENT                  0x00000100
  96 #define MFC_SIGNAL_1_EVENT                  0x00000200
  97 #define MFC_LLR_LOST_EVENT                  0x00000400
  98 #define MFC_PRIV_ATTN_EVENT                 0x00000800
  99 #define MFC_MULTI_SRC_EVENT                 0x00001000
 100
 101 /* Flag indicating progress during context switch. */
 102 #define SPU_CONTEXT_SWITCH_PENDING      0UL
 103
 104 struct spu_context;
 105 struct spu_runqueue;
 106 struct spu_lscsa;
 107 struct device_node;
 108
 109 enum spu_utilization_state {
 110         SPU_UTIL_USER,
 111         SPU_UTIL_SYSTEM,
 112         SPU_UTIL_IOWAIT,
 113         SPU_UTIL_IDLE_LOADED,
 114         SPU_UTIL_MAX
 115 };
 116
 117 struct spu {
 118         const char *name;
 119         unsigned long local_store_phys;
 120         u8 *local_store;
 121         unsigned long problem_phys;
 122         struct spu_problem __iomem *problem;
 123         struct spu_priv2 __iomem *priv2;
 124         struct list_head cbe_list;
 125         struct list_head full_list;
 126         enum { SPU_FREE, SPU_USED } alloc_state;
 127         int number;
 128         unsigned int irqs[3];
 129         u32 node;
 130         u64 flags;
 131         u64 dar;
 132         u64 dsisr;
 133         u64 class_0_pending;
 134         size_t ls_size;
 135         unsigned int slb_replace;
 136         struct mm_struct *mm;
 137         struct spu_context *ctx;
 138         struct spu_runqueue *rq;
 139         unsigned long long timestamp;
 140         pid_t pid;
 141         pid_t tgid;
 142         spinlock_t register_lock;
 143
 144         void (* wbox_callback)(struct spu *spu);
 145         void (* ibox_callback)(struct spu *spu);
 146         void (* stop_callback)(struct spu *spu);
 147         void (* mfc_callback)(struct spu *spu);
 148
 149         char irq_c0[8];
 150         char irq_c1[8];
 151         char irq_c2[8];
 152
 153         u64 spe_id;
 154
 155         void* pdata; /* platform private data */
 156
 157         /* of based platforms only */
 158         struct device_node *devnode;
 159
 160         /* native only */
 161         struct spu_priv1 __iomem *priv1;
 162
 163         /* beat only */
 164         u64 shadow_int_mask_RW[3];
 165
 166         struct sys_device sysdev;
 167
 168         int has_mem_affinity;
 169         struct list_head aff_list;
 170
 171         struct {
 172                 /* protected by interrupt reentrancy */
 173                 enum spu_utilization_state util_state;
 174                 unsigned long long tstamp;
 175                 unsigned long long times[SPU_UTIL_MAX];
 176                 unsigned long long vol_ctx_switch;
 177                 unsigned long long invol_ctx_switch;
 178                 unsigned long long min_flt;
 179                 unsigned long long maj_flt;
 180                 unsigned long long hash_flt;
 181                 unsigned long long slb_flt;
 182                 unsigned long long class2_intr;
 183                 unsigned long long libassist;
 184         } stats;
 185 };
 186
 187 struct cbe_spu_info {
 188         struct mutex list_mutex;
 189         struct list_head spus;
 190         int n_spus;
 191         int nr_active;
 192         atomic_t reserved_spus;
 193 };
 194
 195 extern struct cbe_spu_info cbe_spu_info[];
 196
 197 void spu_init_channels(struct spu *spu);
 198 void spu_irq_setaffinity(struct spu *spu, int cpu);
 199
 200 void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
 201                 void *code, int code_size);
 202
 203 #ifdef CONFIG_KEXEC
 204 void crash_register_spus(struct list_head *list);
 205 #else
 206 static inline void crash_register_spus(struct list_head *list)
 207 {
 208 }
 209 #endif
 210
 211 extern void spu_invalidate_slbs(struct spu *spu);
 212 extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
 213 int spu_64k_pages_available(void);
 214
 215 /* Calls from the memory management to the SPU */
 216 struct mm_struct;
 217 extern void spu_flush_all_slbs(struct mm_struct *mm);
 218
 219 /* This interface allows a profiler (e.g., OProfile) to store a ref
 220  * to spu context information that it creates.  This caching technique
 221  * avoids the need to recreate this information after a save/restore operation.
 222  *
 223  * Assumes the caller has already incremented the ref count to
 224  * profile_info; then spu_context_destroy must call kref_put
 225  * on prof_info_kref.
 226  */
 227 void spu_set_profile_private_kref(struct spu_context *ctx,
 228                                   struct kref *prof_info_kref,
 229                                   void ( * prof_info_release) (struct kref *kref));
 230
 231 void *spu_get_profile_private_kref(struct spu_context *ctx);
 232
 233 /* system callbacks from the SPU */
 234 struct spu_syscall_block {
 235         u64 nr_ret;
 236         u64 parm[6];
 237 };
 238 extern long spu_sys_callback(struct spu_syscall_block *s);
 239
 240 /* syscalls implemented in spufs */
 241 struct file;
 242 struct spufs_calls {
 243         long (*create_thread)(const char __user *name,
 244                                         unsigned int flags, mode_t mode,
 245                                         struct file *neighbor);
 246         long (*spu_run)(struct file *filp, __u32 __user *unpc,
 247                                                 __u32 __user *ustatus);
 248         int (*coredump_extra_notes_size)(void);
 249         int (*coredump_extra_notes_write)(struct file *file, loff_t *foffset);
 250         void (*notify_spus_active)(void);
 251         struct module *owner;
 252 };
 253
 254 /* return status from spu_run, same as in libspe */
 255 #define SPE_EVENT_DMA_ALIGNMENT         0x0008  /*A DMA alignment error */
 256 #define SPE_EVENT_SPE_ERROR             0x0010  /*An illegal instruction error*/
 257 #define SPE_EVENT_SPE_DATA_SEGMENT      0x0020  /*A DMA segmentation error    */
 258 #define SPE_EVENT_SPE_DATA_STORAGE      0x0040  /*A DMA storage error */
 259 #define SPE_EVENT_INVALID_DMA           0x0800  /* Invalid MFC DMA */
 260
 261 /*
 262  * Flags for sys_spu_create.
 263  */
 264 #define SPU_CREATE_EVENTS_ENABLED       0x0001
 265 #define SPU_CREATE_GANG                 0x0002
 266 #define SPU_CREATE_NOSCHED              0x0004
 267 #define SPU_CREATE_ISOLATE              0x0008
 268 #define SPU_CREATE_AFFINITY_SPU         0x0010
 269 #define SPU_CREATE_AFFINITY_MEM         0x0020
 270
 271 #define SPU_CREATE_FLAG_ALL             0x003f /* mask of all valid flags */
 272
 273
 274 int register_spu_syscalls(struct spufs_calls *calls);
 275 void unregister_spu_syscalls(struct spufs_calls *calls);
 276
 277 int spu_add_sysdev_attr(struct sysdev_attribute *attr);
 278 void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
 279
 280 int spu_add_sysdev_attr_group(struct attribute_group *attrs);
 281 void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
 282
 283 int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea,
 284                 unsigned long dsisr, unsigned *flt);
 285
 286 /*
 287  * Notifier blocks:
 288  *
 289  * oprofile can get notified when a context switch is performed
 290  * on an spe. The notifer function that gets called is passed
 291  * a pointer to the SPU structure as well as the object-id that
 292  * identifies the binary running on that SPU now.
 293  *
 294  * For a context save, the object-id that is passed is zero,
 295  * identifying that the kernel will run from that moment on.
 296  *
 297  * For a context restore, the object-id is the value written
 298  * to object-id spufs file from user space and the notifer
 299  * function can assume that spu->ctx is valid.
 300  */
 301 struct notifier_block;
 302 int spu_switch_event_register(struct notifier_block * n);
 303 int spu_switch_event_unregister(struct notifier_block * n);
 304
 305 extern void notify_spus_active(void);
 306 extern void do_notify_spus_active(void);
 307
 308 /*
 309  * This defines the Local Store, Problem Area and Privilege Area of an SPU.
 310  */
 311
 312 union mfc_tag_size_class_cmd {
 313         struct {
 314                 u16 mfc_size;
 315                 u16 mfc_tag;
 316                 u8  pad;
 317                 u8  mfc_rclassid;
 318                 u16 mfc_cmd;
 319         } u;
 320         struct {
 321                 u32 mfc_size_tag32;
 322                 u32 mfc_class_cmd32;
 323         } by32;
 324         u64 all64;
 325 };
 326
 327 struct mfc_cq_sr {
 328         u64 mfc_cq_data0_RW;
 329         u64 mfc_cq_data1_RW;
 330         u64 mfc_cq_data2_RW;
 331         u64 mfc_cq_data3_RW;
 332 };
 333
 334 struct spu_problem {
 335 #define MS_SYNC_PENDING         1L
 336         u64 spc_mssync_RW;                                      /* 0x0000 */
 337         u8  pad_0x0008_0x3000[0x3000 - 0x0008];
 338
 339         /* DMA Area */
 340         u8  pad_0x3000_0x3004[0x4];                             /* 0x3000 */
 341         u32 mfc_lsa_W;                                          /* 0x3004 */
 342         u64 mfc_ea_W;                                           /* 0x3008 */
 343         union mfc_tag_size_class_cmd mfc_union_W;                       /* 0x3010 */
 344         u8  pad_0x3018_0x3104[0xec];                            /* 0x3018 */
 345         u32 dma_qstatus_R;                                      /* 0x3104 */
 346         u8  pad_0x3108_0x3204[0xfc];                            /* 0x3108 */
 347         u32 dma_querytype_RW;                                   /* 0x3204 */
 348         u8  pad_0x3208_0x321c[0x14];                            /* 0x3208 */
 349         u32 dma_querymask_RW;                                   /* 0x321c */
 350         u8  pad_0x3220_0x322c[0xc];                             /* 0x3220 */
 351         u32 dma_tagstatus_R;                                    /* 0x322c */
 352 #define DMA_TAGSTATUS_INTR_ANY  1u
 353 #define DMA_TAGSTATUS_INTR_ALL  2u
 354         u8  pad_0x3230_0x4000[0x4000 - 0x3230];                 /* 0x3230 */
 355
 356         /* SPU Control Area */
 357         u8  pad_0x4000_0x4004[0x4];                             /* 0x4000 */
 358         u32 pu_mb_R;                                            /* 0x4004 */
 359         u8  pad_0x4008_0x400c[0x4];                             /* 0x4008 */
 360         u32 spu_mb_W;                                           /* 0x400c */
 361         u8  pad_0x4010_0x4014[0x4];                             /* 0x4010 */
 362         u32 mb_stat_R;                                          /* 0x4014 */
 363         u8  pad_0x4018_0x401c[0x4];                             /* 0x4018 */
 364         u32 spu_runcntl_RW;                                     /* 0x401c */
 365 #define SPU_RUNCNTL_STOP        0L
 366 #define SPU_RUNCNTL_RUNNABLE    1L
 367 #define SPU_RUNCNTL_ISOLATE     2L
 368         u8  pad_0x4020_0x4024[0x4];                             /* 0x4020 */
 369         u32 spu_status_R;                                       /* 0x4024 */
 370 #define SPU_STOP_STATUS_SHIFT           16
 371 #define SPU_STATUS_STOPPED              0x0
 372 #define SPU_STATUS_RUNNING              0x1
 373 #define SPU_STATUS_STOPPED_BY_STOP      0x2
 374 #define SPU_STATUS_STOPPED_BY_HALT      0x4
 375 #define SPU_STATUS_WAITING_FOR_CHANNEL  0x8
 376 #define SPU_STATUS_SINGLE_STEP          0x10
 377 #define SPU_STATUS_INVALID_INSTR        0x20
 378 #define SPU_STATUS_INVALID_CH           0x40
 379 #define SPU_STATUS_ISOLATED_STATE       0x80
 380 #define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
 381 #define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
 382         u8  pad_0x4028_0x402c[0x4];                             /* 0x4028 */
 383         u32 spu_spe_R;                                          /* 0x402c */
 384         u8  pad_0x4030_0x4034[0x4];                             /* 0x4030 */
 385         u32 spu_npc_RW;                                         /* 0x4034 */
 386         u8  pad_0x4038_0x14000[0x14000 - 0x4038];               /* 0x4038 */
 387
 388         /* Signal Notification Area */
 389         u8  pad_0x14000_0x1400c[0xc];                           /* 0x14000 */
 390         u32 signal_notify1;                                     /* 0x1400c */
 391         u8  pad_0x14010_0x1c00c[0x7ffc];                        /* 0x14010 */
 392         u32 signal_notify2;                                     /* 0x1c00c */
 393 } __attribute__ ((aligned(0x20000)));
 394
 395 /* SPU Privilege 2 State Area */
 396 struct spu_priv2 {
 397         /* MFC Registers */
 398         u8  pad_0x0000_0x1100[0x1100 - 0x0000];                 /* 0x0000 */
 399
 400         /* SLB Management Registers */
 401         u8  pad_0x1100_0x1108[0x8];                             /* 0x1100 */
 402         u64 slb_index_W;                                        /* 0x1108 */
 403 #define SLB_INDEX_MASK                          0x7L
 404         u64 slb_esid_RW;                                        /* 0x1110 */
 405         u64 slb_vsid_RW;                                        /* 0x1118 */
 406 #define SLB_VSID_SUPERVISOR_STATE       (0x1ull << 11)
 407 #define SLB_VSID_SUPERVISOR_STATE_MASK  (0x1ull << 11)
 408 #define SLB_VSID_PROBLEM_STATE          (0x1ull << 10)
 409 #define SLB_VSID_PROBLEM_STATE_MASK     (0x1ull << 10)
 410 #define SLB_VSID_EXECUTE_SEGMENT        (0x1ull << 9)
 411 #define SLB_VSID_NO_EXECUTE_SEGMENT     (0x1ull << 9)
 412 #define SLB_VSID_EXECUTE_SEGMENT_MASK   (0x1ull << 9)
 413 #define SLB_VSID_4K_PAGE                (0x0 << 8)
 414 #define SLB_VSID_LARGE_PAGE             (0x1ull << 8)
 415 #define SLB_VSID_PAGE_SIZE_MASK         (0x1ull << 8)
 416 #define SLB_VSID_CLASS_MASK             (0x1ull << 7)
 417 #define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
 418         u64 slb_invalidate_entry_W;                             /* 0x1120 */
 419         u64 slb_invalidate_all_W;                               /* 0x1128 */
 420         u8  pad_0x1130_0x2000[0x2000 - 0x1130];                 /* 0x1130 */
 421
 422         /* Context Save / Restore Area */
 423         struct mfc_cq_sr spuq[16];                              /* 0x2000 */
 424         struct mfc_cq_sr puq[8];                                /* 0x2200 */
 425         u8  pad_0x2300_0x3000[0x3000 - 0x2300];                 /* 0x2300 */
 426
 427         /* MFC Control */
 428         u64 mfc_control_RW;                                     /* 0x3000 */
 429 #define MFC_CNTL_RESUME_DMA_QUEUE               (0ull << 0)
 430 #define MFC_CNTL_SUSPEND_DMA_QUEUE              (1ull << 0)
 431 #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK         (1ull << 0)
 432 #define MFC_CNTL_SUSPEND_MASK                   (1ull << 4)
 433 #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION     (0ull << 8)
 434 #define MFC_CNTL_SUSPEND_IN_PROGRESS            (1ull << 8)
 435 #define MFC_CNTL_SUSPEND_COMPLETE               (3ull << 8)
 436 #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK        (3ull << 8)
 437 #define MFC_CNTL_DMA_QUEUES_EMPTY               (1ull << 14)
 438 #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK          (1ull << 14)
 439 #define MFC_CNTL_PURGE_DMA_REQUEST              (1ull << 15)
 440 #define MFC_CNTL_PURGE_DMA_IN_PROGRESS          (1ull << 24)
 441 #define MFC_CNTL_PURGE_DMA_COMPLETE             (3ull << 24)
 442 #define MFC_CNTL_PURGE_DMA_STATUS_MASK          (3ull << 24)
 443 #define MFC_CNTL_RESTART_DMA_COMMAND            (1ull << 32)
 444 #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING    (1ull << 32)
 445 #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
 446 #define MFC_CNTL_MFC_PRIVILEGE_STATE            (2ull << 33)
 447 #define MFC_CNTL_MFC_PROBLEM_STATE              (3ull << 33)
 448 #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK  (3ull << 33)
 449 #define MFC_CNTL_DECREMENTER_HALTED             (1ull << 35)
 450 #define MFC_CNTL_DECREMENTER_RUNNING            (1ull << 40)
 451 #define MFC_CNTL_DECREMENTER_STATUS_MASK        (1ull << 40)
 452         u8  pad_0x3008_0x4000[0x4000 - 0x3008];                 /* 0x3008 */
 453
 454         /* Interrupt Mailbox */
 455         u64 puint_mb_R;                                         /* 0x4000 */
 456         u8  pad_0x4008_0x4040[0x4040 - 0x4008];                 /* 0x4008 */
 457
 458         /* SPU Control */
 459         u64 spu_privcntl_RW;                                    /* 0x4040 */
 460 #define SPU_PRIVCNTL_MODE_NORMAL                (0x0ull << 0)
 461 #define SPU_PRIVCNTL_MODE_SINGLE_STEP           (0x1ull << 0)
 462 #define SPU_PRIVCNTL_MODE_MASK                  (0x1ull << 0)
 463 #define SPU_PRIVCNTL_NO_ATTENTION_EVENT         (0x0ull << 1)
 464 #define SPU_PRIVCNTL_ATTENTION_EVENT            (0x1ull << 1)
 465 #define SPU_PRIVCNTL_ATTENTION_EVENT_MASK       (0x1ull << 1)
 466 #define SPU_PRIVCNT_LOAD_REQUEST_NORMAL         (0x0ull << 2)
 467 #define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK    (0x1ull << 2)
 468         u8  pad_0x4048_0x4058[0x10];                            /* 0x4048 */
 469         u64 spu_lslr_RW;                                        /* 0x4058 */
 470         u64 spu_chnlcntptr_RW;                                  /* 0x4060 */
 471         u64 spu_chnlcnt_RW;                                     /* 0x4068 */
 472         u64 spu_chnldata_RW;                                    /* 0x4070 */
 473         u64 spu_cfg_RW;                                         /* 0x4078 */
 474         u8  pad_0x4080_0x5000[0x5000 - 0x4080];                 /* 0x4080 */
 475
 476         /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
 477         u64 spu_pm_trace_tag_status_RW;                         /* 0x5000 */
 478         u64 spu_tag_status_query_RW;                            /* 0x5008 */
 479 #define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
 480 #define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
 481         u64 spu_cmd_buf1_RW;                                    /* 0x5010 */
 482 #define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
 483 #define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
 484         u64 spu_cmd_buf2_RW;                                    /* 0x5018 */
 485 #define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
 486 #define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
 487 #define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
 488         u64 spu_atomic_status_RW;                               /* 0x5020 */
 489 } __attribute__ ((aligned(0x20000)));
 490
 491 /* SPU Privilege 1 State Area */
 492 struct spu_priv1 {
 493         /* Control and Configuration Area */
 494         u64 mfc_sr1_RW;                                         /* 0x000 */
 495 #define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK    0x01ull
 496 #define MFC_STATE1_BUS_TLBIE_MASK               0x02ull
 497 #define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
 498 #define MFC_STATE1_PROBLEM_STATE_MASK           0x08ull
 499 #define MFC_STATE1_RELOCATE_MASK                0x10ull
 500 #define MFC_STATE1_MASTER_RUN_CONTROL_MASK      0x20ull
 501 #define MFC_STATE1_TABLE_SEARCH_MASK            0x40ull
 502         u64 mfc_lpid_RW;                                        /* 0x008 */
 503         u64 spu_idr_RW;                                         /* 0x010 */
 504         u64 mfc_vr_RO;                                          /* 0x018 */
 505 #define MFC_VERSION_BITS                (0xffff << 16)
 506 #define MFC_REVISION_BITS               (0xffff)
 507 #define MFC_GET_VERSION_BITS(vr)        (((vr) & MFC_VERSION_BITS) >> 16)
 508 #define MFC_GET_REVISION_BITS(vr)       ((vr) & MFC_REVISION_BITS)
 509         u64 spu_vr_RO;                                          /* 0x020 */
 510 #define SPU_VERSION_BITS                (0xffff << 16)
 511 #define SPU_REVISION_BITS               (0xffff)
 512 #define SPU_GET_VERSION_BITS(vr)        (vr & SPU_VERSION_BITS) >> 16
 513 #define SPU_GET_REVISION_BITS(vr)       (vr & SPU_REVISION_BITS)
 514         u8  pad_0x28_0x100[0x100 - 0x28];                       /* 0x28 */
 515
 516         /* Interrupt Area */
 517         u64 int_mask_RW[3];                                     /* 0x100 */
 518 #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR                0x1L
 519 #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR          0x2L
 520 #define CLASS0_ENABLE_SPU_ERROR_INTR                    0x4L
 521 #define CLASS0_ENABLE_MFC_FIR_INTR                      0x8L
 522 #define CLASS1_ENABLE_SEGMENT_FAULT_INTR                0x1L
 523 #define CLASS1_ENABLE_STORAGE_FAULT_INTR                0x2L
 524 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR    0x4L
 525 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR    0x8L
 526 #define CLASS2_ENABLE_MAILBOX_INTR                      0x1L
 527 #define CLASS2_ENABLE_SPU_STOP_INTR                     0x2L
 528 #define CLASS2_ENABLE_SPU_HALT_INTR                     0x4L
 529 #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR   0x8L
 530 #define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR            0x10L
 531         u8  pad_0x118_0x140[0x28];                              /* 0x118 */
 532         u64 int_stat_RW[3];                                     /* 0x140 */
 533 #define CLASS0_DMA_ALIGNMENT_INTR                       0x1L
 534 #define CLASS0_INVALID_DMA_COMMAND_INTR                 0x2L
 535 #define CLASS0_SPU_ERROR_INTR                           0x4L
 536 #define CLASS0_INTR_MASK                                0x7L
 537 #define CLASS1_SEGMENT_FAULT_INTR                       0x1L
 538 #define CLASS1_STORAGE_FAULT_INTR                       0x2L
 539 #define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR           0x4L
 540 #define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR           0x8L
 541 #define CLASS1_INTR_MASK                                0xfL
 542 #define CLASS2_MAILBOX_INTR                             0x1L
 543 #define CLASS2_SPU_STOP_INTR                            0x2L
 544 #define CLASS2_SPU_HALT_INTR                            0x4L
 545 #define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR          0x8L
 546 #define CLASS2_MAILBOX_THRESHOLD_INTR                   0x10L
 547 #define CLASS2_INTR_MASK                                0x1fL
 548         u8  pad_0x158_0x180[0x28];                              /* 0x158 */
 549         u64 int_route_RW;                                       /* 0x180 */
 550
 551         /* Interrupt Routing */
 552         u8  pad_0x188_0x200[0x200 - 0x188];                     /* 0x188 */
 553
 554         /* Atomic Unit Control Area */
 555         u64 mfc_atomic_flush_RW;                                /* 0x200 */
 556 #define mfc_atomic_flush_enable                 0x1L
 557         u8  pad_0x208_0x280[0x78];                              /* 0x208 */
 558         u64 resource_allocation_groupID_RW;                     /* 0x280 */
 559         u64 resource_allocation_enable_RW;                      /* 0x288 */
 560         u8  pad_0x290_0x3c8[0x3c8 - 0x290];                     /* 0x290 */
 561
 562         /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
 563
 564         u64 smf_sbi_signal_sel;                                 /* 0x3c8 */
 565 #define smf_sbi_mask_lsb        56
 566 #define smf_sbi_shift           (63 - smf_sbi_mask_lsb)
 567 #define smf_sbi_mask            (0x301LL << smf_sbi_shift)
 568 #define smf_sbi_bus0_bits       (0x001LL << smf_sbi_shift)
 569 #define smf_sbi_bus2_bits       (0x100LL << smf_sbi_shift)
 570 #define smf_sbi2_bus0_bits      (0x201LL << smf_sbi_shift)
 571 #define smf_sbi2_bus2_bits      (0x300LL << smf_sbi_shift)
 572         u64 smf_ato_signal_sel;                                 /* 0x3d0 */
 573 #define smf_ato_mask_lsb        35
 574 #define smf_ato_shift           (63 - smf_ato_mask_lsb)
 575 #define smf_ato_mask            (0x3LL << smf_ato_shift)
 576 #define smf_ato_bus0_bits       (0x2LL << smf_ato_shift)
 577 #define smf_ato_bus2_bits       (0x1LL << smf_ato_shift)
 578         u8  pad_0x3d8_0x400[0x400 - 0x3d8];                     /* 0x3d8 */
 579
 580         /* TLB Management Registers */
 581         u64 mfc_sdr_RW;                                         /* 0x400 */
 582         u8  pad_0x408_0x500[0xf8];                              /* 0x408 */
 583         u64 tlb_index_hint_RO;                                  /* 0x500 */
 584         u64 tlb_index_W;                                        /* 0x508 */
 585         u64 tlb_vpn_RW;                                         /* 0x510 */
 586         u64 tlb_rpn_RW;                                         /* 0x518 */
 587         u8  pad_0x520_0x540[0x20];                              /* 0x520 */
 588         u64 tlb_invalidate_entry_W;                             /* 0x540 */
 589         u64 tlb_invalidate_all_W;                               /* 0x548 */
 590         u8  pad_0x550_0x580[0x580 - 0x550];                     /* 0x550 */
 591
 592         /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
 593         u64 smm_hid;                                            /* 0x580 */
 594 #define PAGE_SIZE_MASK          0xf000000000000000ull
 595 #define PAGE_SIZE_16MB_64KB     0x2000000000000000ull
 596         u8  pad_0x588_0x600[0x600 - 0x588];                     /* 0x588 */
 597
 598         /* MFC Status/Control Area */
 599         u64 mfc_accr_RW;                                        /* 0x600 */
 600 #define MFC_ACCR_EA_ACCESS_GET          (1 << 0)
 601 #define MFC_ACCR_EA_ACCESS_PUT          (1 << 1)
 602 #define MFC_ACCR_LS_ACCESS_GET          (1 << 3)
 603 #define MFC_ACCR_LS_ACCESS_PUT          (1 << 4)
 604         u8  pad_0x608_0x610[0x8];                               /* 0x608 */
 605         u64 mfc_dsisr_RW;                                       /* 0x610 */
 606 #define MFC_DSISR_PTE_NOT_FOUND         (1 << 30)
 607 #define MFC_DSISR_ACCESS_DENIED         (1 << 27)
 608 #define MFC_DSISR_ATOMIC                (1 << 26)
 609 #define MFC_DSISR_ACCESS_PUT            (1 << 25)
 610 #define MFC_DSISR_ADDR_MATCH            (1 << 22)
 611 #define MFC_DSISR_LS                    (1 << 17)
 612 #define MFC_DSISR_L                     (1 << 16)
 613 #define MFC_DSISR_ADDRESS_OVERFLOW      (1 << 0)
 614         u8  pad_0x618_0x620[0x8];                               /* 0x618 */
 615         u64 mfc_dar_RW;                                         /* 0x620 */
 616         u8  pad_0x628_0x700[0x700 - 0x628];                     /* 0x628 */
 617
 618         /* Replacement Management Table (RMT) Area */
 619         u64 rmt_index_RW;                                       /* 0x700 */
 620         u8  pad_0x708_0x710[0x8];                               /* 0x708 */
 621         u64 rmt_data1_RW;                                       /* 0x710 */
 622         u8  pad_0x718_0x800[0x800 - 0x718];                     /* 0x718 */
 623
 624         /* Control/Configuration Registers */
 625         u64 mfc_dsir_R;                                         /* 0x800 */
 626 #define MFC_DSIR_Q                      (1 << 31)
 627 #define MFC_DSIR_SPU_QUEUE              MFC_DSIR_Q
 628         u64 mfc_lsacr_RW;                                       /* 0x808 */
 629 #define MFC_LSACR_COMPARE_MASK          ((~0ull) << 32)
 630 #define MFC_LSACR_COMPARE_ADDR          ((~0ull) >> 32)
 631         u64 mfc_lscrr_R;                                        /* 0x810 */
 632 #define MFC_LSCRR_Q                     (1 << 31)
 633 #define MFC_LSCRR_SPU_QUEUE             MFC_LSCRR_Q
 634 #define MFC_LSCRR_QI_SHIFT              32
 635 #define MFC_LSCRR_QI_MASK               ((~0ull) << MFC_LSCRR_QI_SHIFT)
 636         u8  pad_0x818_0x820[0x8];                               /* 0x818 */
 637         u64 mfc_tclass_id_RW;                                   /* 0x820 */
 638 #define MFC_TCLASS_ID_ENABLE            (1L << 0L)
 639 #define MFC_TCLASS_SLOT2_ENABLE         (1L << 5L)
 640 #define MFC_TCLASS_SLOT1_ENABLE         (1L << 6L)
 641 #define MFC_TCLASS_SLOT0_ENABLE         (1L << 7L)
 642 #define MFC_TCLASS_QUOTA_2_SHIFT        8L
 643 #define MFC_TCLASS_QUOTA_1_SHIFT        16L
 644 #define MFC_TCLASS_QUOTA_0_SHIFT        24L
 645 #define MFC_TCLASS_QUOTA_2_MASK         (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
 646 #define MFC_TCLASS_QUOTA_1_MASK         (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
 647 #define MFC_TCLASS_QUOTA_0_MASK         (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
 648         u8  pad_0x828_0x900[0x900 - 0x828];                     /* 0x828 */
 649
 650         /* Real Mode Support Registers */
 651         u64 mfc_rm_boundary;                                    /* 0x900 */
 652         u8  pad_0x908_0x938[0x30];                              /* 0x908 */
 653         u64 smf_dma_signal_sel;                                 /* 0x938 */
 654 #define mfc_dma1_mask_lsb       41
 655 #define mfc_dma1_shift          (63 - mfc_dma1_mask_lsb)
 656 #define mfc_dma1_mask           (0x3LL << mfc_dma1_shift)
 657 #define mfc_dma1_bits           (0x1LL << mfc_dma1_shift)
 658 #define mfc_dma2_mask_lsb       43
 659 #define mfc_dma2_shift          (63 - mfc_dma2_mask_lsb)
 660 #define mfc_dma2_mask           (0x3LL << mfc_dma2_shift)
 661 #define mfc_dma2_bits           (0x1LL << mfc_dma2_shift)
 662         u8  pad_0x940_0xa38[0xf8];                              /* 0x940 */
 663         u64 smm_signal_sel;                                     /* 0xa38 */
 664 #define smm_sig_mask_lsb        12
 665 #define smm_sig_shift           (63 - smm_sig_mask_lsb)
 666 #define smm_sig_mask            (0x3LL << smm_sig_shift)
 667 #define smm_sig_bus0_bits       (0x2LL << smm_sig_shift)
 668 #define smm_sig_bus2_bits       (0x1LL << smm_sig_shift)
 669         u8  pad_0xa40_0xc00[0xc00 - 0xa40];                     /* 0xa40 */
 670
 671         /* DMA Command Error Area */
 672         u64 mfc_cer_R;                                          /* 0xc00 */
 673 #define MFC_CER_Q               (1 << 31)
 674 #define MFC_CER_SPU_QUEUE       MFC_CER_Q
 675         u8  pad_0xc08_0x1000[0x1000 - 0xc08];                   /* 0xc08 */
 676
 677         /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
 678         /* DMA Command Error Area */
 679         u64 spu_ecc_cntl_RW;                                    /* 0x1000 */
 680 #define SPU_ECC_CNTL_E                  (1ull << 0ull)
 681 #define SPU_ECC_CNTL_ENABLE             SPU_ECC_CNTL_E
 682 #define SPU_ECC_CNTL_DISABLE            (~SPU_ECC_CNTL_E & 1L)
 683 #define SPU_ECC_CNTL_S                  (1ull << 1ull)
 684 #define SPU_ECC_STOP_AFTER_ERROR        SPU_ECC_CNTL_S
 685 #define SPU_ECC_CONTINUE_AFTER_ERROR    (~SPU_ECC_CNTL_S & 2L)
 686 #define SPU_ECC_CNTL_B                  (1ull << 2ull)
 687 #define SPU_ECC_BACKGROUND_ENABLE       SPU_ECC_CNTL_B
 688 #define SPU_ECC_BACKGROUND_DISABLE      (~SPU_ECC_CNTL_B & 4L)
 689 #define SPU_ECC_CNTL_I_SHIFT            3ull
 690 #define SPU_ECC_CNTL_I_MASK             (3ull << SPU_ECC_CNTL_I_SHIFT)
 691 #define SPU_ECC_WRITE_ALWAYS            (~SPU_ECC_CNTL_I & 12L)
 692 #define SPU_ECC_WRITE_CORRECTABLE       (1ull << SPU_ECC_CNTL_I_SHIFT)
 693 #define SPU_ECC_WRITE_UNCORRECTABLE     (3ull << SPU_ECC_CNTL_I_SHIFT)
 694 #define SPU_ECC_CNTL_D                  (1ull << 5ull)
 695 #define SPU_ECC_DETECTION_ENABLE        SPU_ECC_CNTL_D
 696 #define SPU_ECC_DETECTION_DISABLE       (~SPU_ECC_CNTL_D & 32L)
 697         u64 spu_ecc_stat_RW;                                    /* 0x1008 */
 698 #define SPU_ECC_CORRECTED_ERROR         (1ull << 0ul)
 699 #define SPU_ECC_UNCORRECTED_ERROR       (1ull << 1ul)
 700 #define SPU_ECC_SCRUB_COMPLETE          (1ull << 2ul)
 701 #define SPU_ECC_SCRUB_IN_PROGRESS       (1ull << 3ul)
 702 #define SPU_ECC_INSTRUCTION_ERROR       (1ull << 4ul)
 703 #define SPU_ECC_DATA_ERROR              (1ull << 5ul)
 704 #define SPU_ECC_DMA_ERROR               (1ull << 6ul)
 705 #define SPU_ECC_STATUS_CNT_MASK         (256ull << 8)
 706         u64 spu_ecc_addr_RW;                                    /* 0x1010 */
 707         u64 spu_err_mask_RW;                                    /* 0x1018 */
 708 #define SPU_ERR_ILLEGAL_INSTR           (1ull << 0ul)
 709 #define SPU_ERR_ILLEGAL_CHANNEL         (1ull << 1ul)
 710         u8  pad_0x1020_0x1028[0x1028 - 0x1020];                 /* 0x1020 */
 711
 712         /* SPU Debug-Trace Bus (DTB) Selection Registers */
 713         u64 spu_trig0_sel;                                      /* 0x1028 */
 714         u64 spu_trig1_sel;                                      /* 0x1030 */
 715         u64 spu_trig2_sel;                                      /* 0x1038 */
 716         u64 spu_trig3_sel;                                      /* 0x1040 */
 717         u64 spu_trace_sel;                                      /* 0x1048 */
 718 #define spu_trace_sel_mask              0x1f1fLL
 719 #define spu_trace_sel_bus0_bits         0x1000LL
 720 #define spu_trace_sel_bus2_bits         0x0010LL
 721         u64 spu_event0_sel;                                     /* 0x1050 */
 722         u64 spu_event1_sel;                                     /* 0x1058 */
 723         u64 spu_event2_sel;                                     /* 0x1060 */
 724         u64 spu_event3_sel;                                     /* 0x1068 */
 725         u64 spu_trace_cntl;                                     /* 0x1070 */
 726 } __attribute__ ((aligned(0x2000)));
 727
 728 #endif /* __KERNEL__ */
 729 #endif