drivers/i2c/busses/i2c-i801.c

   1 /*
   2     i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware
   3               monitoring
   4     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   5     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   6     <mdsxyz123@yahoo.com>
   7     Copyright (C) 2007         Jean Delvare <khali@linux-fr.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 */
  23
  24 /*
  25   Supports the following Intel I/O Controller Hubs (ICH):
  26
  27                                   I/O                     Block   I2C
  28                                   region  SMBus   Block   proc.   block
  29   Chip name             PCI ID    size    PEC     buffer  call    read
  30   ----------------------------------------------------------------------
  31   82801AA  (ICH)        0x2413     16      no      no      no      no
  32   82801AB  (ICH0)       0x2423     16      no      no      no      no
  33   82801BA  (ICH2)       0x2443     16      no      no      no      no
  34   82801CA  (ICH3)       0x2483     32     soft     no      no      no
  35   82801DB  (ICH4)       0x24c3     32     hard     yes     no      no
  36   82801E   (ICH5)       0x24d3     32     hard     yes     yes     yes
  37   6300ESB               0x25a4     32     hard     yes     yes     yes
  38   82801F   (ICH6)       0x266a     32     hard     yes     yes     yes
  39   6310ESB/6320ESB       0x269b     32     hard     yes     yes     yes
  40   82801G   (ICH7)       0x27da     32     hard     yes     yes     yes
  41   82801H   (ICH8)       0x283e     32     hard     yes     yes     yes
  42   82801I   (ICH9)       0x2930     32     hard     yes     yes     yes
  43   Tolapai               0x5032     32     hard     yes     yes     yes
  44   ICH10                 0x3a30     32     hard     yes     yes     yes
  45   ICH10                 0x3a60     32     hard     yes     yes     yes
  46
  47   Features supported by this driver:
  48   Software PEC                     no
  49   Hardware PEC                     yes
  50   Block buffer                     yes
  51   Block process call transaction   no
  52   I2C block read transaction       yes  (doesn't use the block buffer)
  53
  54   See the file Documentation/i2c/busses/i2c-i801 for details.
  55 */
  56
  57 /* Note: we assume there can only be one I801, with one SMBus interface */
  58
  59 #include <linux/module.h>
  60 #include <linux/pci.h>
  61 #include <linux/kernel.h>
  62 #include <linux/stddef.h>
  63 #include <linux/delay.h>
  64 #include <linux/ioport.h>
  65 #include <linux/init.h>
  66 #include <linux/i2c.h>
  67 #include <linux/acpi.h>
  68 #include <asm/io.h>
  69
  70 /* I801 SMBus address offsets */
  71 #define SMBHSTSTS       (0 + i801_smba)
  72 #define SMBHSTCNT       (2 + i801_smba)
  73 #define SMBHSTCMD       (3 + i801_smba)
  74 #define SMBHSTADD       (4 + i801_smba)
  75 #define SMBHSTDAT0      (5 + i801_smba)
  76 #define SMBHSTDAT1      (6 + i801_smba)
  77 #define SMBBLKDAT       (7 + i801_smba)
  78 #define SMBPEC          (8 + i801_smba)         /* ICH3 and later */
  79 #define SMBAUXSTS       (12 + i801_smba)        /* ICH4 and later */
  80 #define SMBAUXCTL       (13 + i801_smba)        /* ICH4 and later */
  81
  82 /* PCI Address Constants */
  83 #define SMBBAR          4
  84 #define SMBHSTCFG       0x040
  85
  86 /* Host configuration bits for SMBHSTCFG */
  87 #define SMBHSTCFG_HST_EN        1
  88 #define SMBHSTCFG_SMB_SMI_EN    2
  89 #define SMBHSTCFG_I2C_EN        4
  90
  91 /* Auxillary control register bits, ICH4+ only */
  92 #define SMBAUXCTL_CRC           1
  93 #define SMBAUXCTL_E32B          2
  94
  95 /* kill bit for SMBHSTCNT */
  96 #define SMBHSTCNT_KILL          2
  97
  98 /* Other settings */
  99 #define MAX_TIMEOUT             100
 100 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
 101
 102 /* I801 command constants */
 103 #define I801_QUICK              0x00
 104 #define I801_BYTE               0x04
 105 #define I801_BYTE_DATA          0x08
 106 #define I801_WORD_DATA          0x0C
 107 #define I801_PROC_CALL          0x10    /* unimplemented */
 108 #define I801_BLOCK_DATA         0x14
 109 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 110 #define I801_BLOCK_LAST         0x34
 111 #define I801_I2C_BLOCK_LAST     0x38    /* ICH5 and later */
 112 #define I801_START              0x40
 113 #define I801_PEC_EN             0x80    /* ICH3 and later */
 114
 115 /* I801 Hosts Status register bits */
 116 #define SMBHSTSTS_BYTE_DONE     0x80
 117 #define SMBHSTSTS_INUSE_STS     0x40
 118 #define SMBHSTSTS_SMBALERT_STS  0x20
 119 #define SMBHSTSTS_FAILED        0x10
 120 #define SMBHSTSTS_BUS_ERR       0x08
 121 #define SMBHSTSTS_DEV_ERR       0x04
 122 #define SMBHSTSTS_INTR          0x02
 123 #define SMBHSTSTS_HOST_BUSY     0x01
 124
 125 static unsigned long i801_smba;
 126 static unsigned char i801_original_hstcfg;
 127 static struct pci_driver i801_driver;
 128 static struct pci_dev *I801_dev;
 129
 130 #define FEATURE_SMBUS_PEC       (1 << 0)
 131 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 132 #define FEATURE_BLOCK_PROC      (1 << 2)
 133 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 134 static unsigned int i801_features;
 135
 136 static int i801_transaction(int xact)
 137 {
 138         int temp;
 139         int result = 0;
 140         int timeout = 0;
 141
 142         dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
 143                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 144                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 145                 inb_p(SMBHSTDAT1));
 146
 147         /* Make sure the SMBus host is ready to start transmitting */
 148         /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
 149         if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
 150                 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n",
 151                         temp);
 152                 outb_p(temp, SMBHSTSTS);
 153                 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
 154                         dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
 155                         return -1;
 156                 } else {
 157                         dev_dbg(&I801_dev->dev, "Successful!\n");
 158                 }
 159         }
 160
 161         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 162          * INTREN, SMBSCMD are passed in xact */
 163         outb_p(xact | I801_START, SMBHSTCNT);
 164
 165         /* We will always wait for a fraction of a second! */
 166         do {
 167                 msleep(1);
 168                 temp = inb_p(SMBHSTSTS);
 169         } while ((temp & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
 170
 171         /* If the SMBus is still busy, we give up */
 172         if (timeout >= MAX_TIMEOUT) {
 173                 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
 174                 result = -1;
 175                 /* try to stop the current command */
 176                 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
 177                 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
 178                 msleep(1);
 179                 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
 180         }
 181
 182         if (temp & SMBHSTSTS_FAILED) {
 183                 result = -1;
 184                 dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
 185         }
 186
 187         if (temp & SMBHSTSTS_BUS_ERR) {
 188                 result = -1;
 189                 dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
 190                         "until next hard reset. (sorry!)\n");
 191                 /* Clock stops and slave is stuck in mid-transmission */
 192         }
 193
 194         if (temp & SMBHSTSTS_DEV_ERR) {
 195                 result = -1;
 196                 dev_dbg(&I801_dev->dev, "Error: no response!\n");
 197         }
 198
 199         if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
 200                 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
 201
 202         if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
 203                 dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
 204                         "(%02x)\n", temp);
 205         }
 206         dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
 207                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 208                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 209                 inb_p(SMBHSTDAT1));
 210         return result;
 211 }
 212
 213 /* wait for INTR bit as advised by Intel */
 214 static void i801_wait_hwpec(void)
 215 {
 216         int timeout = 0;
 217         int temp;
 218
 219         do {
 220                 msleep(1);
 221                 temp = inb_p(SMBHSTSTS);
 222         } while ((!(temp & SMBHSTSTS_INTR))
 223                  && (timeout++ < MAX_TIMEOUT));
 224
 225         if (timeout >= MAX_TIMEOUT) {
 226                 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
 227         }
 228         outb_p(temp, SMBHSTSTS);
 229 }
 230
 231 static int i801_block_transaction_by_block(union i2c_smbus_data *data,
 232                                            char read_write, int hwpec)
 233 {
 234         int i, len;
 235
 236         inb_p(SMBHSTCNT); /* reset the data buffer index */
 237
 238         /* Use 32-byte buffer to process this transaction */
 239         if (read_write == I2C_SMBUS_WRITE) {
 240                 len = data->block[0];
 241                 outb_p(len, SMBHSTDAT0);
 242                 for (i = 0; i < len; i++)
 243                         outb_p(data->block[i+1], SMBBLKDAT);
 244         }
 245
 246         if (i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
 247                              I801_PEC_EN * hwpec))
 248                 return -1;
 249
 250         if (read_write == I2C_SMBUS_READ) {
 251                 len = inb_p(SMBHSTDAT0);
 252                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 253                         return -1;
 254
 255                 data->block[0] = len;
 256                 for (i = 0; i < len; i++)
 257                         data->block[i + 1] = inb_p(SMBBLKDAT);
 258         }
 259         return 0;
 260 }
 261
 262 static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
 263                                                char read_write, int command,
 264                                                int hwpec)
 265 {
 266         int i, len;
 267         int smbcmd;
 268         int temp;
 269         int result = 0;
 270         int timeout;
 271         unsigned char errmask;
 272
 273         len = data->block[0];
 274
 275         if (read_write == I2C_SMBUS_WRITE) {
 276                 outb_p(len, SMBHSTDAT0);
 277                 outb_p(data->block[1], SMBBLKDAT);
 278         }
 279
 280         for (i = 1; i <= len; i++) {
 281                 if (i == len && read_write == I2C_SMBUS_READ) {
 282                         if (command == I2C_SMBUS_I2C_BLOCK_DATA)
 283                                 smbcmd = I801_I2C_BLOCK_LAST;
 284                         else
 285                                 smbcmd = I801_BLOCK_LAST;
 286                 } else {
 287                         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 288                          && read_write == I2C_SMBUS_READ)
 289                                 smbcmd = I801_I2C_BLOCK_DATA;
 290                         else
 291                                 smbcmd = I801_BLOCK_DATA;
 292                 }
 293                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
 294
 295                 dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
 296                         "ADD=%02x, DAT0=%02x, DAT1=%02x, BLKDAT=%02x\n", i,
 297                         inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
 298                         inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1), inb_p(SMBBLKDAT));
 299
 300                 /* Make sure the SMBus host is ready to start transmitting */
 301                 temp = inb_p(SMBHSTSTS);
 302                 if (i == 1) {
 303                         /* Erroneous conditions before transaction:
 304                          * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
 305                         errmask = 0x9f;
 306                 } else {
 307                         /* Erroneous conditions during transaction:
 308                          * Failed, Bus_Err, Dev_Err, Intr */
 309                         errmask = 0x1e;
 310                 }
 311                 if (temp & errmask) {
 312                         dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
 313                                 "Resetting...\n", temp);
 314                         outb_p(temp, SMBHSTSTS);
 315                         if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
 316                                 dev_err(&I801_dev->dev,
 317                                         "Reset failed! (%02x)\n", temp);
 318                                 return -1;
 319                         }
 320                         if (i != 1)
 321                                 /* if die in middle of block transaction, fail */
 322                                 return -1;
 323                 }
 324
 325                 if (i == 1)
 326                         outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
 327
 328                 /* We will always wait for a fraction of a second! */
 329                 timeout = 0;
 330                 do {
 331                         msleep(1);
 332                         temp = inb_p(SMBHSTSTS);
 333                 }
 334                 while ((!(temp & SMBHSTSTS_BYTE_DONE))
 335                        && (timeout++ < MAX_TIMEOUT));
 336
 337                 /* If the SMBus is still busy, we give up */
 338                 if (timeout >= MAX_TIMEOUT) {
 339                         /* try to stop the current command */
 340                         dev_dbg(&I801_dev->dev, "Terminating the current "
 341                                                 "operation\n");
 342                         outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
 343                         msleep(1);
 344                         outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL),
 345                                 SMBHSTCNT);
 346                         result = -1;
 347                         dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
 348                 }
 349
 350                 if (temp & SMBHSTSTS_FAILED) {
 351                         result = -1;
 352                         dev_dbg(&I801_dev->dev,
 353                                 "Error: Failed bus transaction\n");
 354                 } else if (temp & SMBHSTSTS_BUS_ERR) {
 355                         result = -1;
 356                         dev_err(&I801_dev->dev, "Bus collision!\n");
 357                 } else if (temp & SMBHSTSTS_DEV_ERR) {
 358                         result = -1;
 359                         dev_dbg(&I801_dev->dev, "Error: no response!\n");
 360                 }
 361
 362                 if (i == 1 && read_write == I2C_SMBUS_READ
 363                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 364                         len = inb_p(SMBHSTDAT0);
 365                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 366                                 return -1;
 367                         data->block[0] = len;
 368                 }
 369
 370                 /* Retrieve/store value in SMBBLKDAT */
 371                 if (read_write == I2C_SMBUS_READ)
 372                         data->block[i] = inb_p(SMBBLKDAT);
 373                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 374                         outb_p(data->block[i+1], SMBBLKDAT);
 375                 if ((temp & 0x9e) != 0x00)
 376                         outb_p(temp, SMBHSTSTS);  /* signals SMBBLKDAT ready */
 377
 378                 if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
 379                         dev_dbg(&I801_dev->dev,
 380                                 "Bad status (%02x) at end of transaction\n",
 381                                 temp);
 382                 }
 383                 dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
 384                         "ADD=%02x, DAT0=%02x, DAT1=%02x, BLKDAT=%02x\n", i,
 385                         inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
 386                         inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1), inb_p(SMBBLKDAT));
 387
 388                 if (result < 0)
 389                         return result;
 390         }
 391         return result;
 392 }
 393
 394 static int i801_set_block_buffer_mode(void)
 395 {
 396         outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
 397         if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
 398                 return -1;
 399         return 0;
 400 }
 401
 402 /* Block transaction function */
 403 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
 404                                   int command, int hwpec)
 405 {
 406         int result = 0;
 407         unsigned char hostc;
 408
 409         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 410                 if (read_write == I2C_SMBUS_WRITE) {
 411                         /* set I2C_EN bit in configuration register */
 412                         pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
 413                         pci_write_config_byte(I801_dev, SMBHSTCFG,
 414                                               hostc | SMBHSTCFG_I2C_EN);
 415                 } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
 416                         dev_err(&I801_dev->dev,
 417                                 "I2C block read is unsupported!\n");
 418                         return -1;
 419                 }
 420         }
 421
 422         if (read_write == I2C_SMBUS_WRITE
 423          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 424                 if (data->block[0] < 1)
 425                         data->block[0] = 1;
 426                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 427                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 428         } else {
 429                 data->block[0] = 32;    /* max for SMBus block reads */
 430         }
 431
 432         if ((i801_features & FEATURE_BLOCK_BUFFER)
 433          && !(command == I2C_SMBUS_I2C_BLOCK_DATA
 434               && read_write == I2C_SMBUS_READ)
 435          && i801_set_block_buffer_mode() == 0)
 436                 result = i801_block_transaction_by_block(data, read_write,
 437                                                          hwpec);
 438         else
 439                 result = i801_block_transaction_byte_by_byte(data, read_write,
 440                                                              command, hwpec);
 441
 442         if (result == 0 && hwpec)
 443                 i801_wait_hwpec();
 444
 445         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 446          && read_write == I2C_SMBUS_WRITE) {
 447                 /* restore saved configuration register value */
 448                 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
 449         }
 450         return result;
 451 }
 452
 453 /* Return -1 on error. */
 454 static s32 i801_access(struct i2c_adapter * adap, u16 addr,
 455                        unsigned short flags, char read_write, u8 command,
 456                        int size, union i2c_smbus_data * data)
 457 {
 458         int hwpec;
 459         int block = 0;
 460         int ret, xact = 0;
 461
 462         hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 463                 && size != I2C_SMBUS_QUICK
 464                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 465
 466         switch (size) {
 467         case I2C_SMBUS_QUICK:
 468                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 469                        SMBHSTADD);
 470                 xact = I801_QUICK;
 471                 break;
 472         case I2C_SMBUS_BYTE:
 473                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 474                        SMBHSTADD);
 475                 if (read_write == I2C_SMBUS_WRITE)
 476                         outb_p(command, SMBHSTCMD);
 477                 xact = I801_BYTE;
 478                 break;
 479         case I2C_SMBUS_BYTE_DATA:
 480                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 481                        SMBHSTADD);
 482                 outb_p(command, SMBHSTCMD);
 483                 if (read_write == I2C_SMBUS_WRITE)
 484                         outb_p(data->byte, SMBHSTDAT0);
 485                 xact = I801_BYTE_DATA;
 486                 break;
 487         case I2C_SMBUS_WORD_DATA:
 488                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 489                        SMBHSTADD);
 490                 outb_p(command, SMBHSTCMD);
 491                 if (read_write == I2C_SMBUS_WRITE) {
 492                         outb_p(data->word & 0xff, SMBHSTDAT0);
 493                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
 494                 }
 495                 xact = I801_WORD_DATA;
 496                 break;
 497         case I2C_SMBUS_BLOCK_DATA:
 498                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 499                        SMBHSTADD);
 500                 outb_p(command, SMBHSTCMD);
 501                 block = 1;
 502                 break;
 503         case I2C_SMBUS_I2C_BLOCK_DATA:
 504                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 505                  * bit should be cleared here, even when reading */
 506                 outb_p((addr & 0x7f) << 1, SMBHSTADD);
 507                 if (read_write == I2C_SMBUS_READ) {
 508                         /* NB: page 240 of ICH5 datasheet also shows
 509                          * that DATA1 is the cmd field when reading */
 510                         outb_p(command, SMBHSTDAT1);
 511                 } else
 512                         outb_p(command, SMBHSTCMD);
 513                 block = 1;
 514                 break;
 515         case I2C_SMBUS_PROC_CALL:
 516         default:
 517                 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
 518                 return -1;
 519         }
 520
 521         if (hwpec)      /* enable/disable hardware PEC */
 522                 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
 523         else
 524                 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
 525
 526         if(block)
 527                 ret = i801_block_transaction(data, read_write, size, hwpec);
 528         else
 529                 ret = i801_transaction(xact | ENABLE_INT9);
 530
 531         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 532            time, so we forcibly disable it after every transaction. Turn off
 533            E32B for the same reason. */
 534         if (hwpec || block)
 535                 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
 536                        SMBAUXCTL);
 537
 538         if(block)
 539                 return ret;
 540         if(ret)
 541                 return -1;
 542         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 543                 return 0;
 544
 545         switch (xact & 0x7f) {
 546         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 547         case I801_BYTE_DATA:
 548                 data->byte = inb_p(SMBHSTDAT0);
 549                 break;
 550         case I801_WORD_DATA:
 551                 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
 552                 break;
 553         }
 554         return 0;
 555 }
 556
 557
 558 static u32 i801_func(struct i2c_adapter *adapter)
 559 {
 560         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 561                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 562                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 563                ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 564                ((i801_features & FEATURE_I2C_BLOCK_READ) ?
 565                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 566 }
 567
 568 static const struct i2c_algorithm smbus_algorithm = {
 569         .smbus_xfer     = i801_access,
 570         .functionality  = i801_func,
 571 };
 572
 573 static struct i2c_adapter i801_adapter = {
 574         .owner          = THIS_MODULE,
 575         .id             = I2C_HW_SMBUS_I801,
 576         .class          = I2C_CLASS_HWMON,
 577         .algo           = &smbus_algorithm,
 578 };
 579
 580 static struct pci_device_id i801_ids[] = {
 581         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 582         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 583         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 584         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 585         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 586         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 587         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 588         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 589         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 590         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 591         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 592         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 593         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) },
 594         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 595         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 596         { 0, }
 597 };
 598
 599 MODULE_DEVICE_TABLE (pci, i801_ids);
 600
 601 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
 602 {
 603         unsigned char temp;
 604         int err;
 605
 606         I801_dev = dev;
 607         i801_features = 0;
 608         switch (dev->device) {
 609         case PCI_DEVICE_ID_INTEL_82801EB_3:
 610         case PCI_DEVICE_ID_INTEL_ESB_4:
 611         case PCI_DEVICE_ID_INTEL_ICH6_16:
 612         case PCI_DEVICE_ID_INTEL_ICH7_17:
 613         case PCI_DEVICE_ID_INTEL_ESB2_17:
 614         case PCI_DEVICE_ID_INTEL_ICH8_5:
 615         case PCI_DEVICE_ID_INTEL_ICH9_6:
 616         case PCI_DEVICE_ID_INTEL_TOLAPAI_1:
 617         case PCI_DEVICE_ID_INTEL_ICH10_4:
 618         case PCI_DEVICE_ID_INTEL_ICH10_5:
 619                 i801_features |= FEATURE_I2C_BLOCK_READ;
 620                 /* fall through */
 621         case PCI_DEVICE_ID_INTEL_82801DB_3:
 622                 i801_features |= FEATURE_SMBUS_PEC;
 623                 i801_features |= FEATURE_BLOCK_BUFFER;
 624                 break;
 625         }
 626
 627         err = pci_enable_device(dev);
 628         if (err) {
 629                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
 630                         err);
 631                 goto exit;
 632         }
 633
 634         /* Determine the address of the SMBus area */
 635         i801_smba = pci_resource_start(dev, SMBBAR);
 636         if (!i801_smba) {
 637                 dev_err(&dev->dev, "SMBus base address uninitialized, "
 638                         "upgrade BIOS\n");
 639                 err = -ENODEV;
 640                 goto exit;
 641         }
 642
 643         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
 644         if (err)
 645                 goto exit;
 646
 647         err = pci_request_region(dev, SMBBAR, i801_driver.name);
 648         if (err) {
 649                 dev_err(&dev->dev, "Failed to request SMBus region "
 650                         "0x%lx-0x%Lx\n", i801_smba,
 651                         (unsigned long long)pci_resource_end(dev, SMBBAR));
 652                 goto exit;
 653         }
 654
 655         pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
 656         i801_original_hstcfg = temp;
 657         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
 658         if (!(temp & SMBHSTCFG_HST_EN)) {
 659                 dev_info(&dev->dev, "Enabling SMBus device\n");
 660                 temp |= SMBHSTCFG_HST_EN;
 661         }
 662         pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
 663
 664         if (temp & SMBHSTCFG_SMB_SMI_EN)
 665                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
 666         else
 667                 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
 668
 669         /* Clear special mode bits */
 670         if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
 671                 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
 672                        SMBAUXCTL);
 673
 674         /* set up the sysfs linkage to our parent device */
 675         i801_adapter.dev.parent = &dev->dev;
 676
 677         snprintf(i801_adapter.name, sizeof(i801_adapter.name),
 678                 "SMBus I801 adapter at %04lx", i801_smba);
 679         err = i2c_add_adapter(&i801_adapter);
 680         if (err) {
 681                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
 682                 goto exit_release;
 683         }
 684         return 0;
 685
 686 exit_release:
 687         pci_release_region(dev, SMBBAR);
 688 exit:
 689         return err;
 690 }
 691
 692 static void __devexit i801_remove(struct pci_dev *dev)
 693 {
 694         i2c_del_adapter(&i801_adapter);
 695         pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
 696         pci_release_region(dev, SMBBAR);
 697         /*
 698          * do not call pci_disable_device(dev) since it can cause hard hangs on
 699          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
 700          */
 701 }
 702
 703 #ifdef CONFIG_PM
 704 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
 705 {
 706         pci_save_state(dev);
 707         pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
 708         pci_set_power_state(dev, pci_choose_state(dev, mesg));
 709         return 0;
 710 }
 711
 712 static int i801_resume(struct pci_dev *dev)
 713 {
 714         pci_set_power_state(dev, PCI_D0);
 715         pci_restore_state(dev);
 716         return pci_enable_device(dev);
 717 }
 718 #else
 719 #define i801_suspend NULL
 720 #define i801_resume NULL
 721 #endif
 722
 723 static struct pci_driver i801_driver = {
 724         .name           = "i801_smbus",
 725         .id_table       = i801_ids,
 726         .probe          = i801_probe,
 727         .remove         = __devexit_p(i801_remove),
 728         .suspend        = i801_suspend,
 729         .resume         = i801_resume,
 730 };
 731
 732 static int __init i2c_i801_init(void)
 733 {
 734         return pci_register_driver(&i801_driver);
 735 }
 736
 737 static void __exit i2c_i801_exit(void)
 738 {
 739         pci_unregister_driver(&i801_driver);
 740 }
 741
 742 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
 743               "Jean Delvare <khali@linux-fr.org>");
 744 MODULE_DESCRIPTION("I801 SMBus driver");
 745 MODULE_LICENSE("GPL");
 746
 747 module_init(i2c_i801_init);
 748 module_exit(i2c_i801_exit);