arch/mips/mips-boards/malta/malta_setup.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
   4  * Copyright (C) Dmitri Vorobiev
   5  *
   6  *  This program is free software; you can distribute it and/or modify it
   7  *  under the terms of the GNU General Public License (Version 2) as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  *  for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License along
  16  *  with this program; if not, write to the Free Software Foundation, Inc.,
  17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18  */
  19 #include <linux/cpu.h>
  20 #include <linux/init.h>
  21 #include <linux/sched.h>
  22 #include <linux/ioport.h>
  23 #include <linux/irq.h>
  24 #include <linux/pci.h>
  25 #include <linux/screen_info.h>
  26 #include <linux/time.h>
  27
  28 #include <asm/bootinfo.h>
  29 #include <asm/mips-boards/generic.h>
  30 #include <asm/mips-boards/prom.h>
  31 #include <asm/mips-boards/malta.h>
  32 #include <asm/mips-boards/maltaint.h>
  33 #include <asm/dma.h>
  34 #include <asm/traps.h>
  35 #ifdef CONFIG_VT
  36 #include <linux/console.h>
  37 #endif
  38
  39 struct resource standard_io_resources[] = {
  40         {
  41                 .name = "dma1",
  42                 .start = 0x00,
  43                 .end = 0x1f,
  44                 .flags = IORESOURCE_BUSY
  45         },
  46         {
  47                 .name = "timer",
  48                 .start = 0x40,
  49                 .end = 0x5f,
  50                 .flags = IORESOURCE_BUSY
  51         },
  52         {
  53                 .name = "keyboard",
  54                 .start = 0x60,
  55                 .end = 0x6f,
  56                 .flags = IORESOURCE_BUSY
  57         },
  58         {
  59                 .name = "dma page reg",
  60                 .start = 0x80,
  61                 .end = 0x8f,
  62                 .flags = IORESOURCE_BUSY
  63         },
  64         {
  65                 .name = "dma2",
  66                 .start = 0xc0,
  67                 .end = 0xdf,
  68                 .flags = IORESOURCE_BUSY
  69         },
  70 };
  71
  72 const char *get_system_type(void)
  73 {
  74         return "MIPS Malta";
  75 }
  76
  77 #if defined(CONFIG_MIPS_MT_SMTC)
  78 const char display_string[] = "       SMTC LINUX ON MALTA       ";
  79 #else
  80 const char display_string[] = "        LINUX ON MALTA       ";
  81 #endif /* CONFIG_MIPS_MT_SMTC */
  82
  83 #ifdef CONFIG_BLK_DEV_FD
  84 static void __init fd_activate(void)
  85 {
  86         /*
  87          * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
  88          * Controller.
  89          * Done by YAMON 2.00 onwards
  90          */
  91         /* Entering config state. */
  92         SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
  93
  94         /* Activate floppy controller. */
  95         SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
  96         SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
  97         SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
  98         SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
  99
 100         /* Exit config state. */
 101         SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
 102 }
 103 #endif
 104
 105 #ifdef CONFIG_BLK_DEV_IDE
 106 static void __init pci_clock_check(void)
 107 {
 108         unsigned int __iomem *jmpr_p =
 109                 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
 110         int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
 111         static const int pciclocks[] __initdata = {
 112                 33, 20, 25, 30, 12, 16, 37, 10
 113         };
 114         int pciclock = pciclocks[jmpr];
 115         char *argptr = prom_getcmdline();
 116
 117         if (pciclock != 33 && !strstr(argptr, "idebus=")) {
 118                 printk(KERN_WARNING "WARNING: PCI clock is %dMHz, "
 119                                 "setting idebus\n", pciclock);
 120                 argptr += strlen(argptr);
 121                 sprintf(argptr, " idebus=%d", pciclock);
 122                 if (pciclock < 20 || pciclock > 66)
 123                         printk(KERN_WARNING "WARNING: IDE timing "
 124                                         "calculations will be incorrect\n");
 125         }
 126 }
 127 #endif
 128
 129 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
 130 static void __init screen_info_setup(void)
 131 {
 132         screen_info = (struct screen_info) {
 133                 .orig_x = 0,
 134                 .orig_y = 25,
 135                 .ext_mem_k = 0,
 136                 .orig_video_page = 0,
 137                 .orig_video_mode = 0,
 138                 .orig_video_cols = 80,
 139                 .unused2 = 0,
 140                 .orig_video_ega_bx = 0,
 141                 .unused3 = 0,
 142                 .orig_video_lines = 25,
 143                 .orig_video_isVGA = VIDEO_TYPE_VGAC,
 144                 .orig_video_points = 16
 145         };
 146 }
 147 #endif
 148
 149 static void __init bonito_quirks_setup(void)
 150 {
 151         char *argptr;
 152
 153         argptr = prom_getcmdline();
 154         if (strstr(argptr, "debug")) {
 155                 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
 156                 printk(KERN_INFO "Enabled Bonito debug mode\n");
 157         } else
 158                 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
 159
 160 #ifdef CONFIG_DMA_COHERENT
 161         if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
 162                 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
 163                 printk(KERN_INFO "Enabled Bonito CPU coherency\n");
 164
 165                 argptr = prom_getcmdline();
 166                 if (strstr(argptr, "iobcuncached")) {
 167                         BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
 168                         BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
 169                                 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 170                                         BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 171                         printk(KERN_INFO "Disabled Bonito IOBC coherency\n");
 172                 } else {
 173                         BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
 174                         BONITO_PCIMEMBASECFG |=
 175                                 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 176                                         BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 177                         printk(KERN_INFO "Enabled Bonito IOBC coherency\n");
 178                 }
 179         } else
 180                 panic("Hardware DMA cache coherency not supported");
 181 #endif
 182 }
 183
 184 void __init plat_mem_setup(void)
 185 {
 186         unsigned int i;
 187
 188         mips_pcibios_init();
 189
 190         /* Request I/O space for devices used on the Malta board. */
 191         for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
 192                 request_resource(&ioport_resource, standard_io_resources+i);
 193
 194         /*
 195          * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
 196          */
 197         enable_dma(4);
 198
 199 #ifdef CONFIG_KGDB
 200         kgdb_config();
 201 #endif
 202
 203 #ifdef CONFIG_DMA_COHERENT
 204         if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
 205                 panic("Hardware DMA cache coherency not supported");
 206 #endif
 207
 208         if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
 209                 bonito_quirks_setup();
 210
 211 #ifdef CONFIG_BLK_DEV_IDE
 212         pci_clock_check();
 213 #endif
 214
 215 #ifdef CONFIG_BLK_DEV_FD
 216         fd_activate();
 217 #endif
 218
 219 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
 220         screen_info_setup();
 221 #endif
 222         mips_reboot_setup();
 223 }