5 * Access to machine-specific registers (available on 586 and better only)
6 * Note: the rd* operations modify the parameters directly (without using
7 * pointer indirection), this allows gcc to optimize better
10 #define rdmsr(msr,val1,val2) \
11 __asm__ __volatile__("rdmsr" \
12 : "=a" (val1), "=d" (val2) \
15 #define wrmsr(msr,val1,val2) \
16 __asm__ __volatile__("wrmsr" \
18 : "c" (msr), "a" (val1), "d" (val2))
20 #define rdtsc(low,high) \
21 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
24 __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
26 #define rdtscll(val) \
27 __asm__ __volatile__("rdtsc" : "=A" (val))
29 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
31 #define rdpmc(counter,low,high) \
32 __asm__ __volatile__("rdpmc" \
33 : "=a" (low), "=d" (high) \
36 /* symbolic names for some interesting MSRs */
37 /* Intel defined MSRs. */
38 #define MSR_IA32_P5_MC_ADDR 0
39 #define MSR_IA32_P5_MC_TYPE 1
40 #define MSR_IA32_PLATFORM_ID 0x17
41 #define MSR_IA32_EBL_CR_POWERON 0x2a
43 #define MSR_IA32_APICBASE 0x1b
44 #define MSR_IA32_APICBASE_BSP (1<<8)
45 #define MSR_IA32_APICBASE_ENABLE (1<<11)
46 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
48 #define MSR_IA32_UCODE_WRITE 0x79
49 #define MSR_IA32_UCODE_REV 0x8b
51 #define MSR_P6_PERFCTR0 0xc1
52 #define MSR_P6_PERFCTR1 0xc2
54 #define MSR_IA32_BBL_CR_CTL 0x119
56 #define MSR_IA32_SYSENTER_CS 0x174
57 #define MSR_IA32_SYSENTER_ESP 0x175
58 #define MSR_IA32_SYSENTER_EIP 0x176
60 #define MSR_IA32_MCG_CAP 0x179
61 #define MSR_IA32_MCG_STATUS 0x17a
62 #define MSR_IA32_MCG_CTL 0x17b
64 /* P4/Xeon+ specific */
65 #define MSR_IA32_MCG_EAX 0x180
66 #define MSR_IA32_MCG_EBX 0x181
67 #define MSR_IA32_MCG_ECX 0x182
68 #define MSR_IA32_MCG_EDX 0x183
69 #define MSR_IA32_MCG_ESI 0x184
70 #define MSR_IA32_MCG_EDI 0x185
71 #define MSR_IA32_MCG_EBP 0x186
72 #define MSR_IA32_MCG_ESP 0x187
73 #define MSR_IA32_MCG_EFLAGS 0x188
74 #define MSR_IA32_MCG_EIP 0x189
75 #define MSR_IA32_MCG_RESERVED 0x18A
77 #define MSR_P6_EVNTSEL0 0x186
78 #define MSR_P6_EVNTSEL1 0x187
80 #define MSR_IA32_PERF_STATUS 0x198
81 #define MSR_IA32_PERF_CTL 0x199
83 #define MSR_IA32_THERM_CONTROL 0x19a
84 #define MSR_IA32_THERM_INTERRUPT 0x19b
85 #define MSR_IA32_THERM_STATUS 0x19c
86 #define MSR_IA32_MISC_ENABLE 0x1a0
88 #define MSR_IA32_DEBUGCTLMSR 0x1d9
89 #define MSR_IA32_LASTBRANCHFROMIP 0x1db
90 #define MSR_IA32_LASTBRANCHTOIP 0x1dc
91 #define MSR_IA32_LASTINTFROMIP 0x1dd
92 #define MSR_IA32_LASTINTTOIP 0x1de
94 #define MSR_IA32_MC0_CTL 0x400
95 #define MSR_IA32_MC0_STATUS 0x401
96 #define MSR_IA32_MC0_ADDR 0x402
97 #define MSR_IA32_MC0_MISC 0x403
99 /* Pentium IV performance counter MSRs */
100 #define MSR_P4_BPU_PERFCTR0 0x300
101 #define MSR_P4_BPU_PERFCTR1 0x301
102 #define MSR_P4_BPU_PERFCTR2 0x302
103 #define MSR_P4_BPU_PERFCTR3 0x303
104 #define MSR_P4_MS_PERFCTR0 0x304
105 #define MSR_P4_MS_PERFCTR1 0x305
106 #define MSR_P4_MS_PERFCTR2 0x306
107 #define MSR_P4_MS_PERFCTR3 0x307
108 #define MSR_P4_FLAME_PERFCTR0 0x308
109 #define MSR_P4_FLAME_PERFCTR1 0x309
110 #define MSR_P4_FLAME_PERFCTR2 0x30a
111 #define MSR_P4_FLAME_PERFCTR3 0x30b
112 #define MSR_P4_IQ_PERFCTR0 0x30c
113 #define MSR_P4_IQ_PERFCTR1 0x30d
114 #define MSR_P4_IQ_PERFCTR2 0x30e
115 #define MSR_P4_IQ_PERFCTR3 0x30f
116 #define MSR_P4_IQ_PERFCTR4 0x310
117 #define MSR_P4_IQ_PERFCTR5 0x311
118 #define MSR_P4_BPU_CCCR0 0x360
119 #define MSR_P4_BPU_CCCR1 0x361
120 #define MSR_P4_BPU_CCCR2 0x362
121 #define MSR_P4_BPU_CCCR3 0x363
122 #define MSR_P4_MS_CCCR0 0x364
123 #define MSR_P4_MS_CCCR1 0x365
124 #define MSR_P4_MS_CCCR2 0x366
125 #define MSR_P4_MS_CCCR3 0x367
126 #define MSR_P4_FLAME_CCCR0 0x368
127 #define MSR_P4_FLAME_CCCR1 0x369
128 #define MSR_P4_FLAME_CCCR2 0x36a
129 #define MSR_P4_FLAME_CCCR3 0x36b
130 #define MSR_P4_IQ_CCCR0 0x36c
131 #define MSR_P4_IQ_CCCR1 0x36d
132 #define MSR_P4_IQ_CCCR2 0x36e
133 #define MSR_P4_IQ_CCCR3 0x36f
134 #define MSR_P4_IQ_CCCR4 0x370
135 #define MSR_P4_IQ_CCCR5 0x371
136 #define MSR_P4_ALF_ESCR0 0x3ca
137 #define MSR_P4_ALF_ESCR1 0x3cb
138 #define MSR_P4_BPU_ESCR0 0x3b2
139 #define MSR_P4_BPU_ESCR1 0x3b3
140 #define MSR_P4_BSU_ESCR0 0x3a0
141 #define MSR_P4_BSU_ESCR1 0x3a1
142 #define MSR_P4_CRU_ESCR0 0x3b8
143 #define MSR_P4_CRU_ESCR1 0x3b9
144 #define MSR_P4_CRU_ESCR2 0x3cc
145 #define MSR_P4_CRU_ESCR3 0x3cd
146 #define MSR_P4_CRU_ESCR4 0x3e0
147 #define MSR_P4_CRU_ESCR5 0x3e1
148 #define MSR_P4_DAC_ESCR0 0x3a8
149 #define MSR_P4_DAC_ESCR1 0x3a9
150 #define MSR_P4_FIRM_ESCR0 0x3a4
151 #define MSR_P4_FIRM_ESCR1 0x3a5
152 #define MSR_P4_FLAME_ESCR0 0x3a6
153 #define MSR_P4_FLAME_ESCR1 0x3a7
154 #define MSR_P4_FSB_ESCR0 0x3a2
155 #define MSR_P4_FSB_ESCR1 0x3a3
156 #define MSR_P4_IQ_ESCR0 0x3ba
157 #define MSR_P4_IQ_ESCR1 0x3bb
158 #define MSR_P4_IS_ESCR0 0x3b4
159 #define MSR_P4_IS_ESCR1 0x3b5
160 #define MSR_P4_ITLB_ESCR0 0x3b6
161 #define MSR_P4_ITLB_ESCR1 0x3b7
162 #define MSR_P4_IX_ESCR0 0x3c8
163 #define MSR_P4_IX_ESCR1 0x3c9
164 #define MSR_P4_MOB_ESCR0 0x3aa
165 #define MSR_P4_MOB_ESCR1 0x3ab
166 #define MSR_P4_MS_ESCR0 0x3c0
167 #define MSR_P4_MS_ESCR1 0x3c1
168 #define MSR_P4_PMH_ESCR0 0x3ac
169 #define MSR_P4_PMH_ESCR1 0x3ad
170 #define MSR_P4_RAT_ESCR0 0x3bc
171 #define MSR_P4_RAT_ESCR1 0x3bd
172 #define MSR_P4_SAAT_ESCR0 0x3ae
173 #define MSR_P4_SAAT_ESCR1 0x3af
174 #define MSR_P4_SSU_ESCR0 0x3be
175 #define MSR_P4_SSU_ESCR1 0x3bf /* guess: not defined in manual */
176 #define MSR_P4_TBPU_ESCR0 0x3c2
177 #define MSR_P4_TBPU_ESCR1 0x3c3
178 #define MSR_P4_TC_ESCR0 0x3c4
179 #define MSR_P4_TC_ESCR1 0x3c5
180 #define MSR_P4_U2L_ESCR0 0x3b0
181 #define MSR_P4_U2L_ESCR1 0x3b1
183 /* AMD Defined MSRs */
184 #define MSR_K6_EFER 0xC0000080
185 #define MSR_K6_STAR 0xC0000081
186 #define MSR_K6_WHCR 0xC0000082
187 #define MSR_K6_UWCCR 0xC0000085
188 #define MSR_K6_EPMR 0xC0000086
189 #define MSR_K6_PSOR 0xC0000087
190 #define MSR_K6_PFIR 0xC0000088
192 #define MSR_K7_EVNTSEL0 0xC0010000
193 #define MSR_K7_EVNTSEL1 0xC0010001
194 #define MSR_K7_EVNTSEL2 0xC0010002
195 #define MSR_K7_EVNTSEL3 0xC0010003
196 #define MSR_K7_PERFCTR0 0xC0010004
197 #define MSR_K7_PERFCTR1 0xC0010005
198 #define MSR_K7_PERFCTR2 0xC0010006
199 #define MSR_K7_PERFCTR3 0xC0010007
200 #define MSR_K7_HWCR 0xC0010015
201 #define MSR_K7_CLK_CTL 0xC001001b
202 #define MSR_K7_FID_VID_CTL 0xC0010041
203 #define MSR_K7_VID_STATUS 0xC0010042
205 /* Centaur-Hauls/IDT defined MSRs. */
206 #define MSR_IDT_FCR1 0x107
207 #define MSR_IDT_FCR2 0x108
208 #define MSR_IDT_FCR3 0x109
209 #define MSR_IDT_FCR4 0x10a
211 #define MSR_IDT_MCR0 0x110
212 #define MSR_IDT_MCR1 0x111
213 #define MSR_IDT_MCR2 0x112
214 #define MSR_IDT_MCR3 0x113
215 #define MSR_IDT_MCR4 0x114
216 #define MSR_IDT_MCR5 0x115
217 #define MSR_IDT_MCR6 0x116
218 #define MSR_IDT_MCR7 0x117
219 #define MSR_IDT_MCR_CTRL 0x120
221 /* VIA Cyrix defined MSRs*/
222 #define MSR_VIA_FCR 0x1107
223 #define MSR_VIA_LONGHAUL 0x110a
224 #define MSR_VIA_RNG 0x110b
225 #define MSR_VIA_BCR2 0x1147
227 /* Transmeta defined MSRs */
228 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
229 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
230 #define MSR_TMTA_LRTI_READOUT 0x80868018
231 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
233 #endif /* __ASM_MSR_H */