arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <trace/events/power.h>
  32
  33 #include <asm/suspend.h>
  34 #include <asm/system_misc.h>
  35
  36 #include <plat/sram.h>
  37 #include "clockdomain.h"
  38 #include "powerdomain.h"
  39 #include <plat/sdrc.h>
  40 #include <plat/prcm.h>
  41 #include <plat/gpmc.h>
  42 #include <plat/dma.h>
  43
  44 #include "common.h"
  45 #include "cm2xxx_3xxx.h"
  46 #include "cm-regbits-34xx.h"
  47 #include "prm-regbits-34xx.h"
  48
  49 #include "prm2xxx_3xxx.h"
  50 #include "pm.h"
  51 #include "sdrc.h"
  52 #include "control.h"
  53
  54 /* pm34xx errata defined in pm.h */
  55 u16 pm34xx_errata;
  56
  57 struct power_state {
  58         struct powerdomain *pwrdm;
  59         u32 next_state;
  60 #ifdef CONFIG_SUSPEND
  61         u32 saved_state;
  62 #endif
  63         struct list_head node;
  64 };
  65
  66 static LIST_HEAD(pwrst_list);
  67
  68 static int (*_omap_save_secure_sram)(u32 *addr);
  69 void (*omap3_do_wfi_sram)(void);
  70
  71 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  72 static struct powerdomain *core_pwrdm, *per_pwrdm;
  73 static struct powerdomain *cam_pwrdm;
  74
  75 static void omap3_enable_io_chain(void)
  76 {
  77         int timeout = 0;
  78
  79         omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
  80                                    PM_WKEN);
  81         /* Do a readback to assure write has been done */
  82         omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
  83
  84         while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
  85                  OMAP3430_ST_IO_CHAIN_MASK)) {
  86                 timeout++;
  87                 if (timeout > 1000) {
  88                         pr_err("Wake up daisy chain activation failed.\n");
  89                         return;
  90                 }
  91                 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
  92                                            WKUP_MOD, PM_WKEN);
  93         }
  94 }
  95
  96 static void omap3_disable_io_chain(void)
  97 {
  98         omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
  99                                      PM_WKEN);
 100 }
 101
 102 static void omap3_core_save_context(void)
 103 {
 104         omap3_ctrl_save_padconf();
 105
 106         /*
 107          * Force write last pad into memory, as this can fail in some
 108          * cases according to errata 1.157, 1.185
 109          */
 110         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 111                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 112
 113         /* Save the Interrupt controller context */
 114         omap_intc_save_context();
 115         /* Save the GPMC context */
 116         omap3_gpmc_save_context();
 117         /* Save the system control module context, padconf already save above*/
 118         omap3_control_save_context();
 119         omap_dma_global_context_save();
 120 }
 121
 122 static void omap3_core_restore_context(void)
 123 {
 124         /* Restore the control module context, padconf restored by h/w */
 125         omap3_control_restore_context();
 126         /* Restore the GPMC context */
 127         omap3_gpmc_restore_context();
 128         /* Restore the interrupt controller context */
 129         omap_intc_restore_context();
 130         omap_dma_global_context_restore();
 131 }
 132
 133 /*
 134  * FIXME: This function should be called before entering off-mode after
 135  * OMAP3 secure services have been accessed. Currently it is only called
 136  * once during boot sequence, but this works as we are not using secure
 137  * services.
 138  */
 139 static void omap3_save_secure_ram_context(void)
 140 {
 141         u32 ret;
 142         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 143
 144         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 145                 /*
 146                  * MPU next state must be set to POWER_ON temporarily,
 147                  * otherwise the WFI executed inside the ROM code
 148                  * will hang the system.
 149                  */
 150                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 151                 ret = _omap_save_secure_sram((u32 *)
 152                                 __pa(omap3_secure_ram_storage));
 153                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 154                 /* Following is for error tracking, it should not happen */
 155                 if (ret) {
 156                         pr_err("save_secure_sram() returns %08x\n", ret);
 157                         while (1)
 158                                 ;
 159                 }
 160         }
 161 }
 162
 163 /*
 164  * PRCM Interrupt Handler Helper Function
 165  *
 166  * The purpose of this function is to clear any wake-up events latched
 167  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 168  * may occur whilst attempting to clear a PM_WKST_x register and thus
 169  * set another bit in this register. A while loop is used to ensure
 170  * that any peripheral wake-up events occurring while attempting to
 171  * clear the PM_WKST_x are detected and cleared.
 172  */
 173 static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
 174 {
 175         u32 wkst, fclk, iclk, clken;
 176         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 177         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 178         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 179         u16 grpsel_off = (regs == 3) ?
 180                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 181         int c = 0;
 182
 183         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 184         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 185         wkst &= ~ignore_bits;
 186         if (wkst) {
 187                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 188                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 189                 while (wkst) {
 190                         clken = wkst;
 191                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 192                         /*
 193                          * For USBHOST, we don't know whether HOST1 or
 194                          * HOST2 woke us up, so enable both f-clocks
 195                          */
 196                         if (module == OMAP3430ES2_USBHOST_MOD)
 197                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 198                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 199                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 200                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 201                         wkst &= ~ignore_bits;
 202                         c++;
 203                 }
 204                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 205                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 206         }
 207
 208         return c;
 209 }
 210
 211 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
 212 {
 213         int c;
 214
 215         c = prcm_clear_mod_irqs(WKUP_MOD, 1,
 216                 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
 217
 218         return c ? IRQ_HANDLED : IRQ_NONE;
 219 }
 220
 221 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
 222 {
 223         int c;
 224
 225         /*
 226          * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
 227          * these are handled in a separate handler to avoid acking
 228          * IO events before parsing in mux code
 229          */
 230         c = prcm_clear_mod_irqs(WKUP_MOD, 1,
 231                 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
 232         c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
 233         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
 234         if (omap_rev() > OMAP3430_REV_ES1_0) {
 235                 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
 236                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
 237         }
 238
 239         return c ? IRQ_HANDLED : IRQ_NONE;
 240 }
 241
 242 static void omap34xx_save_context(u32 *save)
 243 {
 244         u32 val;
 245
 246         /* Read Auxiliary Control Register */
 247         asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
 248         *save++ = 1;
 249         *save++ = val;
 250
 251         /* Read L2 AUX ctrl register */
 252         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
 253         *save++ = 1;
 254         *save++ = val;
 255 }
 256
 257 static int omap34xx_do_sram_idle(unsigned long save_state)
 258 {
 259         omap34xx_cpu_suspend(save_state);
 260         return 0;
 261 }
 262
 263 void omap_sram_idle(void)
 264 {
 265         /* Variable to tell what needs to be saved and restored
 266          * in omap_sram_idle*/
 267         /* save_state = 0 => Nothing to save and restored */
 268         /* save_state = 1 => Only L1 and logic lost */
 269         /* save_state = 2 => Only L2 lost */
 270         /* save_state = 3 => L1, L2 and logic lost */
 271         int save_state = 0;
 272         int mpu_next_state = PWRDM_POWER_ON;
 273         int per_next_state = PWRDM_POWER_ON;
 274         int core_next_state = PWRDM_POWER_ON;
 275         int per_going_off;
 276         int core_prev_state, per_prev_state;
 277         u32 sdrc_pwr = 0;
 278
 279         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 280         switch (mpu_next_state) {
 281         case PWRDM_POWER_ON:
 282         case PWRDM_POWER_RET:
 283                 /* No need to save context */
 284                 save_state = 0;
 285                 break;
 286         case PWRDM_POWER_OFF:
 287                 save_state = 3;
 288                 break;
 289         default:
 290                 /* Invalid state */
 291                 pr_err("Invalid mpu state in sram_idle\n");
 292                 return;
 293         }
 294
 295         /* NEON control */
 296         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 297                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 298
 299         /* Enable IO-PAD and IO-CHAIN wakeups */
 300         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 301         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 302         if (omap3_has_io_wakeup() &&
 303             (per_next_state < PWRDM_POWER_ON ||
 304              core_next_state < PWRDM_POWER_ON)) {
 305                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 306                 if (omap3_has_io_chain_ctrl())
 307                         omap3_enable_io_chain();
 308         }
 309
 310         pwrdm_pre_transition();
 311
 312         /* PER */
 313         if (per_next_state < PWRDM_POWER_ON) {
 314                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 315                 omap2_gpio_prepare_for_idle(per_going_off);
 316         }
 317
 318         /* CORE */
 319         if (core_next_state < PWRDM_POWER_ON) {
 320                 if (core_next_state == PWRDM_POWER_OFF) {
 321                         omap3_core_save_context();
 322                         omap3_cm_save_context();
 323                 }
 324         }
 325
 326         omap3_intc_prepare_idle();
 327
 328         /*
 329          * On EMU/HS devices ROM code restores a SRDC value
 330          * from scratchpad which has automatic self refresh on timeout
 331          * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 332          * Hence store/restore the SDRC_POWER register here.
 333          */
 334         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 335             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 336              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 337             core_next_state == PWRDM_POWER_OFF)
 338                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 339
 340         /*
 341          * omap3_arm_context is the location where some ARM context
 342          * get saved. The rest is placed on the stack, and restored
 343          * from there before resuming.
 344          */
 345         if (save_state)
 346                 omap34xx_save_context(omap3_arm_context);
 347         if (save_state == 1 || save_state == 3)
 348                 cpu_suspend(save_state, omap34xx_do_sram_idle);
 349         else
 350                 omap34xx_do_sram_idle(save_state);
 351
 352         /* Restore normal SDRC POWER settings */
 353         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 354             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 355              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 356             core_next_state == PWRDM_POWER_OFF)
 357                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 358
 359         /* CORE */
 360         if (core_next_state < PWRDM_POWER_ON) {
 361                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 362                 if (core_prev_state == PWRDM_POWER_OFF) {
 363                         omap3_core_restore_context();
 364                         omap3_cm_restore_context();
 365                         omap3_sram_restore_context();
 366                         omap2_sms_restore_context();
 367                 }
 368                 if (core_next_state == PWRDM_POWER_OFF)
 369                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 370                                                OMAP3430_GR_MOD,
 371                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 372         }
 373         omap3_intc_resume_idle();
 374
 375         pwrdm_post_transition();
 376
 377         /* PER */
 378         if (per_next_state < PWRDM_POWER_ON) {
 379                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 380                 omap2_gpio_resume_after_idle();
 381         }
 382
 383         /* Disable IO-PAD and IO-CHAIN wakeup */
 384         if (omap3_has_io_wakeup() &&
 385             (per_next_state < PWRDM_POWER_ON ||
 386              core_next_state < PWRDM_POWER_ON)) {
 387                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 388                                              PM_WKEN);
 389                 if (omap3_has_io_chain_ctrl())
 390                         omap3_disable_io_chain();
 391         }
 392
 393         clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 394 }
 395
 396 static void omap3_pm_idle(void)
 397 {
 398         local_fiq_disable();
 399
 400         if (omap_irq_pending())
 401                 goto out;
 402
 403         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
 404         trace_cpu_idle(1, smp_processor_id());
 405
 406         omap_sram_idle();
 407
 408         trace_power_end(smp_processor_id());
 409         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 410
 411 out:
 412         local_fiq_enable();
 413 }
 414
 415 #ifdef CONFIG_SUSPEND
 416 static int omap3_pm_suspend(void)
 417 {
 418         struct power_state *pwrst;
 419         int state, ret = 0;
 420
 421         /* Read current next_pwrsts */
 422         list_for_each_entry(pwrst, &pwrst_list, node)
 423                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 424         /* Set ones wanted by suspend */
 425         list_for_each_entry(pwrst, &pwrst_list, node) {
 426                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 427                         goto restore;
 428                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 429                         goto restore;
 430         }
 431
 432         omap3_intc_suspend();
 433
 434         omap_sram_idle();
 435
 436 restore:
 437         /* Restore next_pwrsts */
 438         list_for_each_entry(pwrst, &pwrst_list, node) {
 439                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 440                 if (state > pwrst->next_state) {
 441                         pr_info("Powerdomain (%s) didn't enter "
 442                                 "target state %d\n",
 443                                pwrst->pwrdm->name, pwrst->next_state);
 444                         ret = -1;
 445                 }
 446                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 447         }
 448         if (ret)
 449                 pr_err("Could not enter target state in pm_suspend\n");
 450         else
 451                 pr_info("Successfully put all powerdomains to target state\n");
 452
 453         return ret;
 454 }
 455
 456 #endif /* CONFIG_SUSPEND */
 457
 458
 459 /**
 460  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 461  *                   retention
 462  *
 463  * In cases where IVA2 is activated by bootcode, it may prevent
 464  * full-chip retention or off-mode because it is not idle.  This
 465  * function forces the IVA2 into idle state so it can go
 466  * into retention/off and thus allow full-chip retention/off.
 467  *
 468  **/
 469 static void __init omap3_iva_idle(void)
 470 {
 471         /* ensure IVA2 clock is disabled */
 472         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 473
 474         /* if no clock activity, nothing else to do */
 475         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 476               OMAP3430_CLKACTIVITY_IVA2_MASK))
 477                 return;
 478
 479         /* Reset IVA2 */
 480         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 481                           OMAP3430_RST2_IVA2_MASK |
 482                           OMAP3430_RST3_IVA2_MASK,
 483                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 484
 485         /* Enable IVA2 clock */
 486         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 487                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 488
 489         /* Set IVA2 boot mode to 'idle' */
 490         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 491                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 492
 493         /* Un-reset IVA2 */
 494         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 495
 496         /* Disable IVA2 clock */
 497         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 498
 499         /* Reset IVA2 */
 500         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 501                           OMAP3430_RST2_IVA2_MASK |
 502                           OMAP3430_RST3_IVA2_MASK,
 503                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 504 }
 505
 506 static void __init omap3_d2d_idle(void)
 507 {
 508         u16 mask, padconf;
 509
 510         /* In a stand alone OMAP3430 where there is not a stacked
 511          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 512          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 513          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 514         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 515         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 516         padconf |= mask;
 517         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 518
 519         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 520         padconf |= mask;
 521         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 522
 523         /* reset modem */
 524         omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 525                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 526                           CORE_MOD, OMAP2_RM_RSTCTRL);
 527         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 528 }
 529
 530 static void __init prcm_setup_regs(void)
 531 {
 532         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 533                                         OMAP3630_EN_UART4_MASK : 0;
 534         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 535                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 536
 537         /* XXX This should be handled by hwmod code or SCM init code */
 538         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 539
 540         /*
 541          * Enable control of expternal oscillator through
 542          * sys_clkreq. In the long run clock framework should
 543          * take care of this.
 544          */
 545         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 546                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 547                              OMAP3430_GR_MOD,
 548                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 549
 550         /* setup wakup source */
 551         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 552                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 553                           WKUP_MOD, PM_WKEN);
 554         /* No need to write EN_IO, that is always enabled */
 555         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 556                           OMAP3430_GRPSEL_GPT1_MASK |
 557                           OMAP3430_GRPSEL_GPT12_MASK,
 558                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 559
 560         /* Enable PM_WKEN to support DSS LPR */
 561         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 562                                 OMAP3430_DSS_MOD, PM_WKEN);
 563
 564         /* Enable wakeups in PER */
 565         omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
 566                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 567                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 568                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 569                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 570                           OMAP3430_EN_MCBSP4_MASK,
 571                           OMAP3430_PER_MOD, PM_WKEN);
 572         /* and allow them to wake up MPU */
 573         omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 574                           OMAP3430_GRPSEL_GPIO2_MASK |
 575                           OMAP3430_GRPSEL_GPIO3_MASK |
 576                           OMAP3430_GRPSEL_GPIO4_MASK |
 577                           OMAP3430_GRPSEL_GPIO5_MASK |
 578                           OMAP3430_GRPSEL_GPIO6_MASK |
 579                           OMAP3430_GRPSEL_UART3_MASK |
 580                           OMAP3430_GRPSEL_MCBSP2_MASK |
 581                           OMAP3430_GRPSEL_MCBSP3_MASK |
 582                           OMAP3430_GRPSEL_MCBSP4_MASK,
 583                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 584
 585         /* Don't attach IVA interrupts */
 586         omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 587         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 588         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 589         omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 590
 591         /* Clear any pending 'reset' flags */
 592         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 593         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 594         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 595         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 596         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 597         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 598         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 599
 600         /* Clear any pending PRCM interrupts */
 601         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 602
 603         omap3_iva_idle();
 604         omap3_d2d_idle();
 605 }
 606
 607 void omap3_pm_off_mode_enable(int enable)
 608 {
 609         struct power_state *pwrst;
 610         u32 state;
 611
 612         if (enable)
 613                 state = PWRDM_POWER_OFF;
 614         else
 615                 state = PWRDM_POWER_RET;
 616
 617         list_for_each_entry(pwrst, &pwrst_list, node) {
 618                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 619                                 pwrst->pwrdm == core_pwrdm &&
 620                                 state == PWRDM_POWER_OFF) {
 621                         pwrst->next_state = PWRDM_POWER_RET;
 622                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 623                                 __func__);
 624                 } else {
 625                         pwrst->next_state = state;
 626                 }
 627                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 628         }
 629 }
 630
 631 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 632 {
 633         struct power_state *pwrst;
 634
 635         list_for_each_entry(pwrst, &pwrst_list, node) {
 636                 if (pwrst->pwrdm == pwrdm)
 637                         return pwrst->next_state;
 638         }
 639         return -EINVAL;
 640 }
 641
 642 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 643 {
 644         struct power_state *pwrst;
 645
 646         list_for_each_entry(pwrst, &pwrst_list, node) {
 647                 if (pwrst->pwrdm == pwrdm) {
 648                         pwrst->next_state = state;
 649                         return 0;
 650                 }
 651         }
 652         return -EINVAL;
 653 }
 654
 655 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 656 {
 657         struct power_state *pwrst;
 658
 659         if (!pwrdm->pwrsts)
 660                 return 0;
 661
 662         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 663         if (!pwrst)
 664                 return -ENOMEM;
 665         pwrst->pwrdm = pwrdm;
 666         pwrst->next_state = PWRDM_POWER_RET;
 667         list_add(&pwrst->node, &pwrst_list);
 668
 669         if (pwrdm_has_hdwr_sar(pwrdm))
 670                 pwrdm_enable_hdwr_sar(pwrdm);
 671
 672         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 673 }
 674
 675 /*
 676  * Push functions to SRAM
 677  *
 678  * The minimum set of functions is pushed to SRAM for execution:
 679  * - omap3_do_wfi for erratum i581 WA,
 680  * - save_secure_ram_context for security extensions.
 681  */
 682 void omap_push_sram_idle(void)
 683 {
 684         omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
 685
 686         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 687                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 688                                 save_secure_ram_context_sz);
 689 }
 690
 691 static void __init pm_errata_configure(void)
 692 {
 693         if (cpu_is_omap3630()) {
 694                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 695                 /* Enable the l2 cache toggling in sleep logic */
 696                 enable_omap3630_toggle_l2_on_restore();
 697                 if (omap_rev() < OMAP3630_REV_ES1_2)
 698                         pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
 699         }
 700 }
 701
 702 static int __init omap3_pm_init(void)
 703 {
 704         struct power_state *pwrst, *tmp;
 705         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
 706         int ret;
 707
 708         if (!cpu_is_omap34xx())
 709                 return -ENODEV;
 710
 711         if (!omap3_has_io_chain_ctrl())
 712                 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
 713
 714         pm_errata_configure();
 715
 716         /* XXX prcm_setup_regs needs to be before enabling hw
 717          * supervised mode for powerdomains */
 718         prcm_setup_regs();
 719
 720         ret = request_irq(omap_prcm_event_to_irq("wkup"),
 721                 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
 722
 723         if (ret) {
 724                 pr_err("pm: Failed to request pm_wkup irq\n");
 725                 goto err1;
 726         }
 727
 728         /* IO interrupt is shared with mux code */
 729         ret = request_irq(omap_prcm_event_to_irq("io"),
 730                 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
 731                 omap3_pm_init);
 732
 733         if (ret) {
 734                 pr_err("pm: Failed to request pm_io irq\n");
 735                 goto err2;
 736         }
 737
 738         ret = pwrdm_for_each(pwrdms_setup, NULL);
 739         if (ret) {
 740                 pr_err("Failed to setup powerdomains\n");
 741                 goto err3;
 742         }
 743
 744         (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
 745
 746         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 747         if (mpu_pwrdm == NULL) {
 748                 pr_err("Failed to get mpu_pwrdm\n");
 749                 ret = -EINVAL;
 750                 goto err3;
 751         }
 752
 753         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 754         per_pwrdm = pwrdm_lookup("per_pwrdm");
 755         core_pwrdm = pwrdm_lookup("core_pwrdm");
 756         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
 757
 758         neon_clkdm = clkdm_lookup("neon_clkdm");
 759         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 760         per_clkdm = clkdm_lookup("per_clkdm");
 761         core_clkdm = clkdm_lookup("core_clkdm");
 762
 763 #ifdef CONFIG_SUSPEND
 764         omap_pm_suspend = omap3_pm_suspend;
 765 #endif
 766
 767         arm_pm_idle = omap3_pm_idle;
 768         omap3_idle_init();
 769
 770         /*
 771          * RTA is disabled during initialization as per erratum i608
 772          * it is safer to disable RTA by the bootloader, but we would like
 773          * to be doubly sure here and prevent any mishaps.
 774          */
 775         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 776                 omap3630_ctrl_disable_rta();
 777
 778         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 779         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 780                 omap3_secure_ram_storage =
 781                         kmalloc(0x803F, GFP_KERNEL);
 782                 if (!omap3_secure_ram_storage)
 783                         pr_err("Memory allocation failed when "
 784                                "allocating for secure sram context\n");
 785
 786                 local_irq_disable();
 787                 local_fiq_disable();
 788
 789                 omap_dma_global_context_save();
 790                 omap3_save_secure_ram_context();
 791                 omap_dma_global_context_restore();
 792
 793                 local_irq_enable();
 794                 local_fiq_enable();
 795         }
 796
 797         omap3_save_scratchpad_contents();
 798         return ret;
 799
 800 err3:
 801         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 802                 list_del(&pwrst->node);
 803                 kfree(pwrst);
 804         }
 805         free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
 806 err2:
 807         free_irq(omap_prcm_event_to_irq("wkup"), NULL);
 808 err1:
 809         return ret;
 810 }
 811
 812 late_initcall(omap3_pm_init);