1 #ifndef _ASM_IA64_SAL_H
2 #define _ASM_IA64_SAL_H
5 * System Abstraction Layer definitions.
7 * This is based on version 2.5 of the manual "IA-64 System
10 * Copyright (C) 2001 Intel
11 * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
12 * Copyright (C) 2001 Fred Lewis <frederick.v.lewis@intel.com>
13 * Copyright (C) 1998, 1999, 2001, 2003 Hewlett-Packard Co
14 * David Mosberger-Tang <davidm@hpl.hp.com>
15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
17 * 02/01/04 J. Hall Updated Error Record Structures to conform to July 2001
18 * revision of the SAL spec.
19 * 01/01/03 fvlewis Updated Error Record Structures to conform with Nov. 2000
20 * revision of the SAL spec.
21 * 99/09/29 davidm Updated for SAL 2.6.
22 * 00/03/29 cfleck Updated SAL Error Logging info for processor (SAL 2.6)
23 * (plus examples of platform error info structures from smariset @ Intel)
26 #include <linux/spinlock.h>
27 #include <linux/efi.h>
30 #include <asm/system.h>
33 extern spinlock_t sal_lock;
35 /* SAL spec _requires_ eight args for each call. */
36 #define __SAL_CALL(result,a0,a1,a2,a3,a4,a5,a6,a7) \
37 result = (*ia64_sal)(a0,a1,a2,a3,a4,a5,a6,a7)
39 # define SAL_CALL(result,args...) do { \
40 unsigned long __ia64_sc_flags; \
41 struct ia64_fpreg __ia64_sc_fr[6]; \
42 ia64_save_scratch_fpregs(__ia64_sc_fr); \
43 spin_lock_irqsave(&sal_lock, __ia64_sc_flags); \
44 __SAL_CALL(result, args); \
45 spin_unlock_irqrestore(&sal_lock, __ia64_sc_flags); \
46 ia64_load_scratch_fpregs(__ia64_sc_fr); \
49 # define SAL_CALL_NOLOCK(result,args...) do { \
50 unsigned long __ia64_scn_flags; \
51 struct ia64_fpreg __ia64_scn_fr[6]; \
52 ia64_save_scratch_fpregs(__ia64_scn_fr); \
53 local_irq_save(__ia64_scn_flags); \
54 __SAL_CALL(result, args); \
55 local_irq_restore(__ia64_scn_flags); \
56 ia64_load_scratch_fpregs(__ia64_scn_fr); \
59 #define SAL_SET_VECTORS 0x01000000
60 #define SAL_GET_STATE_INFO 0x01000001
61 #define SAL_GET_STATE_INFO_SIZE 0x01000002
62 #define SAL_CLEAR_STATE_INFO 0x01000003
63 #define SAL_MC_RENDEZ 0x01000004
64 #define SAL_MC_SET_PARAMS 0x01000005
65 #define SAL_REGISTER_PHYSICAL_ADDR 0x01000006
67 #define SAL_CACHE_FLUSH 0x01000008
68 #define SAL_CACHE_INIT 0x01000009
69 #define SAL_PCI_CONFIG_READ 0x01000010
70 #define SAL_PCI_CONFIG_WRITE 0x01000011
71 #define SAL_FREQ_BASE 0x01000012
73 #define SAL_UPDATE_PAL 0x01000020
75 struct ia64_sal_retval {
77 * A zero status value indicates call completed without error.
78 * A negative status value indicates reason of call failure.
79 * A positive status value indicates success but an
80 * informational value should be printed (e.g., "reboot for
81 * change to take effect").
89 typedef struct ia64_sal_retval (*ia64_sal_handler) (u64, ...);
92 SAL_FREQ_BASE_PLATFORM = 0,
93 SAL_FREQ_BASE_INTERVAL_TIMER = 1,
94 SAL_FREQ_BASE_REALTIME_CLOCK = 2
98 * The SAL system table is followed by a variable number of variable
99 * length descriptors. The structure of these descriptors follows
101 * The defininition follows SAL specs from July 2000
103 struct ia64_sal_systab {
104 u8 signature[4]; /* should be "SST_" */
105 u32 size; /* size of this table in bytes */
108 u16 entry_count; /* # of entries in variable portion */
115 /* oem_id & product_id: terminating NUL is missing if string is exactly 32 bytes long. */
117 u8 product_id[32]; /* ASCII product id */
121 enum sal_systab_entry_type {
122 SAL_DESC_ENTRY_POINT = 0,
124 SAL_DESC_PLATFORM_FEATURE = 2,
127 SAL_DESC_AP_WAKEUP = 5
139 #define SAL_DESC_SIZE(type) "\060\040\020\040\020\020"[(unsigned) type]
141 typedef struct ia64_sal_desc_entry_point {
148 }ia64_sal_desc_entry_point_t;
150 typedef struct ia64_sal_desc_memory {
152 u8 used_by_sal; /* needs to be mapped for SAL? */
153 u8 mem_attr; /* current memory attribute setting */
154 u8 access_rights; /* access rights set up by SAL */
155 u8 mem_attr_mask; /* mask of supported memory attributes */
157 u8 mem_type; /* memory type */
158 u8 mem_usage; /* memory usage */
159 u64 addr; /* physical address of memory */
160 u32 length; /* length (multiple of 4KB pages) */
163 } ia64_sal_desc_memory_t;
165 #define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK (1 << 0)
166 #define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT (1 << 1)
167 #define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT (1 << 2)
168 #define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT (1 << 3)
170 typedef struct ia64_sal_desc_platform_feature {
174 } ia64_sal_desc_platform_feature_t;
176 typedef struct ia64_sal_desc_tr {
178 u8 tr_type; /* 0 == instruction, 1 == data */
179 u8 regnum; /* translation register number */
181 u64 addr; /* virtual address of area covered */
182 u64 page_size; /* encoded page size */
184 } ia64_sal_desc_tr_t;
186 typedef struct ia64_sal_desc_ptc {
189 u32 num_domains; /* # of coherence domains */
190 u64 domain_info; /* physical address of domain info table */
191 } ia64_sal_desc_ptc_t;
193 typedef struct ia64_sal_ptc_domain_info {
194 u64 proc_count; /* number of processors in domain */
195 u64 proc_list; /* physical address of LID array */
196 } ia64_sal_ptc_domain_info_t;
198 typedef struct ia64_sal_ptc_domain_proc_entry {
199 u64 id : 8; /* id of processor */
200 u64 eid : 8; /* eid of processor */
201 } ia64_sal_ptc_domain_proc_entry_t;
204 #define IA64_SAL_AP_EXTERNAL_INT 0
206 typedef struct ia64_sal_desc_ap_wakeup {
208 u8 mechanism; /* 0 == external interrupt */
210 u64 vector; /* interrupt vector in range 0x10-0xff */
211 } ia64_sal_desc_ap_wakeup_t ;
213 extern ia64_sal_handler ia64_sal;
214 extern struct ia64_sal_desc_ptc *ia64_ptc_domain_info;
216 extern const char *ia64_sal_strerror (long status);
217 extern void ia64_sal_init (struct ia64_sal_systab *sal_systab);
219 /* SAL information type encodings */
221 SAL_INFO_TYPE_MCA = 0, /* Machine check abort information */
222 SAL_INFO_TYPE_INIT = 1, /* Init information */
223 SAL_INFO_TYPE_CMC = 2, /* Corrected machine check information */
224 SAL_INFO_TYPE_CPE = 3 /* Corrected platform error information */
227 /* Encodings for machine check parameter types */
229 SAL_MC_PARAM_RENDEZ_INT = 1, /* Rendezvous interrupt */
230 SAL_MC_PARAM_RENDEZ_WAKEUP = 2, /* Wakeup */
231 SAL_MC_PARAM_CPE_INT = 3 /* Corrected Platform Error Int */
234 /* Encodings for rendezvous mechanisms */
236 SAL_MC_PARAM_MECHANISM_INT = 1, /* Use interrupt */
237 SAL_MC_PARAM_MECHANISM_MEM = 2 /* Use memory synchronization variable*/
240 /* Encodings for vectors which can be registered by the OS with SAL */
242 SAL_VECTOR_OS_MCA = 0,
243 SAL_VECTOR_OS_INIT = 1,
244 SAL_VECTOR_OS_BOOT_RENDEZ = 2
247 /* Encodings for mca_opt parameter sent to SAL_MC_SET_PARAMS */
248 #define SAL_MC_PARAM_RZ_ALWAYS 0x1
249 #define SAL_MC_PARAM_BINIT_ESCALATE 0x10
252 * Definition of the SAL Error Log from the SAL spec
255 /* SAL Error Record Section GUID Definitions */
256 #define SAL_PROC_DEV_ERR_SECT_GUID \
257 EFI_GUID(0xe429faf1, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
258 #define SAL_PLAT_MEM_DEV_ERR_SECT_GUID \
259 EFI_GUID(0xe429faf2, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
260 #define SAL_PLAT_SEL_DEV_ERR_SECT_GUID \
261 EFI_GUID(0xe429faf3, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
262 #define SAL_PLAT_PCI_BUS_ERR_SECT_GUID \
263 EFI_GUID(0xe429faf4, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
264 #define SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID \
265 EFI_GUID(0xe429faf5, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
266 #define SAL_PLAT_PCI_COMP_ERR_SECT_GUID \
267 EFI_GUID(0xe429faf6, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
268 #define SAL_PLAT_SPECIFIC_ERR_SECT_GUID \
269 EFI_GUID(0xe429faf7, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
270 #define SAL_PLAT_HOST_CTLR_ERR_SECT_GUID \
271 EFI_GUID(0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
272 #define SAL_PLAT_BUS_ERR_SECT_GUID \
273 EFI_GUID(0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
275 #define MAX_CACHE_ERRORS 6
276 #define MAX_TLB_ERRORS 6
277 #define MAX_BUS_ERRORS 1
279 /* Definition of version according to SAL spec for logging purposes */
280 typedef struct sal_log_revision {
281 u8 minor; /* BCD (0..99) */
282 u8 major; /* BCD (0..99) */
283 } sal_log_revision_t;
285 /* Definition of timestamp according to SAL spec for logging purposes */
286 typedef struct sal_log_timestamp {
287 u8 slh_second; /* Second (0..59) */
288 u8 slh_minute; /* Minute (0..59) */
289 u8 slh_hour; /* Hour (0..23) */
291 u8 slh_day; /* Day (1..31) */
292 u8 slh_month; /* Month (1..12) */
293 u8 slh_year; /* Year (00..99) */
294 u8 slh_century; /* Century (19, 20, 21, ...) */
295 } sal_log_timestamp_t;
297 /* Definition of log record header structures */
298 typedef struct sal_log_record_header {
299 u64 id; /* Unique monotonically increasing ID */
300 sal_log_revision_t revision; /* Major and Minor revision of header */
301 u16 severity; /* Error Severity */
302 u32 len; /* Length of this error log in bytes */
303 sal_log_timestamp_t timestamp; /* Timestamp */
304 efi_guid_t platform_guid; /* Unique OEM Platform ID */
305 } sal_log_record_header_t;
307 /* Definition of log section header structures */
308 typedef struct sal_log_sec_header {
309 efi_guid_t guid; /* Unique Section ID */
310 sal_log_revision_t revision; /* Major and Minor revision of Section */
312 u32 len; /* Section length */
313 } sal_log_section_hdr_t;
315 typedef struct sal_log_mod_error_info {
318 requestor_identifier : 1,
319 responder_identifier : 1,
320 target_identifier : 1,
325 u64 requestor_identifier;
326 u64 responder_identifier;
327 u64 target_identifier;
329 } sal_log_mod_error_info_t;
331 typedef struct sal_processor_static_info {
341 pal_min_state_area_t min_state_area;
346 struct ia64_fpreg fr[128];
347 } sal_processor_static_info_t;
349 struct sal_cpuid_info {
354 typedef struct sal_log_processor_info {
355 sal_log_section_hdr_t header;
357 u64 proc_error_map : 1,
358 proc_state_param : 1,
360 psi_static_struct : 1,
364 num_reg_file_check : 4,
370 u64 proc_state_parameter;
373 * The rest of this structure consists of variable-length arrays, which can't be
376 sal_log_mod_error_info_t info[0];
378 * This is what the rest looked like if C supported variable-length arrays:
380 * sal_log_mod_error_info_t cache_check_info[.valid.num_cache_check];
381 * sal_log_mod_error_info_t tlb_check_info[.valid.num_tlb_check];
382 * sal_log_mod_error_info_t bus_check_info[.valid.num_bus_check];
383 * sal_log_mod_error_info_t reg_file_check_info[.valid.num_reg_file_check];
384 * sal_log_mod_error_info_t ms_check_info[.valid.num_ms_check];
385 * struct sal_cpuid_info cpuid_info;
386 * sal_processor_static_info_t processor_static_info;
388 } sal_log_processor_info_t;
390 /* Given a sal_log_processor_info_t pointer, return a pointer to the processor_static_info: */
391 #define SAL_LPI_PSI_INFO(l) \
392 ({ sal_log_processor_info_t *_l = (l); \
393 ((sal_processor_static_info_t *) \
394 ((char *) _l->info + ((_l->valid.num_cache_check + _l->valid.num_tlb_check \
395 + _l->valid.num_bus_check + _l->valid.num_reg_file_check \
396 + _l->valid.num_ms_check) * sizeof(sal_log_mod_error_info_t) \
397 + sizeof(struct sal_cpuid_info)))); \
400 /* platform error log structures */
402 typedef struct sal_log_mem_dev_err_info {
403 sal_log_section_hdr_t header;
405 u64 error_status : 1,
440 u8 oem_data[1]; /* Variable length data */
441 } sal_log_mem_dev_err_info_t;
443 typedef struct sal_log_sel_dev_err_info {
444 sal_log_section_hdr_t header;
469 } sal_log_sel_dev_err_info_t;
471 typedef struct sal_log_pci_bus_err_info {
472 sal_log_section_hdr_t header;
496 u8 oem_data[1]; /* Variable length data */
497 } sal_log_pci_bus_err_info_t;
499 typedef struct sal_log_smbios_dev_err_info {
500 sal_log_section_hdr_t header;
511 u8 data[1]; /* data of variable length, length == slsmb_length */
512 } sal_log_smbios_dev_err_info_t;
514 typedef struct sal_log_pci_comp_err_info {
515 sal_log_section_hdr_t header;
538 u64 reg_data_pairs[1];
540 * array of address/data register pairs is num_mem_regs + num_io_regs elements
541 * long. Each array element consists of a u64 address followed by a u64 data
542 * value. The oem_data array immediately follows the reg_data_pairs array
544 u8 oem_data[1]; /* Variable length data */
545 } sal_log_pci_comp_err_info_t;
547 typedef struct sal_log_plat_specific_err_info {
548 sal_log_section_hdr_t header;
557 u8 oem_data[1]; /* platform specific variable length data */
558 } sal_log_plat_specific_err_info_t;
560 typedef struct sal_log_host_ctlr_err_info {
561 sal_log_section_hdr_t header;
576 u8 oem_data[1]; /* Variable length OEM data */
577 } sal_log_host_ctlr_err_info_t;
579 typedef struct sal_log_plat_bus_err_info {
580 sal_log_section_hdr_t header;
595 u8 oem_data[1]; /* Variable length OEM data */
596 } sal_log_plat_bus_err_info_t;
598 /* Overall platform error section structure */
599 typedef union sal_log_platform_err_info {
600 sal_log_mem_dev_err_info_t mem_dev_err;
601 sal_log_sel_dev_err_info_t sel_dev_err;
602 sal_log_pci_bus_err_info_t pci_bus_err;
603 sal_log_smbios_dev_err_info_t smbios_dev_err;
604 sal_log_pci_comp_err_info_t pci_comp_err;
605 sal_log_plat_specific_err_info_t plat_specific_err;
606 sal_log_host_ctlr_err_info_t host_ctlr_err;
607 sal_log_plat_bus_err_info_t plat_bus_err;
608 } sal_log_platform_err_info_t;
610 /* SAL log over-all, multi-section error record structure (processor+platform) */
611 typedef struct err_rec {
612 sal_log_record_header_t sal_elog_header;
613 sal_log_processor_info_t proc_err;
614 sal_log_platform_err_info_t plat_err;
615 u8 oem_data_pad[1024];
619 * Now define a couple of inline functions for improved type checking
623 ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second,
624 unsigned long *drift_info)
626 struct ia64_sal_retval isrv;
628 SAL_CALL(isrv, SAL_FREQ_BASE, which, 0, 0, 0, 0, 0, 0);
629 *ticks_per_second = isrv.v0;
630 *drift_info = isrv.v1;
634 /* Flush all the processor and platform level instruction and/or data caches */
636 ia64_sal_cache_flush (u64 cache_type)
638 struct ia64_sal_retval isrv;
639 SAL_CALL(isrv, SAL_CACHE_FLUSH, cache_type, 0, 0, 0, 0, 0, 0);
644 /* Initialize all the processor and platform level instruction and data caches */
646 ia64_sal_cache_init (void)
648 struct ia64_sal_retval isrv;
649 SAL_CALL(isrv, SAL_CACHE_INIT, 0, 0, 0, 0, 0, 0, 0);
654 * Clear the processor and platform information logged by SAL with respect to the machine
655 * state at the time of MCA's, INITs, CMCs, or CPEs.
658 ia64_sal_clear_state_info (u64 sal_info_type)
660 struct ia64_sal_retval isrv;
661 SAL_CALL(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, 0,
667 /* Get the processor and platform information logged by SAL with respect to the machine
668 * state at the time of the MCAs, INITs, CMCs, or CPEs.
671 ia64_sal_get_state_info (u64 sal_info_type, u64 *sal_info)
673 struct ia64_sal_retval isrv;
674 SAL_CALL(isrv, SAL_GET_STATE_INFO, sal_info_type, 0,
675 sal_info, 0, 0, 0, 0);
683 * Get the maximum size of the information logged by SAL with respect to the machine state
684 * at the time of MCAs, INITs, CMCs, or CPEs.
687 ia64_sal_get_state_info_size (u64 sal_info_type)
689 struct ia64_sal_retval isrv;
690 SAL_CALL(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, 0,
698 * Causes the processor to go into a spin loop within SAL where SAL awaits a wakeup from
699 * the monarch processor. Must not lock, because it will not return on any cpu until the
700 * monarch processor sends a wake up.
703 ia64_sal_mc_rendez (void)
705 struct ia64_sal_retval isrv;
706 SAL_CALL_NOLOCK(isrv, SAL_MC_RENDEZ, 0, 0, 0, 0, 0, 0, 0);
711 * Allow the OS to specify the interrupt number to be used by SAL to interrupt OS during
712 * the machine check rendezvous sequence as well as the mechanism to wake up the
713 * non-monarch processor at the end of machine check processing.
716 ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout, u64 rz_always)
718 struct ia64_sal_retval isrv;
719 SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val,
720 timeout, rz_always, 0, 0);
724 /* Read from PCI configuration space */
726 ia64_sal_pci_config_read (u64 pci_config_addr, u64 size, u64 *value)
728 struct ia64_sal_retval isrv;
729 SAL_CALL(isrv, SAL_PCI_CONFIG_READ, pci_config_addr, size, 0, 0, 0, 0, 0);
735 /* Write to PCI configuration space */
737 ia64_sal_pci_config_write (u64 pci_config_addr, u64 size, u64 value)
739 struct ia64_sal_retval isrv;
740 SAL_CALL(isrv, SAL_PCI_CONFIG_WRITE, pci_config_addr, size, value,
746 * Register physical addresses of locations needed by SAL when SAL procedures are invoked
750 ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)
752 struct ia64_sal_retval isrv;
753 SAL_CALL(isrv, SAL_REGISTER_PHYSICAL_ADDR, phys_entry, phys_addr,
759 * Register software dependent code locations within SAL. These locations are handlers or
760 * entry points where SAL will pass control for the specified event. These event handlers
761 * are for the bott rendezvous, MCAs and INIT scenarios.
764 ia64_sal_set_vectors (u64 vector_type,
765 u64 handler_addr1, u64 gp1, u64 handler_len1,
766 u64 handler_addr2, u64 gp2, u64 handler_len2)
768 struct ia64_sal_retval isrv;
769 SAL_CALL(isrv, SAL_SET_VECTORS, vector_type,
770 handler_addr1, gp1, handler_len1,
771 handler_addr2, gp2, handler_len2);
776 /* Update the contents of PAL block in the non-volatile storage device */
778 ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
779 u64 *error_code, u64 *scratch_buf_size_needed)
781 struct ia64_sal_retval isrv;
782 SAL_CALL(isrv, SAL_UPDATE_PAL, param_buf, scratch_buf, scratch_buf_size,
785 *error_code = isrv.v0;
786 if (scratch_buf_size_needed)
787 *scratch_buf_size_needed = isrv.v1;
791 extern unsigned long sal_platform_features;
793 #endif /* _ASM_IA64_PAL_H */