1 #ifndef _ASM_IA64_PGTABLE_H
2 #define _ASM_IA64_PGTABLE_H
5 * This file contains the functions and defines necessary to modify and use
6 * the IA-64 page table tree.
8 * This hopefully works with any (fixed) IA-64 page-size, as defined
9 * in <asm/page.h> (currently 8192).
11 * Copyright (C) 1998-2002 Hewlett-Packard Co
12 * David Mosberger-Tang <davidm@hpl.hp.com>
15 #include <linux/config.h>
19 #include <asm/processor.h>
20 #include <asm/system.h>
21 #include <asm/types.h>
23 #define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */
26 * First, define the various bits in a PTE. Note that the PTE format
27 * matches the VHPT short format, the firt doubleword of the VHPD long
28 * format, and the first doubleword of the TLB insertion format.
34 #define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */
35 #define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */
36 #define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */
37 #define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */
38 #define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */
39 #define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */
40 #define _PAGE_MA_MASK (0x7 << 2)
41 #define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */
42 #define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */
43 #define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */
44 #define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */
45 #define _PAGE_PL_MASK (3 << 7)
46 #define _PAGE_AR_R (0 << 9) /* read only */
47 #define _PAGE_AR_RX (1 << 9) /* read & execute */
48 #define _PAGE_AR_RW (2 << 9) /* read & write */
49 #define _PAGE_AR_RWX (3 << 9) /* read, write & execute */
50 #define _PAGE_AR_R_RW (4 << 9) /* read / read & write */
51 #define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */
52 #define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */
53 #define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */
54 #define _PAGE_AR_MASK (7 << 9)
55 #define _PAGE_AR_SHIFT 9
56 #define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */
57 #define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */
58 #define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
59 #define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */
60 #define _PAGE_PROTNONE (__IA64_UL(1) << 63)
62 /* Valid only for a PTE with the present bit cleared: */
63 #define _PAGE_FILE (1 << 1) /* see swap & file pte remarks below */
65 #define _PFN_MASK _PAGE_PPN_MASK
66 #define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_A | _PAGE_D)
68 #define _PAGE_SIZE_4K 12
69 #define _PAGE_SIZE_8K 13
70 #define _PAGE_SIZE_16K 14
71 #define _PAGE_SIZE_64K 16
72 #define _PAGE_SIZE_256K 18
73 #define _PAGE_SIZE_1M 20
74 #define _PAGE_SIZE_4M 22
75 #define _PAGE_SIZE_16M 24
76 #define _PAGE_SIZE_64M 26
77 #define _PAGE_SIZE_256M 28
79 #define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB
80 #define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
81 #define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED
84 * Definitions for first level:
86 * PGDIR_SHIFT determines what a first-level page table entry can map.
88 #define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3))
89 #define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT)
90 #define PGDIR_MASK (~(PGDIR_SIZE-1))
91 #define PTRS_PER_PGD (__IA64_UL(1) << (PAGE_SHIFT-3))
92 #define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */
93 #define FIRST_USER_PGD_NR 0
96 * Definitions for second level:
98 * PMD_SHIFT determines the size of the area a second-level page table
101 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
102 #define PMD_SIZE (__IA64_UL(1) << PMD_SHIFT)
103 #define PMD_MASK (~(PMD_SIZE-1))
104 #define PTRS_PER_PMD (__IA64_UL(1) << (PAGE_SHIFT-3))
107 * Definitions for third level:
109 #define PTRS_PER_PTE (__IA64_UL(1) << (PAGE_SHIFT-3))
112 * All the normal masks have the "page accessed" bits on, as any time
113 * they are used, the page is accessed. They are cleared only by the
116 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A)
117 #define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
118 #define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
119 #define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
120 #define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
121 #define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX)
122 #define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
124 # ifndef __ASSEMBLY__
126 #include <asm/bitops.h>
127 #include <asm/cacheflush.h>
128 #include <asm/mmu_context.h>
129 #include <asm/processor.h>
132 * Next come the mappings that determine how mmap() protection bits
133 * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The
134 * _P version gets used for a private shared memory segment, the _S
135 * version gets used for a shared memory segment with MAP_SHARED on.
136 * In a private shared memory segment, we do a copy-on-write if a task
137 * attempts to write to the page.
140 #define __P000 PAGE_NONE
141 #define __P001 PAGE_READONLY
142 #define __P010 PAGE_READONLY /* write to priv pg -> copy & make writable */
143 #define __P011 PAGE_READONLY /* ditto */
144 #define __P100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
145 #define __P101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
146 #define __P110 PAGE_COPY
147 #define __P111 PAGE_COPY
149 #define __S000 PAGE_NONE
150 #define __S001 PAGE_READONLY
151 #define __S010 PAGE_SHARED /* we don't have (and don't need) write-only */
152 #define __S011 PAGE_SHARED
153 #define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
154 #define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
155 #define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
156 #define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
158 #define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
159 #define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
160 #define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
164 * Some definitions to translate between mem_map, PTEs, and page addresses:
168 /* Quick test to see if ADDR is a (potentially) valid physical address. */
170 ia64_phys_addr_valid (unsigned long addr)
172 return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
175 #ifndef CONFIG_DISCONTIGMEM
177 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
178 * memory. For the return value to be meaningful, ADDR must be >=
179 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
180 * require a hash-, or multi-level tree-lookup or something of that
181 * sort) but it guarantees to return TRUE only if accessing the page
182 * at that address does not cause an error. Note that there may be
183 * addresses for which kern_addr_valid() returns FALSE even though an
184 * access would not cause an error (e.g., this is typically true for
185 * memory mapped I/O regions.
187 * XXX Need to implement this for IA-64.
189 #define kern_addr_valid(addr) (1)
194 * Now come the defines and routines to manage and access the three-level
199 * On some architectures, special things need to be done when setting
200 * the PTE in a page table. Nothing special needs to be on IA-64.
202 #define set_pte(ptep, pteval) (*(ptep) = (pteval))
204 #define RGN_SIZE (1UL << 61)
205 #define RGN_MAP_LIMIT ((1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE) /* per region addr limit */
208 #define VMALLOC_START (0xa000000000000000 + 3*PERCPU_PAGE_SIZE)
209 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
210 #ifdef CONFIG_VIRTUAL_MEM_MAP
211 # define VMALLOC_END_INIT (0xa000000000000000 + (1UL << (4*PAGE_SHIFT - 9)))
212 # define VMALLOC_END vmalloc_end
213 extern unsigned long vmalloc_end;
215 # define VMALLOC_END (0xa000000000000000 + (1UL << (4*PAGE_SHIFT - 9)))
219 * Conversion functions: convert page frame number (pfn) and a protection value to a page
222 #define pfn_pte(pfn, pgprot) \
223 ({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; })
225 /* Extract pfn from pte. */
226 #define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT)
228 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
230 #define pte_modify(_pte, newprot) \
231 (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
233 #define page_pte_prot(page,prot) mk_pte(page, prot)
234 #define page_pte(page) page_pte_prot(page, __pgprot(0))
236 #define pte_none(pte) (!pte_val(pte))
237 #define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
238 #define pte_clear(pte) (pte_val(*(pte)) = 0UL)
239 #ifndef CONFIG_DISCONTIGMEM
240 /* pte_page() returns the "struct page *" corresponding to the PTE: */
241 #define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
244 #define pmd_none(pmd) (!pmd_val(pmd))
245 #define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd)))
246 #define pmd_present(pmd) (pmd_val(pmd) != 0UL)
247 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
248 #define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
249 #define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
251 #define pgd_none(pgd) (!pgd_val(pgd))
252 #define pgd_bad(pgd) (!ia64_phys_addr_valid(pgd_val(pgd)))
253 #define pgd_present(pgd) (pgd_val(pgd) != 0UL)
254 #define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL)
255 #define pgd_page(pgd) ((unsigned long) __va(pgd_val(pgd) & _PFN_MASK))
258 * The following have defined behavior only work if pte_present() is true.
260 #define pte_read(pte) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) < 6)
261 #define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
262 #define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0)
263 #define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0)
264 #define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0)
265 #define pte_file(pte) ((pte_val(pte) & _PAGE_FILE) != 0)
267 * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
270 #define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW))
271 #define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW))
272 #define pte_mkexec(pte) (__pte(pte_val(pte) | _PAGE_AR_RX))
273 #define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A))
274 #define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A))
275 #define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D))
276 #define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
279 * Macro to make mark a page protection value as "uncacheable". Note
280 * that "protection" is really a misnomer here as the protection value
281 * contains the memory attribute bits, dirty bits, and various other
284 #define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC)
287 * Macro to make mark a page protection value as "write-combining".
288 * Note that "protection" is really a misnomer here as the protection
289 * value contains the memory attribute bits, dirty bits, and various
290 * other bits as well. Accesses through a write-combining translation
291 * works bypasses the caches, but does allow for consecutive writes to
292 * be combined into single (but larger) write transactions.
294 #ifdef CONFIG_MCKINLEY_A0_SPECIFIC
295 # define pgprot_writecombine(prot) prot
297 # define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC)
300 static inline unsigned long
301 pgd_index (unsigned long address)
303 unsigned long region = address >> 61;
304 unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
306 return (region << (PAGE_SHIFT - 6)) | l1index;
309 /* The offset in the 1-level directory is given by the 3 region bits
310 (61..63) and the seven level-1 bits (33-39). */
312 pgd_offset (struct mm_struct *mm, unsigned long address)
314 return mm->pgd + pgd_index(address);
317 /* In the kernel's mapped region we have a full 43 bit space available and completely
318 ignore the region number (since we know its in region number 5). */
319 #define pgd_offset_k(addr) \
320 (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
322 /* Find an entry in the second-level page table.. */
323 #define pmd_offset(dir,addr) \
324 ((pmd_t *) pgd_page(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
327 * Find an entry in the third-level page table. This looks more complicated than it
328 * should be because some platforms place page tables in high memory.
330 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
331 #define pte_offset_kernel(dir,addr) ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr))
332 #define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr)
333 #define pte_offset_map_nested(dir,addr) pte_offset_map(dir, addr)
334 #define pte_unmap(pte) do { } while (0)
335 #define pte_unmap_nested(pte) do { } while (0)
337 /* atomic versions of the some PTE manipulations: */
340 ptep_test_and_clear_young (pte_t *ptep)
343 return test_and_clear_bit(_PAGE_A_BIT, ptep);
348 set_pte(ptep, pte_mkold(pte));
354 ptep_test_and_clear_dirty (pte_t *ptep)
357 return test_and_clear_bit(_PAGE_D_BIT, ptep);
362 set_pte(ptep, pte_mkclean(pte));
368 ptep_get_and_clear (pte_t *ptep)
371 return __pte(xchg((long *) ptep, 0));
380 ptep_set_wrprotect (pte_t *ptep)
383 unsigned long new, old;
386 old = pte_val(*ptep);
387 new = pte_val(pte_wrprotect(__pte (old)));
388 } while (cmpxchg((unsigned long *) ptep, old, new) != old);
390 pte_t old_pte = *ptep;
391 set_pte(ptep, pte_wrprotect(old_pte));
396 ptep_mkdirty (pte_t *ptep)
399 set_bit(_PAGE_D_BIT, ptep);
401 pte_t old_pte = *ptep;
402 set_pte(ptep, pte_mkdirty(old_pte));
407 pte_same (pte_t a, pte_t b)
409 return pte_val(a) == pte_val(b);
412 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
413 extern void paging_init (void);
416 * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of
417 * bits in the swap-type field of the swap pte. It would be nice to
418 * enforce that, but we can't easily include <linux/swap.h> here.
419 * (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...).
421 * Format of swap pte:
422 * bit 0 : present bit (must be zero)
423 * bit 1 : _PAGE_FILE (must be zero)
424 * bits 2- 8: swap-type
425 * bits 9-62: swap offset
426 * bit 63 : _PAGE_PROTNONE bit
428 * Format of file pte:
429 * bit 0 : present bit (must be zero)
430 * bit 1 : _PAGE_FILE (must be one)
431 * bits 2-62: file_offset/PAGE_SIZE
432 * bit 63 : _PAGE_PROTNONE bit
434 #define __swp_type(entry) (((entry).val >> 2) & 0x7f)
435 #define __swp_offset(entry) (((entry).val << 1) >> 10)
436 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((long) (offset) << 9) })
437 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
438 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
440 #define PTE_FILE_MAX_BITS 61
441 #define pte_to_pgoff(pte) ((pte_val(pte) << 1) >> 3)
442 #define pgoff_to_pte(off) ((pte_t) { ((off) << 2) | _PAGE_FILE })
444 #define io_remap_page_range remap_page_range /* XXX is this right? */
447 * ZERO_PAGE is a global shared page that is always zero: used
448 * for zero-mapped memory areas etc..
450 extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
451 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
453 /* We provide our own get_unmapped_area to cope with VA holes for userland */
454 #define HAVE_ARCH_UNMAPPED_AREA
456 typedef pte_t *pte_addr_t;
458 # ifdef CONFIG_VIRTUAL_MEM_MAP
460 /* arch mem_map init routine is needed due to holes in a virtual mem_map */
461 # define __HAVE_ARCH_MEMMAP_INIT
463 extern void memmap_init (struct page *start, unsigned long size, int nid, unsigned long zone,
464 unsigned long start_pfn);
465 # endif /* CONFIG_VIRTUAL_MEM_MAP */
466 # endif /* !__ASSEMBLY__ */
469 * Identity-mapped regions use a large page size. We'll call such large pages
470 * "granules". If you can think of a better name that's unambiguous, let me
473 #if defined(CONFIG_IA64_GRANULE_64MB)
474 # define IA64_GRANULE_SHIFT _PAGE_SIZE_64M
475 #elif defined(CONFIG_IA64_GRANULE_16MB)
476 # define IA64_GRANULE_SHIFT _PAGE_SIZE_16M
478 #define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT)
480 * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL):
482 #define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M
483 #define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT)
484 #define KERNEL_TR_PAGE_NUM ((KERNEL_START - PAGE_OFFSET) / KERNEL_TR_PAGE_SIZE)
487 * No page table caches to initialise
489 #define pgtable_cache_init() do { } while (0)
491 #endif /* _ASM_IA64_PGTABLE_H */