2 * pci.c - Low-Level PCI Access in IA-64
4 * Derived from bios32.c of i386 tree.
6 * Copyright (C) 2002 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Bjorn Helgaas <bjorn_helgaas@hp.com>
10 * Note: Above list of copyright holders is incomplete...
12 #include <linux/config.h>
14 #include <linux/acpi.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/smp_lock.h>
22 #include <linux/spinlock.h>
24 #include <asm/machvec.h>
26 #include <asm/segment.h>
27 #include <asm/system.h>
43 #define DBG(x...) printk(x)
48 struct pci_fixup pcibios_fixups[1];
51 * Low-level SAL-based PCI configuration access functions. Note that SAL
52 * calls are already serialized (via sal_lock), so we don't need another
53 * synchronization mechanism here.
56 #define PCI_SAL_ADDRESS(seg, bus, dev, fn, reg) \
57 ((u64)(seg << 24) | (u64)(bus << 16) | \
58 (u64)(dev << 11) | (u64)(fn << 8) | (u64)(reg))
62 __pci_sal_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
67 if (!value || (seg > 255) || (bus > 255) || (dev > 31) || (fn > 7) || (reg > 255))
70 result = ia64_sal_pci_config_read(PCI_SAL_ADDRESS(seg, bus, dev, fn, reg), len, &data);
78 __pci_sal_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
80 if ((seg > 255) || (bus > 255) || (dev > 31) || (fn > 7) || (reg > 255))
83 return ia64_sal_pci_config_write(PCI_SAL_ADDRESS(seg, bus, dev, fn, reg), len, value);
88 pci_sal_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
90 return __pci_sal_read(PCI_SEGMENT(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
95 pci_sal_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
97 return __pci_sal_write(PCI_SEGMENT(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
101 struct pci_ops pci_sal_ops = {
102 .read = pci_sal_read,
103 .write = pci_sal_write
106 struct pci_ops *pci_root_ops = &pci_sal_ops; /* default to SAL */
111 if (!acpi_pci_irq_init())
112 printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
114 printk(KERN_WARNING "PCI: Invalid ACPI-PCI IRQ routing table\n");
118 subsys_initcall(pci_acpi_init);
120 /* Called by ACPI when it finds a new root bus. */
122 static struct pci_controller *
123 alloc_pci_controller (int seg)
125 struct pci_controller *controller;
127 controller = kmalloc(sizeof(*controller), GFP_KERNEL);
131 memset(controller, 0, sizeof(*controller));
132 controller->segment = seg;
136 static struct pci_bus *
137 scan_root_bus (int bus, struct pci_ops *ops, void *sysdata)
142 * We know this is a new root bus we haven't seen before, so
143 * scan it, even if we've seen the same bus number in a different
146 b = kmalloc(sizeof(*b), GFP_KERNEL);
150 memset(b, 0, sizeof(*b));
151 INIT_LIST_HEAD(&b->children);
152 INIT_LIST_HEAD(&b->devices);
154 list_add_tail(&b->node, &pci_root_buses);
156 b->number = b->secondary = bus;
157 b->resource[0] = &ioport_resource;
158 b->resource[1] = &iomem_resource;
160 b->sysdata = sysdata;
162 b->subordinate = pci_do_scan_bus(b);
168 alloc_resource (char *name, struct resource *root, unsigned long start, unsigned long end, unsigned long flags)
170 struct resource *res;
172 res = kmalloc(sizeof(*res), GFP_KERNEL);
176 memset(res, 0, sizeof(*res));
182 if (request_resource(root, res))
189 add_io_space (struct acpi_resource_address64 *addr)
195 if (addr->address_translation_offset == 0)
196 return IO_SPACE_BASE(0); /* part of legacy IO space */
198 if (addr->attribute.io.translation_attribute == ACPI_SPARSE_TRANSLATION)
201 offset = (u64) ioremap(addr->address_translation_offset, 0);
202 for (i = 0; i < num_io_spaces; i++)
203 if (io_space[i].mmio_base == offset &&
204 io_space[i].sparse == sparse)
205 return IO_SPACE_BASE(i);
207 if (num_io_spaces == MAX_IO_SPACES) {
208 printk("Too many IO port spaces\n");
213 io_space[i].mmio_base = offset;
214 io_space[i].sparse = sparse;
216 return IO_SPACE_BASE(i);
220 count_window (struct acpi_resource *resource, void *data)
222 unsigned int *windows = (unsigned int *) data;
223 struct acpi_resource_address64 addr;
226 status = acpi_resource_to_address64(resource, &addr);
227 if (ACPI_SUCCESS(status))
228 if (addr.resource_type == ACPI_MEMORY_RANGE ||
229 addr.resource_type == ACPI_IO_RANGE)
235 struct pci_root_info {
236 struct pci_controller *controller;
241 add_window (struct acpi_resource *res, void *data)
243 struct pci_root_info *info = (struct pci_root_info *) data;
244 struct pci_window *window;
245 struct acpi_resource_address64 addr;
247 unsigned long flags, offset = 0;
248 struct resource *root;
250 status = acpi_resource_to_address64(res, &addr);
251 if (ACPI_SUCCESS(status)) {
252 if (addr.resource_type == ACPI_MEMORY_RANGE) {
253 flags = IORESOURCE_MEM;
254 root = &iomem_resource;
255 offset = addr.address_translation_offset;
256 } else if (addr.resource_type == ACPI_IO_RANGE) {
257 flags = IORESOURCE_IO;
258 root = &ioport_resource;
259 offset = add_io_space(&addr);
265 window = &info->controller->window[info->controller->windows++];
266 window->resource.flags |= flags;
267 window->resource.start = addr.min_address_range;
268 window->resource.end = addr.max_address_range;
269 window->offset = offset;
271 if (alloc_resource(info->name, root, addr.min_address_range + offset,
272 addr.max_address_range + offset, flags))
273 printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
274 addr.min_address_range + offset, addr.max_address_range + offset,
275 root->name, info->name);
282 pcibios_scan_root (void *handle, int seg, int bus)
284 struct pci_root_info info;
285 struct pci_controller *controller;
286 unsigned int windows = 0;
289 printk("PCI: Probing PCI hardware on bus (%02x:%02x)\n", seg, bus);
290 controller = alloc_pci_controller(seg);
294 controller->acpi_handle = handle;
296 acpi_walk_resources(handle, METHOD_NAME__CRS, count_window, &windows);
297 controller->window = kmalloc(sizeof(*controller->window) * windows, GFP_KERNEL);
298 if (!controller->window)
301 name = kmalloc(16, GFP_KERNEL);
305 sprintf(name, "PCI Bus %02x:%02x", seg, bus);
306 info.controller = controller;
308 acpi_walk_resources(handle, METHOD_NAME__CRS, add_window, &info);
310 return scan_root_bus(bus, pci_root_ops, controller);
313 kfree(controller->window);
321 pcibios_fixup_device_resources (struct pci_dev *dev, struct pci_bus *bus)
323 struct pci_controller *controller = PCI_CONTROLLER(dev);
324 struct pci_window *window;
327 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
328 if (!dev->resource[i].start)
331 #define contains(win, res) ((res)->start >= (win)->start && \
332 (res)->end <= (win)->end)
334 for (j = 0; j < controller->windows; j++) {
335 window = &controller->window[j];
336 if (((dev->resource[i].flags & IORESOURCE_MEM &&
337 window->resource.flags & IORESOURCE_MEM) ||
338 (dev->resource[i].flags & IORESOURCE_IO &&
339 window->resource.flags & IORESOURCE_IO)) &&
340 contains(&window->resource, &dev->resource[i])) {
341 dev->resource[i].start += window->offset;
342 dev->resource[i].end += window->offset;
349 * Called after each bus is probed, but before its children are examined.
352 pcibios_fixup_bus (struct pci_bus *b)
354 struct list_head *ln;
356 for (ln = b->devices.next; ln != &b->devices; ln = ln->next)
357 pcibios_fixup_device_resources(pci_dev_b(ln), b);
362 #warning pcibios_update_resource() is now a generic implementation - please check
365 pcibios_update_irq (struct pci_dev *dev, int irq)
367 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
369 /* ??? FIXME -- record old value for shutdown. */
373 pcibios_enable_resources (struct pci_dev *dev, int mask)
382 pci_read_config_word(dev, PCI_COMMAND, &cmd);
384 for (idx=0; idx<6; idx++) {
385 /* Only set up the desired resources. */
386 if (!(mask & (1 << idx)))
389 r = &dev->resource[idx];
390 if (!r->start && r->end) {
392 "PCI: Device %s not available because of resource collisions\n",
396 if (r->flags & IORESOURCE_IO)
397 cmd |= PCI_COMMAND_IO;
398 if (r->flags & IORESOURCE_MEM)
399 cmd |= PCI_COMMAND_MEMORY;
401 if (dev->resource[PCI_ROM_RESOURCE].start)
402 cmd |= PCI_COMMAND_MEMORY;
403 if (cmd != old_cmd) {
404 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
405 pci_write_config_word(dev, PCI_COMMAND, cmd);
411 pcibios_enable_device (struct pci_dev *dev, int mask)
415 ret = pcibios_enable_resources(dev, mask);
419 printk(KERN_INFO "PCI: Found IRQ %d for device %s\n", dev->irq, dev->slot_name);
420 return acpi_pci_irq_enable(dev);
424 pcibios_align_resource (void *data, struct resource *res,
425 unsigned long size, unsigned long align)
430 * PCI BIOS setup, always defaults to SAL interface
433 pcibios_setup (char *str)
439 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
440 enum pci_mmap_state mmap_state, int write_combine)
443 * I/O space cannot be accessed via normal processor loads and stores on this
446 if (mmap_state == pci_mmap_io)
448 * XXX we could relax this for I/O spaces for which ACPI indicates that
449 * the space is 1-to-1 mapped. But at the moment, we don't support
450 * multiple PCI address spaces and the legacy I/O space is not 1-to-1
451 * mapped, so this is moot.
456 * Leave vm_pgoff as-is, the PCI space address is the physical address on this
459 vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO);
462 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
464 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
466 if (remap_page_range(vma, vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
467 vma->vm_end - vma->vm_start, vma->vm_page_prot))
474 * pci_cacheline_size - determine cacheline size for PCI devices
477 * We want to use the line-size of the outer-most cache. We assume
478 * that this line-size is the same for all CPUs.
480 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
482 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
485 pci_cacheline_size (void)
487 u64 levels, unique_caches;
489 pal_cache_config_info_t cci;
490 static u8 cacheline_size;
493 return cacheline_size;
495 status = ia64_pal_cache_summary(&levels, &unique_caches);
497 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
498 __FUNCTION__, status);
499 return SMP_CACHE_BYTES;
502 status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
505 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
506 __FUNCTION__, status);
507 return SMP_CACHE_BYTES;
509 cacheline_size = 1 << cci.pcci_line_size;
510 return cacheline_size;
514 * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
515 * @dev: the PCI device for which MWI is enabled
517 * For ia64, we can get the cacheline sizes from PAL.
519 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
522 pcibios_prep_mwi (struct pci_dev *dev)
524 unsigned long desired_linesize, current_linesize;
528 desired_linesize = pci_cacheline_size();
530 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
531 current_linesize = 4 * pci_linesize;
532 if (desired_linesize != current_linesize) {
533 printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
534 dev->slot_name, current_linesize);
535 if (current_linesize > desired_linesize) {
536 printk(" expected %lu bytes instead\n", desired_linesize);
539 printk(" correcting to %lu\n", desired_linesize);
540 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);