2 Driver for Zarlink MT312 Satellite Channel Decoder
4 Copyright (C) 2003 Andreas Oberritter <obi@saftware.de>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 http://products.zarlink.com/product_profiles/MT312.htm
23 http://products.zarlink.com/product_profiles/SL1935.htm
26 #include <linux/delay.h>
27 #include <linux/errno.h>
28 #include <linux/init.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
32 #include "dvb_frontend.h"
35 #define I2C_ADDR_MT312 0x0e
36 #define I2C_ADDR_SL1935 0x61
37 #define I2C_ADDR_TSA5059 0x61
41 #define MT312_SYS_CLK 90000000UL /* 90 MHz */
42 #define MT312_PLL_CLK 10000000UL /* 10 MHz */
44 static struct dvb_frontend_info mt312_info = {
45 .name = "Zarlink MT312",
47 .frequency_min = 950000,
48 .frequency_max = 2150000,
49 .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128,
50 /*.frequency_tolerance = 29500, FIXME: binary compatibility waste? */
51 .symbol_rate_min = MT312_SYS_CLK / 128,
52 .symbol_rate_max = MT312_SYS_CLK / 2,
53 /*.symbol_rate_tolerance = 500, FIXME: binary compatibility waste? 2% */
56 FE_CAN_INVERSION_AUTO | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
57 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
58 FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_RECOVER |
59 FE_CAN_CLEAN_SETUP | FE_CAN_MUTE_TS
62 static int mt312_read(struct dvb_i2c_bus *i2c,
63 const enum mt312_reg_addr reg, void *buf,
67 struct i2c_msg msg[2];
68 u8 regbuf[1] = { reg };
70 msg[0].addr = I2C_ADDR_MT312;
74 msg[1].addr = I2C_ADDR_MT312;
75 msg[1].flags = I2C_M_RD;
79 ret = i2c->xfer(i2c, msg, 2);
82 printk(KERN_ERR "%s: ret == %d\n", __FUNCTION__, ret);
88 printk(KERN_INFO "R(%d):", reg & 0x7f);
89 for (i = 0; i < count; i++)
90 printk(" %02x", ((const u8 *) buf)[i]);
98 static int mt312_write(struct dvb_i2c_bus *i2c,
99 const enum mt312_reg_addr reg, const void *src,
109 printk(KERN_INFO "W(%d):", reg & 0x7f);
110 for (i = 0; i < count; i++)
111 printk(" %02x", ((const u8 *) src)[i]);
117 memcpy(&buf[1], src, count);
119 msg.addr = I2C_ADDR_MT312;
124 ret = i2c->xfer(i2c, &msg, 1);
127 printk(KERN_ERR "%s: ret == %d\n", __FUNCTION__, ret);
134 static inline int mt312_readreg(struct dvb_i2c_bus *i2c,
135 const enum mt312_reg_addr reg, u8 * val)
137 return mt312_read(i2c, reg, val, 1);
140 static inline int mt312_writereg(struct dvb_i2c_bus *i2c,
141 const enum mt312_reg_addr reg, const u8 val)
143 return mt312_write(i2c, reg, &val, 1);
146 static int mt312_pll_write(struct dvb_i2c_bus *i2c, const u8 addr,
147 u8 * buf, const u8 len)
157 if ((ret = mt312_writereg(i2c, GPP_CTRL, 0x40)) < 0)
160 if ((ret = i2c->xfer(i2c, &msg, 1)) != 1)
161 printk(KERN_ERR "%s: i/o error (ret == %d)\n", __FUNCTION__, ret);
163 if ((ret = mt312_writereg(i2c, GPP_CTRL, 0x00)) < 0)
169 static inline u32 mt312_div(u32 a, u32 b)
171 return (a + (b / 2)) / b;
174 static int sl1935_set_tv_freq(struct dvb_i2c_bus *i2c, u32 freq, u32 sr)
176 /* 155 uA, Baseband Path B */
177 u8 buf[4] = { 0x00, 0x00, 0x80, 0x00 };
183 if (sr < 10000000) { /* 1-10 MSym/s: ratio 2 ^ 3 */
185 buf[2] |= 0x40; /* 690 uA */
186 } else if (sr < 15000000) { /* 10-15 MSym/s: ratio 2 ^ 4 */
188 buf[2] |= 0x20; /* 330 uA */
189 } else { /* 15-45 MSym/s: ratio 2 ^ 7 */
191 buf[3] |= 0x08; /* Baseband Path A */
194 div = mt312_div(MT312_PLL_CLK, 1 << exp);
195 ref = mt312_div(freq * 1000, div);
196 mt312_info.frequency_stepsize = mt312_div(div, 1000);
198 buf[0] = (ref >> 8) & 0x7f;
199 buf[1] = (ref >> 0) & 0xff;
205 printk(KERN_INFO "synth dword = %02x%02x%02x%02x\n", buf[0],
206 buf[1], buf[2], buf[3]);
208 return mt312_pll_write(i2c, I2C_ADDR_SL1935, buf, sizeof(buf));
211 static int tsa5059_set_tv_freq(struct dvb_i2c_bus *i2c, u32 freq, u32 sr)
215 u32 ref = mt312_div(freq, 125);
217 buf[0] = (ref >> 8) & 0x7f;
218 buf[1] = (ref >> 0) & 0xff;
219 buf[2] = 0x84 | ((ref >> 10) & 0x60);
225 printk(KERN_INFO "synth dword = %02x%02x%02x%02x\n", buf[0],
226 buf[1], buf[2], buf[3]);
228 return mt312_pll_write(i2c, I2C_ADDR_TSA5059, buf, sizeof(buf));
231 static int mt312_reset(struct dvb_i2c_bus *i2c, const u8 full)
233 return mt312_writereg(i2c, RESET, full ? 0x80 : 0x40);
236 static int mt312_init(struct dvb_i2c_bus *i2c, const long id)
242 if ((ret = mt312_writereg(i2c, CONFIG, 0x8c)) < 0)
245 /* wait at least 150 usec */
249 if ((ret = mt312_reset(i2c, 1)) < 0)
253 buf[0] = mt312_div(MT312_SYS_CLK * 2, 1000000);
256 buf[1] = mt312_div(MT312_PLL_CLK, 15000 * 4);
258 if ((ret = mt312_write(i2c, SYS_CLK, buf, sizeof(buf))) < 0)
261 if ((ret = mt312_writereg(i2c, SNR_THS_HIGH, 0x32)) < 0)
264 if ((ret = mt312_writereg(i2c, OP_CTRL, 0x53)) < 0)
271 if ((ret = mt312_write(i2c, TS_SW_LIM_L, buf, sizeof(buf))) < 0)
274 if ((ret = mt312_writereg(i2c, CS_SW_LIM, 0x69)) < 0)
280 static int mt312_send_master_cmd(struct dvb_i2c_bus *i2c,
281 const struct dvb_diseqc_master_cmd *c)
286 if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
289 if ((ret = mt312_readreg(i2c, DISEQC_MODE, &diseqc_mode)) < 0)
293 mt312_write(i2c, (0x80 | DISEQC_INSTR), c->msg, c->msg_len)) < 0)
297 mt312_writereg(i2c, DISEQC_MODE,
298 (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
302 /* set DISEQC_MODE[2:0] to zero if a return message is expected */
303 if (c->msg[0] & 0x02)
305 mt312_writereg(i2c, DISEQC_MODE, (diseqc_mode & 0x40))) < 0)
311 static int mt312_recv_slave_reply(struct dvb_i2c_bus *i2c,
312 struct dvb_diseqc_slave_reply *r)
318 static int mt312_send_burst(struct dvb_i2c_bus *i2c, const fe_sec_mini_cmd_t c)
320 const u8 mini_tab[2] = { 0x02, 0x03 };
328 if ((ret = mt312_readreg(i2c, DISEQC_MODE, &diseqc_mode)) < 0)
332 mt312_writereg(i2c, DISEQC_MODE,
333 (diseqc_mode & 0x40) | mini_tab[c])) < 0)
339 static int mt312_set_tone(struct dvb_i2c_bus *i2c, const fe_sec_tone_mode_t t)
341 const u8 tone_tab[2] = { 0x01, 0x00 };
346 if (t > SEC_TONE_OFF)
349 if ((ret = mt312_readreg(i2c, DISEQC_MODE, &diseqc_mode)) < 0)
353 mt312_writereg(i2c, DISEQC_MODE,
354 (diseqc_mode & 0x40) | tone_tab[t])) < 0)
360 static int mt312_set_voltage(struct dvb_i2c_bus *i2c, const fe_sec_voltage_t v)
362 const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
364 if (v > SEC_VOLTAGE_OFF)
367 return mt312_writereg(i2c, DISEQC_MODE, volt_tab[v]);
370 static int mt312_read_status(struct dvb_i2c_bus *i2c, fe_status_t * s)
377 if ((ret = mt312_read(i2c, QPSK_STAT_H, status, sizeof(status))) < 0)
380 if (status[0] & 0xc0)
381 *s |= FE_HAS_SIGNAL; /* signal noise ratio */
382 if (status[0] & 0x04)
383 *s |= FE_HAS_CARRIER; /* qpsk carrier lock */
384 if (status[2] & 0x02)
385 *s |= FE_HAS_VITERBI; /* viterbi lock */
386 if (status[2] & 0x04)
387 *s |= FE_HAS_SYNC; /* byte align lock */
388 if (status[0] & 0x01)
389 *s |= FE_HAS_LOCK; /* qpsk lock */
394 static int mt312_read_bercnt(struct dvb_i2c_bus *i2c, u32 * ber)
399 if ((ret = mt312_read(i2c, RS_BERCNT_H, buf, 3)) < 0)
402 *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
407 static int mt312_read_agc(struct dvb_i2c_bus *i2c, u16 * signal_strength)
414 if ((ret = mt312_read(i2c, AGC_H, buf, sizeof(buf))) < 0)
417 agc = (buf[0] << 6) | (buf[1] >> 2);
418 err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
420 *signal_strength = agc;
422 printk(KERN_DEBUG "agc=%08x err_db=%hd\n", agc, err_db);
427 static int mt312_read_snr(struct dvb_i2c_bus *i2c, u16 * snr)
432 if ((ret = mt312_read(i2c, M_SNR_H, &buf, sizeof(buf))) < 0)
435 *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
440 static int mt312_read_ubc(struct dvb_i2c_bus *i2c, u32 * ubc)
445 if ((ret = mt312_read(i2c, RS_UBC_H, &buf, sizeof(buf))) < 0)
448 *ubc = (buf[0] << 8) | buf[1];
453 static int mt312_set_frontend(struct dvb_i2c_bus *i2c,
454 const struct dvb_frontend_parameters *p,
461 const u8 fec_tab[10] =
462 { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
463 const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
465 int (*set_tv_freq)(struct dvb_i2c_bus *i2c, u32 freq, u32 sr);
467 if ((p->frequency < mt312_info.frequency_min)
468 || (p->frequency > mt312_info.frequency_max))
471 if ((p->inversion < INVERSION_OFF)
472 || (p->inversion > INVERSION_AUTO))
475 if ((p->u.qpsk.symbol_rate < mt312_info.symbol_rate_min)
476 || (p->u.qpsk.symbol_rate > mt312_info.symbol_rate_max))
479 if ((p->u.qpsk.fec_inner < FEC_NONE)
480 || (p->u.qpsk.fec_inner > FEC_AUTO))
483 if ((p->u.qpsk.fec_inner == FEC_4_5)
484 || (p->u.qpsk.fec_inner == FEC_8_9))
489 set_tv_freq = tsa5059_set_tv_freq;
492 set_tv_freq = sl1935_set_tv_freq;
498 if ((ret = set_tv_freq(i2c, p->frequency, p->u.qpsk.symbol_rate)) < 0)
501 /* sr = (u16)(sr * 256.0 / 1000000.0) */
502 sr = mt312_div(p->u.qpsk.symbol_rate * 4, 15625);
505 buf[0] = (sr >> 8) & 0x3f;
506 buf[1] = (sr >> 0) & 0xff;
509 buf[2] = inv_tab[p->inversion] | fec_tab[p->u.qpsk.fec_inner];
512 buf[3] = 0x40; /* swap I and Q before QPSK demodulation */
514 if (p->u.qpsk.symbol_rate < 10000000)
515 buf[3] |= 0x04; /* use afc mode */
520 if ((ret = mt312_write(i2c, SYM_RATE_H, buf, sizeof(buf))) < 0)
526 static int mt312_get_inversion(struct dvb_i2c_bus *i2c,
527 fe_spectral_inversion_t * i)
532 if ((ret = mt312_readreg(i2c, VIT_MODE, &vit_mode)) < 0)
535 if (vit_mode & 0x80) /* auto inversion was used */
536 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
541 static int mt312_get_symbol_rate(struct dvb_i2c_bus *i2c, u32 * sr)
550 if ((ret = mt312_readreg(i2c, SYM_RATE_H, &sym_rate_h)) < 0)
553 if (sym_rate_h & 0x80) { /* symbol rate search was used */
554 if ((ret = mt312_writereg(i2c, MON_CTRL, 0x03)) < 0)
557 if ((ret = mt312_read(i2c, MONITOR_H, buf, sizeof(buf))) < 0)
560 monitor = (buf[0] << 8) | buf[1];
562 printk(KERN_DEBUG "sr(auto) = %u\n",
563 mt312_div(monitor * 15625, 4));
565 if ((ret = mt312_writereg(i2c, MON_CTRL, 0x05)) < 0)
568 if ((ret = mt312_read(i2c, MONITOR_H, buf, sizeof(buf))) < 0)
571 dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
573 if ((ret = mt312_read(i2c, SYM_RAT_OP_H, buf, sizeof(buf))) < 0)
576 sym_rat_op = (buf[0] << 8) | buf[1];
578 printk(KERN_DEBUG "sym_rat_op=%d dec_ratio=%d\n",
579 sym_rat_op, dec_ratio);
580 printk(KERN_DEBUG "*sr(manual) = %lu\n",
581 (((MT312_PLL_CLK * 8192) / (sym_rat_op + 8192)) *
588 static int mt312_get_code_rate(struct dvb_i2c_bus *i2c, fe_code_rate_t * cr)
590 const fe_code_rate_t fec_tab[8] =
591 { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
592 FEC_AUTO, FEC_AUTO };
597 if ((ret = mt312_readreg(i2c, FEC_STATUS, &fec_status)) < 0)
600 *cr = fec_tab[(fec_status >> 4) & 0x07];
605 static int mt312_get_frontend(struct dvb_i2c_bus *i2c,
606 struct dvb_frontend_parameters *p)
610 if ((ret = mt312_get_inversion(i2c, &p->inversion)) < 0)
613 if ((ret = mt312_get_symbol_rate(i2c, &p->u.qpsk.symbol_rate)) < 0)
616 if ((ret = mt312_get_code_rate(i2c, &p->u.qpsk.fec_inner)) < 0)
622 static int mt312_sleep(struct dvb_i2c_bus *i2c)
627 /* reset all registers to defaults */
628 if ((ret = mt312_reset(i2c, 1)) < 0)
631 if ((ret = mt312_readreg(i2c, CONFIG, &config)) < 0)
635 if ((ret = mt312_writereg(i2c, CONFIG, config & 0x7f)) < 0)
641 static int mt312_ioctl(struct dvb_frontend *fe, unsigned int cmd, void *arg)
643 struct dvb_i2c_bus *i2c = fe->i2c;
647 memcpy(arg, &mt312_info, sizeof(struct dvb_frontend_info));
650 case FE_DISEQC_RESET_OVERLOAD:
653 case FE_DISEQC_SEND_MASTER_CMD:
654 return mt312_send_master_cmd(i2c, arg);
656 case FE_DISEQC_RECV_SLAVE_REPLY:
657 if ((long) fe->data == ID_MT312)
658 return mt312_recv_slave_reply(i2c, arg);
662 case FE_DISEQC_SEND_BURST:
663 return mt312_send_burst(i2c, (fe_sec_mini_cmd_t) arg);
666 return mt312_set_tone(i2c, (fe_sec_tone_mode_t) arg);
669 return mt312_set_voltage(i2c, (fe_sec_voltage_t) arg);
671 case FE_ENABLE_HIGH_LNB_VOLTAGE:
675 return mt312_read_status(i2c, arg);
678 return mt312_read_bercnt(i2c, arg);
680 case FE_READ_SIGNAL_STRENGTH:
681 return mt312_read_agc(i2c, arg);
684 return mt312_read_snr(i2c, arg);
686 case FE_READ_UNCORRECTED_BLOCKS:
687 return mt312_read_ubc(i2c, arg);
689 case FE_SET_FRONTEND:
690 return mt312_set_frontend(i2c, arg, (long) fe->data);
692 case FE_GET_FRONTEND:
693 return mt312_get_frontend(i2c, arg);
699 return mt312_sleep(i2c);
702 return mt312_init(i2c, (long) fe->data);
705 return mt312_reset(i2c, 0);
714 static int mt312_attach(struct dvb_i2c_bus *i2c)
719 if ((ret = mt312_readreg(i2c, ID, &id)) < 0)
722 if ((id != ID_VP310) && (id != ID_MT312))
725 return dvb_register_frontend(mt312_ioctl, i2c, (void *) (long) id,
729 static void mt312_detach(struct dvb_i2c_bus *i2c)
731 dvb_unregister_frontend(mt312_ioctl, i2c);
734 static int __init mt312_module_init(void)
736 return dvb_register_i2c_device(THIS_MODULE, mt312_attach, mt312_detach);
739 static void __exit mt312_module_exit(void)
741 dvb_unregister_i2c_device(mt312_attach);
744 module_init(mt312_module_init);
745 module_exit(mt312_module_exit);
747 MODULE_DESCRIPTION("MT312 Satellite Channel Decoder Driver");
748 MODULE_AUTHOR("Andreas Oberritter <obi@saftware.de>");
749 MODULE_LICENSE("GPL");