arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uio_driver.h>
  26 #include <linux/delay.h>
  27 #include <linux/input.h>
  28 #include <linux/io.h>
  29 #include <linux/serial_sci.h>
  30 #include <linux/sh_dma.h>
  31 #include <linux/sh_intc.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/pm_domain.h>
  34 #include <mach/hardware.h>
  35 #include <mach/irqs.h>
  36 #include <mach/sh7372.h>
  37 #include <asm/mach-types.h>
  38 #include <asm/mach/arch.h>
  39
  40 /* SCIFA0 */
  41 static struct plat_sci_port scif0_platform_data = {
  42         .mapbase        = 0xe6c40000,
  43         .flags          = UPF_BOOT_AUTOCONF,
  44         .scscr          = SCSCR_RE | SCSCR_TE,
  45         .scbrr_algo_id  = SCBRR_ALGO_4,
  46         .type           = PORT_SCIFA,
  47         .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
  48                             evt2irq(0x0c00), evt2irq(0x0c00) },
  49 };
  50
  51 static struct platform_device scif0_device = {
  52         .name           = "sh-sci",
  53         .id             = 0,
  54         .dev            = {
  55                 .platform_data  = &scif0_platform_data,
  56         },
  57 };
  58
  59 /* SCIFA1 */
  60 static struct plat_sci_port scif1_platform_data = {
  61         .mapbase        = 0xe6c50000,
  62         .flags          = UPF_BOOT_AUTOCONF,
  63         .scscr          = SCSCR_RE | SCSCR_TE,
  64         .scbrr_algo_id  = SCBRR_ALGO_4,
  65         .type           = PORT_SCIFA,
  66         .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
  67                             evt2irq(0x0c20), evt2irq(0x0c20) },
  68 };
  69
  70 static struct platform_device scif1_device = {
  71         .name           = "sh-sci",
  72         .id             = 1,
  73         .dev            = {
  74                 .platform_data  = &scif1_platform_data,
  75         },
  76 };
  77
  78 /* SCIFA2 */
  79 static struct plat_sci_port scif2_platform_data = {
  80         .mapbase        = 0xe6c60000,
  81         .flags          = UPF_BOOT_AUTOCONF,
  82         .scscr          = SCSCR_RE | SCSCR_TE,
  83         .scbrr_algo_id  = SCBRR_ALGO_4,
  84         .type           = PORT_SCIFA,
  85         .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
  86                             evt2irq(0x0c40), evt2irq(0x0c40) },
  87 };
  88
  89 static struct platform_device scif2_device = {
  90         .name           = "sh-sci",
  91         .id             = 2,
  92         .dev            = {
  93                 .platform_data  = &scif2_platform_data,
  94         },
  95 };
  96
  97 /* SCIFA3 */
  98 static struct plat_sci_port scif3_platform_data = {
  99         .mapbase        = 0xe6c70000,
 100         .flags          = UPF_BOOT_AUTOCONF,
 101         .scscr          = SCSCR_RE | SCSCR_TE,
 102         .scbrr_algo_id  = SCBRR_ALGO_4,
 103         .type           = PORT_SCIFA,
 104         .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
 105                             evt2irq(0x0c60), evt2irq(0x0c60) },
 106 };
 107
 108 static struct platform_device scif3_device = {
 109         .name           = "sh-sci",
 110         .id             = 3,
 111         .dev            = {
 112                 .platform_data  = &scif3_platform_data,
 113         },
 114 };
 115
 116 /* SCIFA4 */
 117 static struct plat_sci_port scif4_platform_data = {
 118         .mapbase        = 0xe6c80000,
 119         .flags          = UPF_BOOT_AUTOCONF,
 120         .scscr          = SCSCR_RE | SCSCR_TE,
 121         .scbrr_algo_id  = SCBRR_ALGO_4,
 122         .type           = PORT_SCIFA,
 123         .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
 124                             evt2irq(0x0d20), evt2irq(0x0d20) },
 125 };
 126
 127 static struct platform_device scif4_device = {
 128         .name           = "sh-sci",
 129         .id             = 4,
 130         .dev            = {
 131                 .platform_data  = &scif4_platform_data,
 132         },
 133 };
 134
 135 /* SCIFA5 */
 136 static struct plat_sci_port scif5_platform_data = {
 137         .mapbase        = 0xe6cb0000,
 138         .flags          = UPF_BOOT_AUTOCONF,
 139         .scscr          = SCSCR_RE | SCSCR_TE,
 140         .scbrr_algo_id  = SCBRR_ALGO_4,
 141         .type           = PORT_SCIFA,
 142         .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
 143                             evt2irq(0x0d40), evt2irq(0x0d40) },
 144 };
 145
 146 static struct platform_device scif5_device = {
 147         .name           = "sh-sci",
 148         .id             = 5,
 149         .dev            = {
 150                 .platform_data  = &scif5_platform_data,
 151         },
 152 };
 153
 154 /* SCIFB */
 155 static struct plat_sci_port scif6_platform_data = {
 156         .mapbase        = 0xe6c30000,
 157         .flags          = UPF_BOOT_AUTOCONF,
 158         .scscr          = SCSCR_RE | SCSCR_TE,
 159         .scbrr_algo_id  = SCBRR_ALGO_4,
 160         .type           = PORT_SCIFB,
 161         .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
 162                             evt2irq(0x0d60), evt2irq(0x0d60) },
 163 };
 164
 165 static struct platform_device scif6_device = {
 166         .name           = "sh-sci",
 167         .id             = 6,
 168         .dev            = {
 169                 .platform_data  = &scif6_platform_data,
 170         },
 171 };
 172
 173 /* CMT */
 174 static struct sh_timer_config cmt2_platform_data = {
 175         .name = "CMT2",
 176         .channel_offset = 0x40,
 177         .timer_bit = 5,
 178         .clockevent_rating = 125,
 179         .clocksource_rating = 125,
 180 };
 181
 182 static struct resource cmt2_resources[] = {
 183         [0] = {
 184                 .name   = "CMT2",
 185                 .start  = 0xe6130040,
 186                 .end    = 0xe613004b,
 187                 .flags  = IORESOURCE_MEM,
 188         },
 189         [1] = {
 190                 .start  = evt2irq(0x0b80), /* CMT2 */
 191                 .flags  = IORESOURCE_IRQ,
 192         },
 193 };
 194
 195 static struct platform_device cmt2_device = {
 196         .name           = "sh_cmt",
 197         .id             = 2,
 198         .dev = {
 199                 .platform_data  = &cmt2_platform_data,
 200         },
 201         .resource       = cmt2_resources,
 202         .num_resources  = ARRAY_SIZE(cmt2_resources),
 203 };
 204
 205 /* TMU */
 206 static struct sh_timer_config tmu00_platform_data = {
 207         .name = "TMU00",
 208         .channel_offset = 0x4,
 209         .timer_bit = 0,
 210         .clockevent_rating = 200,
 211 };
 212
 213 static struct resource tmu00_resources[] = {
 214         [0] = {
 215                 .name   = "TMU00",
 216                 .start  = 0xfff60008,
 217                 .end    = 0xfff60013,
 218                 .flags  = IORESOURCE_MEM,
 219         },
 220         [1] = {
 221                 .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
 222                 .flags  = IORESOURCE_IRQ,
 223         },
 224 };
 225
 226 static struct platform_device tmu00_device = {
 227         .name           = "sh_tmu",
 228         .id             = 0,
 229         .dev = {
 230                 .platform_data  = &tmu00_platform_data,
 231         },
 232         .resource       = tmu00_resources,
 233         .num_resources  = ARRAY_SIZE(tmu00_resources),
 234 };
 235
 236 static struct sh_timer_config tmu01_platform_data = {
 237         .name = "TMU01",
 238         .channel_offset = 0x10,
 239         .timer_bit = 1,
 240         .clocksource_rating = 200,
 241 };
 242
 243 static struct resource tmu01_resources[] = {
 244         [0] = {
 245                 .name   = "TMU01",
 246                 .start  = 0xfff60014,
 247                 .end    = 0xfff6001f,
 248                 .flags  = IORESOURCE_MEM,
 249         },
 250         [1] = {
 251                 .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
 252                 .flags  = IORESOURCE_IRQ,
 253         },
 254 };
 255
 256 static struct platform_device tmu01_device = {
 257         .name           = "sh_tmu",
 258         .id             = 1,
 259         .dev = {
 260                 .platform_data  = &tmu01_platform_data,
 261         },
 262         .resource       = tmu01_resources,
 263         .num_resources  = ARRAY_SIZE(tmu01_resources),
 264 };
 265
 266 /* I2C */
 267 static struct resource iic0_resources[] = {
 268         [0] = {
 269                 .name   = "IIC0",
 270                 .start  = 0xFFF20000,
 271                 .end    = 0xFFF20425 - 1,
 272                 .flags  = IORESOURCE_MEM,
 273         },
 274         [1] = {
 275                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 276                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 277                 .flags  = IORESOURCE_IRQ,
 278         },
 279 };
 280
 281 static struct platform_device iic0_device = {
 282         .name           = "i2c-sh_mobile",
 283         .id             = 0, /* "i2c0" clock */
 284         .num_resources  = ARRAY_SIZE(iic0_resources),
 285         .resource       = iic0_resources,
 286 };
 287
 288 static struct resource iic1_resources[] = {
 289         [0] = {
 290                 .name   = "IIC1",
 291                 .start  = 0xE6C20000,
 292                 .end    = 0xE6C20425 - 1,
 293                 .flags  = IORESOURCE_MEM,
 294         },
 295         [1] = {
 296                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 297                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 298                 .flags  = IORESOURCE_IRQ,
 299         },
 300 };
 301
 302 static struct platform_device iic1_device = {
 303         .name           = "i2c-sh_mobile",
 304         .id             = 1, /* "i2c1" clock */
 305         .num_resources  = ARRAY_SIZE(iic1_resources),
 306         .resource       = iic1_resources,
 307 };
 308
 309 /* DMA */
 310 /* Transmit sizes and respective CHCR register values */
 311 enum {
 312         XMIT_SZ_8BIT            = 0,
 313         XMIT_SZ_16BIT           = 1,
 314         XMIT_SZ_32BIT           = 2,
 315         XMIT_SZ_64BIT           = 7,
 316         XMIT_SZ_128BIT          = 3,
 317         XMIT_SZ_256BIT          = 4,
 318         XMIT_SZ_512BIT          = 5,
 319 };
 320
 321 /* log2(size / 8) - used to calculate number of transfers */
 322 #define TS_SHIFT {                      \
 323         [XMIT_SZ_8BIT]          = 0,    \
 324         [XMIT_SZ_16BIT]         = 1,    \
 325         [XMIT_SZ_32BIT]         = 2,    \
 326         [XMIT_SZ_64BIT]         = 3,    \
 327         [XMIT_SZ_128BIT]        = 4,    \
 328         [XMIT_SZ_256BIT]        = 5,    \
 329         [XMIT_SZ_512BIT]        = 6,    \
 330 }
 331
 332 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
 333                          (((i) & 0xc) << (20 - 2)))
 334
 335 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 336         {
 337                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 338                 .addr           = 0xe6c40020,
 339                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 340                 .mid_rid        = 0x21,
 341         }, {
 342                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 343                 .addr           = 0xe6c40024,
 344                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 345                 .mid_rid        = 0x22,
 346         }, {
 347                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 348                 .addr           = 0xe6c50020,
 349                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 350                 .mid_rid        = 0x25,
 351         }, {
 352                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 353                 .addr           = 0xe6c50024,
 354                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 355                 .mid_rid        = 0x26,
 356         }, {
 357                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 358                 .addr           = 0xe6c60020,
 359                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 360                 .mid_rid        = 0x29,
 361         }, {
 362                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 363                 .addr           = 0xe6c60024,
 364                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 365                 .mid_rid        = 0x2a,
 366         }, {
 367                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 368                 .addr           = 0xe6c70020,
 369                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 370                 .mid_rid        = 0x2d,
 371         }, {
 372                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 373                 .addr           = 0xe6c70024,
 374                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 375                 .mid_rid        = 0x2e,
 376         }, {
 377                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 378                 .addr           = 0xe6c80020,
 379                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 380                 .mid_rid        = 0x39,
 381         }, {
 382                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 383                 .addr           = 0xe6c80024,
 384                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 385                 .mid_rid        = 0x3a,
 386         }, {
 387                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 388                 .addr           = 0xe6cb0020,
 389                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 390                 .mid_rid        = 0x35,
 391         }, {
 392                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 393                 .addr           = 0xe6cb0024,
 394                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 395                 .mid_rid        = 0x36,
 396         }, {
 397                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 398                 .addr           = 0xe6c30040,
 399                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 400                 .mid_rid        = 0x3d,
 401         }, {
 402                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 403                 .addr           = 0xe6c30060,
 404                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 405                 .mid_rid        = 0x3e,
 406         }, {
 407                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 408                 .addr           = 0xe6850030,
 409                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 410                 .mid_rid        = 0xc1,
 411         }, {
 412                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 413                 .addr           = 0xe6850030,
 414                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 415                 .mid_rid        = 0xc2,
 416         }, {
 417                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 418                 .addr           = 0xe6860030,
 419                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 420                 .mid_rid        = 0xc9,
 421         }, {
 422                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 423                 .addr           = 0xe6860030,
 424                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 425                 .mid_rid        = 0xca,
 426         }, {
 427                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 428                 .addr           = 0xe6870030,
 429                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 430                 .mid_rid        = 0xcd,
 431         }, {
 432                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 433                 .addr           = 0xe6870030,
 434                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 435                 .mid_rid        = 0xce,
 436         }, {
 437                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 438                 .addr           = 0xe6bd0034,
 439                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 440                 .mid_rid        = 0xd1,
 441         }, {
 442                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 443                 .addr           = 0xe6bd0034,
 444                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 445                 .mid_rid        = 0xd2,
 446         },
 447 };
 448
 449 #define SH7372_CHCLR 0x220
 450
 451 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 452         {
 453                 .offset = 0,
 454                 .dmars = 0,
 455                 .dmars_bit = 0,
 456                 .chclr_offset = SH7372_CHCLR + 0,
 457         }, {
 458                 .offset = 0x10,
 459                 .dmars = 0,
 460                 .dmars_bit = 8,
 461                 .chclr_offset = SH7372_CHCLR + 0x10,
 462         }, {
 463                 .offset = 0x20,
 464                 .dmars = 4,
 465                 .dmars_bit = 0,
 466                 .chclr_offset = SH7372_CHCLR + 0x20,
 467         }, {
 468                 .offset = 0x30,
 469                 .dmars = 4,
 470                 .dmars_bit = 8,
 471                 .chclr_offset = SH7372_CHCLR + 0x30,
 472         }, {
 473                 .offset = 0x50,
 474                 .dmars = 8,
 475                 .dmars_bit = 0,
 476                 .chclr_offset = SH7372_CHCLR + 0x50,
 477         }, {
 478                 .offset = 0x60,
 479                 .dmars = 8,
 480                 .dmars_bit = 8,
 481                 .chclr_offset = SH7372_CHCLR + 0x60,
 482         }
 483 };
 484
 485 static const unsigned int ts_shift[] = TS_SHIFT;
 486
 487 static struct sh_dmae_pdata dma_platform_data = {
 488         .slave          = sh7372_dmae_slaves,
 489         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 490         .channel        = sh7372_dmae_channels,
 491         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 492         .ts_low_shift   = 3,
 493         .ts_low_mask    = 0x18,
 494         .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
 495         .ts_high_mask   = 0x00300000,
 496         .ts_shift       = ts_shift,
 497         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 498         .dmaor_init     = DMAOR_DME,
 499         .chclr_present  = 1,
 500 };
 501
 502 /* Resource order important! */
 503 static struct resource sh7372_dmae0_resources[] = {
 504         {
 505                 /* Channel registers and DMAOR */
 506                 .start  = 0xfe008020,
 507                 .end    = 0xfe00828f,
 508                 .flags  = IORESOURCE_MEM,
 509         },
 510         {
 511                 /* DMARSx */
 512                 .start  = 0xfe009000,
 513                 .end    = 0xfe00900b,
 514                 .flags  = IORESOURCE_MEM,
 515         },
 516         {
 517                 .name   = "error_irq",
 518                 .start  = evt2irq(0x20c0),
 519                 .end    = evt2irq(0x20c0),
 520                 .flags  = IORESOURCE_IRQ,
 521         },
 522         {
 523                 /* IRQ for channels 0-5 */
 524                 .start  = evt2irq(0x2000),
 525                 .end    = evt2irq(0x20a0),
 526                 .flags  = IORESOURCE_IRQ,
 527         },
 528 };
 529
 530 /* Resource order important! */
 531 static struct resource sh7372_dmae1_resources[] = {
 532         {
 533                 /* Channel registers and DMAOR */
 534                 .start  = 0xfe018020,
 535                 .end    = 0xfe01828f,
 536                 .flags  = IORESOURCE_MEM,
 537         },
 538         {
 539                 /* DMARSx */
 540                 .start  = 0xfe019000,
 541                 .end    = 0xfe01900b,
 542                 .flags  = IORESOURCE_MEM,
 543         },
 544         {
 545                 .name   = "error_irq",
 546                 .start  = evt2irq(0x21c0),
 547                 .end    = evt2irq(0x21c0),
 548                 .flags  = IORESOURCE_IRQ,
 549         },
 550         {
 551                 /* IRQ for channels 0-5 */
 552                 .start  = evt2irq(0x2100),
 553                 .end    = evt2irq(0x21a0),
 554                 .flags  = IORESOURCE_IRQ,
 555         },
 556 };
 557
 558 /* Resource order important! */
 559 static struct resource sh7372_dmae2_resources[] = {
 560         {
 561                 /* Channel registers and DMAOR */
 562                 .start  = 0xfe028020,
 563                 .end    = 0xfe02828f,
 564                 .flags  = IORESOURCE_MEM,
 565         },
 566         {
 567                 /* DMARSx */
 568                 .start  = 0xfe029000,
 569                 .end    = 0xfe02900b,
 570                 .flags  = IORESOURCE_MEM,
 571         },
 572         {
 573                 .name   = "error_irq",
 574                 .start  = evt2irq(0x22c0),
 575                 .end    = evt2irq(0x22c0),
 576                 .flags  = IORESOURCE_IRQ,
 577         },
 578         {
 579                 /* IRQ for channels 0-5 */
 580                 .start  = evt2irq(0x2200),
 581                 .end    = evt2irq(0x22a0),
 582                 .flags  = IORESOURCE_IRQ,
 583         },
 584 };
 585
 586 static struct platform_device dma0_device = {
 587         .name           = "sh-dma-engine",
 588         .id             = 0,
 589         .resource       = sh7372_dmae0_resources,
 590         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 591         .dev            = {
 592                 .platform_data  = &dma_platform_data,
 593         },
 594 };
 595
 596 static struct platform_device dma1_device = {
 597         .name           = "sh-dma-engine",
 598         .id             = 1,
 599         .resource       = sh7372_dmae1_resources,
 600         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 601         .dev            = {
 602                 .platform_data  = &dma_platform_data,
 603         },
 604 };
 605
 606 static struct platform_device dma2_device = {
 607         .name           = "sh-dma-engine",
 608         .id             = 2,
 609         .resource       = sh7372_dmae2_resources,
 610         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 611         .dev            = {
 612                 .platform_data  = &dma_platform_data,
 613         },
 614 };
 615
 616 /*
 617  * USB-DMAC
 618  */
 619
 620 unsigned int usbts_shift[] = {3, 4, 5};
 621
 622 enum {
 623         XMIT_SZ_8BYTE           = 0,
 624         XMIT_SZ_16BYTE          = 1,
 625         XMIT_SZ_32BYTE          = 2,
 626 };
 627
 628 #define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
 629
 630 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
 631         {
 632                 .offset = 0,
 633         }, {
 634                 .offset = 0x20,
 635         },
 636 };
 637
 638 /* USB DMAC0 */
 639 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
 640         {
 641                 .slave_id       = SHDMA_SLAVE_USB0_TX,
 642                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 643         }, {
 644                 .slave_id       = SHDMA_SLAVE_USB0_RX,
 645                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 646         },
 647 };
 648
 649 static struct sh_dmae_pdata usb_dma0_platform_data = {
 650         .slave          = sh7372_usb_dmae0_slaves,
 651         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
 652         .channel        = sh7372_usb_dmae_channels,
 653         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 654         .ts_low_shift   = 6,
 655         .ts_low_mask    = 0xc0,
 656         .ts_high_shift  = 0,
 657         .ts_high_mask   = 0,
 658         .ts_shift       = usbts_shift,
 659         .ts_shift_num   = ARRAY_SIZE(usbts_shift),
 660         .dmaor_init     = DMAOR_DME,
 661         .chcr_offset    = 0x14,
 662         .chcr_ie_bit    = 1 << 5,
 663         .dmaor_is_32bit = 1,
 664         .needs_tend_set = 1,
 665         .no_dmars       = 1,
 666 };
 667
 668 static struct resource sh7372_usb_dmae0_resources[] = {
 669         {
 670                 /* Channel registers and DMAOR */
 671                 .start  = 0xe68a0020,
 672                 .end    = 0xe68a0064 - 1,
 673                 .flags  = IORESOURCE_MEM,
 674         },
 675         {
 676                 /* VCR/SWR/DMICR */
 677                 .start  = 0xe68a0000,
 678                 .end    = 0xe68a0014 - 1,
 679                 .flags  = IORESOURCE_MEM,
 680         },
 681         {
 682                 /* IRQ for channels */
 683                 .start  = evt2irq(0x0a00),
 684                 .end    = evt2irq(0x0a00),
 685                 .flags  = IORESOURCE_IRQ,
 686         },
 687 };
 688
 689 static struct platform_device usb_dma0_device = {
 690         .name           = "sh-dma-engine",
 691         .id             = 3,
 692         .resource       = sh7372_usb_dmae0_resources,
 693         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
 694         .dev            = {
 695                 .platform_data  = &usb_dma0_platform_data,
 696         },
 697 };
 698
 699 /* USB DMAC1 */
 700 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
 701         {
 702                 .slave_id       = SHDMA_SLAVE_USB1_TX,
 703                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 704         }, {
 705                 .slave_id       = SHDMA_SLAVE_USB1_RX,
 706                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
 707         },
 708 };
 709
 710 static struct sh_dmae_pdata usb_dma1_platform_data = {
 711         .slave          = sh7372_usb_dmae1_slaves,
 712         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
 713         .channel        = sh7372_usb_dmae_channels,
 714         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 715         .ts_low_shift   = 6,
 716         .ts_low_mask    = 0xc0,
 717         .ts_high_shift  = 0,
 718         .ts_high_mask   = 0,
 719         .ts_shift       = usbts_shift,
 720         .ts_shift_num   = ARRAY_SIZE(usbts_shift),
 721         .dmaor_init     = DMAOR_DME,
 722         .chcr_offset    = 0x14,
 723         .chcr_ie_bit    = 1 << 5,
 724         .dmaor_is_32bit = 1,
 725         .needs_tend_set = 1,
 726         .no_dmars       = 1,
 727 };
 728
 729 static struct resource sh7372_usb_dmae1_resources[] = {
 730         {
 731                 /* Channel registers and DMAOR */
 732                 .start  = 0xe68c0020,
 733                 .end    = 0xe68c0064 - 1,
 734                 .flags  = IORESOURCE_MEM,
 735         },
 736         {
 737                 /* VCR/SWR/DMICR */
 738                 .start  = 0xe68c0000,
 739                 .end    = 0xe68c0014 - 1,
 740                 .flags  = IORESOURCE_MEM,
 741         },
 742         {
 743                 /* IRQ for channels */
 744                 .start  = evt2irq(0x1d00),
 745                 .end    = evt2irq(0x1d00),
 746                 .flags  = IORESOURCE_IRQ,
 747         },
 748 };
 749
 750 static struct platform_device usb_dma1_device = {
 751         .name           = "sh-dma-engine",
 752         .id             = 4,
 753         .resource       = sh7372_usb_dmae1_resources,
 754         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
 755         .dev            = {
 756                 .platform_data  = &usb_dma1_platform_data,
 757         },
 758 };
 759
 760 /* VPU */
 761 static struct uio_info vpu_platform_data = {
 762         .name = "VPU5HG",
 763         .version = "0",
 764         .irq = intcs_evt2irq(0x980),
 765 };
 766
 767 static struct resource vpu_resources[] = {
 768         [0] = {
 769                 .name   = "VPU",
 770                 .start  = 0xfe900000,
 771                 .end    = 0xfe900157,
 772                 .flags  = IORESOURCE_MEM,
 773         },
 774 };
 775
 776 static struct platform_device vpu_device = {
 777         .name           = "uio_pdrv_genirq",
 778         .id             = 0,
 779         .dev = {
 780                 .platform_data  = &vpu_platform_data,
 781         },
 782         .resource       = vpu_resources,
 783         .num_resources  = ARRAY_SIZE(vpu_resources),
 784 };
 785
 786 /* VEU0 */
 787 static struct uio_info veu0_platform_data = {
 788         .name = "VEU0",
 789         .version = "0",
 790         .irq = intcs_evt2irq(0x700),
 791 };
 792
 793 static struct resource veu0_resources[] = {
 794         [0] = {
 795                 .name   = "VEU0",
 796                 .start  = 0xfe920000,
 797                 .end    = 0xfe9200cb,
 798                 .flags  = IORESOURCE_MEM,
 799         },
 800 };
 801
 802 static struct platform_device veu0_device = {
 803         .name           = "uio_pdrv_genirq",
 804         .id             = 1,
 805         .dev = {
 806                 .platform_data  = &veu0_platform_data,
 807         },
 808         .resource       = veu0_resources,
 809         .num_resources  = ARRAY_SIZE(veu0_resources),
 810 };
 811
 812 /* VEU1 */
 813 static struct uio_info veu1_platform_data = {
 814         .name = "VEU1",
 815         .version = "0",
 816         .irq = intcs_evt2irq(0x720),
 817 };
 818
 819 static struct resource veu1_resources[] = {
 820         [0] = {
 821                 .name   = "VEU1",
 822                 .start  = 0xfe924000,
 823                 .end    = 0xfe9240cb,
 824                 .flags  = IORESOURCE_MEM,
 825         },
 826 };
 827
 828 static struct platform_device veu1_device = {
 829         .name           = "uio_pdrv_genirq",
 830         .id             = 2,
 831         .dev = {
 832                 .platform_data  = &veu1_platform_data,
 833         },
 834         .resource       = veu1_resources,
 835         .num_resources  = ARRAY_SIZE(veu1_resources),
 836 };
 837
 838 /* VEU2 */
 839 static struct uio_info veu2_platform_data = {
 840         .name = "VEU2",
 841         .version = "0",
 842         .irq = intcs_evt2irq(0x740),
 843 };
 844
 845 static struct resource veu2_resources[] = {
 846         [0] = {
 847                 .name   = "VEU2",
 848                 .start  = 0xfe928000,
 849                 .end    = 0xfe928307,
 850                 .flags  = IORESOURCE_MEM,
 851         },
 852 };
 853
 854 static struct platform_device veu2_device = {
 855         .name           = "uio_pdrv_genirq",
 856         .id             = 3,
 857         .dev = {
 858                 .platform_data  = &veu2_platform_data,
 859         },
 860         .resource       = veu2_resources,
 861         .num_resources  = ARRAY_SIZE(veu2_resources),
 862 };
 863
 864 /* VEU3 */
 865 static struct uio_info veu3_platform_data = {
 866         .name = "VEU3",
 867         .version = "0",
 868         .irq = intcs_evt2irq(0x760),
 869 };
 870
 871 static struct resource veu3_resources[] = {
 872         [0] = {
 873                 .name   = "VEU3",
 874                 .start  = 0xfe92c000,
 875                 .end    = 0xfe92c307,
 876                 .flags  = IORESOURCE_MEM,
 877         },
 878 };
 879
 880 static struct platform_device veu3_device = {
 881         .name           = "uio_pdrv_genirq",
 882         .id             = 4,
 883         .dev = {
 884                 .platform_data  = &veu3_platform_data,
 885         },
 886         .resource       = veu3_resources,
 887         .num_resources  = ARRAY_SIZE(veu3_resources),
 888 };
 889
 890 /* JPU */
 891 static struct uio_info jpu_platform_data = {
 892         .name = "JPU",
 893         .version = "0",
 894         .irq = intcs_evt2irq(0x560),
 895 };
 896
 897 static struct resource jpu_resources[] = {
 898         [0] = {
 899                 .name   = "JPU",
 900                 .start  = 0xfe980000,
 901                 .end    = 0xfe9902d3,
 902                 .flags  = IORESOURCE_MEM,
 903         },
 904 };
 905
 906 static struct platform_device jpu_device = {
 907         .name           = "uio_pdrv_genirq",
 908         .id             = 5,
 909         .dev = {
 910                 .platform_data  = &jpu_platform_data,
 911         },
 912         .resource       = jpu_resources,
 913         .num_resources  = ARRAY_SIZE(jpu_resources),
 914 };
 915
 916 /* SPU2DSP0 */
 917 static struct uio_info spu0_platform_data = {
 918         .name = "SPU2DSP0",
 919         .version = "0",
 920         .irq = evt2irq(0x1800),
 921 };
 922
 923 static struct resource spu0_resources[] = {
 924         [0] = {
 925                 .name   = "SPU2DSP0",
 926                 .start  = 0xfe200000,
 927                 .end    = 0xfe2fffff,
 928                 .flags  = IORESOURCE_MEM,
 929         },
 930 };
 931
 932 static struct platform_device spu0_device = {
 933         .name           = "uio_pdrv_genirq",
 934         .id             = 6,
 935         .dev = {
 936                 .platform_data  = &spu0_platform_data,
 937         },
 938         .resource       = spu0_resources,
 939         .num_resources  = ARRAY_SIZE(spu0_resources),
 940 };
 941
 942 /* SPU2DSP1 */
 943 static struct uio_info spu1_platform_data = {
 944         .name = "SPU2DSP1",
 945         .version = "0",
 946         .irq = evt2irq(0x1820),
 947 };
 948
 949 static struct resource spu1_resources[] = {
 950         [0] = {
 951                 .name   = "SPU2DSP1",
 952                 .start  = 0xfe300000,
 953                 .end    = 0xfe3fffff,
 954                 .flags  = IORESOURCE_MEM,
 955         },
 956 };
 957
 958 static struct platform_device spu1_device = {
 959         .name           = "uio_pdrv_genirq",
 960         .id             = 7,
 961         .dev = {
 962                 .platform_data  = &spu1_platform_data,
 963         },
 964         .resource       = spu1_resources,
 965         .num_resources  = ARRAY_SIZE(spu1_resources),
 966 };
 967
 968 static struct platform_device *sh7372_early_devices[] __initdata = {
 969         &scif0_device,
 970         &scif1_device,
 971         &scif2_device,
 972         &scif3_device,
 973         &scif4_device,
 974         &scif5_device,
 975         &scif6_device,
 976         &cmt2_device,
 977         &tmu00_device,
 978         &tmu01_device,
 979 };
 980
 981 static struct platform_device *sh7372_late_devices[] __initdata = {
 982         &iic0_device,
 983         &iic1_device,
 984         &dma0_device,
 985         &dma1_device,
 986         &dma2_device,
 987         &usb_dma0_device,
 988         &usb_dma1_device,
 989         &vpu_device,
 990         &veu0_device,
 991         &veu1_device,
 992         &veu2_device,
 993         &veu3_device,
 994         &jpu_device,
 995         &spu0_device,
 996         &spu1_device,
 997 };
 998
 999 void __init sh7372_add_standard_devices(void)
1000 {
1001         sh7372_init_pm_domain(&sh7372_a4lc);
1002         sh7372_init_pm_domain(&sh7372_a4mp);
1003         sh7372_init_pm_domain(&sh7372_d4);
1004         sh7372_init_pm_domain(&sh7372_a4r);
1005         sh7372_init_pm_domain(&sh7372_a3rv);
1006         sh7372_init_pm_domain(&sh7372_a3ri);
1007         sh7372_init_pm_domain(&sh7372_a4s);
1008         sh7372_init_pm_domain(&sh7372_a3sp);
1009         sh7372_init_pm_domain(&sh7372_a3sg);
1010
1011         sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
1012         sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
1013
1014         sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg);
1015         sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp);
1016
1017         platform_add_devices(sh7372_early_devices,
1018                             ARRAY_SIZE(sh7372_early_devices));
1019
1020         platform_add_devices(sh7372_late_devices,
1021                             ARRAY_SIZE(sh7372_late_devices));
1022
1023         sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
1024         sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
1025         sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
1026         sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
1027         sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
1028         sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
1029         sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
1030         sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
1031         sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
1032         sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
1033         sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
1034         sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
1035         sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
1036         sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
1037         sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
1038         sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
1039         sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
1040         sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
1041         sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
1042         sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
1043         sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
1044         sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
1045 }
1046
1047 void __init sh7372_add_early_devices(void)
1048 {
1049         early_platform_add_devices(sh7372_early_devices,
1050                                    ARRAY_SIZE(sh7372_early_devices));
1051 }