1 /* $Id: etrap.S,v 1.43 2000/03/29 09:55:30 davem Exp $
2 * etrap.S: Preparing for entry into the kernel on Sparc V9.
4 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <asm/pstate.h>
10 #include <asm/ptrace.h>
12 #include <asm/spitfire.h>
15 #define TASK_REGOFF ((PAGE_SIZE<<1)-TRACEREG_SZ-REGWIN_SZ)
16 #define ETRAP_PSTATE1 (PSTATE_RMO | PSTATE_PRIV)
17 #define ETRAP_PSTATE2 (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
20 * On entry, %g7 is return address - 0x4.
21 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
26 .globl etrap, etrap_irq, etraptl1
28 etrap: rdpr %pil, %g2 ! Single Group
29 etrap_irq: rdpr %tstate, %g1 ! Single Group
30 sllx %g2, 20, %g3 ! IEU0 Group
31 andcc %g1, TSTATE_PRIV, %g0 ! IEU1
32 or %g1, %g3, %g1 ! IEU0 Group
34 sub %sp, REGWIN_SZ+TRACEREG_SZ-STACK_BIAS, %g2 ! IEU1
35 wrpr %g0, 7, %cleanwin ! Single Group+4bubbles
37 sethi %hi(TASK_REGOFF), %g2 ! IEU0 Group
38 sethi %hi(TSTATE_PEF), %g3 ! IEU1
39 or %g2, %lo(TASK_REGOFF), %g2 ! IEU0 Group
40 and %g1, %g3, %g3 ! IEU1
41 brnz,pn %g3, 1f ! CTI+IEU1 Group
42 add %g6, %g2, %g2 ! IEU0
43 wr %g0, 0, %fprs ! Single Group+4bubbles
44 1: rdpr %tpc, %g3 ! Single Group
46 stx %g1, [%g2 + REGWIN_SZ + PT_V9_TSTATE] ! Store Group
47 rdpr %tnpc, %g1 ! Single Group
48 stx %g3, [%g2 + REGWIN_SZ + PT_V9_TPC] ! Store Group
49 rd %y, %g3 ! Single Group+4bubbles
50 stx %g1, [%g2 + REGWIN_SZ + PT_V9_TNPC] ! Store Group
51 st %g3, [%g2 + REGWIN_SZ + PT_V9_Y] ! Store Group
52 save %g2, -STACK_BIAS, %sp ! Ordering here is critical ! Single Group
53 mov %g6, %l6 ! IEU0 Group
56 mov PRIMARY_CONTEXT, %l4 ! IEU1
57 rdpr %canrestore, %g3 ! Single Group+4bubbles
58 rdpr %wstate, %g2 ! Single Group+4bubbles
59 wrpr %g0, 0, %canrestore ! Single Group+4bubbles
60 sll %g2, 3, %g2 ! IEU0 Group
62 stb %l5, [%l6 + AOFF_task_thread + AOFF_thread_fpdepth] ! Store
64 wrpr %g3, 0, %otherwin ! Single Group+4bubbles
65 wrpr %g2, 0, %wstate ! Single Group+4bubbles
66 stxa %g0, [%l4] ASI_DMMU ! Store Group
67 flush %l6 ! Single Group+9bubbles
68 wr %g0, ASI_AIUS, %asi ! Single Group+4bubbles
69 2: wrpr %g0, 0x0, %tl ! Single Group+4bubbles
71 mov %g5, %l5 ! IEU0 Group
74 wrpr %g0, ETRAP_PSTATE1, %pstate ! Single Group+4bubbles
75 stx %g1, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G1] ! Store Group
76 stx %g2, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G2] ! Store Group
77 stx %g3, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G3] ! Store Group
78 stx %g4, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G4] ! Store Group
79 stx %g5, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G5] ! Store Group
80 stx %g6, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G6] ! Store Group
82 stx %g7, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G7] ! Store Group
83 stx %i0, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I0] ! Store Group
84 stx %i1, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I1] ! Store Group
85 stx %i2, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I2] ! Store Group
86 stx %i3, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I3] ! Store Group
87 stx %i4, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I4] ! Store Group
88 sethi %uhi(PAGE_OFFSET), %g4 ! IEU0
89 stx %i5, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I5] ! Store Group
91 stx %i6, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I6] ! Store Group
92 sllx %g4, 32, %g4 ! IEU0
93 stx %i7, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I7] ! Store Group
94 wrpr %g0, ETRAP_PSTATE2, %pstate ! Single Group+4bubbles
95 jmpl %l2 + 0x4, %g0 ! CTI Group
100 3: ldub [%l6 + AOFF_task_thread + AOFF_thread_fpdepth], %l5 ! Load Group
101 add %l6, AOFF_task_thread + AOFF_thread_fpsaved + 1, %l4 ! IEU0
102 srl %l5, 1, %l3 ! IEU0 Group
103 add %l5, 2, %l5 ! IEU1
104 stb %l5, [%l6 + AOFF_task_thread + AOFF_thread_fpdepth] ! Store
106 stb %g0, [%l4 + %l3] ! Store Group
109 etraptl1: rdpr %tstate, %g1 ! Single Group+4bubbles
110 sub %sp, REGWIN_SZ + TRACEREG_SZ - STACK_BIAS, %g2 ! IEU1
111 ba,pt %xcc, 1b ! CTI Group
112 andcc %g1, TSTATE_PRIV, %g0 ! IEU0
116 scetrap: rdpr %pil, %g2 ! Single Group
117 rdpr %tstate, %g1 ! Single Group
118 sllx %g2, 20, %g3 ! IEU0 Group
119 andcc %g1, TSTATE_PRIV, %g0 ! IEU1
120 or %g1, %g3, %g1 ! IEU0 Group
121 bne,pn %xcc, 1f ! CTI
122 sub %sp, (REGWIN_SZ+TRACEREG_SZ-STACK_BIAS), %g2 ! IEU1
123 wrpr %g0, 7, %cleanwin ! Single Group+4bubbles
125 sllx %g1, 51, %g3 ! IEU0 Group
126 sethi %hi(TASK_REGOFF), %g2 ! IEU1
127 or %g2, %lo(TASK_REGOFF), %g2 ! IEU0 Group
128 brlz,pn %g3, 1f ! CTI+IEU1
129 add %g6, %g2, %g2 ! IEU0 Group
130 wr %g0, 0, %fprs ! Single Group+4bubbles
131 1: rdpr %tpc, %g3 ! Single Group
132 stx %g1, [%g2 + REGWIN_SZ + PT_V9_TSTATE] ! Store Group
134 rdpr %tnpc, %g1 ! Single Group
135 stx %g3, [%g2 + REGWIN_SZ + PT_V9_TPC] ! Store Group
136 stx %g1, [%g2 + REGWIN_SZ + PT_V9_TNPC] ! Store Group
137 save %g2, -STACK_BIAS, %sp ! Ordering here is critical ! Single Group
138 mov %g6, %l6 ! IEU0 Group
139 bne,pn %xcc, 2f ! CTI
140 mov ASI_P, %l7 ! IEU1
141 rdpr %canrestore, %g3 ! Single Group+4bubbles
143 rdpr %wstate, %g2 ! Single Group+4bubbles
144 wrpr %g0, 0, %canrestore ! Single Group+4bubbles
145 sll %g2, 3, %g2 ! IEU0 Group
146 mov PRIMARY_CONTEXT, %l4 ! IEU1
147 wrpr %g3, 0, %otherwin ! Single Group+4bubbles
148 wrpr %g2, 0, %wstate ! Single Group+4bubbles
149 stxa %g0, [%l4] ASI_DMMU ! Store
150 flush %l6 ! Single Group+9bubbles
152 mov ASI_AIUS, %l7 ! IEU0 Group
153 2: mov %g4, %l4 ! IEU1
154 mov %g5, %l5 ! IEU0 Group
155 add %g7, 0x4, %l2 ! IEU1
156 wrpr %g0, ETRAP_PSTATE1, %pstate ! Single Group+4bubbles
157 stx %g1, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G1] ! Store Group
158 stx %g2, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G2] ! Store Group
159 sllx %l7, 24, %l7 ! IEU0
161 stx %g3, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G3] ! Store Group
162 rdpr %cwp, %l0 ! Single Group
163 stx %g4, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G4] ! Store Group
164 stx %g5, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G5] ! Store Group
165 stx %g6, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G6] ! Store Group
166 stx %g7, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_G7] ! Store Group
167 or %l7, %l0, %l7 ! IEU0
168 sethi %hi(TSTATE_RMO | TSTATE_PEF), %l0 ! IEU1
170 or %l7, %l0, %l7 ! IEU0 Group
171 wrpr %l2, %tnpc ! Single Group+4bubbles
172 wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate ! Single Group+4bubbles
173 stx %i0, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I0] ! Store Group
174 stx %i1, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I1] ! Store Group
175 stx %i2, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I2] ! Store Group
176 stx %i3, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I3] ! Store Group
177 stx %i4, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I4] ! Store Group
179 sethi %uhi(PAGE_OFFSET), %g4 ! IEU0
180 stx %i5, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I5] ! Store Group
181 stx %i6, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I6] ! Store Group
182 sllx %g4, 32, %g4 ! IEU0
184 stx %i7, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I7] ! Store Group