2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 * Copyright SUSE Linux Products GmbH 2010
17 * Authors: Alexander Graf <agraf@suse.de>
20 /* Real mode helpers */
22 #if defined(CONFIG_PPC_BOOK3S_64)
24 #define GET_SHADOW_VCPU(reg) \
25 addi reg, r13, PACA_KVM_SVCPU
27 #elif defined(CONFIG_PPC_BOOK3S_32)
29 #define GET_SHADOW_VCPU(reg) \
31 lwz reg, (THREAD + THREAD_KVM_SVCPU)(reg); \
36 /* Disable for nested KVM */
37 #define USE_QUICK_LAST_INST
40 /* Get helper functions for subarch specific functionality */
42 #if defined(CONFIG_PPC_BOOK3S_64)
43 #include "book3s_64_slb.S"
44 #elif defined(CONFIG_PPC_BOOK3S_32)
45 #include "book3s_32_sr.S"
48 /******************************************************************************
52 *****************************************************************************/
54 .global kvmppc_handler_trampoline_enter
55 kvmppc_handler_trampoline_enter:
64 * all other volatile GPRS = free
65 * SVCPU[CR] = guest CR
66 * SVCPU[XER] = guest XER
67 * SVCPU[CTR] = guest CTR
68 * SVCPU[LR] = guest LR
71 /* r3 = shadow vcpu */
74 /* Move SRR0 and SRR1 into the respective regs */
75 PPC_LL r9, SVCPU_PC(r3)
79 /* Activate guest mode, so faults get handled by KVM */
80 li r11, KVM_GUEST_MODE_GUEST
81 stb r11, SVCPU_IN_GUEST(r3)
83 /* Switch to guest segment. This is subarch specific. */
88 PPC_LL r4, (SVCPU_CTR)(r3)
89 PPC_LL r5, (SVCPU_LR)(r3)
90 lwz r6, (SVCPU_CR)(r3)
91 lwz r7, (SVCPU_XER)(r3)
98 PPC_LL r0, (SVCPU_R0)(r3)
99 PPC_LL r1, (SVCPU_R1)(r3)
100 PPC_LL r2, (SVCPU_R2)(r3)
101 PPC_LL r4, (SVCPU_R4)(r3)
102 PPC_LL r5, (SVCPU_R5)(r3)
103 PPC_LL r6, (SVCPU_R6)(r3)
104 PPC_LL r7, (SVCPU_R7)(r3)
105 PPC_LL r8, (SVCPU_R8)(r3)
106 PPC_LL r9, (SVCPU_R9)(r3)
107 PPC_LL r10, (SVCPU_R10)(r3)
108 PPC_LL r11, (SVCPU_R11)(r3)
109 PPC_LL r12, (SVCPU_R12)(r3)
110 PPC_LL r13, (SVCPU_R13)(r3)
112 PPC_LL r3, (SVCPU_R3)(r3)
115 kvmppc_handler_trampoline_enter_end:
119 /******************************************************************************
123 *****************************************************************************/
125 .global kvmppc_handler_trampoline_exit
126 kvmppc_handler_trampoline_exit:
128 .global kvmppc_interrupt
131 /* Register usage at this point:
133 * SPRG_SCRATCH0 = guest R13
134 * R12 = exit handler id
135 * R13 = shadow vcpu - SHADOW_VCPU_OFF [=PACA on PPC64]
136 * SVCPU.SCRATCH0 = guest R12
137 * SVCPU.SCRATCH1 = guest CR
143 PPC_STL r0, (SHADOW_VCPU_OFF + SVCPU_R0)(r13)
144 PPC_STL r1, (SHADOW_VCPU_OFF + SVCPU_R1)(r13)
145 PPC_STL r2, (SHADOW_VCPU_OFF + SVCPU_R2)(r13)
146 PPC_STL r3, (SHADOW_VCPU_OFF + SVCPU_R3)(r13)
147 PPC_STL r4, (SHADOW_VCPU_OFF + SVCPU_R4)(r13)
148 PPC_STL r5, (SHADOW_VCPU_OFF + SVCPU_R5)(r13)
149 PPC_STL r6, (SHADOW_VCPU_OFF + SVCPU_R6)(r13)
150 PPC_STL r7, (SHADOW_VCPU_OFF + SVCPU_R7)(r13)
151 PPC_STL r8, (SHADOW_VCPU_OFF + SVCPU_R8)(r13)
152 PPC_STL r9, (SHADOW_VCPU_OFF + SVCPU_R9)(r13)
153 PPC_STL r10, (SHADOW_VCPU_OFF + SVCPU_R10)(r13)
154 PPC_STL r11, (SHADOW_VCPU_OFF + SVCPU_R11)(r13)
156 /* Restore R1/R2 so we can handle faults */
157 PPC_LL r1, (SHADOW_VCPU_OFF + SVCPU_HOST_R1)(r13)
158 PPC_LL r2, (SHADOW_VCPU_OFF + SVCPU_HOST_R2)(r13)
160 /* Save guest PC and MSR */
169 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE_206)
174 PPC_STL r3, (SHADOW_VCPU_OFF + SVCPU_PC)(r13)
175 PPC_STL r4, (SHADOW_VCPU_OFF + SVCPU_SHADOW_SRR1)(r13)
177 /* Get scratch'ed off registers */
179 PPC_LL r8, (SHADOW_VCPU_OFF + SVCPU_SCRATCH0)(r13)
180 lwz r7, (SHADOW_VCPU_OFF + SVCPU_SCRATCH1)(r13)
182 PPC_STL r9, (SHADOW_VCPU_OFF + SVCPU_R13)(r13)
183 PPC_STL r8, (SHADOW_VCPU_OFF + SVCPU_R12)(r13)
184 stw r7, (SHADOW_VCPU_OFF + SVCPU_CR)(r13)
186 /* Save more register state */
194 stw r5, (SHADOW_VCPU_OFF + SVCPU_XER)(r13)
195 PPC_STL r6, (SHADOW_VCPU_OFF + SVCPU_FAULT_DAR)(r13)
196 stw r7, (SHADOW_VCPU_OFF + SVCPU_FAULT_DSISR)(r13)
197 PPC_STL r8, (SHADOW_VCPU_OFF + SVCPU_CTR)(r13)
198 PPC_STL r9, (SHADOW_VCPU_OFF + SVCPU_LR)(r13)
201 * In order for us to easily get the last instruction,
202 * we got the #vmexit at, we exploit the fact that the
203 * virtual layout is still the same here, so we can just
204 * ld from the guest's PC address
207 /* We only load the last instruction when it's safe */
208 cmpwi r12, BOOK3S_INTERRUPT_DATA_STORAGE
210 cmpwi r12, BOOK3S_INTERRUPT_PROGRAM
212 cmpwi r12, BOOK3S_INTERRUPT_ALIGNMENT
218 /* Save off the guest instruction we're at */
220 /* In case lwz faults */
221 li r0, KVM_INST_FETCH_FAILED
223 #ifdef USE_QUICK_LAST_INST
225 /* Set guest mode to 'jump over instruction' so if lwz faults
226 * we'll just continue at the next IP. */
227 li r9, KVM_GUEST_MODE_SKIP
228 stb r9, (SHADOW_VCPU_OFF + SVCPU_IN_GUEST)(r13)
230 /* 1) enable paging for data */
232 ori r11, r9, MSR_DR /* Enable paging for data */
235 /* 2) fetch the instruction */
237 /* 3) disable paging again */
242 stw r0, (SHADOW_VCPU_OFF + SVCPU_LAST_INST)(r13)
246 /* Unset guest mode */
247 li r9, KVM_GUEST_MODE_NONE
248 stb r9, (SHADOW_VCPU_OFF + SVCPU_IN_GUEST)(r13)
250 /* Switch back to host MMU */
253 /* Register usage at this point:
257 * R12 = exit handler id
258 * R13 = shadow vcpu - SHADOW_VCPU_OFF [=PACA on PPC64]
263 /* RFI into the highmem handler */
265 ori r7, r7, MSR_IR|MSR_DR|MSR_RI|MSR_ME /* Enable paging */
267 /* Load highmem handler address */
268 PPC_LL r8, (SHADOW_VCPU_OFF + SVCPU_VMHANDLER)(r13)
272 kvmppc_handler_trampoline_exit_end: