sound/pci/maestro3.c

   1 /*
   2  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
   3  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
   4  *                       Takashi Iwai <tiwai@suse.de>
   5  *
   6  * Most of the hardware init stuffs are based on maestro3 driver for
   7  * OSS/Free by Zach Brown.  Many thanks to Zach!
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of the GNU General Public License as published by
  11  *   the Free Software Foundation; either version 2 of the License, or
  12  *   (at your option) any later version.
  13  *
  14  *   This program is distributed in the hope that it will be useful,
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *   GNU General Public License for more details.
  18  *
  19  *   You should have received a copy of the GNU General Public License
  20  *   along with this program; if not, write to the Free Software
  21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  *
  23  *
  24  * ChangeLog:
  25  * Aug. 27, 2001
  26  *     - Fixed deadlock on capture
  27  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  28  *
  29  */
  30
  31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  32 #define DRIVER_NAME "Maestro3"
  33
  34 #include <sound/driver.h>
  35 #include <asm/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/init.h>
  39 #include <linux/pci.h>
  40 #include <linux/slab.h>
  41 #include <linux/vmalloc.h>
  42 #include <sound/core.h>
  43 #include <sound/info.h>
  44 #include <sound/control.h>
  45 #include <sound/pcm.h>
  46 #include <sound/ac97_codec.h>
  47 #define SNDRV_GET_ID
  48 #include <sound/initval.h>
  49
  50 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  51 MODULE_DESCRIPTION("ESS Maestro3 PCI");
  52 MODULE_LICENSE("GPL");
  53 MODULE_CLASSES("{sound}");
  54 MODULE_DEVICES("{{ESS,Maestro3 PCI},"
  55                 "{ESS,ES1988},"
  56                 "{ESS,Allegro PCI},"
  57                 "{ESS,Allegro-1 PCI},"
  58                 "{ESS,Canyon3D-2/LE PCI}}");
  59
  60 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  61 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  62 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  63 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  64 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  65
  66 MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  67 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  68 MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
  69 MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
  70 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  71 MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
  72 MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  73 MODULE_PARM_DESC(enable, "Enable this soundcard.");
  74 MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
  75 MODULE_PARM(external_amp, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  76 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  77 MODULE_PARM_SYNTAX(external_amp, SNDRV_ENABLED "," SNDRV_BOOLEAN_TRUE_DESC);
  78 MODULE_PARM(amp_gpio, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
  79 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  80 MODULE_PARM_SYNTAX(amp_gpio, SNDRV_ENABLED);
  81
  82 #define MAX_PLAYBACKS   2
  83 #define MAX_CAPTURES    1
  84 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
  85
  86
  87 /*
  88  * maestro3 registers
  89  */
  90
  91 /* Allegro PCI configuration registers */
  92 #define PCI_LEGACY_AUDIO_CTRL   0x40
  93 #define SOUND_BLASTER_ENABLE    0x00000001
  94 #define FM_SYNTHESIS_ENABLE     0x00000002
  95 #define GAME_PORT_ENABLE        0x00000004
  96 #define MPU401_IO_ENABLE        0x00000008
  97 #define MPU401_IRQ_ENABLE       0x00000010
  98 #define ALIAS_10BIT_IO          0x00000020
  99 #define SB_DMA_MASK             0x000000C0
 100 #define SB_DMA_0                0x00000040
 101 #define SB_DMA_1                0x00000040
 102 #define SB_DMA_R                0x00000080
 103 #define SB_DMA_3                0x000000C0
 104 #define SB_IRQ_MASK             0x00000700
 105 #define SB_IRQ_5                0x00000000
 106 #define SB_IRQ_7                0x00000100
 107 #define SB_IRQ_9                0x00000200
 108 #define SB_IRQ_10               0x00000300
 109 #define MIDI_IRQ_MASK           0x00003800
 110 #define SERIAL_IRQ_ENABLE       0x00004000
 111 #define DISABLE_LEGACY          0x00008000
 112
 113 #define PCI_ALLEGRO_CONFIG      0x50
 114 #define SB_ADDR_240             0x00000004
 115 #define MPU_ADDR_MASK           0x00000018
 116 #define MPU_ADDR_330            0x00000000
 117 #define MPU_ADDR_300            0x00000008
 118 #define MPU_ADDR_320            0x00000010
 119 #define MPU_ADDR_340            0x00000018
 120 #define USE_PCI_TIMING          0x00000040
 121 #define POSTED_WRITE_ENABLE     0x00000080
 122 #define DMA_POLICY_MASK         0x00000700
 123 #define DMA_DDMA                0x00000000
 124 #define DMA_TDMA                0x00000100
 125 #define DMA_PCPCI               0x00000200
 126 #define DMA_WBDMA16             0x00000400
 127 #define DMA_WBDMA4              0x00000500
 128 #define DMA_WBDMA2              0x00000600
 129 #define DMA_WBDMA1              0x00000700
 130 #define DMA_SAFE_GUARD          0x00000800
 131 #define HI_PERF_GP_ENABLE       0x00001000
 132 #define PIC_SNOOP_MODE_0        0x00002000
 133 #define PIC_SNOOP_MODE_1        0x00004000
 134 #define SOUNDBLASTER_IRQ_MASK   0x00008000
 135 #define RING_IN_ENABLE          0x00010000
 136 #define SPDIF_TEST_MODE         0x00020000
 137 #define CLK_MULT_MODE_SELECT_2  0x00040000
 138 #define EEPROM_WRITE_ENABLE     0x00080000
 139 #define CODEC_DIR_IN            0x00100000
 140 #define HV_BUTTON_FROM_GD       0x00200000
 141 #define REDUCED_DEBOUNCE        0x00400000
 142 #define HV_CTRL_ENABLE          0x00800000
 143 #define SPDIF_ENABLE            0x01000000
 144 #define CLK_DIV_SELECT          0x06000000
 145 #define CLK_DIV_BY_48           0x00000000
 146 #define CLK_DIV_BY_49           0x02000000
 147 #define CLK_DIV_BY_50           0x04000000
 148 #define CLK_DIV_RESERVED        0x06000000
 149 #define PM_CTRL_ENABLE          0x08000000
 150 #define CLK_MULT_MODE_SELECT    0x30000000
 151 #define CLK_MULT_MODE_SHIFT     28
 152 #define CLK_MULT_MODE_0         0x00000000
 153 #define CLK_MULT_MODE_1         0x10000000
 154 #define CLK_MULT_MODE_2         0x20000000
 155 #define CLK_MULT_MODE_3         0x30000000
 156 #define INT_CLK_SELECT          0x40000000
 157 #define INT_CLK_MULT_RESET      0x80000000
 158
 159 /* M3 */
 160 #define INT_CLK_SRC_NOT_PCI     0x00100000
 161 #define INT_CLK_MULT_ENABLE     0x80000000
 162
 163 #define PCI_ACPI_CONTROL        0x54
 164 #define PCI_ACPI_D0             0x00000000
 165 #define PCI_ACPI_D1             0xB4F70000
 166 #define PCI_ACPI_D2             0xB4F7B4F7
 167
 168 #define PCI_USER_CONFIG         0x58
 169 #define EXT_PCI_MASTER_ENABLE   0x00000001
 170 #define SPDIF_OUT_SELECT        0x00000002
 171 #define TEST_PIN_DIR_CTRL       0x00000004
 172 #define AC97_CODEC_TEST         0x00000020
 173 #define TRI_STATE_BUFFER        0x00000080
 174 #define IN_CLK_12MHZ_SELECT     0x00000100
 175 #define MULTI_FUNC_DISABLE      0x00000200
 176 #define EXT_MASTER_PAIR_SEL     0x00000400
 177 #define PCI_MASTER_SUPPORT      0x00000800
 178 #define STOP_CLOCK_ENABLE       0x00001000
 179 #define EAPD_DRIVE_ENABLE       0x00002000
 180 #define REQ_TRI_STATE_ENABLE    0x00004000
 181 #define REQ_LOW_ENABLE          0x00008000
 182 #define MIDI_1_ENABLE           0x00010000
 183 #define MIDI_2_ENABLE           0x00020000
 184 #define SB_AUDIO_SYNC           0x00040000
 185 #define HV_CTRL_TEST            0x00100000
 186 #define SOUNDBLASTER_TEST       0x00400000
 187
 188 #define PCI_USER_CONFIG_C       0x5C
 189
 190 #define PCI_DDMA_CTRL           0x60
 191 #define DDMA_ENABLE             0x00000001
 192
 193
 194 /* Allegro registers */
 195 #define HOST_INT_CTRL           0x18
 196 #define SB_INT_ENABLE           0x0001
 197 #define MPU401_INT_ENABLE       0x0002
 198 #define ASSP_INT_ENABLE         0x0010
 199 #define RING_INT_ENABLE         0x0020
 200 #define HV_INT_ENABLE           0x0040
 201 #define CLKRUN_GEN_ENABLE       0x0100
 202 #define HV_CTRL_TO_PME          0x0400
 203 #define SOFTWARE_RESET_ENABLE   0x8000
 204
 205 /*
 206  * should be using the above defines, probably.
 207  */
 208 #define REGB_ENABLE_RESET               0x01
 209 #define REGB_STOP_CLOCK                 0x10
 210
 211 #define HOST_INT_STATUS         0x1A
 212 #define SB_INT_PENDING          0x01
 213 #define MPU401_INT_PENDING      0x02
 214 #define ASSP_INT_PENDING        0x10
 215 #define RING_INT_PENDING        0x20
 216 #define HV_INT_PENDING          0x40
 217
 218 #define HARDWARE_VOL_CTRL       0x1B
 219 #define SHADOW_MIX_REG_VOICE    0x1C
 220 #define HW_VOL_COUNTER_VOICE    0x1D
 221 #define SHADOW_MIX_REG_MASTER   0x1E
 222 #define HW_VOL_COUNTER_MASTER   0x1F
 223
 224 #define CODEC_COMMAND           0x30
 225 #define CODEC_READ_B            0x80
 226
 227 #define CODEC_STATUS            0x30
 228 #define CODEC_BUSY_B            0x01
 229
 230 #define CODEC_DATA              0x32
 231
 232 #define RING_BUS_CTRL_A         0x36
 233 #define RAC_PME_ENABLE          0x0100
 234 #define RAC_SDFS_ENABLE         0x0200
 235 #define LAC_PME_ENABLE          0x0400
 236 #define LAC_SDFS_ENABLE         0x0800
 237 #define SERIAL_AC_LINK_ENABLE   0x1000
 238 #define IO_SRAM_ENABLE          0x2000
 239 #define IIS_INPUT_ENABLE        0x8000
 240
 241 #define RING_BUS_CTRL_B         0x38
 242 #define SECOND_CODEC_ID_MASK    0x0003
 243 #define SPDIF_FUNC_ENABLE       0x0010
 244 #define SECOND_AC_ENABLE        0x0020
 245 #define SB_MODULE_INTF_ENABLE   0x0040
 246 #define SSPE_ENABLE             0x0040
 247 #define M3I_DOCK_ENABLE         0x0080
 248
 249 #define SDO_OUT_DEST_CTRL       0x3A
 250 #define COMMAND_ADDR_OUT        0x0003
 251 #define PCM_LR_OUT_LOCAL        0x0000
 252 #define PCM_LR_OUT_REMOTE       0x0004
 253 #define PCM_LR_OUT_MUTE         0x0008
 254 #define PCM_LR_OUT_BOTH         0x000C
 255 #define LINE1_DAC_OUT_LOCAL     0x0000
 256 #define LINE1_DAC_OUT_REMOTE    0x0010
 257 #define LINE1_DAC_OUT_MUTE      0x0020
 258 #define LINE1_DAC_OUT_BOTH      0x0030
 259 #define PCM_CLS_OUT_LOCAL       0x0000
 260 #define PCM_CLS_OUT_REMOTE      0x0040
 261 #define PCM_CLS_OUT_MUTE        0x0080
 262 #define PCM_CLS_OUT_BOTH        0x00C0
 263 #define PCM_RLF_OUT_LOCAL       0x0000
 264 #define PCM_RLF_OUT_REMOTE      0x0100
 265 #define PCM_RLF_OUT_MUTE        0x0200
 266 #define PCM_RLF_OUT_BOTH        0x0300
 267 #define LINE2_DAC_OUT_LOCAL     0x0000
 268 #define LINE2_DAC_OUT_REMOTE    0x0400
 269 #define LINE2_DAC_OUT_MUTE      0x0800
 270 #define LINE2_DAC_OUT_BOTH      0x0C00
 271 #define HANDSET_OUT_LOCAL       0x0000
 272 #define HANDSET_OUT_REMOTE      0x1000
 273 #define HANDSET_OUT_MUTE        0x2000
 274 #define HANDSET_OUT_BOTH        0x3000
 275 #define IO_CTRL_OUT_LOCAL       0x0000
 276 #define IO_CTRL_OUT_REMOTE      0x4000
 277 #define IO_CTRL_OUT_MUTE        0x8000
 278 #define IO_CTRL_OUT_BOTH        0xC000
 279
 280 #define SDO_IN_DEST_CTRL        0x3C
 281 #define STATUS_ADDR_IN          0x0003
 282 #define PCM_LR_IN_LOCAL         0x0000
 283 #define PCM_LR_IN_REMOTE        0x0004
 284 #define PCM_LR_RESERVED         0x0008
 285 #define PCM_LR_IN_BOTH          0x000C
 286 #define LINE1_ADC_IN_LOCAL      0x0000
 287 #define LINE1_ADC_IN_REMOTE     0x0010
 288 #define LINE1_ADC_IN_MUTE       0x0020
 289 #define MIC_ADC_IN_LOCAL        0x0000
 290 #define MIC_ADC_IN_REMOTE       0x0040
 291 #define MIC_ADC_IN_MUTE         0x0080
 292 #define LINE2_DAC_IN_LOCAL      0x0000
 293 #define LINE2_DAC_IN_REMOTE     0x0400
 294 #define LINE2_DAC_IN_MUTE       0x0800
 295 #define HANDSET_IN_LOCAL        0x0000
 296 #define HANDSET_IN_REMOTE       0x1000
 297 #define HANDSET_IN_MUTE         0x2000
 298 #define IO_STATUS_IN_LOCAL      0x0000
 299 #define IO_STATUS_IN_REMOTE     0x4000
 300
 301 #define SPDIF_IN_CTRL           0x3E
 302 #define SPDIF_IN_ENABLE         0x0001
 303
 304 #define GPIO_DATA               0x60
 305 #define GPIO_DATA_MASK          0x0FFF
 306 #define GPIO_HV_STATUS          0x3000
 307 #define GPIO_PME_STATUS         0x4000
 308
 309 #define GPIO_MASK               0x64
 310 #define GPIO_DIRECTION          0x68
 311 #define GPO_PRIMARY_AC97        0x0001
 312 #define GPI_LINEOUT_SENSE       0x0004
 313 #define GPO_SECONDARY_AC97      0x0008
 314 #define GPI_VOL_DOWN            0x0010
 315 #define GPI_VOL_UP              0x0020
 316 #define GPI_IIS_CLK             0x0040
 317 #define GPI_IIS_LRCLK           0x0080
 318 #define GPI_IIS_DATA            0x0100
 319 #define GPI_DOCKING_STATUS      0x0100
 320 #define GPI_HEADPHONE_SENSE     0x0200
 321 #define GPO_EXT_AMP_SHUTDOWN    0x1000
 322
 323 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
 324 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
 325
 326 /* M3 */
 327 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
 328
 329 #define ASSP_INDEX_PORT         0x80
 330 #define ASSP_MEMORY_PORT        0x82
 331 #define ASSP_DATA_PORT          0x84
 332
 333 #define MPU401_DATA_PORT        0x98
 334 #define MPU401_STATUS_PORT      0x99
 335
 336 #define CLK_MULT_DATA_PORT      0x9C
 337
 338 #define ASSP_CONTROL_A          0xA2
 339 #define ASSP_0_WS_ENABLE        0x01
 340 #define ASSP_CTRL_A_RESERVED1   0x02
 341 #define ASSP_CTRL_A_RESERVED2   0x04
 342 #define ASSP_CLK_49MHZ_SELECT   0x08
 343 #define FAST_PLU_ENABLE         0x10
 344 #define ASSP_CTRL_A_RESERVED3   0x20
 345 #define DSP_CLK_36MHZ_SELECT    0x40
 346
 347 #define ASSP_CONTROL_B          0xA4
 348 #define RESET_ASSP              0x00
 349 #define RUN_ASSP                0x01
 350 #define ENABLE_ASSP_CLOCK       0x00
 351 #define STOP_ASSP_CLOCK         0x10
 352 #define RESET_TOGGLE            0x40
 353
 354 #define ASSP_CONTROL_C          0xA6
 355 #define ASSP_HOST_INT_ENABLE    0x01
 356 #define FM_ADDR_REMAP_DISABLE   0x02
 357 #define HOST_WRITE_PORT_ENABLE  0x08
 358
 359 #define ASSP_HOST_INT_STATUS    0xAC
 360 #define DSP2HOST_REQ_PIORECORD  0x01
 361 #define DSP2HOST_REQ_I2SRATE    0x02
 362 #define DSP2HOST_REQ_TIMER      0x04
 363
 364 /* AC97 registers */
 365 /* XXX fix this crap up */
 366 /*#define AC97_RESET              0x00*/
 367
 368 #define AC97_VOL_MUTE_B         0x8000
 369 #define AC97_VOL_M              0x1F
 370 #define AC97_LEFT_VOL_S         8
 371
 372 #define AC97_MASTER_VOL         0x02
 373 #define AC97_LINE_LEVEL_VOL     0x04
 374 #define AC97_MASTER_MONO_VOL    0x06
 375 #define AC97_PC_BEEP_VOL        0x0A
 376 #define AC97_PC_BEEP_VOL_M      0x0F
 377 #define AC97_SROUND_MASTER_VOL  0x38
 378 #define AC97_PC_BEEP_VOL_S      1
 379
 380 /*#define AC97_PHONE_VOL          0x0C
 381 #define AC97_MIC_VOL            0x0E*/
 382 #define AC97_MIC_20DB_ENABLE    0x40
 383
 384 /*#define AC97_LINEIN_VOL         0x10
 385 #define AC97_CD_VOL             0x12
 386 #define AC97_VIDEO_VOL          0x14
 387 #define AC97_AUX_VOL            0x16*/
 388 #define AC97_PCM_OUT_VOL        0x18
 389 /*#define AC97_RECORD_SELECT      0x1A*/
 390 #define AC97_RECORD_MIC         0x00
 391 #define AC97_RECORD_CD          0x01
 392 #define AC97_RECORD_VIDEO       0x02
 393 #define AC97_RECORD_AUX         0x03
 394 #define AC97_RECORD_MONO_MUX    0x02
 395 #define AC97_RECORD_DIGITAL     0x03
 396 #define AC97_RECORD_LINE        0x04
 397 #define AC97_RECORD_STEREO      0x05
 398 #define AC97_RECORD_MONO        0x06
 399 #define AC97_RECORD_PHONE       0x07
 400
 401 /*#define AC97_RECORD_GAIN        0x1C*/
 402 #define AC97_RECORD_VOL_M       0x0F
 403
 404 /*#define AC97_GENERAL_PURPOSE    0x20*/
 405 #define AC97_POWER_DOWN_CTRL    0x26
 406 #define AC97_ADC_READY          0x0001
 407 #define AC97_DAC_READY          0x0002
 408 #define AC97_ANALOG_READY       0x0004
 409 #define AC97_VREF_ON            0x0008
 410 #define AC97_PR0                0x0100
 411 #define AC97_PR1                0x0200
 412 #define AC97_PR2                0x0400
 413 #define AC97_PR3                0x0800
 414 #define AC97_PR4                0x1000
 415
 416 #define AC97_RESERVED1          0x28
 417
 418 #define AC97_VENDOR_TEST        0x5A
 419
 420 #define AC97_CLOCK_DELAY        0x5C
 421 #define AC97_LINEOUT_MUX_SEL    0x0001
 422 #define AC97_MONO_MUX_SEL       0x0002
 423 #define AC97_CLOCK_DELAY_SEL    0x1F
 424 #define AC97_DAC_CDS_SHIFT      6
 425 #define AC97_ADC_CDS_SHIFT      11
 426
 427 #define AC97_MULTI_CHANNEL_SEL  0x74
 428
 429 /*#define AC97_VENDOR_ID1         0x7C
 430 #define AC97_VENDOR_ID2         0x7E*/
 431
 432 /*
 433  * ASSP control regs
 434  */
 435 #define DSP_PORT_TIMER_COUNT    0x06
 436
 437 #define DSP_PORT_MEMORY_INDEX   0x80
 438
 439 #define DSP_PORT_MEMORY_TYPE    0x82
 440 #define MEMTYPE_INTERNAL_CODE   0x0002
 441 #define MEMTYPE_INTERNAL_DATA   0x0003
 442 #define MEMTYPE_MASK            0x0003
 443
 444 #define DSP_PORT_MEMORY_DATA    0x84
 445
 446 #define DSP_PORT_CONTROL_REG_A  0xA2
 447 #define DSP_PORT_CONTROL_REG_B  0xA4
 448 #define DSP_PORT_CONTROL_REG_C  0xA6
 449
 450 #define REV_A_CODE_MEMORY_BEGIN         0x0000
 451 #define REV_A_CODE_MEMORY_END           0x0FFF
 452 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
 453 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
 454
 455 #define REV_B_CODE_MEMORY_BEGIN         0x0000
 456 #define REV_B_CODE_MEMORY_END           0x0BFF
 457 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
 458 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
 459
 460 #define REV_A_DATA_MEMORY_BEGIN         0x1000
 461 #define REV_A_DATA_MEMORY_END           0x2FFF
 462 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
 463 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
 464
 465 #define REV_B_DATA_MEMORY_BEGIN         0x1000
 466 #define REV_B_DATA_MEMORY_END           0x2BFF
 467 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
 468 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
 469
 470
 471 #define NUM_UNITS_KERNEL_CODE          16
 472 #define NUM_UNITS_KERNEL_DATA           2
 473
 474 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
 475 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
 476
 477 /*
 478  * Kernel data layout
 479  */
 480
 481 #define DP_SHIFT_COUNT                  7
 482
 483 #define KDATA_BASE_ADDR                 0x1000
 484 #define KDATA_BASE_ADDR2                0x1080
 485
 486 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
 487 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
 488 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
 489 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
 490 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
 491 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
 492 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
 493 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
 494 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
 495
 496 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
 497 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
 498
 499 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
 500 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
 501 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
 502 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
 503 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
 504 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
 505 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
 506 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
 507 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
 508 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
 509
 510 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
 511 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
 512
 513 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
 514 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
 515
 516 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
 517 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
 518
 519 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
 520 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
 521 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
 522
 523 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
 524 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
 525 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
 526 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
 527 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
 528
 529 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
 530 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
 531 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
 532
 533 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
 534 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
 535 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
 536
 537 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
 538 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
 539 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
 540 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
 541 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
 542 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
 543 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
 544 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
 545 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
 546 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
 547
 548 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
 549 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
 550 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
 551
 552 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
 553 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
 554
 555 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
 556 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
 557 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
 558
 559 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
 560 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
 561 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
 562 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
 563 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
 564 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
 565
 566 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
 567 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
 568 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
 569 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
 570 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
 571 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
 572
 573 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)
 574 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
 575 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
 576 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
 577 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
 578 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
 579
 580 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
 581 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
 582 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
 583 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
 584
 585 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
 586 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
 587
 588 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
 589 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
 590
 591 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
 592 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
 593 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
 594 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
 595 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
 596
 597 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
 598 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
 599
 600 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
 601 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
 602 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
 603
 604 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
 605 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
 606
 607 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
 608
 609 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
 610 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
 611 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
 612 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
 613 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
 614 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
 615 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
 616 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
 617 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
 618 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
 619 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
 620 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
 621
 622 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
 623 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
 624 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
 625 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
 626
 627 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
 628 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
 629
 630 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
 631 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
 632 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
 633 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
 634
 635 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
 636 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
 637 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
 638 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
 639 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
 640
 641 /*
 642  * second 'segment' (?) reserved for mixer
 643  * buffers..
 644  */
 645
 646 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
 647 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
 648 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
 649 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
 650 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
 651 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
 652 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
 653 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
 654 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
 655 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
 656 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
 657 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
 658 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
 659 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
 660 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
 661 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
 662
 663 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
 664 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
 665 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
 666 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
 667 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
 668 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
 669 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
 670 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
 671 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
 672 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
 673 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
 674
 675 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
 676 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
 677 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
 678 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
 679 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
 680 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
 681
 682 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
 683 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
 684 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
 685 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
 686
 687 /*
 688  * client data area offsets
 689  */
 690 #define CDATA_INSTANCE_READY            0x00
 691
 692 #define CDATA_HOST_SRC_ADDRL            0x01
 693 #define CDATA_HOST_SRC_ADDRH            0x02
 694 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
 695 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
 696 #define CDATA_HOST_SRC_CURRENTL         0x05
 697 #define CDATA_HOST_SRC_CURRENTH         0x06
 698
 699 #define CDATA_IN_BUF_CONNECT            0x07
 700 #define CDATA_OUT_BUF_CONNECT           0x08
 701
 702 #define CDATA_IN_BUF_BEGIN              0x09
 703 #define CDATA_IN_BUF_END_PLUS_1         0x0A
 704 #define CDATA_IN_BUF_HEAD               0x0B
 705 #define CDATA_IN_BUF_TAIL               0x0C
 706 #define CDATA_OUT_BUF_BEGIN             0x0D
 707 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
 708 #define CDATA_OUT_BUF_HEAD              0x0F
 709 #define CDATA_OUT_BUF_TAIL              0x10
 710
 711 #define CDATA_DMA_CONTROL               0x11
 712 #define CDATA_RESERVED                  0x12
 713
 714 #define CDATA_FREQUENCY                 0x13
 715 #define CDATA_LEFT_VOLUME               0x14
 716 #define CDATA_RIGHT_VOLUME              0x15
 717 #define CDATA_LEFT_SUR_VOL              0x16
 718 #define CDATA_RIGHT_SUR_VOL             0x17
 719
 720 #define CDATA_HEADER_LEN                0x18
 721
 722 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
 723 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
 724 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
 725 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
 726 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
 727 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
 728 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
 729 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
 730
 731 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
 732 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 733 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 734 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
 735 #define MINISRC_BIQUAD_STAGE    2
 736 #define MINISRC_COEF_LOC          0x175
 737
 738 #define DMACONTROL_BLOCK_MASK           0x000F
 739 #define  DMAC_BLOCK0_SELECTOR           0x0000
 740 #define  DMAC_BLOCK1_SELECTOR           0x0001
 741 #define  DMAC_BLOCK2_SELECTOR           0x0002
 742 #define  DMAC_BLOCK3_SELECTOR           0x0003
 743 #define  DMAC_BLOCK4_SELECTOR           0x0004
 744 #define  DMAC_BLOCK5_SELECTOR           0x0005
 745 #define  DMAC_BLOCK6_SELECTOR           0x0006
 746 #define  DMAC_BLOCK7_SELECTOR           0x0007
 747 #define  DMAC_BLOCK8_SELECTOR           0x0008
 748 #define  DMAC_BLOCK9_SELECTOR           0x0009
 749 #define  DMAC_BLOCKA_SELECTOR           0x000A
 750 #define  DMAC_BLOCKB_SELECTOR           0x000B
 751 #define  DMAC_BLOCKC_SELECTOR           0x000C
 752 #define  DMAC_BLOCKD_SELECTOR           0x000D
 753 #define  DMAC_BLOCKE_SELECTOR           0x000E
 754 #define  DMAC_BLOCKF_SELECTOR           0x000F
 755 #define DMACONTROL_PAGE_MASK            0x00F0
 756 #define  DMAC_PAGE0_SELECTOR            0x0030
 757 #define  DMAC_PAGE1_SELECTOR            0x0020
 758 #define  DMAC_PAGE2_SELECTOR            0x0010
 759 #define  DMAC_PAGE3_SELECTOR            0x0000
 760 #define DMACONTROL_AUTOREPEAT           0x1000
 761 #define DMACONTROL_STOPPED              0x2000
 762 #define DMACONTROL_DIRECTION            0x0100
 763
 764 /*
 765  * an arbitrary volume we set the internal
 766  * volume settings to so that the ac97 volume
 767  * range is a little less insane.  0x7fff is
 768  * max.
 769  */
 770 #define ARB_VOLUME ( 0x6800 )
 771
 772 /*
 773  */
 774
 775 typedef struct snd_m3_dma m3_dma_t;
 776 typedef struct snd_m3 m3_t;
 777 #define chip_t m3_t
 778
 779
 780 /* quirk lists */
 781 struct m3_quirk {
 782         const char *name;       /* device name */
 783         u16 vendor, device;     /* subsystem ids */
 784         int amp_gpio;           /* gpio pin #  for external amp, -1 = default */
 785         int irda_workaround;    /* non-zero if avoid to touch 0x10 on GPIO_DIRECTION
 786                                    (e.g. for IrDA on Dell Inspirons) */
 787 };
 788
 789 struct m3_list {
 790         int curlen;
 791         int mem_addr;
 792         int max;
 793 };
 794
 795 struct snd_m3_dma {
 796
 797         int number;
 798         m3_t *chip;
 799         snd_pcm_substream_t *substream;
 800
 801         struct assp_instance {
 802                 unsigned short code, data;
 803         } inst;
 804
 805         int running;
 806         int opened;
 807
 808         unsigned long buffer_addr;
 809         int dma_size;
 810         int period_size;
 811         unsigned int hwptr;
 812         int count;
 813
 814         int index[3];
 815         struct m3_list *index_list[3];
 816
 817         int in_lists;
 818
 819         struct list_head list;
 820
 821 };
 822
 823 struct snd_m3 {
 824
 825         snd_card_t *card;
 826
 827         unsigned long iobase;
 828         struct resource *iobase_res;
 829
 830         int irq;
 831         int allegro_flag : 1;
 832
 833         ac97_t *ac97;
 834
 835         snd_pcm_t *pcm;
 836
 837         struct pci_dev *pci;
 838         struct m3_quirk *quirk;
 839
 840         int dacs_active;
 841         int timer_users;
 842
 843         struct m3_list  msrc_list;
 844         struct m3_list  mixer_list;
 845         struct m3_list  adc1_list;
 846         struct m3_list  dma_list;
 847
 848         /* for storing reset state..*/
 849         u8 reset_state;
 850
 851         int external_amp;
 852         int amp_gpio;
 853
 854         /* pcm streams */
 855         int num_substreams;
 856         m3_dma_t *substreams;
 857
 858         spinlock_t reg_lock;
 859
 860 #ifdef CONFIG_PM
 861         u16 *suspend_mem;
 862 #endif
 863 };
 864
 865 /*
 866  * pci ids
 867  */
 868
 869 #ifndef PCI_VENDOR_ID_ESS
 870 #define PCI_VENDOR_ID_ESS         0x125D
 871 #endif
 872 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO_1
 873 #define PCI_DEVICE_ID_ESS_ALLEGRO_1     0x1988
 874 #endif
 875 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO
 876 #define PCI_DEVICE_ID_ESS_ALLEGRO       0x1989
 877 #endif
 878 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2LE
 879 #define PCI_DEVICE_ID_ESS_CANYON3D_2LE  0x1990
 880 #endif
 881 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2
 882 #define PCI_DEVICE_ID_ESS_CANYON3D_2    0x1992
 883 #endif
 884 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3
 885 #define PCI_DEVICE_ID_ESS_MAESTRO3      0x1998
 886 #endif
 887 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_1
 888 #define PCI_DEVICE_ID_ESS_MAESTRO3_1    0x1999
 889 #endif
 890 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_HW
 891 #define PCI_DEVICE_ID_ESS_MAESTRO3_HW   0x199a
 892 #endif
 893 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_2
 894 #define PCI_DEVICE_ID_ESS_MAESTRO3_2    0x199b
 895 #endif
 896
 897 static struct pci_device_id snd_m3_ids[] __devinitdata = {
 898         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
 899          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 900         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
 901          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 902         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
 903          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 904         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
 905          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 906         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
 907          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 908         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
 909          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 910         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
 911          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 912         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
 913          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 914         {0,},
 915 };
 916
 917 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
 918
 919 static struct m3_quirk m3_quirk_list[] = {
 920         /* panasonic CF-28 "toughbook" */
 921         {
 922                 .name = "Panasonic CF-28",
 923                 .vendor = 0x10f7,
 924                 .device = 0x833e,
 925                 .amp_gpio = 0x0d,
 926         },
 927         /* panasonic CF-72 "toughbook" */
 928         {
 929                 .name = "Panasonic CF-72",
 930                 .vendor = 0x10f7,
 931                 .device = 0x833d,
 932                 .amp_gpio = 0x0d,
 933         },
 934         /* Dell Inspiron 4000 */
 935         {
 936                 .name = "Dell Inspiron 4000",
 937                 .vendor = 0x1028,
 938                 .device = 0x00b0,
 939                 .amp_gpio = -1,
 940                 .irda_workaround = 1,
 941         },
 942         /* Dell Inspiron 8000 */
 943         {
 944                 .name = "Dell Inspiron 8000",
 945                 .vendor = 0x1028,
 946                 .device = 0x00a4,
 947                 .amp_gpio = -1,
 948                 .irda_workaround = 1,
 949         },
 950         /* Dell Inspiron 8100 */
 951         {
 952                 .name = "Dell Inspiron 8100",
 953                 .vendor = 0x1028,
 954                 .device = 0x00e6,
 955                 .amp_gpio = -1,
 956                 .irda_workaround = 1,
 957         },
 958         /* NEC LM800J/7 */
 959         {
 960                 .name = "NEC LM800J/7",
 961                 .vendor = 0x1033,
 962                 .device = 0x80f1,
 963                 .amp_gpio = 0x03,
 964         },
 965         /* END */
 966         { 0 }
 967 };
 968
 969
 970 /*
 971  * lowlevel functions
 972  */
 973
 974 inline static void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg)
 975 {
 976         outw(value, chip->iobase + reg);
 977 }
 978
 979 inline static u16 snd_m3_inw(m3_t *chip, unsigned long reg)
 980 {
 981         return inw(chip->iobase + reg);
 982 }
 983
 984 inline static void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg)
 985 {
 986         outb(value, chip->iobase + reg);
 987 }
 988
 989 inline static u8 snd_m3_inb(m3_t *chip, unsigned long reg)
 990 {
 991         return inb(chip->iobase + reg);
 992 }
 993
 994 /*
 995  * access 16bit words to the code or data regions of the dsp's memory.
 996  * index addresses 16bit words.
 997  */
 998 static u16 snd_m3_assp_read(m3_t *chip, u16 region, u16 index)
 999 {
1000         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1001         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1002         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1003 }
1004
1005 static void snd_m3_assp_write(m3_t *chip, u16 region, u16 index, u16 data)
1006 {
1007         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1008         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1009         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1010 }
1011
1012 static void snd_m3_assp_halt(m3_t *chip)
1013 {
1014         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1015         mdelay(10);
1016         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1017 }
1018
1019 static void snd_m3_assp_continue(m3_t *chip)
1020 {
1021         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1022 }
1023
1024
1025 /*
1026  * This makes me sad. the maestro3 has lists
1027  * internally that must be packed.. 0 terminates,
1028  * apparently, or maybe all unused entries have
1029  * to be 0, the lists have static lengths set
1030  * by the binary code images.
1031  */
1032
1033 static int snd_m3_add_list(m3_t *chip, struct m3_list *list, u16 val)
1034 {
1035         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1036                           list->mem_addr + list->curlen,
1037                           val);
1038         return list->curlen++;
1039 }
1040
1041 static void snd_m3_remove_list(m3_t *chip, struct m3_list *list, int index)
1042 {
1043         u16  val;
1044         int lastindex = list->curlen - 1;
1045
1046         if (index != lastindex) {
1047                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1048                                        list->mem_addr + lastindex);
1049                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1050                                   list->mem_addr + index,
1051                                   val);
1052         }
1053
1054         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1055                           list->mem_addr + lastindex,
1056                           0);
1057
1058         list->curlen--;
1059 }
1060
1061 static void snd_m3_inc_timer_users(m3_t *chip)
1062 {
1063         chip->timer_users++;
1064         if (chip->timer_users != 1)
1065                 return;
1066
1067         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1068                           KDATA_TIMER_COUNT_RELOAD,
1069                           240);
1070
1071         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1072                           KDATA_TIMER_COUNT_CURRENT,
1073                           240);
1074
1075         snd_m3_outw(chip,
1076                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1077                     HOST_INT_CTRL);
1078 }
1079
1080 static void snd_m3_dec_timer_users(m3_t *chip)
1081 {
1082         chip->timer_users--;
1083         if (chip->timer_users > 0)
1084                 return;
1085
1086         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1087                           KDATA_TIMER_COUNT_RELOAD,
1088                           0);
1089
1090         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1091                           KDATA_TIMER_COUNT_CURRENT,
1092                           0);
1093
1094         snd_m3_outw(chip,
1095                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1096                     HOST_INT_CTRL);
1097 }
1098
1099 /*
1100  * start/stop
1101  */
1102
1103 /* spinlock held! */
1104 static int snd_m3_pcm_start(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1105 {
1106         if (! s || ! subs)
1107                 return -EINVAL;
1108
1109         snd_m3_inc_timer_users(chip);
1110         switch (subs->stream) {
1111         case SNDRV_PCM_STREAM_PLAYBACK:
1112                 chip->dacs_active++;
1113                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1114                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1115                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1116                                   KDATA_MIXER_TASK_NUMBER,
1117                                   chip->dacs_active);
1118                 break;
1119         case SNDRV_PCM_STREAM_CAPTURE:
1120                 snd_m3_assp_write(s->chip, MEMTYPE_INTERNAL_DATA,
1121                                   KDATA_ADC1_REQUEST, 1);
1122                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1123                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1124                 break;
1125         }
1126         return 0;
1127 }
1128
1129 /* spinlock held! */
1130 static int snd_m3_pcm_stop(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1131 {
1132         if (! s || ! subs)
1133                 return -EINVAL;
1134
1135         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1136                           s->inst.data + CDATA_INSTANCE_READY, 0);
1137         snd_m3_dec_timer_users(chip);
1138         switch (subs->stream) {
1139         case SNDRV_PCM_STREAM_PLAYBACK:
1140                 chip->dacs_active--;
1141                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1142                                   KDATA_MIXER_TASK_NUMBER,
1143                                   chip->dacs_active);
1144                 break;
1145         case SNDRV_PCM_STREAM_CAPTURE:
1146                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1147                                   KDATA_ADC1_REQUEST, 0);
1148                 break;
1149         }
1150         return 0;
1151 }
1152
1153 static int
1154 snd_m3_pcm_trigger(snd_pcm_substream_t *subs, int cmd)
1155 {
1156         m3_t *chip = snd_pcm_substream_chip(subs);
1157         m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1158         unsigned long flags;
1159         int err = -EINVAL;
1160
1161         snd_assert(s != NULL, return -ENXIO);
1162
1163         spin_lock_irqsave(&chip->reg_lock, flags);
1164         switch (cmd) {
1165         case SNDRV_PCM_TRIGGER_START:
1166         case SNDRV_PCM_TRIGGER_RESUME:
1167                 if (s->running)
1168                         err = -EBUSY;
1169                 else {
1170                         s->running = 1;
1171                         err = snd_m3_pcm_start(chip, s, subs);
1172                 }
1173                 break;
1174         case SNDRV_PCM_TRIGGER_STOP:
1175         case SNDRV_PCM_TRIGGER_SUSPEND:
1176                 if (! s->running)
1177                         err = 0; /* should return error? */
1178                 else {
1179                         s->running = 0;
1180                         err = snd_m3_pcm_stop(chip, s, subs);
1181                 }
1182                 break;
1183         }
1184         spin_unlock_irqrestore(&chip->reg_lock, flags);
1185         return err;
1186 }
1187
1188 /*
1189  * setup
1190  */
1191 static void
1192 snd_m3_pcm_setup1(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1193 {
1194         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1195         snd_pcm_runtime_t *runtime = subs->runtime;
1196
1197         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1198                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1199                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1200         } else {
1201                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1202                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1203         }
1204         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1205         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1206
1207         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1208         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1209         s->hwptr = 0;
1210         s->count = 0;
1211
1212 #define LO(x) ((x) & 0xffff)
1213 #define HI(x) LO((x) >> 16)
1214
1215         /* host dma buffer pointers */
1216         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1217                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1218                           LO(s->buffer_addr));
1219
1220         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1221                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1222                           HI(s->buffer_addr));
1223
1224         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1225                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1226                           LO(s->buffer_addr + s->dma_size));
1227
1228         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1229                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1230                           HI(s->buffer_addr + s->dma_size));
1231
1232         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1233                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1234                           LO(s->buffer_addr));
1235
1236         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1237                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1238                           HI(s->buffer_addr));
1239 #undef LO
1240 #undef HI
1241
1242         /* dsp buffers */
1243
1244         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1245                           s->inst.data + CDATA_IN_BUF_BEGIN,
1246                           dsp_in_buffer);
1247
1248         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1249                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1250                           dsp_in_buffer + (dsp_in_size / 2));
1251
1252         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1253                           s->inst.data + CDATA_IN_BUF_HEAD,
1254                           dsp_in_buffer);
1255
1256         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1257                           s->inst.data + CDATA_IN_BUF_TAIL,
1258                           dsp_in_buffer);
1259
1260         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1261                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1262                           dsp_out_buffer);
1263
1264         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1265                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1266                           dsp_out_buffer + (dsp_out_size / 2));
1267
1268         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1269                           s->inst.data + CDATA_OUT_BUF_HEAD,
1270                           dsp_out_buffer);
1271
1272         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1273                           s->inst.data + CDATA_OUT_BUF_TAIL,
1274                           dsp_out_buffer);
1275 }
1276
1277 static void snd_m3_pcm_setup2(m3_t *chip, m3_dma_t *s, snd_pcm_runtime_t *runtime)
1278 {
1279         u32 freq;
1280
1281         /*
1282          * put us in the lists if we're not already there
1283          */
1284         if (! s->in_lists) {
1285                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1286                                               s->inst.data >> DP_SHIFT_COUNT);
1287                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1288                                               s->inst.data >> DP_SHIFT_COUNT);
1289                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1290                                               s->inst.data >> DP_SHIFT_COUNT);
1291                 s->in_lists = 1;
1292         }
1293
1294         /* write to 'mono' word */
1295         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1296                           s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1297                           runtime->channels == 2 ? 0 : 1);
1298         /* write to '8bit' word */
1299         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1300                           s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1301                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1302
1303         /* set up dac/adc rate */
1304         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1305         if (freq)
1306                 freq--;
1307
1308         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1309                           s->inst.data + CDATA_FREQUENCY,
1310                           freq);
1311 }
1312
1313
1314 static struct play_vals {
1315         u16 addr, val;
1316 } pv[] = {
1317         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1318         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1319         {SRC3_DIRECTION_OFFSET, 0} ,
1320         /* +1, +2 are stereo/16 bit */
1321         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1322         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1323         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1324         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1325         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1326         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1327         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1328         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1329         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1330         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1331         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1332         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1333         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1334         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1335         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1336         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1337         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1338 };
1339
1340
1341 /* the mode passed should be already shifted and masked */
1342 static void
1343 snd_m3_playback_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1344 {
1345         unsigned int i;
1346
1347         /*
1348          * some per client initializers
1349          */
1350
1351         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1352                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1353                           s->inst.data + 40 + 8);
1354
1355         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1356                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1357                           s->inst.code + MINISRC_COEF_LOC);
1358
1359         /* enable or disable low pass filter? */
1360         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1361                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1362                           subs->runtime->rate > 45000 ? 0xff : 0);
1363
1364         /* tell it which way dma is going? */
1365         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1366                           s->inst.data + CDATA_DMA_CONTROL,
1367                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1368
1369         /*
1370          * set an armload of static initializers
1371          */
1372         for (i = 0; i < ARRAY_SIZE(pv); i++)
1373                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1374                                   s->inst.data + pv[i].addr, pv[i].val);
1375 }
1376
1377 /*
1378  *    Native record driver
1379  */
1380 static struct rec_vals {
1381         u16 addr, val;
1382 } rv[] = {
1383         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1384         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1385         {SRC3_DIRECTION_OFFSET, 1} ,
1386         /* +1, +2 are stereo/16 bit */
1387         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1388         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1389         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1390         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1391         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1392         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1393         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1394         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1395         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1396         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1397         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1398         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1399         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1400         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1401         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1402         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1403         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1404         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1405         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1406 };
1407
1408 static void
1409 snd_m3_capture_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1410 {
1411         unsigned int i;
1412
1413         /*
1414          * some per client initializers
1415          */
1416
1417         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1418                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1419                           s->inst.data + 40 + 8);
1420
1421         /* tell it which way dma is going? */
1422         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1423                           s->inst.data + CDATA_DMA_CONTROL,
1424                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1425                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1426
1427         /*
1428          * set an armload of static initializers
1429          */
1430         for (i = 0; i < ARRAY_SIZE(rv); i++)
1431                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1432                                   s->inst.data + rv[i].addr, rv[i].val);
1433 }
1434
1435 static int snd_m3_pcm_hw_params(snd_pcm_substream_t * substream,
1436                                 snd_pcm_hw_params_t * hw_params)
1437 {
1438         m3_dma_t *s = (m3_dma_t*) substream->runtime->private_data;
1439         int err;
1440
1441         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1442                 return err;
1443         /* set buffer address */
1444         s->buffer_addr = substream->runtime->dma_addr;
1445         if (s->buffer_addr & 0x3) {
1446                 snd_printk("oh my, not aligned\n");
1447                 s->buffer_addr = s->buffer_addr & ~0x3;
1448         }
1449         return 0;
1450 }
1451
1452 static int snd_m3_pcm_hw_free(snd_pcm_substream_t * substream)
1453 {
1454         m3_dma_t *s;
1455
1456         if (substream->runtime->private_data == NULL)
1457                 return 0;
1458         s = (m3_dma_t*) substream->runtime->private_data;
1459         snd_pcm_lib_free_pages(substream);
1460         s->buffer_addr = 0;
1461         return 0;
1462 }
1463
1464 static int
1465 snd_m3_pcm_prepare(snd_pcm_substream_t *subs)
1466 {
1467         m3_t *chip = snd_pcm_substream_chip(subs);
1468         snd_pcm_runtime_t *runtime = subs->runtime;
1469         m3_dma_t *s = (m3_dma_t*)runtime->private_data;
1470         unsigned long flags;
1471
1472         snd_assert(s != NULL, return -ENXIO);
1473
1474         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1475             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1476                 return -EINVAL;
1477         if (runtime->rate > 48000 ||
1478             runtime->rate < 8000)
1479                 return -EINVAL;
1480
1481         spin_lock_irqsave(&chip->reg_lock, flags);
1482
1483         snd_m3_pcm_setup1(chip, s, subs);
1484
1485         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1486                 snd_m3_playback_setup(chip, s, subs);
1487         else
1488                 snd_m3_capture_setup(chip, s, subs);
1489
1490         snd_m3_pcm_setup2(chip, s, runtime);
1491
1492         spin_unlock_irqrestore(&chip->reg_lock, flags);
1493
1494         return 0;
1495 }
1496
1497 /*
1498  * get current pointer
1499  */
1500 static unsigned int
1501 snd_m3_get_pointer(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs)
1502 {
1503         u16 hi = 0, lo = 0;
1504         int retry = 10;
1505         u32 addr;
1506
1507         /*
1508          * try and get a valid answer
1509          */
1510         while (retry--) {
1511                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1512                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1513
1514                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1515                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1516
1517                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1518                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1519                         break;
1520         }
1521         addr = lo | ((u32)hi<<16);
1522         return (unsigned int)(addr - s->buffer_addr);
1523 }
1524
1525 static snd_pcm_uframes_t
1526 snd_m3_pcm_pointer(snd_pcm_substream_t * subs)
1527 {
1528         m3_t *chip = snd_pcm_substream_chip(subs);
1529         m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data;
1530         snd_assert(s != NULL, return 0);
1531         return bytes_to_frames(subs->runtime, snd_m3_get_pointer(chip, s, subs));
1532 }
1533
1534
1535 /* update pointer */
1536 /* spinlock held! */
1537 static void snd_m3_update_ptr(m3_t *chip, m3_dma_t *s)
1538 {
1539         snd_pcm_substream_t *subs = s->substream;
1540         unsigned int hwptr;
1541         int diff;
1542
1543         if (! s->running)
1544                 return;
1545
1546         hwptr = snd_m3_get_pointer(chip, s, subs) % s->dma_size;
1547         diff = (s->dma_size + hwptr - s->hwptr) % s->dma_size;
1548         s->hwptr = hwptr;
1549         s->count += diff;
1550         if (s->count >= (signed)s->period_size) {
1551                 s->count %= s->period_size;
1552                 spin_unlock(&chip->reg_lock);
1553                 snd_pcm_period_elapsed(subs);
1554                 spin_lock(&chip->reg_lock);
1555         }
1556 }
1557
1558 static irqreturn_t
1559 snd_m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1560 {
1561         m3_t *chip = snd_magic_cast(m3_t, dev_id, );
1562         u8 status;
1563         int i;
1564
1565         status = inb(chip->iobase + 0x1A);
1566
1567         if (status == 0xff)
1568                 return IRQ_NONE;
1569
1570         /* presumably acking the ints? */
1571         outw(status, chip->iobase + 0x1A);
1572
1573         /*if (in_suspend)
1574                 return IRQ_NONE;*/
1575
1576         /*
1577          * ack an assp int if its running
1578          * and has an int pending
1579          */
1580         if (status & ASSP_INT_PENDING) {
1581                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1582                 if (!(ctl & STOP_ASSP_CLOCK)) {
1583                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1584                         if (ctl & DSP2HOST_REQ_TIMER) {
1585                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1586                                 /* update adc/dac info if it was a timer int */
1587                                 spin_lock(&chip->reg_lock);
1588                                 for (i = 0; i < chip->num_substreams; i++) {
1589                                         m3_dma_t *s = &chip->substreams[i];
1590                                         if (s->running)
1591                                                 snd_m3_update_ptr(chip, s);
1592                                 }
1593                                 spin_unlock(&chip->reg_lock);
1594                         }
1595                 }
1596         }
1597
1598         /* XXX is this needed? */
1599         if (status & 0x40)
1600                 outb(0x40, chip->iobase+0x1A);
1601
1602         return IRQ_HANDLED;
1603 }
1604
1605
1606 /*
1607  */
1608
1609 static snd_pcm_hardware_t snd_m3_playback =
1610 {
1611         .info =                 (SNDRV_PCM_INFO_MMAP |
1612                                  SNDRV_PCM_INFO_INTERLEAVED |
1613                                  SNDRV_PCM_INFO_MMAP_VALID |
1614                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1615                                  /*SNDRV_PCM_INFO_PAUSE |*/
1616                                  SNDRV_PCM_INFO_RESUME),
1617         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1618         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1619         .rate_min =             8000,
1620         .rate_max =             48000,
1621         .channels_min =         1,
1622         .channels_max =         2,
1623         .buffer_bytes_max =     (512*1024),
1624         .period_bytes_min =     64,
1625         .period_bytes_max =     (512*1024),
1626         .periods_min =          1,
1627         .periods_max =          1024,
1628 };
1629
1630 static snd_pcm_hardware_t snd_m3_capture =
1631 {
1632         .info =                 (SNDRV_PCM_INFO_MMAP |
1633                                  SNDRV_PCM_INFO_INTERLEAVED |
1634                                  SNDRV_PCM_INFO_MMAP_VALID |
1635                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1636                                  /*SNDRV_PCM_INFO_PAUSE |*/
1637                                  SNDRV_PCM_INFO_RESUME),
1638         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1639         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1640         .rate_min =             8000,
1641         .rate_max =             48000,
1642         .channels_min =         1,
1643         .channels_max =         2,
1644         .buffer_bytes_max =     (512*1024),
1645         .period_bytes_min =     64,
1646         .period_bytes_max =     (512*1024),
1647         .periods_min =          1,
1648         .periods_max =          1024,
1649 };
1650
1651
1652 /*
1653  */
1654
1655 static int
1656 snd_m3_substream_open(m3_t *chip, snd_pcm_substream_t *subs)
1657 {
1658         int i;
1659         m3_dma_t *s;
1660         unsigned long flags;
1661
1662         spin_lock_irqsave(&chip->reg_lock, flags);
1663         for (i = 0; i < chip->num_substreams; i++) {
1664                 s = &chip->substreams[i];
1665                 if (! s->opened)
1666                         goto __found;
1667         }
1668         spin_unlock_irqrestore(&chip->reg_lock, flags);
1669         return -ENOMEM;
1670 __found:
1671         s->opened = 1;
1672         s->running = 0;
1673         spin_unlock_irqrestore(&chip->reg_lock, flags);
1674
1675         subs->runtime->private_data = s;
1676         s->substream = subs;
1677
1678         /* set list owners */
1679         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1680                 s->index_list[0] = &chip->mixer_list;
1681         } else
1682                 s->index_list[0] = &chip->adc1_list;
1683         s->index_list[1] = &chip->msrc_list;
1684         s->index_list[2] = &chip->dma_list;
1685
1686         return 0;
1687 }
1688
1689 static void
1690 snd_m3_substream_close(m3_t *chip, snd_pcm_substream_t *subs)
1691 {
1692         m3_dma_t *s = (m3_dma_t*) subs->runtime->private_data;
1693         unsigned long flags;
1694
1695         if (s == NULL)
1696                 return; /* not opened properly */
1697
1698         spin_lock_irqsave(&chip->reg_lock, flags);
1699         if (s->substream && s->running)
1700                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1701         if (s->in_lists) {
1702                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1703                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1704                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1705                 s->in_lists = 0;
1706         }
1707         s->running = 0;
1708         s->opened = 0;
1709         spin_unlock_irqrestore(&chip->reg_lock, flags);
1710 }
1711
1712 static int
1713 snd_m3_playback_open(snd_pcm_substream_t *subs)
1714 {
1715         m3_t *chip = snd_pcm_substream_chip(subs);
1716         snd_pcm_runtime_t *runtime = subs->runtime;
1717         int err;
1718
1719         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1720                 return err;
1721
1722         runtime->hw = snd_m3_playback;
1723         snd_pcm_set_sync(subs);
1724
1725         return 0;
1726 }
1727
1728 static int
1729 snd_m3_playback_close(snd_pcm_substream_t *subs)
1730 {
1731         m3_t *chip = snd_pcm_substream_chip(subs);
1732
1733         snd_m3_substream_close(chip, subs);
1734         return 0;
1735 }
1736
1737 static int
1738 snd_m3_capture_open(snd_pcm_substream_t *subs)
1739 {
1740         m3_t *chip = snd_pcm_substream_chip(subs);
1741         snd_pcm_runtime_t *runtime = subs->runtime;
1742         int err;
1743
1744         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1745                 return err;
1746
1747         runtime->hw = snd_m3_capture;
1748         snd_pcm_set_sync(subs);
1749
1750         return 0;
1751 }
1752
1753 static int
1754 snd_m3_capture_close(snd_pcm_substream_t *subs)
1755 {
1756         m3_t *chip = snd_pcm_substream_chip(subs);
1757
1758         snd_m3_substream_close(chip, subs);
1759         return 0;
1760 }
1761
1762 /*
1763  * create pcm instance
1764  */
1765
1766 static snd_pcm_ops_t snd_m3_playback_ops = {
1767         .open =         snd_m3_playback_open,
1768         .close =        snd_m3_playback_close,
1769         .ioctl =        snd_pcm_lib_ioctl,
1770         .hw_params =    snd_m3_pcm_hw_params,
1771         .hw_free =      snd_m3_pcm_hw_free,
1772         .prepare =      snd_m3_pcm_prepare,
1773         .trigger =      snd_m3_pcm_trigger,
1774         .pointer =      snd_m3_pcm_pointer,
1775 };
1776
1777 static snd_pcm_ops_t snd_m3_capture_ops = {
1778         .open =         snd_m3_capture_open,
1779         .close =        snd_m3_capture_close,
1780         .ioctl =        snd_pcm_lib_ioctl,
1781         .hw_params =    snd_m3_pcm_hw_params,
1782         .hw_free =      snd_m3_pcm_hw_free,
1783         .prepare =      snd_m3_pcm_prepare,
1784         .trigger =      snd_m3_pcm_trigger,
1785         .pointer =      snd_m3_pcm_pointer,
1786 };
1787
1788 static int __devinit
1789 snd_m3_pcm(m3_t * chip, int device)
1790 {
1791         snd_pcm_t *pcm;
1792         int err;
1793
1794         err = snd_pcm_new(chip->card, chip->card->driver, device,
1795                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1796         if (err < 0)
1797                 return err;
1798
1799         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1800         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1801
1802         pcm->private_data = chip;
1803         pcm->info_flags = 0;
1804         strcpy(pcm->name, chip->card->driver);
1805         chip->pcm = pcm;
1806
1807         snd_pcm_lib_preallocate_pci_pages_for_all(chip->pci, pcm, 64*1024, 64*1024);
1808
1809         return 0;
1810 }
1811
1812
1813 /*
1814  * ac97 interface
1815  */
1816
1817 /*
1818  * Wait for the ac97 serial bus to be free.
1819  * return nonzero if the bus is still busy.
1820  */
1821 static int snd_m3_ac97_wait(m3_t *chip)
1822 {
1823         int i = 10000;
1824
1825         do {
1826                 if (! (snd_m3_inb(chip, 0x30) & 1))
1827                         return 0;
1828         } while (i-- > 0);
1829
1830         snd_printk("ac97 serial bus busy\n");
1831         return 1;
1832 }
1833
1834 static unsigned short
1835 snd_m3_ac97_read(ac97_t *ac97, unsigned short reg)
1836 {
1837         m3_t *chip = snd_magic_cast(m3_t, ac97->private_data, return -ENXIO);
1838         unsigned short ret = 0;
1839         unsigned long flags;
1840
1841         spin_lock_irqsave(&chip->reg_lock, flags);
1842         if (snd_m3_ac97_wait(chip))
1843                 goto __error;
1844         snd_m3_outb(chip, 0x80 | (reg & 0x7f), 0x30);
1845         if (snd_m3_ac97_wait(chip))
1846                 goto __error;
1847         ret = snd_m3_inw(chip, 0x32);
1848 __error:
1849         spin_unlock_irqrestore(&chip->reg_lock, flags);
1850         return ret;
1851 }
1852
1853 static void
1854 snd_m3_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
1855 {
1856         m3_t *chip = snd_magic_cast(m3_t, ac97->private_data, return);
1857         unsigned long flags;
1858
1859         spin_lock_irqsave(&chip->reg_lock, flags);
1860         if (snd_m3_ac97_wait(chip))
1861                 goto __error;
1862         snd_m3_outw(chip, val, 0x32);
1863         snd_m3_outb(chip, reg & 0x7f, 0x30);
1864 __error:
1865         spin_unlock_irqrestore(&chip->reg_lock, flags);
1866 }
1867
1868
1869 static void snd_m3_remote_codec_config(int io, int isremote)
1870 {
1871         isremote = isremote ? 1 : 0;
1872
1873         outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1874              io + RING_BUS_CTRL_B);
1875         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1876              io + SDO_OUT_DEST_CTRL);
1877         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1878              io + SDO_IN_DEST_CTRL);
1879 }
1880
1881 /*
1882  * hack, returns non zero on err
1883  */
1884 static int snd_m3_try_read_vendor(m3_t *chip)
1885 {
1886         u16 ret;
1887
1888         if (snd_m3_ac97_wait(chip))
1889                 return 1;
1890
1891         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1892
1893         if (snd_m3_ac97_wait(chip))
1894                 return 1;
1895
1896         ret = snd_m3_inw(chip, 0x32);
1897
1898         return (ret == 0) || (ret == 0xffff);
1899 }
1900
1901 static void snd_m3_ac97_reset(m3_t *chip, int busywait)
1902 {
1903         u16 dir;
1904         int delay1 = 0, delay2 = 0, i;
1905         int io = chip->iobase;
1906
1907         if (chip->allegro_flag) {
1908                 /*
1909                  * the onboard codec on the allegro seems
1910                  * to want to wait a very long time before
1911                  * coming back to life
1912                  */
1913                 delay1 = 50;
1914                 delay2 = 800;
1915         } else {
1916                 /* maestro3 */
1917                 delay1 = 20;
1918                 delay2 = 500;
1919         }
1920
1921         for (i = 0; i < 5; i++) {
1922                 dir = inw(io + GPIO_DIRECTION);
1923                 if (! chip->quirk || ! chip->quirk->irda_workaround)
1924                         dir |= 0x10; /* assuming pci bus master? */
1925
1926                 snd_m3_remote_codec_config(io, 0);
1927
1928                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
1929                 udelay(20);
1930
1931                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
1932                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
1933                 outw(0, io + GPIO_DATA);
1934                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
1935
1936                 if (busywait)  {
1937                         mdelay(delay1);
1938                 } else {
1939                         set_current_state(TASK_UNINTERRUPTIBLE);
1940                         schedule_timeout((delay1 * HZ) / 1000);
1941                 }
1942
1943                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
1944                 udelay(5);
1945                 /* ok, bring back the ac-link */
1946                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
1947                 outw(~0, io + GPIO_MASK);
1948
1949                 if (busywait) {
1950                         mdelay(delay2);
1951                 } else {
1952                         set_current_state(TASK_UNINTERRUPTIBLE);
1953                         schedule_timeout((delay2 * HZ) / 1000);
1954                 }
1955                 if (! snd_m3_try_read_vendor(chip))
1956                         break;
1957
1958                 delay1 += 10;
1959                 delay2 += 100;
1960
1961                 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
1962                            delay1, delay2);
1963         }
1964
1965 #if 0
1966         /* more gung-ho reset that doesn't
1967          * seem to work anywhere :)
1968          */
1969         tmp = inw(io + RING_BUS_CTRL_A);
1970         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
1971         mdelay(20);
1972         outw(tmp, io + RING_BUS_CTRL_A);
1973         mdelay(50);
1974 #endif
1975 }
1976
1977 static int __devinit snd_m3_mixer(m3_t *chip)
1978 {
1979         ac97_t ac97;
1980         int err;
1981
1982         memset(&ac97, 0, sizeof(ac97));
1983         ac97.write = snd_m3_ac97_write;
1984         ac97.read = snd_m3_ac97_read;
1985         ac97.private_data = chip;
1986         if ((err = snd_ac97_mixer(chip->card, &ac97, &chip->ac97)) < 0)
1987                 return err;
1988
1989         /* seems ac97 PCM needs initialization.. hack hack.. */
1990         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
1991         set_current_state(TASK_UNINTERRUPTIBLE);
1992         schedule_timeout(HZ / 10);
1993         snd_ac97_write(chip->ac97, AC97_PCM, 0);
1994
1995         return 0;
1996 }
1997
1998
1999 /*
2000  * DSP Code images
2001  */
2002
2003 static u16 assp_kernel_image[] __devinitdata = {
2004     0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
2005     0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2006     0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2007     0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
2008     0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
2009     0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
2010     0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2011     0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2012     0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2013     0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2014     0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2015     0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2016     0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2017     0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2018     0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2019     0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2020     0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2021     0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2022     0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2023     0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2024     0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2025     0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2026     0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2027     0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2028     0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2029     0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2030     0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2031     0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2032     0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2033     0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2034     0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2035     0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2036     0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2037     0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2038     0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2039     0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2040     0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2041     0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2042     0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2043     0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2044     0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2045     0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2046     0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2047     0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2048     0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2049     0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2050     0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2051     0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2052     0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2053     0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2054     0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2055     0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2056     0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2057     0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2058     0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2059     0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2060     0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2061     0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2062     0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2063     0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2064     0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2065     0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2066     0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2067     0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2068     0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2069     0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2070     0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2071     0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2072     0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2073     0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2074     0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2075     0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2076     0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2077     0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2078     0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2079     0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2080     0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2081     0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2082     0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2083     0xBE3A,
2084 };
2085
2086 /*
2087  * Mini sample rate converter code image
2088  * that is to be loaded at 0x400 on the DSP.
2089  */
2090 static u16 assp_minisrc_image[] __devinitdata = {
2091
2092     0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2093     0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2094     0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2095     0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2096     0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2097     0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2098     0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2099     0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2100     0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2101     0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2102     0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2103     0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2104     0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2105     0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2106     0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2107     0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2108     0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2109     0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2110     0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2111     0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2112     0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2113     0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2114     0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2115     0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2116     0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2117     0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2118     0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2119     0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2120     0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2121     0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2122     0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2123     0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2124     0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2125 };
2126
2127
2128 /*
2129  * initialize ASSP
2130  */
2131
2132 #define MINISRC_LPF_LEN 10
2133 static u16 minisrc_lpf[MINISRC_LPF_LEN] __devinitdata = {
2134         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2135         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2136 };
2137
2138 static void __devinit snd_m3_assp_init(m3_t *chip)
2139 {
2140         unsigned int i;
2141
2142         /* zero kernel data */
2143         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2144                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2145                                   KDATA_BASE_ADDR + i, 0);
2146
2147         /* zero mixer data? */
2148         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2149                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2150                                   KDATA_BASE_ADDR2 + i, 0);
2151
2152         /* init dma pointer */
2153         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2154                           KDATA_CURRENT_DMA,
2155                           KDATA_DMA_XFER0);
2156
2157         /* write kernel into code memory.. */
2158         for (i = 0 ; i < sizeof(assp_kernel_image) / 2; i++) {
2159                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2160                                   REV_B_CODE_MEMORY_BEGIN + i,
2161                                   assp_kernel_image[i]);
2162         }
2163
2164         /*
2165          * We only have this one client and we know that 0x400
2166          * is free in our kernel's mem map, so lets just
2167          * drop it there.  It seems that the minisrc doesn't
2168          * need vectors, so we won't bother with them..
2169          */
2170         for (i = 0; i < sizeof(assp_minisrc_image) / 2; i++) {
2171                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2172                                   0x400 + i,
2173                                   assp_minisrc_image[i]);
2174         }
2175
2176         /*
2177          * write the coefficients for the low pass filter?
2178          */
2179         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2180                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2181                                   0x400 + MINISRC_COEF_LOC + i,
2182                                   minisrc_lpf[i]);
2183         }
2184
2185         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2186                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2187                           0x8000);
2188
2189         /*
2190          * the minisrc is the only thing on
2191          * our task list..
2192          */
2193         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2194                           KDATA_TASK0,
2195                           0x400);
2196
2197         /*
2198          * init the mixer number..
2199          */
2200
2201         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2202                           KDATA_MIXER_TASK_NUMBER,0);
2203
2204         /*
2205          * EXTREME KERNEL MASTER VOLUME
2206          */
2207         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2208                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2209         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2210                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2211
2212         chip->mixer_list.curlen = 0;
2213         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2214         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2215         chip->adc1_list.curlen = 0;
2216         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2217         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2218         chip->dma_list.curlen = 0;
2219         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2220         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2221         chip->msrc_list.curlen = 0;
2222         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2223         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2224 }
2225
2226
2227 static int __devinit snd_m3_assp_client_init(m3_t *chip, m3_dma_t *s, int index)
2228 {
2229         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2230                                MINISRC_IN_BUFFER_SIZE / 2 +
2231                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2232         int address, i;
2233
2234         /*
2235          * the revb memory map has 0x1100 through 0x1c00
2236          * free.
2237          */
2238
2239         /*
2240          * align instance address to 256 bytes so that it's
2241          * shifted list address is aligned.
2242          * list address = (mem address >> 1) >> 7;
2243          */
2244         data_bytes = (data_bytes + 255) & ~255;
2245         address = 0x1100 + ((data_bytes/2) * index);
2246
2247         if ((address + (data_bytes/2)) >= 0x1c00) {
2248                 snd_printk("no memory for %d bytes at ind %d (addr 0x%x)\n",
2249                            data_bytes, index, address);
2250                 return -ENOMEM;
2251         }
2252
2253         s->number = index;
2254         s->inst.code = 0x400;
2255         s->inst.data = address;
2256
2257         for (i = data_bytes / 2; i > 0; address++, i--) {
2258                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2259                                   address, 0);
2260         }
2261
2262         return 0;
2263 }
2264
2265
2266 /*
2267  * this works for the reference board, have to find
2268  * out about others
2269  *
2270  * this needs more magic for 4 speaker, but..
2271  */
2272 static void
2273 snd_m3_amp_enable(m3_t *chip, int enable)
2274 {
2275         int io = chip->iobase;
2276         u16 gpo, polarity;
2277
2278         if (! chip->external_amp)
2279                 return;
2280
2281         polarity = enable ? 0 : 1;
2282         polarity = polarity << chip->amp_gpio;
2283         gpo = 1 << chip->amp_gpio;
2284
2285         outw(~gpo, io + GPIO_MASK);
2286
2287         outw(inw(io + GPIO_DIRECTION) | gpo,
2288              io + GPIO_DIRECTION);
2289
2290         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2291              io + GPIO_DATA);
2292
2293         outw(0xffff, io + GPIO_MASK);
2294 }
2295
2296 static int
2297 snd_m3_chip_init(m3_t *chip)
2298 {
2299         struct pci_dev *pcidev = chip->pci;
2300         u32 n;
2301         u8 t; /* makes as much sense as 'n', no? */
2302
2303         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2304         n &= REDUCED_DEBOUNCE;
2305         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2306         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2307
2308         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2309         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2310         n &= ~INT_CLK_SELECT;
2311         if (!chip->allegro_flag) {
2312                 n &= ~INT_CLK_MULT_ENABLE;
2313                 n |= INT_CLK_SRC_NOT_PCI;
2314         }
2315         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2316         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2317
2318         if (chip->allegro_flag) {
2319                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2320                 n |= IN_CLK_12MHZ_SELECT;
2321                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2322         }
2323
2324         t = inb(chip->iobase + ASSP_CONTROL_A);
2325         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2326         t |= ASSP_CLK_49MHZ_SELECT;
2327         t |= ASSP_0_WS_ENABLE;
2328         outb(t, chip->iobase + ASSP_CONTROL_A);
2329
2330         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2331
2332         return 0;
2333 }
2334
2335 static void
2336 snd_m3_enable_ints(m3_t *chip)
2337 {
2338         unsigned long io = chip->iobase;
2339
2340         outw(ASSP_INT_ENABLE, io + HOST_INT_CTRL);
2341         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2342              io + ASSP_CONTROL_C);
2343 }
2344
2345
2346 /*
2347  */
2348
2349 static int snd_m3_free(m3_t *chip)
2350 {
2351         unsigned long flags;
2352         m3_dma_t *s;
2353         int i;
2354
2355         if (chip->substreams) {
2356                 spin_lock_irqsave(&chip->reg_lock, flags);
2357                 for (i = 0; i < chip->num_substreams; i++) {
2358                         s = &chip->substreams[i];
2359                         /* check surviving pcms; this should not happen though.. */
2360                         if (s->substream && s->running)
2361                                 snd_m3_pcm_stop(chip, s, s->substream);
2362                 }
2363                 spin_unlock_irqrestore(&chip->reg_lock, flags);
2364                 kfree(chip->substreams);
2365         }
2366 #ifdef CONFIG_PM
2367         if (chip->suspend_mem)
2368                 vfree(chip->suspend_mem);
2369 #endif
2370
2371         if (chip->irq >= 0)
2372                 synchronize_irq(chip->irq);
2373
2374         if (chip->iobase_res) {
2375                 release_resource(chip->iobase_res);
2376                 kfree_nocheck(chip->iobase_res);
2377         }
2378         if (chip->irq >= 0)
2379                 free_irq(chip->irq, (void *)chip);
2380
2381         snd_magic_kfree(chip);
2382         return 0;
2383 }
2384
2385
2386 /*
2387  * APM support
2388  */
2389 #ifdef CONFIG_PM
2390
2391 static void m3_suspend(m3_t *chip)
2392 {
2393         snd_card_t *card = chip->card;
2394         int i, index;
2395
2396         if (chip->suspend_mem == NULL)
2397                 return;
2398         if (card->power_state == SNDRV_CTL_POWER_D3hot)
2399                 return;
2400
2401         snd_pcm_suspend_all(chip->pcm);
2402
2403         mdelay(10); /* give the assp a chance to idle.. */
2404
2405         snd_m3_assp_halt(chip);
2406
2407         /* save dsp image */
2408         index = 0;
2409         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2410                 chip->suspend_mem[index++] =
2411                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2412         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2413                 chip->suspend_mem[index++] =
2414                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2415
2416         /* power down apci registers */
2417         snd_m3_outw(chip, 0xffff, 0x54);
2418         snd_m3_outw(chip, 0xffff, 0x56);
2419         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2420 }
2421
2422 static void m3_resume(m3_t *chip)
2423 {
2424         snd_card_t *card = chip->card;
2425         int i, index;
2426
2427         if (chip->suspend_mem == NULL)
2428                 return;
2429         if (card->power_state == SNDRV_CTL_POWER_D0)
2430                 return;
2431
2432         /* first lets just bring everything back. .*/
2433         snd_m3_outw(chip, 0, 0x54);
2434         snd_m3_outw(chip, 0, 0x56);
2435
2436         snd_m3_chip_init(chip);
2437         snd_m3_assp_halt(chip);
2438         snd_m3_ac97_reset(chip, 1);
2439
2440         /* restore dsp image */
2441         index = 0;
2442         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2443                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2444                                   chip->suspend_mem[index++]);
2445         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2446                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2447                                   chip->suspend_mem[index++]);
2448
2449         /* tell the dma engine to restart itself */
2450         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2451                           KDATA_DMA_ACTIVE, 0);
2452
2453         /* restore ac97 registers */
2454         snd_ac97_resume(chip->ac97);
2455
2456         snd_m3_assp_continue(chip);
2457         snd_m3_enable_ints(chip);
2458         snd_m3_amp_enable(chip, 1);
2459
2460         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2461 }
2462
2463 #ifndef PCI_OLD_SUSPEND
2464 static int snd_m3_suspend(struct pci_dev *pci, u32 state)
2465 {
2466         m3_t *chip = snd_magic_cast(m3_t, pci_get_drvdata(pci), return -ENXIO);
2467         m3_suspend(chip);
2468         return 0;
2469 }
2470 static int snd_m3_resume(struct pci_dev *pci)
2471 {
2472         m3_t *chip = snd_magic_cast(m3_t, pci_get_drvdata(pci), return -ENXIO);
2473         m3_resume(chip);
2474         return 0;
2475 }
2476 #else
2477 static void snd_m3_suspend(struct pci_dev *pci)
2478 {
2479         m3_t *chip = snd_magic_cast(m3_t, pci_get_drvdata(pci), return);
2480         m3_suspend(chip);
2481 }
2482 static void snd_m3_resume(struct pci_dev *pci)
2483 {
2484         m3_t *chip = snd_magic_cast(m3_t, pci_get_drvdata(pci), return);
2485         m3_resume(chip);
2486 }
2487 #endif
2488
2489 /* callback */
2490 static int snd_m3_set_power_state(snd_card_t *card, unsigned int power_state)
2491 {
2492         m3_t *chip = snd_magic_cast(m3_t, card->power_state_private_data, return -ENXIO);
2493         switch (power_state) {
2494         case SNDRV_CTL_POWER_D0:
2495         case SNDRV_CTL_POWER_D1:
2496         case SNDRV_CTL_POWER_D2:
2497                 m3_resume(chip);
2498                 break;
2499         case SNDRV_CTL_POWER_D3hot:
2500         case SNDRV_CTL_POWER_D3cold:
2501                 m3_suspend(chip);
2502                 break;
2503         default:
2504                 return -EINVAL;
2505         }
2506         return 0;
2507 }
2508
2509 #endif /* CONFIG_PM */
2510
2511
2512 /*
2513  */
2514
2515 static int snd_m3_dev_free(snd_device_t *device)
2516 {
2517         m3_t *chip = snd_magic_cast(m3_t, device->device_data, return -ENXIO);
2518         return snd_m3_free(chip);
2519 }
2520
2521 static int __devinit
2522 snd_m3_create(snd_card_t *card, struct pci_dev *pci,
2523               int enable_amp,
2524               int amp_gpio,
2525               m3_t **chip_ret)
2526 {
2527         m3_t *chip;
2528         int i, err;
2529         struct m3_quirk *quirk;
2530         u16 subsystem_vendor, subsystem_device;
2531         static snd_device_ops_t ops = {
2532                 .dev_free =     snd_m3_dev_free,
2533         };
2534
2535         *chip_ret = NULL;
2536
2537         if (pci_enable_device(pci))
2538                 return -EIO;
2539
2540         /* check, if we can restrict PCI DMA transfers to 28 bits */
2541         if (!pci_dma_supported(pci, 0x0fffffff)) {
2542                 snd_printk("architecture does not support 28bit PCI busmaster DMA\n");
2543                 return -ENXIO;
2544         }
2545         pci_set_dma_mask(pci, 0x0fffffff);
2546
2547         chip = snd_magic_kcalloc(m3_t, 0, GFP_KERNEL);
2548         if (chip == NULL)
2549                 return -ENOMEM;
2550
2551         spin_lock_init(&chip->reg_lock);
2552         switch (pci->device) {
2553         case PCI_DEVICE_ID_ESS_ALLEGRO:
2554         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2555         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2556         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2557                 chip->allegro_flag = 1;
2558                 break;
2559         }
2560
2561         chip->card = card;
2562         chip->pci = pci;
2563         chip->irq = -1;
2564
2565         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vendor);
2566         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &subsystem_device);
2567
2568         for (quirk = m3_quirk_list; quirk->vendor; quirk++) {
2569                 if (subsystem_vendor == quirk->vendor &&
2570                     subsystem_device == quirk->device) {
2571                         printk(KERN_INFO "maestro3: enabled hack for '%s'\n", quirk->name);
2572                         chip->quirk = quirk;
2573                         break;
2574                 }
2575         }
2576
2577         chip->external_amp = enable_amp;
2578         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2579                 chip->amp_gpio = amp_gpio;
2580         else if (chip->quirk && chip->quirk->amp_gpio >= 0)
2581                 chip->amp_gpio = chip->quirk->amp_gpio;
2582         else if (chip->allegro_flag)
2583                 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2584         else /* presumably this is for all 'maestro3's.. */
2585                 chip->amp_gpio = GPO_EXT_AMP_M3;
2586
2587         chip->num_substreams = NR_DSPS;
2588         chip->substreams = kmalloc(sizeof(m3_dma_t) * chip->num_substreams, GFP_KERNEL);
2589         if (chip->substreams == NULL) {
2590                 snd_magic_kfree(chip);
2591                 return -ENOMEM;
2592         }
2593         memset(chip->substreams, 0, sizeof(m3_dma_t) * chip->num_substreams);
2594
2595         chip->iobase = pci_resource_start(pci, 0);
2596         if ((chip->iobase_res = request_region(chip->iobase, 256,
2597                                                card->driver)) == NULL) {
2598                 snd_printk("unable to grab i/o ports %ld\n", chip->iobase);
2599                 snd_m3_free(chip);
2600                 return -EBUSY;
2601         }
2602
2603         /* just to be sure */
2604         pci_set_master(pci);
2605
2606         snd_m3_chip_init(chip);
2607         snd_m3_assp_halt(chip);
2608
2609         snd_m3_ac97_reset(chip, 0);
2610
2611         snd_m3_assp_init(chip);
2612         snd_m3_amp_enable(chip, 1);
2613
2614         if ((err = snd_m3_mixer(chip)) < 0) {
2615                 snd_m3_free(chip);
2616                 return err;
2617         }
2618
2619         for (i = 0; i < chip->num_substreams; i++) {
2620                 m3_dma_t *s = &chip->substreams[i];
2621                 s->chip = chip;
2622                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0) {
2623                         snd_m3_free(chip);
2624                         return err;
2625                 }
2626         }
2627
2628         if ((err = snd_m3_pcm(chip, 0)) < 0) {
2629                 snd_m3_free(chip);
2630                 return err;
2631         }
2632
2633         if (request_irq(pci->irq, snd_m3_interrupt, SA_INTERRUPT|SA_SHIRQ,
2634                         card->driver, (void *)chip)) {
2635                 snd_printk("unable to grab IRQ %d\n", pci->irq);
2636                 snd_m3_free(chip);
2637                 return -ENOMEM;
2638         }
2639         chip->irq = pci->irq;
2640
2641 #ifdef CONFIG_PM
2642         chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2643         if (chip->suspend_mem == NULL)
2644                 snd_printk("can't allocate apm buffer\n");
2645         else {
2646                 card->set_power_state = snd_m3_set_power_state;
2647                 card->power_state_private_data = chip;
2648         }
2649 #endif
2650
2651         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2652                 snd_m3_free(chip);
2653                 return err;
2654         }
2655
2656         snd_m3_enable_ints(chip);
2657         snd_m3_assp_continue(chip);
2658
2659         *chip_ret = chip;
2660
2661         return 0;
2662 }
2663
2664 /*
2665  */
2666 static int __devinit
2667 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2668 {
2669         static int dev;
2670         snd_card_t *card;
2671         m3_t *chip;
2672         int err;
2673
2674         /* don't pick up modems */
2675         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2676                 return -ENODEV;
2677
2678         if (dev >= SNDRV_CARDS)
2679                 return -ENODEV;
2680         if (!enable[dev]) {
2681                 dev++;
2682                 return -ENOENT;
2683         }
2684
2685         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2686         if (card == NULL)
2687                 return -ENOMEM;
2688
2689         switch (pci->device) {
2690         case PCI_DEVICE_ID_ESS_ALLEGRO:
2691         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2692                 strcpy(card->driver, "Allegro");
2693                 break;
2694         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2695         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2696                 strcpy(card->driver, "Canyon3D-2");
2697                 break;
2698         default:
2699                 strcpy(card->driver, "Maestro3");
2700                 break;
2701         }
2702
2703         if ((err = snd_m3_create(card, pci,
2704                                  external_amp[dev],
2705                                  amp_gpio[dev],
2706                                  &chip)) < 0) {
2707                 snd_card_free(card);
2708                 return err;
2709         }
2710
2711         sprintf(card->shortname, "ESS %s PCI", card->driver);
2712         sprintf(card->longname, "%s at 0x%lx, irq %d",
2713                 card->shortname, chip->iobase, chip->irq);
2714
2715         if ((err = snd_card_register(card)) < 0) {
2716                 snd_card_free(card);
2717                 return err;
2718         }
2719
2720         pci_set_drvdata(pci, chip);
2721         dev++;
2722         return 0;
2723 }
2724
2725 static void __devexit snd_m3_remove(struct pci_dev *pci)
2726 {
2727         m3_t *chip = snd_magic_cast(m3_t, pci_get_drvdata(pci), return);
2728         if (chip)
2729                 snd_card_free(chip->card);
2730         pci_set_drvdata(pci, NULL);
2731 }
2732
2733 static struct pci_driver driver = {
2734         .name = "Maestro3",
2735         .id_table = snd_m3_ids,
2736         .probe = snd_m3_probe,
2737         .remove = __devexit_p(snd_m3_remove),
2738 #ifdef CONFIG_PM
2739         .suspend = snd_m3_suspend,
2740         .resume = snd_m3_resume,
2741 #endif
2742 };
2743
2744 static int __init alsa_card_m3_init(void)
2745 {
2746         int err;
2747
2748         if ((err = pci_module_init(&driver)) < 0) {
2749 #ifdef MODULE
2750                 printk(KERN_ERR "Maestro3/Allegro soundcard not found or device busy\n");
2751 #endif
2752                 return err;
2753         }
2754         return 0;
2755 }
2756
2757 static void __exit alsa_card_m3_exit(void)
2758 {
2759         pci_unregister_driver(&driver);
2760 }
2761
2762 module_init(alsa_card_m3_init)
2763 module_exit(alsa_card_m3_exit)
2764
2765 #ifndef MODULE
2766
2767 /* format is: snd-maestro3=enable,index,id,external_amp,amp_gpio */
2768
2769 static int __init alsa_card_maestro3_setup(char *str)
2770 {
2771         static unsigned __initdata nr_dev = 0;
2772
2773         if (nr_dev >= SNDRV_CARDS)
2774                 return 0;
2775         (void)(get_option(&str,&enable[nr_dev]) == 2 &&
2776                get_option(&str,&index[nr_dev]) == 2 &&
2777                get_id(&str,&id[nr_dev]) == 2 &&
2778                get_option(&str,&external_amp[nr_dev]) == 2 &&
2779                get_option(&str,&amp_gpio[nr_dev]) == 2);
2780         nr_dev++;
2781         return 1;
2782 }
2783
2784 __setup("snd-maestro3=", alsa_card_maestro3_setup);
2785
2786 #endif /* ifndef MODULE */