sound/pci/cs46xx/cs46xx_lib.c

   1 /*
   2  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>
   3  *                   Abramo Bagnara <abramo@alsa-project.org>
   4  *                   Cirrus Logic, Inc.
   5  *  Routines for control of Cirrus Logic CS461x chips
   6  *
   7  *  KNOWN BUGS:
   8  *    - Sometimes the SPDIF input DSP tasks get's unsynchronized
   9  *      and the SPDIF get somewhat "distorcionated", or/and left right channel
  10  *      are swapped. To get around this problem when it happens, mute and unmute
  11  *      the SPDIF input mixer controll.
  12  *    - On the Hercules Game Theater XP the amplifier are sometimes turned
  13  *      off on inadecuate moments which causes distorcions on sound.
  14  *
  15  *  TODO:
  16  *    - Secondary CODEC on some soundcards
  17  *    - SPDIF input support for other sample rates then 48khz
  18  *    - Posibility to mix the SPDIF output with analog sources.
  19  *    - PCM channels for Center and LFE on secondary codec
  20  *
  21  *  NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
  22  *        is default configuration), no SPDIF, no secondary codec, no
  23  *        multi channel PCM.  But known to work.
  24  *
  25  *  FINALLY: A credit to the developers Tom and Jordan
  26  *           at Cirrus for have helping me out with the DSP, however we
  27  *           still don't have sufficient documentation and technical
  28  *           references to be able to implement all fancy feutures
  29  *           supported by the cs46xx DSP's.
  30  *           Benny <benny@hostmobility.com>
  31  *
  32  *   This program is free software; you can redistribute it and/or modify
  33  *   it under the terms of the GNU General Public License as published by
  34  *   the Free Software Foundation; either version 2 of the License, or
  35  *   (at your option) any later version.
  36  *
  37  *   This program is distributed in the hope that it will be useful,
  38  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  39  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  40  *   GNU General Public License for more details.
  41  *
  42  *   You should have received a copy of the GNU General Public License
  43  *   along with this program; if not, write to the Free Software
  44  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  45  *
  46  */
  47
  48 #include <sound/driver.h>
  49 #include <linux/delay.h>
  50 #include <linux/pci.h>
  51 #include <linux/pm.h>
  52 #include <linux/init.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/slab.h>
  55 #include <linux/gameport.h>
  56
  57 #include <sound/core.h>
  58 #include <sound/control.h>
  59 #include <sound/info.h>
  60 #include <sound/pcm.h>
  61 #include <sound/pcm_params.h>
  62 #include <sound/cs46xx.h>
  63
  64 #include <asm/io.h>
  65
  66 #include "cs46xx_lib.h"
  67 #include "dsp_spos.h"
  68
  69 static unsigned short snd_cs46xx_codec_read(cs46xx_t *chip,
  70                                             unsigned short reg,
  71                                             int codec_index)
  72 {
  73         int count;
  74         unsigned short result,tmp;
  75         u32 offset = 0;
  76         snd_assert ( (codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
  77                      (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
  78                      return -EINVAL);
  79
  80         if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
  81                 offset = CS46XX_SECONDARY_CODEC_OFFSET;
  82
  83         /*
  84          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
  85          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
  86          *  3. Write ACCTL = Control Register = 460h for initiating the write7---55
  87          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
  88          *  5. if DCV not cleared, break and return error
  89          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
  90          */
  91
  92         snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
  93
  94         tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
  95         if ((tmp & ACCTL_VFRM) == 0) {
  96                 snd_printk(KERN_WARNING  "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp);
  97                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
  98                 mdelay(50);
  99                 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
 100                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
 101
 102         }
 103
 104         /*
 105          *  Setup the AC97 control registers on the CS461x to send the
 106          *  appropriate command to the AC97 to perform the read.
 107          *  ACCAD = Command Address Register = 46Ch
 108          *  ACCDA = Command Data Register = 470h
 109          *  ACCTL = Control Register = 460h
 110          *  set DCV - will clear when process completed
 111          *  set CRW - Read command
 112          *  set VFRM - valid frame enabled
 113          *  set ESYN - ASYNC generation enabled
 114          *  set RSTN - ARST# inactive, AC97 codec not reset
 115          */
 116
 117         snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
 118         snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
 119         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 120                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
 121                                    ACCTL_VFRM | ACCTL_ESYN |
 122                                    ACCTL_RSTN);
 123                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
 124                                    ACCTL_VFRM | ACCTL_ESYN |
 125                                    ACCTL_RSTN);
 126         } else {
 127                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 128                                    ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
 129                                    ACCTL_RSTN);
 130         }
 131
 132         /*
 133          *  Wait for the read to occur.
 134          */
 135         for (count = 0; count < 1000; count++) {
 136                 /*
 137                  *  First, we want to wait for a short time.
 138                  */
 139                 udelay(10);
 140                 /*
 141                  *  Now, check to see if the read has completed.
 142                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
 143                  */
 144                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
 145                         goto ok1;
 146         }
 147
 148         snd_printk("AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
 149         result = 0xffff;
 150         goto end;
 151
 152  ok1:
 153         /*
 154          *  Wait for the valid status bit to go active.
 155          */
 156         for (count = 0; count < 100; count++) {
 157                 /*
 158                  *  Read the AC97 status register.
 159                  *  ACSTS = Status Register = 464h
 160                  *  VSTS - Valid Status
 161                  */
 162                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
 163                         goto ok2;
 164                 udelay(10);
 165         }
 166
 167         snd_printk("AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg);
 168         result = 0xffff;
 169         goto end;
 170
 171  ok2:
 172         /*
 173          *  Read the data returned from the AC97 register.
 174          *  ACSDA = Status Data Register = 474h
 175          */
 176 #if 0
 177         printk("e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
 178                         snd_cs46xx_peekBA0(chip, BA0_ACSDA),
 179                         snd_cs46xx_peekBA0(chip, BA0_ACCAD));
 180 #endif
 181
 182         //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
 183         result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 184  end:
 185         return result;
 186 }
 187
 188 static unsigned short snd_cs46xx_ac97_read(ac97_t * ac97,
 189                                             unsigned short reg)
 190 {
 191         cs46xx_t *chip = snd_magic_cast(cs46xx_t, ac97->private_data, return -ENXIO);
 192         unsigned short val;
 193         int codec_index = -1;
 194
 195         /* UGGLY: nr_ac97_codecs == 0 primery codec detection is in progress */
 196         if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] || chip->nr_ac97_codecs == 0)
 197                 codec_index = CS46XX_PRIMARY_CODEC_INDEX;
 198         /* UGGLY: nr_ac97_codecs == 1 secondary codec detection is in progress */
 199         else if (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] || chip->nr_ac97_codecs == 1)
 200                 codec_index = CS46XX_SECONDARY_CODEC_INDEX;
 201         else
 202                 snd_assert(0, return 0xffff);
 203         chip->active_ctrl(chip, 1);
 204         val = snd_cs46xx_codec_read(chip, reg, codec_index);
 205         chip->active_ctrl(chip, -1);
 206         return val;
 207 }
 208
 209
 210 static void snd_cs46xx_codec_write(cs46xx_t *chip,
 211                                    unsigned short reg,
 212                                    unsigned short val,
 213                                    int codec_index)
 214 {
 215         int count;
 216
 217         snd_assert ((codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
 218                     (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
 219                     return);
 220
 221         /*
 222          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 223          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 224          *  3. Write ACCTL = Control Register = 460h for initiating the write
 225          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 226          *  5. if DCV not cleared, break and return error
 227          */
 228
 229         /*
 230          *  Setup the AC97 control registers on the CS461x to send the
 231          *  appropriate command to the AC97 to perform the read.
 232          *  ACCAD = Command Address Register = 46Ch
 233          *  ACCDA = Command Data Register = 470h
 234          *  ACCTL = Control Register = 460h
 235          *  set DCV - will clear when process completed
 236          *  reset CRW - Write command
 237          *  set VFRM - valid frame enabled
 238          *  set ESYN - ASYNC generation enabled
 239          *  set RSTN - ARST# inactive, AC97 codec not reset
 240          */
 241         snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
 242         snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
 243         snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 244
 245         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 246                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
 247                                    ACCTL_ESYN | ACCTL_RSTN);
 248                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
 249                                    ACCTL_ESYN | ACCTL_RSTN);
 250         } else {
 251                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 252                                    ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
 253         }
 254
 255         for (count = 0; count < 4000; count++) {
 256                 /*
 257                  *  First, we want to wait for a short time.
 258                  */
 259                 udelay(10);
 260                 /*
 261                  *  Now, check to see if the write has completed.
 262                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
 263                  */
 264                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
 265                         return;
 266                 }
 267         }
 268         snd_printk("AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val);
 269 }
 270
 271 static void snd_cs46xx_ac97_write(ac97_t *ac97,
 272                                    unsigned short reg,
 273                                    unsigned short val)
 274 {
 275         cs46xx_t *chip = snd_magic_cast(cs46xx_t, ac97->private_data, return);
 276         int codec_index = -1;
 277
 278         /* UGGLY: nr_ac97_codecs == 0 primery codec detection is in progress */
 279         if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] || chip->nr_ac97_codecs == 0)
 280                 codec_index = CS46XX_PRIMARY_CODEC_INDEX;
 281         /* UGGLY: nr_ac97_codecs == 1 secondary codec detection is in progress */
 282         else  if (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] || chip->nr_ac97_codecs == 1)
 283                 codec_index = CS46XX_SECONDARY_CODEC_INDEX;
 284         else
 285                 snd_assert(0,return);
 286
 287         chip->active_ctrl(chip, 1);
 288         snd_cs46xx_codec_write(chip, reg, val, codec_index);
 289         chip->active_ctrl(chip, -1);
 290 }
 291
 292
 293 /*
 294  *  Chip initialization
 295  */
 296
 297 int snd_cs46xx_download(cs46xx_t *chip,
 298                         u32 *src,
 299                         unsigned long offset,
 300                         unsigned long len)
 301 {
 302         unsigned long dst;
 303         unsigned int bank = offset >> 16;
 304         offset = offset & 0xffff;
 305
 306         snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
 307         dst = chip->region.idx[bank+1].remap_addr + offset;
 308         len /= sizeof(u32);
 309
 310         /* writel already converts 32-bit value to right endianess */
 311         while (len-- > 0) {
 312                 writel(*src++, dst);
 313                 dst += sizeof(u32);
 314         }
 315         return 0;
 316 }
 317
 318 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 319
 320 #include "imgs/cwc4630.h"
 321 #include "imgs/cwcasync.h"
 322 #include "imgs/cwcsnoop.h"
 323 #include "imgs/cwcbinhack.h"
 324 #include "imgs/cwcdma.h"
 325
 326 int snd_cs46xx_clear_BA1(cs46xx_t *chip,
 327                          unsigned long offset,
 328                          unsigned long len)
 329 {
 330         unsigned long dst;
 331         unsigned int bank = offset >> 16;
 332         offset = offset & 0xffff;
 333
 334         snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
 335         dst = chip->region.idx[bank+1].remap_addr + offset;
 336         len /= sizeof(u32);
 337
 338         /* writel already converts 32-bit value to right endianess */
 339         while (len-- > 0) {
 340                 writel(0, dst);
 341                 dst += sizeof(u32);
 342         }
 343         return 0;
 344 }
 345
 346 #else /* old DSP image */
 347
 348 #include "cs46xx_image.h"
 349
 350 int snd_cs46xx_download_image(cs46xx_t *chip)
 351 {
 352         int idx, err;
 353         unsigned long offset = 0;
 354
 355         for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
 356                 if ((err = snd_cs46xx_download(chip,
 357                                                &BA1Struct.map[offset],
 358                                                BA1Struct.memory[idx].offset,
 359                                                BA1Struct.memory[idx].size)) < 0)
 360                         return err;
 361                 offset += BA1Struct.memory[idx].size >> 2;
 362         }
 363         return 0;
 364 }
 365 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
 366
 367 /*
 368  *  Chip reset
 369  */
 370
 371 static void snd_cs46xx_reset(cs46xx_t *chip)
 372 {
 373         int idx;
 374
 375         /*
 376          *  Write the reset bit of the SP control register.
 377          */
 378         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
 379
 380         /*
 381          *  Write the control register.
 382          */
 383         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
 384
 385         /*
 386          *  Clear the trap registers.
 387          */
 388         for (idx = 0; idx < 8; idx++) {
 389                 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
 390                 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
 391         }
 392         snd_cs46xx_poke(chip, BA1_DREG, 0);
 393
 394         /*
 395          *  Set the frame timer to reflect the number of cycles per frame.
 396          */
 397         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 398 }
 399
 400 static int cs46xx_wait_for_fifo(cs46xx_t * chip,int retry_timeout)
 401 {
 402         u32 i, status = 0;
 403         /*
 404          * Make sure the previous FIFO write operation has completed.
 405          */
 406         for(i = 0; i < 50; i++){
 407                 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
 408
 409                 if( !(status & SERBST_WBSY) )
 410                         break;
 411
 412                 mdelay(retry_timeout);
 413         }
 414
 415         if(status & SERBST_WBSY) {
 416                 snd_printk( KERN_ERR "cs46xx: failure waiting for FIFO command to complete\n");
 417
 418                 return -EINVAL;
 419         }
 420
 421         return 0;
 422 }
 423
 424 static void snd_cs46xx_clear_serial_FIFOs(cs46xx_t *chip)
 425 {
 426         int idx, powerdown = 0;
 427         unsigned int tmp;
 428
 429         /*
 430          *  See if the devices are powered down.  If so, we must power them up first
 431          *  or they will not respond.
 432          */
 433         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
 434         if (!(tmp & CLKCR1_SWCE)) {
 435                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
 436                 powerdown = 1;
 437         }
 438
 439         /*
 440          *  We want to clear out the serial port FIFOs so we don't end up playing
 441          *  whatever random garbage happens to be in them.  We fill the sample FIFOS
 442          *  with zero (silence).
 443          */
 444         snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
 445
 446         /*
 447          *  Fill all 256 sample FIFO locations.
 448          */
 449         for (idx = 0; idx < 0xFF; idx++) {
 450                 /*
 451                  *  Make sure the previous FIFO write operation has completed.
 452                  */
 453                 if (cs46xx_wait_for_fifo(chip,1)) {
 454                         snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx);
 455
 456                         if (powerdown)
 457                                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 458
 459                         break;
 460                 }
 461                 /*
 462                  *  Write the serial port FIFO index.
 463                  */
 464                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
 465                 /*
 466                  *  Tell the serial port to load the new value into the FIFO location.
 467                  */
 468                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
 469         }
 470         /*
 471          *  Now, if we powered up the devices, then power them back down again.
 472          *  This is kinda ugly, but should never happen.
 473          */
 474         if (powerdown)
 475                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 476 }
 477
 478 static void snd_cs46xx_proc_start(cs46xx_t *chip)
 479 {
 480         int cnt;
 481
 482         /*
 483          *  Set the frame timer to reflect the number of cycles per frame.
 484          */
 485         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 486         /*
 487          *  Turn on the run, run at frame, and DMA enable bits in the local copy of
 488          *  the SP control register.
 489          */
 490         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
 491         /*
 492          *  Wait until the run at frame bit resets itself in the SP control
 493          *  register.
 494          */
 495         for (cnt = 0; cnt < 25; cnt++) {
 496                 udelay(50);
 497                 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
 498                         break;
 499         }
 500
 501         if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
 502                 snd_printk("SPCR_RUNFR never reset\n");
 503 }
 504
 505 static void snd_cs46xx_proc_stop(cs46xx_t *chip)
 506 {
 507         /*
 508          *  Turn off the run, run at frame, and DMA enable bits in the local copy of
 509          *  the SP control register.
 510          */
 511         snd_cs46xx_poke(chip, BA1_SPCR, 0);
 512 }
 513
 514 /*
 515  *  Sample rate routines
 516  */
 517
 518 #define GOF_PER_SEC 200
 519
 520 static void snd_cs46xx_set_play_sample_rate(cs46xx_t *chip, unsigned int rate)
 521 {
 522         unsigned long flags;
 523         unsigned int tmp1, tmp2;
 524         unsigned int phiIncr;
 525         unsigned int correctionPerGOF, correctionPerSec;
 526
 527         /*
 528          *  Compute the values used to drive the actual sample rate conversion.
 529          *  The following formulas are being computed, using inline assembly
 530          *  since we need to use 64 bit arithmetic to compute the values:
 531          *
 532          *  phiIncr = floor((Fs,in * 2^26) / Fs,out)
 533          *  correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 534          *                                   GOF_PER_SEC)
 535          *  ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
 536          *                       GOF_PER_SEC * correctionPerGOF
 537          *
 538          *  i.e.
 539          *
 540          *  phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
 541          *  correctionPerGOF:correctionPerSec =
 542          *      dividend:remainder(ulOther / GOF_PER_SEC)
 543          */
 544         tmp1 = rate << 16;
 545         phiIncr = tmp1 / 48000;
 546         tmp1 -= phiIncr * 48000;
 547         tmp1 <<= 10;
 548         phiIncr <<= 10;
 549         tmp2 = tmp1 / 48000;
 550         phiIncr += tmp2;
 551         tmp1 -= tmp2 * 48000;
 552         correctionPerGOF = tmp1 / GOF_PER_SEC;
 553         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 554         correctionPerSec = tmp1;
 555
 556         /*
 557          *  Fill in the SampleRateConverter control block.
 558          */
 559         spin_lock_irqsave(&chip->reg_lock, flags);
 560         snd_cs46xx_poke(chip, BA1_PSRC,
 561           ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 562         snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
 563         spin_unlock_irqrestore(&chip->reg_lock, flags);
 564 }
 565
 566 static void snd_cs46xx_set_capture_sample_rate(cs46xx_t *chip, unsigned int rate)
 567 {
 568         unsigned long flags;
 569         unsigned int phiIncr, coeffIncr, tmp1, tmp2;
 570         unsigned int correctionPerGOF, correctionPerSec, initialDelay;
 571         unsigned int frameGroupLength, cnt;
 572
 573         /*
 574          *  We can only decimate by up to a factor of 1/9th the hardware rate.
 575          *  Correct the value if an attempt is made to stray outside that limit.
 576          */
 577         if ((rate * 9) < 48000)
 578                 rate = 48000 / 9;
 579
 580         /*
 581          *  We can not capture at at rate greater than the Input Rate (48000).
 582          *  Return an error if an attempt is made to stray outside that limit.
 583          */
 584         if (rate > 48000)
 585                 rate = 48000;
 586
 587         /*
 588          *  Compute the values used to drive the actual sample rate conversion.
 589          *  The following formulas are being computed, using inline assembly
 590          *  since we need to use 64 bit arithmetic to compute the values:
 591          *
 592          *     coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
 593          *     phiIncr = floor((Fs,in * 2^26) / Fs,out)
 594          *     correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 595          *                                GOF_PER_SEC)
 596          *     correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
 597          *                          GOF_PER_SEC * correctionPerGOF
 598          *     initialDelay = ceil((24 * Fs,in) / Fs,out)
 599          *
 600          * i.e.
 601          *
 602          *     coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
 603          *     phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
 604          *     correctionPerGOF:correctionPerSec =
 605          *          dividend:remainder(ulOther / GOF_PER_SEC)
 606          *     initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
 607          */
 608
 609         tmp1 = rate << 16;
 610         coeffIncr = tmp1 / 48000;
 611         tmp1 -= coeffIncr * 48000;
 612         tmp1 <<= 7;
 613         coeffIncr <<= 7;
 614         coeffIncr += tmp1 / 48000;
 615         coeffIncr ^= 0xFFFFFFFF;
 616         coeffIncr++;
 617         tmp1 = 48000 << 16;
 618         phiIncr = tmp1 / rate;
 619         tmp1 -= phiIncr * rate;
 620         tmp1 <<= 10;
 621         phiIncr <<= 10;
 622         tmp2 = tmp1 / rate;
 623         phiIncr += tmp2;
 624         tmp1 -= tmp2 * rate;
 625         correctionPerGOF = tmp1 / GOF_PER_SEC;
 626         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 627         correctionPerSec = tmp1;
 628         initialDelay = ((48000 * 24) + rate - 1) / rate;
 629
 630         /*
 631          *  Fill in the VariDecimate control block.
 632          */
 633         spin_lock_irqsave(&chip->reg_lock, flags);
 634         snd_cs46xx_poke(chip, BA1_CSRC,
 635                 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 636         snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
 637         snd_cs46xx_poke(chip, BA1_CD,
 638                 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
 639         snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
 640         spin_unlock_irqrestore(&chip->reg_lock, flags);
 641
 642         /*
 643          *  Figure out the frame group length for the write back task.  Basically,
 644          *  this is just the factors of 24000 (2^6*3*5^3) that are not present in
 645          *  the output sample rate.
 646          */
 647         frameGroupLength = 1;
 648         for (cnt = 2; cnt <= 64; cnt *= 2) {
 649                 if (((rate / cnt) * cnt) != rate)
 650                         frameGroupLength *= 2;
 651         }
 652         if (((rate / 3) * 3) != rate) {
 653                 frameGroupLength *= 3;
 654         }
 655         for (cnt = 5; cnt <= 125; cnt *= 5) {
 656                 if (((rate / cnt) * cnt) != rate)
 657                         frameGroupLength *= 5;
 658         }
 659
 660         /*
 661          * Fill in the WriteBack control block.
 662          */
 663         spin_lock_irqsave(&chip->reg_lock, flags);
 664         snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
 665         snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
 666         snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
 667         snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
 668         snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
 669         spin_unlock_irqrestore(&chip->reg_lock, flags);
 670 }
 671
 672 /*
 673  *  PCM part
 674  */
 675
 676 static int snd_cs46xx_playback_transfer(snd_pcm_substream_t *substream)
 677 {
 678         /* cs46xx_t *chip = snd_pcm_substream_chip(substream); */
 679         snd_pcm_runtime_t *runtime = substream->runtime;
 680         cs46xx_pcm_t * cpcm = snd_magic_cast(cs46xx_pcm_t, runtime->private_data, return -ENXIO);
 681         snd_pcm_uframes_t appl_ptr = runtime->control->appl_ptr;
 682         snd_pcm_sframes_t diff = appl_ptr - cpcm->appl_ptr;
 683         int buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
 684
 685         if (diff) {
 686                 if (diff < -(snd_pcm_sframes_t) (runtime->boundary / 2))
 687                         diff += runtime->boundary;
 688                 cpcm->sw_ready += diff * (1 << cpcm->shift);
 689                 cpcm->appl_ptr = appl_ptr;
 690         }
 691         while (cpcm->hw_ready < buffer_size &&
 692                cpcm->sw_ready > 0) {
 693                 size_t hw_to_end = buffer_size - cpcm->hw_data;
 694                 size_t sw_to_end = cpcm->sw_bufsize - cpcm->sw_data;
 695                 size_t bytes = buffer_size - cpcm->hw_ready;
 696                 if (cpcm->sw_ready < (int)bytes)
 697                         bytes = cpcm->sw_ready;
 698                 if (hw_to_end < bytes)
 699                         bytes = hw_to_end;
 700                 if (sw_to_end < bytes)
 701                         bytes = sw_to_end;
 702                 memcpy(cpcm->hw_area + cpcm->hw_data,
 703                        runtime->dma_area + cpcm->sw_data,
 704                        bytes);
 705                 cpcm->hw_data += bytes;
 706                 if ((int)cpcm->hw_data == buffer_size)
 707                         cpcm->hw_data = 0;
 708                 cpcm->sw_data += bytes;
 709                 if (cpcm->sw_data == cpcm->sw_bufsize)
 710                         cpcm->sw_data = 0;
 711                 cpcm->hw_ready += bytes;
 712                 cpcm->sw_ready -= bytes;
 713         }
 714         return 0;
 715 }
 716
 717 static int snd_cs46xx_capture_transfer(snd_pcm_substream_t *substream)
 718 {
 719         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 720         snd_pcm_runtime_t *runtime = substream->runtime;
 721         snd_pcm_uframes_t appl_ptr = runtime->control->appl_ptr;
 722         snd_pcm_sframes_t diff = appl_ptr - chip->capt.appl_ptr;
 723         int buffer_size = runtime->period_size * CS46XX_FRAGS << chip->capt.shift;
 724
 725         if (diff) {
 726                 if (diff < -(snd_pcm_sframes_t) (runtime->boundary / 2))
 727                         diff += runtime->boundary;
 728                 chip->capt.sw_ready -= diff * (1 << chip->capt.shift);
 729                 chip->capt.appl_ptr = appl_ptr;
 730         }
 731         while (chip->capt.hw_ready > 0 &&
 732                chip->capt.sw_ready < (int)chip->capt.sw_bufsize) {
 733                 size_t hw_to_end = buffer_size - chip->capt.hw_data;
 734                 size_t sw_to_end = chip->capt.sw_bufsize - chip->capt.sw_data;
 735                 size_t bytes = chip->capt.sw_bufsize - chip->capt.sw_ready;
 736                 if (chip->capt.hw_ready < (int)bytes)
 737                         bytes = chip->capt.hw_ready;
 738                 if (hw_to_end < bytes)
 739                         bytes = hw_to_end;
 740                 if (sw_to_end < bytes)
 741                         bytes = sw_to_end;
 742                 memcpy(runtime->dma_area + chip->capt.sw_data,
 743                        chip->capt.hw_area + chip->capt.hw_data,
 744                        bytes);
 745                 chip->capt.hw_data += bytes;
 746                 if ((int)chip->capt.hw_data == buffer_size)
 747                         chip->capt.hw_data = 0;
 748                 chip->capt.sw_data += bytes;
 749                 if (chip->capt.sw_data == chip->capt.sw_bufsize)
 750                         chip->capt.sw_data = 0;
 751                 chip->capt.hw_ready -= bytes;
 752                 chip->capt.sw_ready += bytes;
 753         }
 754         return 0;
 755 }
 756
 757 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(snd_pcm_substream_t * substream)
 758 {
 759         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 760         size_t ptr;
 761         cs46xx_pcm_t *cpcm = snd_magic_cast(cs46xx_pcm_t, substream->runtime->private_data, return -ENXIO);
 762         snd_assert (cpcm->pcm_channel,return -ENXIO);
 763
 764 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 765         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 766 #else
 767         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 768 #endif
 769         ptr -= cpcm->hw_addr;
 770         return ptr >> cpcm->shift;
 771 }
 772
 773 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(snd_pcm_substream_t * substream)
 774 {
 775         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 776         size_t ptr;
 777         cs46xx_pcm_t *cpcm = snd_magic_cast(cs46xx_pcm_t, substream->runtime->private_data, return -ENXIO);
 778         ssize_t bytes;
 779         int buffer_size = substream->runtime->period_size * CS46XX_FRAGS << cpcm->shift;
 780
 781 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 782         snd_assert (cpcm->pcm_channel,return -ENXIO);
 783         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 784 #else
 785         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 786 #endif
 787         ptr -= cpcm->hw_addr;
 788
 789         bytes = ptr - cpcm->hw_io;
 790
 791         if (bytes < 0)
 792                 bytes += buffer_size;
 793         cpcm->hw_io = ptr;
 794         cpcm->hw_ready -= bytes;
 795         cpcm->sw_io += bytes;
 796         if (cpcm->sw_io >= cpcm->sw_bufsize)
 797                 cpcm->sw_io -= cpcm->sw_bufsize;
 798         snd_cs46xx_playback_transfer(substream);
 799         return cpcm->sw_io >> cpcm->shift;
 800 }
 801
 802 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(snd_pcm_substream_t * substream)
 803 {
 804         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 805         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_addr;
 806         return ptr >> chip->capt.shift;
 807 }
 808
 809 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(snd_pcm_substream_t * substream)
 810 {
 811         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 812         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_addr;
 813         ssize_t bytes = ptr - chip->capt.hw_io;
 814         int buffer_size = substream->runtime->period_size * CS46XX_FRAGS << chip->capt.shift;
 815
 816         if (bytes < 0)
 817                 bytes += buffer_size;
 818         chip->capt.hw_io = ptr;
 819         chip->capt.hw_ready += bytes;
 820         chip->capt.sw_io += bytes;
 821         if (chip->capt.sw_io >= chip->capt.sw_bufsize)
 822                 chip->capt.sw_io -= chip->capt.sw_bufsize;
 823         snd_cs46xx_capture_transfer(substream);
 824         return chip->capt.sw_io >> chip->capt.shift;
 825 }
 826
 827 static int snd_cs46xx_playback_trigger(snd_pcm_substream_t * substream,
 828                                        int cmd)
 829 {
 830         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 831         /*snd_pcm_runtime_t *runtime = substream->runtime;*/
 832         int result = 0;
 833
 834 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 835         cs46xx_pcm_t *cpcm = snd_magic_cast(cs46xx_pcm_t, substream->runtime->private_data, return -ENXIO);
 836 #else
 837         spin_lock(&chip->reg_lock);
 838 #endif
 839
 840 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 841
 842         if (! cpcm->pcm_channel) {
 843                 return -ENXIO;
 844         }
 845 #endif
 846         switch (cmd) {
 847         case SNDRV_PCM_TRIGGER_START:
 848         case SNDRV_PCM_TRIGGER_RESUME:
 849 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 850                 /* magic value to unmute PCM stream  playback volume */
 851                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 852                                        SCBVolumeCtrl) << 2, 0x80008000);
 853
 854                 if (cpcm->pcm_channel->unlinked)
 855                         cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
 856
 857                 if (substream->runtime->periods != CS46XX_FRAGS)
 858                         snd_cs46xx_playback_transfer(substream);
 859 #else
 860                 if (substream->runtime->periods != CS46XX_FRAGS)
 861                         snd_cs46xx_playback_transfer(substream);
 862                 { unsigned int tmp;
 863                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 864                 tmp &= 0x0000ffff;
 865                 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
 866                 }
 867 #endif
 868                 break;
 869         case SNDRV_PCM_TRIGGER_STOP:
 870         case SNDRV_PCM_TRIGGER_SUSPEND:
 871 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 872                 /* magic mute channel */
 873                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 874                                        SCBVolumeCtrl) << 2, 0xffffffff);
 875
 876                 if (!cpcm->pcm_channel->unlinked)
 877                         cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
 878 #else
 879                 { unsigned int tmp;
 880                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 881                 tmp &= 0x0000ffff;
 882                 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
 883                 }
 884 #endif
 885                 break;
 886         default:
 887                 result = -EINVAL;
 888                 break;
 889         }
 890
 891 #ifndef CONFIG_SND_CS46XX_NEW_DSP
 892         spin_unlock(&chip->reg_lock);
 893 #endif
 894
 895         return result;
 896 }
 897
 898 static int snd_cs46xx_capture_trigger(snd_pcm_substream_t * substream,
 899                                       int cmd)
 900 {
 901         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 902         unsigned int tmp;
 903         int result = 0;
 904
 905         spin_lock(&chip->reg_lock);
 906         switch (cmd) {
 907         case SNDRV_PCM_TRIGGER_START:
 908         case SNDRV_PCM_TRIGGER_RESUME:
 909                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
 910                 tmp &= 0xffff0000;
 911                 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
 912                 break;
 913         case SNDRV_PCM_TRIGGER_STOP:
 914         case SNDRV_PCM_TRIGGER_SUSPEND:
 915                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
 916                 tmp &= 0xffff0000;
 917                 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
 918                 break;
 919         default:
 920                 result = -EINVAL;
 921                 break;
 922         }
 923         spin_unlock(&chip->reg_lock);
 924
 925         return result;
 926 }
 927
 928 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 929 static int _cs46xx_adjust_sample_rate (cs46xx_t *chip, cs46xx_pcm_t *cpcm,
 930                                        int sample_rate)
 931 {
 932
 933         /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
 934         if ( cpcm->pcm_channel == NULL) {
 935                 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
 936                                                                    cpcm, cpcm->hw_addr,cpcm->pcm_channel_id);
 937                 if (cpcm->pcm_channel == NULL) {
 938                         snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n");
 939                         return -ENOMEM;
 940                 }
 941                 cpcm->pcm_channel->sample_rate = sample_rate;
 942         } else
 943         /* if sample rate is changed */
 944         if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
 945                 int unlinked = cpcm->pcm_channel->unlinked;
 946                 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
 947
 948                 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
 949                                                                          cpcm->hw_addr,
 950                                                                          cpcm->pcm_channel_id)) == NULL) {
 951                         snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n");
 952                         return -ENOMEM;
 953                 }
 954
 955                 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
 956                 cpcm->pcm_channel->sample_rate = sample_rate;
 957         }
 958
 959         return 0;
 960 }
 961 #endif
 962
 963
 964 static int snd_cs46xx_playback_hw_params(snd_pcm_substream_t * substream,
 965                                          snd_pcm_hw_params_t * hw_params)
 966 {
 967         snd_pcm_runtime_t *runtime = substream->runtime;
 968         cs46xx_pcm_t *cpcm;
 969         int err;
 970 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 971         cs46xx_t *chip = snd_pcm_substream_chip(substream);
 972         int sample_rate = params_rate(hw_params);
 973         int period_size = params_period_bytes(hw_params);
 974 #endif
 975         cpcm = snd_magic_cast(cs46xx_pcm_t, runtime->private_data, return -ENXIO);
 976
 977 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 978         snd_assert (sample_rate != 0, return -ENXIO);
 979
 980         down (&chip->spos_mutex);
 981
 982         if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
 983                 up (&chip->spos_mutex);
 984                 return -ENXIO;
 985         }
 986
 987         snd_assert (cpcm->pcm_channel != NULL);
 988         if (!cpcm->pcm_channel) {
 989                 up (&chip->spos_mutex);
 990                 return -ENXIO;
 991         }
 992
 993
 994         if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
 995                  up (&chip->spos_mutex);
 996                  return -EINVAL;
 997          }
 998
 999         snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n",
1000                      period_size, params_periods(hw_params),
1001                      params_buffer_bytes(hw_params));
1002 #endif
1003
1004         if (params_periods(hw_params) == CS46XX_FRAGS) {
1005                 if (runtime->dma_area != cpcm->hw_area)
1006                         snd_pcm_lib_free_pages(substream);
1007                 runtime->dma_area = cpcm->hw_area;
1008                 runtime->dma_addr = cpcm->hw_addr;
1009                 runtime->dma_bytes = cpcm->hw_size;
1010
1011
1012 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1013                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1014                         substream->ops = &snd_cs46xx_playback_ops;
1015                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1016                         substream->ops = &snd_cs46xx_playback_rear_ops;
1017                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1018                         substream->ops = &snd_cs46xx_playback_clfe_ops;
1019                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1020                         substream->ops = &snd_cs46xx_playback_iec958_ops;
1021                 } else {
1022                         snd_assert(0);
1023                 }
1024 #else
1025                 substream->ops = &snd_cs46xx_playback_ops;
1026 #endif
1027
1028         } else {
1029                 if (runtime->dma_area == cpcm->hw_area) {
1030                         runtime->dma_area = NULL;
1031                         runtime->dma_addr = 0;
1032                         runtime->dma_bytes = 0;
1033                 }
1034                 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
1035 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1036                         up (&chip->spos_mutex);
1037 #endif
1038                         return err;
1039                 }
1040
1041 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1042                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1043                         substream->ops = &snd_cs46xx_playback_indirect_ops;
1044                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1045                         substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1046                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1047                         substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1048                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1049                         substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1050                 } else {
1051                         snd_assert(0);
1052                 }
1053 #else
1054                 substream->ops = &snd_cs46xx_playback_indirect_ops;
1055 #endif
1056
1057         }
1058
1059 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1060         up (&chip->spos_mutex);
1061 #endif
1062
1063         return 0;
1064 }
1065
1066 static int snd_cs46xx_playback_hw_free(snd_pcm_substream_t * substream)
1067 {
1068         /*cs46xx_t *chip = snd_pcm_substream_chip(substream);*/
1069         snd_pcm_runtime_t *runtime = substream->runtime;
1070         cs46xx_pcm_t *cpcm;
1071
1072         cpcm = snd_magic_cast(cs46xx_pcm_t, runtime->private_data, return -ENXIO);
1073
1074         /* if play_back open fails, then this function
1075            is called and cpcm can actually be NULL here */
1076         if (!cpcm) return -ENXIO;
1077
1078         if (runtime->dma_area != cpcm->hw_area)
1079                 snd_pcm_lib_free_pages(substream);
1080
1081         runtime->dma_area = NULL;
1082         runtime->dma_addr = 0;
1083         runtime->dma_bytes = 0;
1084
1085         return 0;
1086 }
1087
1088 static int snd_cs46xx_playback_prepare(snd_pcm_substream_t * substream)
1089 {
1090         unsigned int tmp;
1091         unsigned int pfie;
1092         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1093         snd_pcm_runtime_t *runtime = substream->runtime;
1094         cs46xx_pcm_t *cpcm;
1095
1096         cpcm = snd_magic_cast(cs46xx_pcm_t, runtime->private_data, return -ENXIO);
1097
1098 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1099     snd_assert (cpcm->pcm_channel != NULL, return -ENXIO);
1100
1101         pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1102         pfie &= ~0x0000f03f;
1103 #else
1104         /* old dsp */
1105         pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1106         pfie &= ~0x0000f03f;
1107 #endif
1108
1109         cpcm->shift = 2;
1110         /* if to convert from stereo to mono */
1111         if (runtime->channels == 1) {
1112                 cpcm->shift--;
1113                 pfie |= 0x00002000;
1114         }
1115         /* if to convert from 8 bit to 16 bit */
1116         if (snd_pcm_format_width(runtime->format) == 8) {
1117                 cpcm->shift--;
1118                 pfie |= 0x00001000;
1119         }
1120         /* if to convert to unsigned */
1121         if (snd_pcm_format_unsigned(runtime->format))
1122                 pfie |= 0x00008000;
1123
1124         /* Never convert byte order when sample stream is 8 bit */
1125         if (snd_pcm_format_width(runtime->format) != 8) {
1126                 /* convert from big endian to little endian */
1127                 if (snd_pcm_format_big_endian(runtime->format))
1128                         pfie |= 0x00004000;
1129         }
1130
1131         cpcm->sw_bufsize = snd_pcm_lib_buffer_bytes(substream);
1132         cpcm->sw_data = cpcm->sw_io = cpcm->sw_ready = 0;
1133         cpcm->hw_data = cpcm->hw_io = cpcm->hw_ready = 0;
1134         cpcm->appl_ptr = 0;
1135
1136 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1137
1138         tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1139         tmp &= ~0x000003ff;
1140         tmp |= (4 << cpcm->shift) - 1;
1141         /* playback transaction count register */
1142         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1143
1144         /* playback format && interrupt enable */
1145         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1146 #else
1147         snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_addr);
1148         tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1149         tmp &= ~0x000003ff;
1150         tmp |= (4 << cpcm->shift) - 1;
1151         snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1152         snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1153         snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1154 #endif
1155
1156         return 0;
1157 }
1158
1159 static int snd_cs46xx_capture_hw_params(snd_pcm_substream_t * substream,
1160                                         snd_pcm_hw_params_t * hw_params)
1161 {
1162         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1163         snd_pcm_runtime_t *runtime = substream->runtime;
1164         int err;
1165
1166 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1167         cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1168 #endif
1169         if (runtime->periods == CS46XX_FRAGS) {
1170                 if (runtime->dma_area != chip->capt.hw_area)
1171                         snd_pcm_lib_free_pages(substream);
1172                 runtime->dma_area = chip->capt.hw_area;
1173                 runtime->dma_addr = chip->capt.hw_addr;
1174                 runtime->dma_bytes = chip->capt.hw_size;
1175                 substream->ops = &snd_cs46xx_capture_ops;
1176         } else {
1177                 if (runtime->dma_area == chip->capt.hw_area) {
1178                         runtime->dma_area = NULL;
1179                         runtime->dma_addr = 0;
1180                         runtime->dma_bytes = 0;
1181                 }
1182                 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1183                         return err;
1184                 substream->ops = &snd_cs46xx_capture_indirect_ops;
1185         }
1186
1187         return 0;
1188 }
1189
1190 static int snd_cs46xx_capture_hw_free(snd_pcm_substream_t * substream)
1191 {
1192         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1193         snd_pcm_runtime_t *runtime = substream->runtime;
1194
1195         if (runtime->dma_area != chip->capt.hw_area)
1196                 snd_pcm_lib_free_pages(substream);
1197         runtime->dma_area = NULL;
1198         runtime->dma_addr = 0;
1199         runtime->dma_bytes = 0;
1200
1201         return 0;
1202 }
1203
1204 static int snd_cs46xx_capture_prepare(snd_pcm_substream_t * substream)
1205 {
1206         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1207         snd_pcm_runtime_t *runtime = substream->runtime;
1208
1209         snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_addr);
1210         chip->capt.shift = 2;
1211         chip->capt.sw_bufsize = snd_pcm_lib_buffer_bytes(substream);
1212         chip->capt.sw_data = chip->capt.sw_io = chip->capt.sw_ready = 0;
1213         chip->capt.hw_data = chip->capt.hw_io = chip->capt.hw_ready = 0;
1214         chip->capt.appl_ptr = 0;
1215         snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1216
1217         return 0;
1218 }
1219
1220 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1221 {
1222         cs46xx_t *chip = snd_magic_cast(cs46xx_t, dev_id, return IRQ_NONE);
1223         u32 status1;
1224 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1225         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1226         u32 status2;
1227         int i;
1228         cs46xx_pcm_t *cpcm = NULL;
1229 #endif
1230
1231         /*
1232          *  Read the Interrupt Status Register to clear the interrupt
1233          */
1234         status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1235         if ((status1 & 0x7fffffff) == 0) {
1236                 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1237                 return IRQ_NONE;
1238         }
1239
1240 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1241         status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1242
1243         for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1244                 if (i <= 15) {
1245                         if ( status1 & (1 << i) ) {
1246                                 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1247                                         if (chip->capt.substream)
1248                                                 snd_pcm_period_elapsed(chip->capt.substream);
1249                                 } else {
1250                                         if (ins->pcm_channels[i].active &&
1251                                             ins->pcm_channels[i].private_data &&
1252                                             !ins->pcm_channels[i].unlinked) {
1253                                                 cpcm = snd_magic_cast(cs46xx_pcm_t, ins->pcm_channels[i].private_data, continue);
1254                                                 snd_pcm_period_elapsed(cpcm->substream);
1255                                         }
1256                                 }
1257                         }
1258                 } else {
1259                         if ( status2 & (1 << (i - 16))) {
1260                                 if (ins->pcm_channels[i].active &&
1261                                     ins->pcm_channels[i].private_data &&
1262                                     !ins->pcm_channels[i].unlinked) {
1263                                         cpcm = snd_magic_cast(cs46xx_pcm_t, ins->pcm_channels[i].private_data, continue);
1264                                         snd_pcm_period_elapsed(cpcm->substream);
1265                                 }
1266                         }
1267                 }
1268         }
1269
1270 #else
1271         /* old dsp */
1272         if ((status1 & HISR_VC0) && chip->playback_pcm) {
1273                 if (chip->playback_pcm->substream)
1274                         snd_pcm_period_elapsed(chip->playback_pcm->substream);
1275         }
1276         if ((status1 & HISR_VC1) && chip->pcm) {
1277                 if (chip->capt.substream)
1278                         snd_pcm_period_elapsed(chip->capt.substream);
1279         }
1280 #endif
1281
1282         if ((status1 & HISR_MIDI) && chip->rmidi) {
1283                 unsigned char c;
1284
1285                 spin_lock(&chip->reg_lock);
1286                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1287                         c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1288                         if ((chip->midcr & MIDCR_RIE) == 0)
1289                                 continue;
1290                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1291                 }
1292                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1293                         if ((chip->midcr & MIDCR_TIE) == 0)
1294                                 break;
1295                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1296                                 chip->midcr &= ~MIDCR_TIE;
1297                                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1298                                 break;
1299                         }
1300                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1301                 }
1302                 spin_unlock(&chip->reg_lock);
1303         }
1304         /*
1305          *  EOI to the PCI part....reenables interrupts
1306          */
1307         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1308
1309         return IRQ_HANDLED;
1310 }
1311
1312 static snd_pcm_hardware_t snd_cs46xx_playback =
1313 {
1314         .info =                 (SNDRV_PCM_INFO_MMAP |
1315                                  SNDRV_PCM_INFO_INTERLEAVED |
1316                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1317                                  SNDRV_PCM_INFO_RESUME),
1318         .formats =              (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1319                                  SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1320                                  SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1321         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1322         .rate_min =             5500,
1323         .rate_max =             48000,
1324         .channels_min =         1,
1325         .channels_max =         2,
1326         .buffer_bytes_max =     (256 * 1024),
1327         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1328         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1329         .periods_min =          CS46XX_FRAGS,
1330         .periods_max =          1024,
1331         .fifo_size =            0,
1332 };
1333
1334 static snd_pcm_hardware_t snd_cs46xx_capture =
1335 {
1336         .info =                 (SNDRV_PCM_INFO_MMAP |
1337                                  SNDRV_PCM_INFO_INTERLEAVED |
1338                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1339                                  SNDRV_PCM_INFO_RESUME),
1340         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1341         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1342         .rate_min =             5500,
1343         .rate_max =             48000,
1344         .channels_min =         2,
1345         .channels_max =         2,
1346         .buffer_bytes_max =     (256 * 1024),
1347         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1348         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1349         .periods_min =          CS46XX_FRAGS,
1350         .periods_max =          1024,
1351         .fifo_size =            0,
1352 };
1353
1354 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1355
1356 static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1357
1358 #define PERIOD_SIZES sizeof(period_sizes) / sizeof(period_sizes[0])
1359
1360 static snd_pcm_hw_constraint_list_t hw_constraints_period_sizes = {
1361         .count = PERIOD_SIZES,
1362         .list = period_sizes,
1363         .mask = 0
1364 };
1365
1366 #endif
1367
1368 static void snd_cs46xx_pcm_free_substream(snd_pcm_runtime_t *runtime)
1369 {
1370         cs46xx_pcm_t * cpcm = snd_magic_cast(cs46xx_pcm_t, runtime->private_data, return);
1371
1372         if (cpcm)
1373                 snd_magic_kfree(cpcm);
1374 }
1375
1376 static int _cs46xx_playback_open_channel (snd_pcm_substream_t * substream,int pcm_channel_id)
1377 {
1378         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1379         cs46xx_pcm_t * cpcm;
1380         snd_pcm_runtime_t *runtime = substream->runtime;
1381
1382         cpcm = snd_magic_kcalloc(cs46xx_pcm_t, 0, GFP_KERNEL);
1383         if (cpcm == NULL)
1384                 return -ENOMEM;
1385         cpcm->hw_size = PAGE_SIZE;
1386         if ((cpcm->hw_area = snd_malloc_pci_pages(chip->pci, cpcm->hw_size, &cpcm->hw_addr)) == NULL) {
1387                 snd_magic_kfree(cpcm);
1388                 return -ENOMEM;
1389         }
1390
1391         runtime->hw = snd_cs46xx_playback;
1392         runtime->private_data = cpcm;
1393         runtime->private_free = snd_cs46xx_pcm_free_substream;
1394
1395         cpcm->substream = substream;
1396 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1397         down (&chip->spos_mutex);
1398         cpcm->pcm_channel = NULL;
1399         cpcm->pcm_channel_id = pcm_channel_id;
1400
1401
1402         snd_pcm_hw_constraint_list(runtime, 0,
1403                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1404                                    &hw_constraints_period_sizes);
1405
1406         up (&chip->spos_mutex);
1407 #else
1408         chip->playback_pcm = cpcm; /* HACK */
1409 #endif
1410
1411         if (chip->accept_valid)
1412                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1413         chip->active_ctrl(chip, 1);
1414
1415         return 0;
1416 }
1417
1418 static int snd_cs46xx_playback_open(snd_pcm_substream_t * substream)
1419 {
1420         snd_printdd("open front channel\n");
1421         return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1422 }
1423
1424 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1425 static int snd_cs46xx_playback_open_rear(snd_pcm_substream_t * substream)
1426 {
1427         snd_printdd("open rear channel\n");
1428
1429         return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1430 }
1431
1432 static int snd_cs46xx_playback_open_clfe(snd_pcm_substream_t * substream)
1433 {
1434         snd_printdd("open center - LFE channel\n");
1435
1436         return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1437 }
1438
1439 static int snd_cs46xx_playback_open_iec958(snd_pcm_substream_t * substream)
1440 {
1441         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1442
1443         snd_printdd("open raw iec958 channel\n");
1444
1445         down (&chip->spos_mutex);
1446         cs46xx_iec958_pre_open (chip);
1447         up (&chip->spos_mutex);
1448
1449         return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1450 }
1451
1452 static int snd_cs46xx_playback_close(snd_pcm_substream_t * substream);
1453
1454 static int snd_cs46xx_playback_close_iec958(snd_pcm_substream_t * substream)
1455 {
1456         int err;
1457         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1458
1459         snd_printdd("close raw iec958 channel\n");
1460
1461         err = snd_cs46xx_playback_close(substream);
1462
1463         down (&chip->spos_mutex);
1464         cs46xx_iec958_post_close (chip);
1465         up (&chip->spos_mutex);
1466
1467         return err;
1468 }
1469 #endif
1470
1471 static int snd_cs46xx_capture_open(snd_pcm_substream_t * substream)
1472 {
1473         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1474
1475         if ((chip->capt.hw_area = snd_malloc_pci_pages(chip->pci, chip->capt.hw_size, &chip->capt.hw_addr)) == NULL)
1476                 return -ENOMEM;
1477         chip->capt.substream = substream;
1478         substream->runtime->hw = snd_cs46xx_capture;
1479
1480         if (chip->accept_valid)
1481                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1482
1483         chip->active_ctrl(chip, 1);
1484
1485 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1486         snd_pcm_hw_constraint_list(substream->runtime, 0,
1487                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1488                                    &hw_constraints_period_sizes);
1489 #endif
1490         return 0;
1491 }
1492
1493 static int snd_cs46xx_playback_close(snd_pcm_substream_t * substream)
1494 {
1495         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1496         snd_pcm_runtime_t *runtime = substream->runtime;
1497         cs46xx_pcm_t * cpcm;
1498
1499         cpcm = snd_magic_cast(cs46xx_pcm_t, runtime->private_data, return -ENXIO);
1500
1501         /* when playback_open fails, then cpcm can be NULL */
1502         if (!cpcm) return -ENXIO;
1503
1504 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1505         down (&chip->spos_mutex);
1506         if (cpcm->pcm_channel) {
1507                 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1508                 cpcm->pcm_channel = NULL;
1509         }
1510         up (&chip->spos_mutex);
1511 #else
1512         chip->playback_pcm = NULL;
1513 #endif
1514
1515         cpcm->substream = NULL;
1516         snd_free_pci_pages(chip->pci, cpcm->hw_size, cpcm->hw_area, cpcm->hw_addr);
1517         chip->active_ctrl(chip, -1);
1518
1519         return 0;
1520 }
1521
1522 static int snd_cs46xx_capture_close(snd_pcm_substream_t * substream)
1523 {
1524         cs46xx_t *chip = snd_pcm_substream_chip(substream);
1525
1526         chip->capt.substream = NULL;
1527         snd_free_pci_pages(chip->pci, chip->capt.hw_size, chip->capt.hw_area, chip->capt.hw_addr);
1528         chip->active_ctrl(chip, -1);
1529
1530         return 0;
1531 }
1532
1533 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1534 snd_pcm_ops_t snd_cs46xx_playback_rear_ops = {
1535         .open =                 snd_cs46xx_playback_open_rear,
1536         .close =                snd_cs46xx_playback_close,
1537         .ioctl =                snd_pcm_lib_ioctl,
1538         .hw_params =            snd_cs46xx_playback_hw_params,
1539         .hw_free =              snd_cs46xx_playback_hw_free,
1540         .prepare =              snd_cs46xx_playback_prepare,
1541         .trigger =              snd_cs46xx_playback_trigger,
1542         .pointer =              snd_cs46xx_playback_direct_pointer,
1543 };
1544
1545 snd_pcm_ops_t snd_cs46xx_playback_indirect_rear_ops = {
1546         .open =                 snd_cs46xx_playback_open_rear,
1547         .close =                snd_cs46xx_playback_close,
1548         .ioctl =                snd_pcm_lib_ioctl,
1549         .hw_params =            snd_cs46xx_playback_hw_params,
1550         .hw_free =              snd_cs46xx_playback_hw_free,
1551         .prepare =              snd_cs46xx_playback_prepare,
1552         .trigger =              snd_cs46xx_playback_trigger,
1553         .pointer =              snd_cs46xx_playback_indirect_pointer,
1554         .ack =                  snd_cs46xx_playback_transfer,
1555 };
1556
1557 snd_pcm_ops_t snd_cs46xx_playback_clfe_ops = {
1558         .open =                 snd_cs46xx_playback_open_clfe,
1559         .close =                snd_cs46xx_playback_close,
1560         .ioctl =                snd_pcm_lib_ioctl,
1561         .hw_params =            snd_cs46xx_playback_hw_params,
1562         .hw_free =              snd_cs46xx_playback_hw_free,
1563         .prepare =              snd_cs46xx_playback_prepare,
1564         .trigger =              snd_cs46xx_playback_trigger,
1565         .pointer =              snd_cs46xx_playback_direct_pointer,
1566 };
1567
1568 snd_pcm_ops_t snd_cs46xx_playback_indirect_clfe_ops = {
1569         .open =                 snd_cs46xx_playback_open_clfe,
1570         .close =                snd_cs46xx_playback_close,
1571         .ioctl =                snd_pcm_lib_ioctl,
1572         .hw_params =            snd_cs46xx_playback_hw_params,
1573         .hw_free =              snd_cs46xx_playback_hw_free,
1574         .prepare =              snd_cs46xx_playback_prepare,
1575         .trigger =              snd_cs46xx_playback_trigger,
1576         .pointer =              snd_cs46xx_playback_indirect_pointer,
1577         .ack =                  snd_cs46xx_playback_transfer,
1578 };
1579
1580 snd_pcm_ops_t snd_cs46xx_playback_iec958_ops = {
1581         .open =                 snd_cs46xx_playback_open_iec958,
1582         .close =                snd_cs46xx_playback_close_iec958,
1583         .ioctl =                snd_pcm_lib_ioctl,
1584         .hw_params =            snd_cs46xx_playback_hw_params,
1585         .hw_free =              snd_cs46xx_playback_hw_free,
1586         .prepare =              snd_cs46xx_playback_prepare,
1587         .trigger =              snd_cs46xx_playback_trigger,
1588         .pointer =              snd_cs46xx_playback_direct_pointer,
1589 };
1590
1591 snd_pcm_ops_t snd_cs46xx_playback_indirect_iec958_ops = {
1592         .open =                 snd_cs46xx_playback_open_iec958,
1593         .close =                snd_cs46xx_playback_close_iec958,
1594         .ioctl =                snd_pcm_lib_ioctl,
1595         .hw_params =            snd_cs46xx_playback_hw_params,
1596         .hw_free =              snd_cs46xx_playback_hw_free,
1597         .prepare =              snd_cs46xx_playback_prepare,
1598         .trigger =              snd_cs46xx_playback_trigger,
1599         .pointer =              snd_cs46xx_playback_indirect_pointer,
1600         .ack =                  snd_cs46xx_playback_transfer,
1601 };
1602
1603 #endif
1604
1605 snd_pcm_ops_t snd_cs46xx_playback_ops = {
1606         .open =                 snd_cs46xx_playback_open,
1607         .close =                snd_cs46xx_playback_close,
1608         .ioctl =                snd_pcm_lib_ioctl,
1609         .hw_params =            snd_cs46xx_playback_hw_params,
1610         .hw_free =              snd_cs46xx_playback_hw_free,
1611         .prepare =              snd_cs46xx_playback_prepare,
1612         .trigger =              snd_cs46xx_playback_trigger,
1613         .pointer =              snd_cs46xx_playback_direct_pointer,
1614 };
1615
1616 snd_pcm_ops_t snd_cs46xx_playback_indirect_ops = {
1617         .open =                 snd_cs46xx_playback_open,
1618         .close =                snd_cs46xx_playback_close,
1619         .ioctl =                snd_pcm_lib_ioctl,
1620         .hw_params =            snd_cs46xx_playback_hw_params,
1621         .hw_free =              snd_cs46xx_playback_hw_free,
1622         .prepare =              snd_cs46xx_playback_prepare,
1623         .trigger =              snd_cs46xx_playback_trigger,
1624         .pointer =              snd_cs46xx_playback_indirect_pointer,
1625         .ack =                  snd_cs46xx_playback_transfer,
1626 };
1627
1628 snd_pcm_ops_t snd_cs46xx_capture_ops = {
1629         .open =                 snd_cs46xx_capture_open,
1630         .close =                snd_cs46xx_capture_close,
1631         .ioctl =                snd_pcm_lib_ioctl,
1632         .hw_params =            snd_cs46xx_capture_hw_params,
1633         .hw_free =              snd_cs46xx_capture_hw_free,
1634         .prepare =              snd_cs46xx_capture_prepare,
1635         .trigger =              snd_cs46xx_capture_trigger,
1636         .pointer =              snd_cs46xx_capture_direct_pointer,
1637 };
1638
1639 snd_pcm_ops_t snd_cs46xx_capture_indirect_ops = {
1640         .open =                 snd_cs46xx_capture_open,
1641         .close =                snd_cs46xx_capture_close,
1642         .ioctl =                snd_pcm_lib_ioctl,
1643         .hw_params =            snd_cs46xx_capture_hw_params,
1644         .hw_free =              snd_cs46xx_capture_hw_free,
1645         .prepare =              snd_cs46xx_capture_prepare,
1646         .trigger =              snd_cs46xx_capture_trigger,
1647         .pointer =              snd_cs46xx_capture_indirect_pointer,
1648         .ack =                  snd_cs46xx_capture_transfer,
1649 };
1650
1651 static void snd_cs46xx_pcm_free(snd_pcm_t *pcm)
1652 {
1653         cs46xx_t *chip = snd_magic_cast(cs46xx_t, pcm->private_data, return);
1654         chip->pcm = NULL;
1655         snd_pcm_lib_preallocate_free_for_all(pcm);
1656 }
1657
1658 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1659 static void snd_cs46xx_pcm_rear_free(snd_pcm_t *pcm)
1660 {
1661         cs46xx_t *chip = snd_magic_cast(cs46xx_t, pcm->private_data, return);
1662         chip->pcm_rear = NULL;
1663         snd_pcm_lib_preallocate_free_for_all(pcm);
1664 }
1665
1666 static void snd_cs46xx_pcm_center_lfe_free(snd_pcm_t *pcm)
1667 {
1668         cs46xx_t *chip = snd_magic_cast(cs46xx_t, pcm->private_data, return);
1669         chip->pcm_center_lfe = NULL;
1670         snd_pcm_lib_preallocate_free_for_all(pcm);
1671 }
1672
1673 static void snd_cs46xx_pcm_iec958_free(snd_pcm_t *pcm)
1674 {
1675         cs46xx_t *chip = snd_magic_cast(cs46xx_t, pcm->private_data, return);
1676         chip->pcm_iec958 = NULL;
1677         snd_pcm_lib_preallocate_free_for_all(pcm);
1678 }
1679
1680 #define MAX_PLAYBACK_CHANNELS   (DSP_MAX_PCM_CHANNELS - 1)
1681 #else
1682 #define MAX_PLAYBACK_CHANNELS   1
1683 #endif
1684
1685 int __devinit snd_cs46xx_pcm(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1686 {
1687         snd_pcm_t *pcm;
1688         int err;
1689
1690         if (rpcm)
1691                 *rpcm = NULL;
1692         if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1693                 return err;
1694
1695         pcm->private_data = chip;
1696         pcm->private_free = snd_cs46xx_pcm_free;
1697
1698         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1699         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1700
1701         /* global setup */
1702         pcm->info_flags = 0;
1703         strcpy(pcm->name, "CS46xx");
1704         chip->pcm = pcm;
1705
1706         snd_pcm_lib_preallocate_pci_pages_for_all(chip->pci, pcm, 64*1024, 256*1024);
1707
1708         if (rpcm)
1709                 *rpcm = pcm;
1710
1711         return 0;
1712 }
1713
1714
1715 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1716 int __devinit snd_cs46xx_pcm_rear(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1717 {
1718         snd_pcm_t *pcm;
1719         int err;
1720
1721         if (rpcm)
1722                 *rpcm = NULL;
1723
1724         if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1725                 return err;
1726
1727         pcm->private_data = chip;
1728         pcm->private_free = snd_cs46xx_pcm_rear_free;
1729
1730         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1731
1732         /* global setup */
1733         pcm->info_flags = 0;
1734         strcpy(pcm->name, "CS46xx - Rear");
1735         chip->pcm_rear = pcm;
1736
1737         snd_pcm_lib_preallocate_pci_pages_for_all(chip->pci, pcm, 64*1024, 256*1024);
1738
1739         if (rpcm)
1740                 *rpcm = pcm;
1741
1742         return 0;
1743 }
1744
1745 int __devinit snd_cs46xx_pcm_center_lfe(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1746 {
1747         snd_pcm_t *pcm;
1748         int err;
1749
1750         if (rpcm)
1751                 *rpcm = NULL;
1752
1753         if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1754                 return err;
1755
1756         pcm->private_data = chip;
1757         pcm->private_free = snd_cs46xx_pcm_center_lfe_free;
1758
1759         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1760
1761         /* global setup */
1762         pcm->info_flags = 0;
1763         strcpy(pcm->name, "CS46xx - Center LFE");
1764         chip->pcm_center_lfe = pcm;
1765
1766         snd_pcm_lib_preallocate_pci_pages_for_all(chip->pci, pcm, 64*1024, 256*1024);
1767
1768         if (rpcm)
1769                 *rpcm = pcm;
1770
1771         return 0;
1772 }
1773
1774 int __devinit snd_cs46xx_pcm_iec958(cs46xx_t *chip, int device, snd_pcm_t ** rpcm)
1775 {
1776         snd_pcm_t *pcm;
1777         int err;
1778
1779         if (rpcm)
1780                 *rpcm = NULL;
1781
1782         if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1783                 return err;
1784
1785         pcm->private_data = chip;
1786         pcm->private_free = snd_cs46xx_pcm_iec958_free;
1787
1788         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1789
1790         /* global setup */
1791         pcm->info_flags = 0;
1792         strcpy(pcm->name, "CS46xx - IEC958");
1793         chip->pcm_rear = pcm;
1794
1795         snd_pcm_lib_preallocate_pci_pages_for_all(chip->pci, pcm, 64*1024, 256*1024);
1796
1797         if (rpcm)
1798                 *rpcm = pcm;
1799
1800         return 0;
1801 }
1802 #endif
1803
1804 /*
1805  *  Mixer routines
1806  */
1807 static void snd_cs46xx_mixer_free_ac97(ac97_t *ac97)
1808 {
1809         cs46xx_t *chip = snd_magic_cast(cs46xx_t, ac97->private_data, return);
1810
1811         snd_assert ((ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) ||
1812                     (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]),
1813                     return);
1814
1815         if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1816                 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1817                 chip->eapd_switch = NULL;
1818         }
1819         else
1820                 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1821 }
1822
1823 static int snd_cs46xx_vol_info(snd_kcontrol_t *kcontrol,
1824                                snd_ctl_elem_info_t *uinfo)
1825 {
1826         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1827         uinfo->count = 2;
1828         uinfo->value.integer.min = 0;
1829         uinfo->value.integer.max = 0x7fff;
1830         return 0;
1831 }
1832
1833 static int snd_cs46xx_vol_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1834 {
1835         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1836         int reg = kcontrol->private_value;
1837         unsigned int val = snd_cs46xx_peek(chip, reg);
1838         ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1839         ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1840         return 0;
1841 }
1842
1843 static int snd_cs46xx_vol_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1844 {
1845         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1846         int reg = kcontrol->private_value;
1847         unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1848                             (0xffff - ucontrol->value.integer.value[1]));
1849         unsigned int old = snd_cs46xx_peek(chip, reg);
1850         int change = (old != val);
1851
1852         if (change) {
1853                 snd_cs46xx_poke(chip, reg, val);
1854         }
1855
1856         return change;
1857 }
1858
1859 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1860
1861 static int snd_cs46xx_vol_dac_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1862 {
1863         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1864
1865         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1866         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1867
1868         return 0;
1869 }
1870
1871 static int snd_cs46xx_vol_dac_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1872 {
1873         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1874         int change = 0;
1875
1876         if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1877             chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1878                 cs46xx_dsp_set_dac_volume(chip,
1879                                           ucontrol->value.integer.value[0],
1880                                           ucontrol->value.integer.value[1]);
1881                 change = 1;
1882         }
1883
1884         return change;
1885 }
1886
1887 #if 0
1888 static int snd_cs46xx_vol_iec958_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1889 {
1890         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1891
1892         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1893         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1894         return 0;
1895 }
1896
1897 static int snd_cs46xx_vol_iec958_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1898 {
1899         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1900         int change = 0;
1901
1902         if (chip->dsp_spos_instance->spdif_input_volume_left  != ucontrol->value.integer.value[0] ||
1903             chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1904                 cs46xx_dsp_set_iec958_volume (chip,
1905                                               ucontrol->value.integer.value[0],
1906                                               ucontrol->value.integer.value[1]);
1907                 change = 1;
1908         }
1909
1910         return change;
1911 }
1912 #endif
1913
1914 static int snd_mixer_boolean_info(snd_kcontrol_t *kcontrol,
1915                                   snd_ctl_elem_info_t *uinfo)
1916 {
1917         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1918         uinfo->count = 1;
1919         uinfo->value.integer.min = 0;
1920         uinfo->value.integer.max = 1;
1921         return 0;
1922 }
1923
1924 static int snd_cs46xx_iec958_get(snd_kcontrol_t *kcontrol,
1925                                  snd_ctl_elem_value_t *ucontrol)
1926 {
1927         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1928         int reg = kcontrol->private_value;
1929
1930         if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1931                 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1932         else
1933                 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1934
1935         return 0;
1936 }
1937
1938 static int snd_cs46xx_iec958_put(snd_kcontrol_t *kcontrol,
1939                                   snd_ctl_elem_value_t *ucontrol)
1940 {
1941         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1942         int change, res;
1943
1944         switch (kcontrol->private_value) {
1945         case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1946                 down (&chip->spos_mutex);
1947                 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1948                 if (ucontrol->value.integer.value[0] && !change)
1949                         cs46xx_dsp_enable_spdif_out(chip);
1950                 else if (change && !ucontrol->value.integer.value[0])
1951                         cs46xx_dsp_disable_spdif_out(chip);
1952
1953                 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1954                 up (&chip->spos_mutex);
1955                 break;
1956         case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
1957                 change = chip->dsp_spos_instance->spdif_status_in;
1958                 if (ucontrol->value.integer.value[0] && !change) {
1959                         cs46xx_dsp_enable_spdif_in(chip);
1960                         /* restore volume */
1961                 }
1962                 else if (change && !ucontrol->value.integer.value[0])
1963                         cs46xx_dsp_disable_spdif_in(chip);
1964
1965                 res = (change != chip->dsp_spos_instance->spdif_status_in);
1966                 break;
1967         default:
1968                 res = -EINVAL;
1969                 snd_assert(0, (void)0);
1970         }
1971
1972         return res;
1973 }
1974
1975 static int snd_cs46xx_adc_capture_get(snd_kcontrol_t *kcontrol,
1976                                       snd_ctl_elem_value_t *ucontrol)
1977 {
1978         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1979         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1980
1981         if (ins->adc_input != NULL)
1982                 ucontrol->value.integer.value[0] = 1;
1983         else
1984                 ucontrol->value.integer.value[0] = 0;
1985
1986         return 0;
1987 }
1988
1989 static int snd_cs46xx_adc_capture_put(snd_kcontrol_t *kcontrol,
1990                                       snd_ctl_elem_value_t *ucontrol)
1991 {
1992         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
1993         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
1994         int change = 0;
1995
1996         if (ucontrol->value.integer.value[0] && !ins->adc_input) {
1997                 cs46xx_dsp_enable_adc_capture(chip);
1998                 change = 1;
1999         } else  if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2000                 cs46xx_dsp_disable_adc_capture(chip);
2001                 change = 1;
2002         }
2003         return change;
2004 }
2005
2006 static int snd_cs46xx_pcm_capture_get(snd_kcontrol_t *kcontrol,
2007                                       snd_ctl_elem_value_t *ucontrol)
2008 {
2009         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2010         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2011
2012         if (ins->pcm_input != NULL)
2013                 ucontrol->value.integer.value[0] = 1;
2014         else
2015                 ucontrol->value.integer.value[0] = 0;
2016
2017         return 0;
2018 }
2019
2020
2021 static int snd_cs46xx_pcm_capture_put(snd_kcontrol_t *kcontrol,
2022                                       snd_ctl_elem_value_t *ucontrol)
2023 {
2024         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2025         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2026         int change = 0;
2027
2028         if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2029                 cs46xx_dsp_enable_pcm_capture(chip);
2030                 change = 1;
2031         } else  if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2032                 cs46xx_dsp_disable_pcm_capture(chip);
2033                 change = 1;
2034         }
2035
2036         return change;
2037 }
2038
2039 static int snd_herc_spdif_select_get(snd_kcontrol_t *kcontrol,
2040                                      snd_ctl_elem_value_t *ucontrol)
2041 {
2042         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2043
2044         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2045
2046         if (val1 & EGPIODR_GPOE0)
2047                 ucontrol->value.integer.value[0] = 1;
2048         else
2049                 ucontrol->value.integer.value[0] = 0;
2050
2051         return 0;
2052 }
2053
2054 /*
2055  *      Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2056  */
2057 static int snd_herc_spdif_select_put(snd_kcontrol_t *kcontrol,
2058                                        snd_ctl_elem_value_t *ucontrol)
2059 {
2060         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2061         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2062         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2063
2064         if (ucontrol->value.integer.value[0]) {
2065                 /* optical is default */
2066                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2067                                    EGPIODR_GPOE0 | val1);  /* enable EGPIO0 output */
2068                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2069                                    EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2070         } else {
2071                 /* coaxial */
2072                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE0); /* disable */
2073                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2074         }
2075
2076         /* checking diff from the EGPIO direction register
2077            should be enough */
2078         return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2079 }
2080
2081
2082 static int snd_cs46xx_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2083 {
2084         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2085         uinfo->count = 1;
2086         return 0;
2087 }
2088
2089 static int snd_cs46xx_spdif_default_get(snd_kcontrol_t * kcontrol,
2090                                         snd_ctl_elem_value_t * ucontrol)
2091 {
2092         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2093         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2094
2095         down (&chip->spos_mutex);
2096         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2097         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2098         ucontrol->value.iec958.status[2] = 0;
2099         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2100         up (&chip->spos_mutex);
2101
2102         return 0;
2103 }
2104
2105 static int snd_cs46xx_spdif_default_put(snd_kcontrol_t * kcontrol,
2106                                         snd_ctl_elem_value_t * ucontrol)
2107 {
2108         cs46xx_t * chip = snd_kcontrol_chip(kcontrol);
2109         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2110         unsigned int val;
2111         int change;
2112
2113         down (&chip->spos_mutex);
2114         val = _wrap_all_bits(((u32)ucontrol->value.iec958.status[0] << 24)) |
2115               _wrap_all_bits(((u32)ucontrol->value.iec958.status[2] << 16)) |
2116               _wrap_all_bits( (u32)ucontrol->value.iec958.status[3])  |
2117                 /* left and right validity bit */
2118                 (1 << 13) | (1 << 12);
2119
2120
2121         change = (unsigned int)ins->spdif_csuv_default != val;
2122         ins->spdif_csuv_default = val;
2123
2124         if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2125                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2126
2127         up (&chip->spos_mutex);
2128
2129         return change;
2130 }
2131
2132 static int snd_cs46xx_spdif_mask_get(snd_kcontrol_t * kcontrol,
2133                                      snd_ctl_elem_value_t * ucontrol)
2134 {
2135         ucontrol->value.iec958.status[0] = 0xff;
2136         ucontrol->value.iec958.status[1] = 0xff;
2137         ucontrol->value.iec958.status[2] = 0x00;
2138         ucontrol->value.iec958.status[3] = 0xff;
2139         return 0;
2140 }
2141
2142 static int snd_cs46xx_spdif_stream_get(snd_kcontrol_t * kcontrol,
2143                                          snd_ctl_elem_value_t * ucontrol)
2144 {
2145         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2146         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2147
2148         down (&chip->spos_mutex);
2149         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2150         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2151         ucontrol->value.iec958.status[2] = 0;
2152         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2153         up (&chip->spos_mutex);
2154
2155         return 0;
2156 }
2157
2158 static int snd_cs46xx_spdif_stream_put(snd_kcontrol_t * kcontrol,
2159                                         snd_ctl_elem_value_t * ucontrol)
2160 {
2161         cs46xx_t * chip = snd_kcontrol_chip(kcontrol);
2162         dsp_spos_instance_t * ins = chip->dsp_spos_instance;
2163         unsigned int val;
2164         int change;
2165
2166         down (&chip->spos_mutex);
2167         val = _wrap_all_bits(((u32)ucontrol->value.iec958.status[0] << 24)) |
2168               _wrap_all_bits(((u32)ucontrol->value.iec958.status[1] << 16)) |
2169               _wrap_all_bits( (u32)ucontrol->value.iec958.status[3]) |
2170                 /* left and right validity bit */
2171                 (1 << 13) | (1 << 12);
2172
2173
2174         change = ins->spdif_csuv_stream != val;
2175         ins->spdif_csuv_stream = val;
2176
2177         if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2178                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2179
2180         up (&chip->spos_mutex);
2181
2182         return change;
2183 }
2184
2185 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2186
2187
2188 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2189 static int snd_cs46xx_egpio_select_info(snd_kcontrol_t *kcontrol,
2190                                         snd_ctl_elem_info_t *uinfo)
2191 {
2192         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2193         uinfo->count = 1;
2194         uinfo->value.integer.min = 0;
2195         uinfo->value.integer.max = 8;
2196         return 0;
2197 }
2198
2199 static int snd_cs46xx_egpio_select_get(snd_kcontrol_t *kcontrol,
2200                                        snd_ctl_elem_value_t *ucontrol)
2201 {
2202         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2203         ucontrol->value.integer.value[0] = chip->current_gpio;
2204
2205         return 0;
2206 }
2207
2208 static int snd_cs46xx_egpio_select_put(snd_kcontrol_t *kcontrol,
2209                                        snd_ctl_elem_value_t *ucontrol)
2210 {
2211         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2212         int change = (chip->current_gpio != ucontrol->value.integer.value[0]);
2213         chip->current_gpio = ucontrol->value.integer.value[0];
2214
2215         return change;
2216 }
2217
2218
2219 static int snd_cs46xx_egpio_get(snd_kcontrol_t *kcontrol,
2220                                        snd_ctl_elem_value_t *ucontrol)
2221 {
2222         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2223         int reg = kcontrol->private_value;
2224
2225         snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2226         ucontrol->value.integer.value[0] =
2227                 (snd_cs46xx_peekBA0(chip, reg) & (1 << chip->current_gpio)) ? 1 : 0;
2228
2229         return 0;
2230 }
2231
2232 static int snd_cs46xx_egpio_put(snd_kcontrol_t *kcontrol,
2233                                        snd_ctl_elem_value_t *ucontrol)
2234 {
2235         cs46xx_t *chip = snd_kcontrol_chip(kcontrol);
2236         int reg = kcontrol->private_value;
2237         int val = snd_cs46xx_peekBA0(chip, reg);
2238         int oldval = val;
2239         snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2240
2241         if (ucontrol->value.integer.value[0])
2242                 val |= (1 << chip->current_gpio);
2243         else
2244                 val &= ~(1 << chip->current_gpio);
2245
2246         snd_cs46xx_pokeBA0(chip, reg,val);
2247         snd_printdd ("put: val %08x oldval %08x\n",val,oldval);
2248
2249         return (oldval != val);
2250 }
2251 #endif /* CONFIG_SND_CS46XX_DEBUG_GPIO */
2252
2253 static snd_kcontrol_new_t snd_cs46xx_controls[] __devinitdata = {
2254 {
2255         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2256         .name = "DAC Volume",
2257         .info = snd_cs46xx_vol_info,
2258 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2259         .get = snd_cs46xx_vol_get,
2260         .put = snd_cs46xx_vol_put,
2261         .private_value = BA1_PVOL,
2262 #else
2263         .get = snd_cs46xx_vol_dac_get,
2264         .put = snd_cs46xx_vol_dac_put,
2265 #endif
2266 },
2267
2268 {
2269         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2270         .name = "ADC Volume",
2271         .info = snd_cs46xx_vol_info,
2272         .get = snd_cs46xx_vol_get,
2273         .put = snd_cs46xx_vol_put,
2274 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2275         .private_value = BA1_CVOL,
2276 #else
2277         .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2278 #endif
2279 },
2280 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2281 {
2282         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2283         .name = "ADC Capture Switch",
2284         .info = snd_mixer_boolean_info,
2285         .get = snd_cs46xx_adc_capture_get,
2286         .put = snd_cs46xx_adc_capture_put
2287 },
2288 {
2289         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2290         .name = "DAC Capture Switch",
2291         .info = snd_mixer_boolean_info,
2292         .get = snd_cs46xx_pcm_capture_get,
2293         .put = snd_cs46xx_pcm_capture_put
2294 },
2295 {
2296         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2297         .name = "IEC958 Output Switch",
2298         .info = snd_mixer_boolean_info,
2299         .get = snd_cs46xx_iec958_get,
2300         .put = snd_cs46xx_iec958_put,
2301         .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2302 },
2303 {
2304         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2305         .name = "IEC958 Input Switch",
2306         .info = snd_mixer_boolean_info,
2307         .get = snd_cs46xx_iec958_get,
2308         .put = snd_cs46xx_iec958_put,
2309         .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2310 },
2311 #if 0
2312 /* Input IEC958 volume does not work for the moment. (Benny) */
2313 {
2314         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2315         .name = "IEC958 Input Volume",
2316         .info = snd_cs46xx_vol_info,
2317         .get = snd_cs46xx_vol_iec958_get,
2318         .put = snd_cs46xx_vol_iec958_put,
2319         .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2320 },
2321 #endif
2322 {
2323         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2324         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2325         .info =  snd_cs46xx_spdif_info,
2326         .get =   snd_cs46xx_spdif_default_get,
2327         .put =   snd_cs46xx_spdif_default_put,
2328 },
2329 {
2330         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2331         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2332         .info =  snd_cs46xx_spdif_info,
2333         .get =   snd_cs46xx_spdif_mask_get,
2334         .access = SNDRV_CTL_ELEM_ACCESS_READ
2335 },
2336 {
2337         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2338         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2339         .info =  snd_cs46xx_spdif_info,
2340         .get =   snd_cs46xx_spdif_stream_get,
2341         .put =   snd_cs46xx_spdif_stream_put
2342 },
2343
2344 #endif
2345 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2346 {
2347         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2348         .name = "EGPIO select",
2349         .info = snd_cs46xx_egpio_select_info,
2350         .get = snd_cs46xx_egpio_select_get,
2351         .put = snd_cs46xx_egpio_select_put,
2352         .private_value = 0,
2353 },
2354 {
2355         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2356         .name = "EGPIO Input/Output",
2357         .info = snd_mixer_boolean_info,
2358         .get = snd_cs46xx_egpio_get,
2359         .put = snd_cs46xx_egpio_put,
2360         .private_value = BA0_EGPIODR,
2361 },
2362 {
2363         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2364         .name = "EGPIO CMOS/Open drain",
2365         .info = snd_mixer_boolean_info,
2366         .get = snd_cs46xx_egpio_get,
2367         .put = snd_cs46xx_egpio_put,
2368         .private_value = BA0_EGPIOPTR,
2369 },
2370 {
2371         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2372         .name = "EGPIO On/Off",
2373         .info = snd_mixer_boolean_info,
2374         .get = snd_cs46xx_egpio_get,
2375         .put = snd_cs46xx_egpio_put,
2376         .private_value = BA0_EGPIOSR,
2377 },
2378 #endif
2379 };
2380
2381 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2382 /* Only available on the Hercules Game Theater XP soundcard */
2383 static snd_kcontrol_new_t snd_hercules_controls[] __devinitdata = {
2384 {
2385         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2386         .name = "Optical/Coaxial SPDIF Input Switch",
2387         .info = snd_mixer_boolean_info,
2388         .get = snd_herc_spdif_select_get,
2389         .put = snd_herc_spdif_select_put,
2390 },
2391 };
2392
2393
2394 static void snd_cs46xx_codec_reset (ac97_t * ac97)
2395 {
2396         unsigned long end_time;
2397         int err;
2398         cs46xx_t * chip = snd_magic_cast(cs46xx_t,ac97->private_data,return /* -ENXIO */);
2399
2400         /* reset to defaults */
2401         snd_ac97_write(ac97, AC97_RESET, 0);
2402
2403         /* set the desired CODEC mode */
2404         if (chip->nr_ac97_codecs == 0) {
2405                 snd_printdd("cs46xx: CODOEC1 mode %04x\n",0x0);
2406                 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x0);
2407         } else if (chip->nr_ac97_codecs == 1) {
2408                 snd_printdd("cs46xx: CODOEC2 mode %04x\n",0x3);
2409                 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x3);
2410         } else {
2411                 snd_assert(0); /* should never happen ... */
2412         }
2413
2414         udelay(50);
2415
2416         /* it's necessary to wait awhile until registers are accessible after RESET */
2417         /* because the PCM or MASTER volume registers can be modified, */
2418         /* the REC_GAIN register is used for tests */
2419         end_time = jiffies + HZ;
2420         do {
2421                 unsigned short ext_mid;
2422
2423                 /* use preliminary reads to settle the communication */
2424                 snd_ac97_read(ac97, AC97_RESET);
2425                 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2426                 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2427                 /* modem? */
2428                 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2429                 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2430                         return;
2431
2432                 /* test if we can write to the record gain volume register */
2433                 snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x8a05);
2434                 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2435                         return;
2436
2437                 set_current_state(TASK_UNINTERRUPTIBLE);
2438                 schedule_timeout(HZ/100);
2439         } while (time_after_eq(end_time, jiffies));
2440
2441         snd_printk("CS46xx secondary codec dont respond!\n");
2442 }
2443 #endif
2444
2445 int __devinit snd_cs46xx_mixer(cs46xx_t *chip)
2446 {
2447         snd_card_t *card = chip->card;
2448         ac97_t ac97;
2449         snd_ctl_elem_id_t id;
2450         int err;
2451         unsigned int idx;
2452
2453         /* detect primary codec */
2454         chip->nr_ac97_codecs = 0;
2455         snd_printdd("snd_cs46xx: detecting primary codec\n");
2456         memset(&ac97, 0, sizeof(ac97));
2457         ac97.write = snd_cs46xx_ac97_write;
2458         ac97.read = snd_cs46xx_ac97_read;
2459         ac97.private_data = chip;
2460         ac97.private_free = snd_cs46xx_mixer_free_ac97;
2461 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2462         ac97.reset = snd_cs46xx_codec_reset;
2463 #endif
2464         chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = &ac97;
2465
2466         snd_cs46xx_ac97_write(&ac97, AC97_MASTER, 0x8000);
2467         for (idx = 0; idx < 100; ++idx) {
2468                 if (snd_cs46xx_ac97_read(&ac97, AC97_MASTER) == 0x8000)
2469                         goto _ok;
2470                 set_current_state(TASK_INTERRUPTIBLE);
2471                 schedule_timeout(HZ/100);
2472         }
2473         chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
2474         return -ENXIO;
2475
2476  _ok:
2477         if ((err = snd_ac97_mixer(card, &ac97, &chip->ac97[CS46XX_PRIMARY_CODEC_INDEX])) < 0)
2478                 return err;
2479         snd_printdd("snd_cs46xx: primary codec phase one\n");
2480         chip->nr_ac97_codecs = 1;
2481
2482 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2483         snd_printdd("snd_cs46xx: detecting seconadry codec\n");
2484         /* try detect a secondary codec */
2485         memset(&ac97, 0, sizeof(ac97));
2486         ac97.write = snd_cs46xx_ac97_write;
2487         ac97.read = snd_cs46xx_ac97_read;
2488         ac97.private_data = chip;
2489         ac97.private_free = snd_cs46xx_mixer_free_ac97;
2490         ac97.num = CS46XX_SECONDARY_CODEC_INDEX;
2491
2492         snd_cs46xx_ac97_write(&ac97, AC97_RESET, 0);
2493         udelay(10);
2494
2495         if (snd_cs46xx_ac97_read(&ac97, AC97_RESET) & 0x8000) {
2496                 snd_printdd("snd_cs46xx: seconadry codec not present\n");
2497                 goto _no_sec_codec;
2498         }
2499
2500         chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = &ac97;
2501         snd_cs46xx_ac97_write(&ac97, AC97_MASTER, 0x8000);
2502         for (idx = 0; idx < 100; ++idx) {
2503                 if (snd_cs46xx_ac97_read(&ac97, AC97_MASTER) == 0x8000) {
2504                         goto _ok2;
2505                 }
2506                 set_current_state(TASK_INTERRUPTIBLE);
2507                 schedule_timeout(HZ/100);
2508         }
2509
2510  _no_sec_codec:
2511         snd_printdd("snd_cs46xx: secondary codec did not respond ...\n");
2512
2513         chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
2514         chip->nr_ac97_codecs = 1;
2515
2516         /* well, one codec only ... */
2517         goto _end;
2518  _ok2:
2519         /* set secondary codec in extended mode */
2520
2521         /* use custom reset to set secondary codec in
2522            extended mode */
2523         ac97.reset = snd_cs46xx_codec_reset;
2524
2525         if ((err = snd_ac97_mixer(card, &ac97, &chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])) < 0)
2526                 return err;
2527         chip->nr_ac97_codecs = 2;
2528
2529  _end:
2530
2531 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2532
2533         /* add cs4630 mixer controls */
2534         for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2535                 snd_kcontrol_t *kctl;
2536                 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2537                 if ((err = snd_ctl_add(card, kctl)) < 0)
2538                         return err;
2539         }
2540
2541         /* get EAPD mixer switch (for voyetra hack) */
2542         memset(&id, 0, sizeof(id));
2543         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2544         strcpy(id.name, "External Amplifier Power Down");
2545         chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2546
2547 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2548         if (chip->nr_ac97_codecs == 1 &&
2549             snd_cs46xx_codec_read(chip, AC97_VENDOR_ID2,
2550                                   CS46XX_PRIMARY_CODEC_INDEX) == 0x592d) {
2551                 /* set primary cs4294 codec into Extended Audio Mode */
2552                 snd_printdd("setting EAM bit on cs4294 CODEC\n");
2553                 snd_cs46xx_codec_write(chip, AC97_CSR_ACMODE, 0x200,
2554                                        CS46XX_PRIMARY_CODEC_INDEX);
2555         }
2556         /* do soundcard specific mixer setup */
2557         if (chip->mixer_init) {
2558                 snd_printdd ("calling chip->mixer_init(chip);\n");
2559                 chip->mixer_init(chip);
2560         }
2561 #endif
2562
2563         /* turn on amplifier */
2564         chip->amplifier_ctrl(chip, 1);
2565
2566         return 0;
2567 }
2568
2569 /*
2570  *  RawMIDI interface
2571  */
2572
2573 static void snd_cs46xx_midi_reset(cs46xx_t *chip)
2574 {
2575         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2576         udelay(100);
2577         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2578 }
2579
2580 static int snd_cs46xx_midi_input_open(snd_rawmidi_substream_t * substream)
2581 {
2582         unsigned long flags;
2583         cs46xx_t *chip = snd_magic_cast(cs46xx_t, substream->rmidi->private_data, return -ENXIO);
2584
2585         chip->active_ctrl(chip, 1);
2586         spin_lock_irqsave(&chip->reg_lock, flags);
2587         chip->uartm |= CS46XX_MODE_INPUT;
2588         chip->midcr |= MIDCR_RXE;
2589         chip->midi_input = substream;
2590         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2591                 snd_cs46xx_midi_reset(chip);
2592         } else {
2593                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2594         }
2595         spin_unlock_irqrestore(&chip->reg_lock, flags);
2596         return 0;
2597 }
2598
2599 static int snd_cs46xx_midi_input_close(snd_rawmidi_substream_t * substream)
2600 {
2601         unsigned long flags;
2602         cs46xx_t *chip = snd_magic_cast(cs46xx_t, substream->rmidi->private_data, return -ENXIO);
2603
2604         spin_lock_irqsave(&chip->reg_lock, flags);
2605         chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2606         chip->midi_input = NULL;
2607         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2608                 snd_cs46xx_midi_reset(chip);
2609         } else {
2610                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2611         }
2612         chip->uartm &= ~CS46XX_MODE_INPUT;
2613         spin_unlock_irqrestore(&chip->reg_lock, flags);
2614         chip->active_ctrl(chip, -1);
2615         return 0;
2616 }
2617
2618 static int snd_cs46xx_midi_output_open(snd_rawmidi_substream_t * substream)
2619 {
2620         unsigned long flags;
2621         cs46xx_t *chip = snd_magic_cast(cs46xx_t, substream->rmidi->private_data, return -ENXIO);
2622
2623         chip->active_ctrl(chip, 1);
2624
2625         spin_lock_irqsave(&chip->reg_lock, flags);
2626         chip->uartm |= CS46XX_MODE_OUTPUT;
2627         chip->midcr |= MIDCR_TXE;
2628         chip->midi_output = substream;
2629         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2630                 snd_cs46xx_midi_reset(chip);
2631         } else {
2632                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2633         }
2634         spin_unlock_irqrestore(&chip->reg_lock, flags);
2635         return 0;
2636 }
2637
2638 static int snd_cs46xx_midi_output_close(snd_rawmidi_substream_t * substream)
2639 {
2640         unsigned long flags;
2641         cs46xx_t *chip = snd_magic_cast(cs46xx_t, substream->rmidi->private_data, return -ENXIO);
2642
2643         spin_lock_irqsave(&chip->reg_lock, flags);
2644         chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2645         chip->midi_output = NULL;
2646         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2647                 snd_cs46xx_midi_reset(chip);
2648         } else {
2649                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2650         }
2651         chip->uartm &= ~CS46XX_MODE_OUTPUT;
2652         spin_unlock_irqrestore(&chip->reg_lock, flags);
2653         chip->active_ctrl(chip, -1);
2654         return 0;
2655 }
2656
2657 static void snd_cs46xx_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2658 {
2659         unsigned long flags;
2660         cs46xx_t *chip = snd_magic_cast(cs46xx_t, substream->rmidi->private_data, return);
2661
2662         spin_lock_irqsave(&chip->reg_lock, flags);
2663         if (up) {
2664                 if ((chip->midcr & MIDCR_RIE) == 0) {
2665                         chip->midcr |= MIDCR_RIE;
2666                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2667                 }
2668         } else {
2669                 if (chip->midcr & MIDCR_RIE) {
2670                         chip->midcr &= ~MIDCR_RIE;
2671                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2672                 }
2673         }
2674         spin_unlock_irqrestore(&chip->reg_lock, flags);
2675 }
2676
2677 static void snd_cs46xx_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2678 {
2679         unsigned long flags;
2680         cs46xx_t *chip = snd_magic_cast(cs46xx_t, substream->rmidi->private_data, return);
2681         unsigned char byte;
2682
2683         spin_lock_irqsave(&chip->reg_lock, flags);
2684         if (up) {
2685                 if ((chip->midcr & MIDCR_TIE) == 0) {
2686                         chip->midcr |= MIDCR_TIE;
2687                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2688                         while ((chip->midcr & MIDCR_TIE) &&
2689                                (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2690                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2691                                         chip->midcr &= ~MIDCR_TIE;
2692                                 } else {
2693                                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2694                                 }
2695                         }
2696                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2697                 }
2698         } else {
2699                 if (chip->midcr & MIDCR_TIE) {
2700                         chip->midcr &= ~MIDCR_TIE;
2701                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2702                 }
2703         }
2704         spin_unlock_irqrestore(&chip->reg_lock, flags);
2705 }
2706
2707 static snd_rawmidi_ops_t snd_cs46xx_midi_output =
2708 {
2709         .open =         snd_cs46xx_midi_output_open,
2710         .close =        snd_cs46xx_midi_output_close,
2711         .trigger =      snd_cs46xx_midi_output_trigger,
2712 };
2713
2714 static snd_rawmidi_ops_t snd_cs46xx_midi_input =
2715 {
2716         .open =         snd_cs46xx_midi_input_open,
2717         .close =        snd_cs46xx_midi_input_close,
2718         .trigger =      snd_cs46xx_midi_input_trigger,
2719 };
2720
2721 int __devinit snd_cs46xx_midi(cs46xx_t *chip, int device, snd_rawmidi_t **rrawmidi)
2722 {
2723         snd_rawmidi_t *rmidi;
2724         int err;
2725
2726         if (rrawmidi)
2727                 *rrawmidi = NULL;
2728         if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2729                 return err;
2730         strcpy(rmidi->name, "CS46XX");
2731         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2732         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2733         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2734         rmidi->private_data = chip;
2735         chip->rmidi = rmidi;
2736         if (rrawmidi)
2737                 *rrawmidi = NULL;
2738         return 0;
2739 }
2740
2741
2742 /*
2743  * gameport interface
2744  */
2745
2746 #if defined(CONFIG_GAMEPORT) || defined(CONFIG_GAMEPORT_MODULE)
2747
2748 typedef struct snd_cs46xx_gameport {
2749         struct gameport info;
2750         cs46xx_t *chip;
2751 } cs46xx_gameport_t;
2752
2753 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2754 {
2755         cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2756         cs46xx_t *chip;
2757         snd_assert(gp, return);
2758         chip = snd_magic_cast(cs46xx_t, gp->chip, return);
2759         snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF);  //outb(gameport->io, 0xFF);
2760 }
2761
2762 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2763 {
2764         cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2765         cs46xx_t *chip;
2766         snd_assert(gp, return 0);
2767         chip = snd_magic_cast(cs46xx_t, gp->chip, return 0);
2768         return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2769 }
2770
2771 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2772 {
2773         cs46xx_gameport_t *gp = (cs46xx_gameport_t *)gameport;
2774         cs46xx_t *chip;
2775         unsigned js1, js2, jst;
2776
2777         snd_assert(gp, return 0);
2778         chip = snd_magic_cast(cs46xx_t, gp->chip, return 0);
2779
2780         js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2781         js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2782         jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2783
2784         *buttons = (~jst >> 4) & 0x0F;
2785
2786         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2787         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2788         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2789         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2790
2791         for(jst=0;jst<4;++jst)
2792                 if(axes[jst]==0xFFFF) axes[jst] = -1;
2793         return 0;
2794 }
2795
2796 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2797 {
2798         switch (mode) {
2799         case GAMEPORT_MODE_COOKED:
2800                 return 0;
2801         case GAMEPORT_MODE_RAW:
2802                 return 0;
2803         default:
2804                 return -1;
2805         }
2806         return 0;
2807 }
2808
2809 void __devinit snd_cs46xx_gameport(cs46xx_t *chip)
2810 {
2811         cs46xx_gameport_t *gp;
2812         gp = kmalloc(sizeof(*gp), GFP_KERNEL);
2813         if (! gp) {
2814                 snd_printk("cannot allocate gameport area\n");
2815                 return;
2816         }
2817         memset(gp, 0, sizeof(*gp));
2818         gp->info.open = snd_cs46xx_gameport_open;
2819         gp->info.read = snd_cs46xx_gameport_read;
2820         gp->info.trigger = snd_cs46xx_gameport_trigger;
2821         gp->info.cooked_read = snd_cs46xx_gameport_cooked_read;
2822         gp->chip = chip;
2823         chip->gameport = gp;
2824
2825         snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2826         snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2827         gameport_register_port(&gp->info);
2828 }
2829
2830 #else
2831
2832 void __devinit snd_cs46xx_gameport(cs46xx_t *chip)
2833 {
2834 }
2835
2836 #endif /* CONFIG_GAMEPORT */
2837
2838 /*
2839  *  proc interface
2840  */
2841
2842 static long snd_cs46xx_io_read(snd_info_entry_t *entry, void *file_private_data,
2843                                struct file *file, char *buf, long count)
2844 {
2845         long size;
2846         snd_cs46xx_region_t *region = (snd_cs46xx_region_t *)entry->private_data;
2847
2848         size = count;
2849         if (file->f_pos + (size_t)size > region->size)
2850                 size = region->size - file->f_pos;
2851         if (size > 0) {
2852                 char *tmp;
2853                 long res;
2854                 unsigned long virt;
2855                 if ((tmp = kmalloc(size, GFP_KERNEL)) == NULL)
2856                         return -ENOMEM;
2857                 virt = region->remap_addr + file->f_pos;
2858                 memcpy_fromio(tmp, virt, size);
2859                 if (copy_to_user(buf, tmp, size))
2860                         res = -EFAULT;
2861                 else {
2862                         res = size;
2863                         file->f_pos += size;
2864                 }
2865                 kfree(tmp);
2866                 return res;
2867         }
2868         return 0;
2869 }
2870
2871 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2872         .read = snd_cs46xx_io_read,
2873 };
2874
2875 static int __devinit snd_cs46xx_proc_init(snd_card_t * card, cs46xx_t *chip)
2876 {
2877         snd_info_entry_t *entry;
2878         int idx;
2879
2880         for (idx = 0; idx < 5; idx++) {
2881                 snd_cs46xx_region_t *region = &chip->region.idx[idx];
2882                 if (! snd_card_proc_new(card, region->name, &entry)) {
2883                         entry->content = SNDRV_INFO_CONTENT_DATA;
2884                         entry->private_data = chip;
2885                         entry->c.ops = &snd_cs46xx_proc_io_ops;
2886                         entry->size = region->size;
2887                         entry->mode = S_IFREG | S_IRUSR;
2888                 }
2889         }
2890 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2891         cs46xx_dsp_proc_init(card, chip);
2892 #endif
2893         return 0;
2894 }
2895
2896 static int snd_cs46xx_proc_done(cs46xx_t *chip)
2897 {
2898 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2899         cs46xx_dsp_proc_done(chip);
2900 #endif
2901         return 0;
2902 }
2903
2904 /*
2905  * stop the h/w
2906  */
2907 static void snd_cs46xx_hw_stop(cs46xx_t *chip)
2908 {
2909         unsigned int tmp;
2910
2911         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2912         tmp &= ~0x0000f03f;
2913         tmp |=  0x00000010;
2914         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt disable */
2915
2916         tmp = snd_cs46xx_peek(chip, BA1_CIE);
2917         tmp &= ~0x0000003f;
2918         tmp |=  0x00000011;
2919         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt disable */
2920
2921         /*
2922          *  Stop playback DMA.
2923          */
2924         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2925         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2926
2927         /*
2928          *  Stop capture DMA.
2929          */
2930         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2931         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2932
2933         /*
2934          *  Reset the processor.
2935          */
2936         snd_cs46xx_reset(chip);
2937
2938         snd_cs46xx_proc_stop(chip);
2939
2940         /*
2941          *  Power down the PLL.
2942          */
2943         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2944
2945         /*
2946          *  Turn off the Processor by turning off the software clock enable flag in
2947          *  the clock control register.
2948          */
2949         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2950         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2951 }
2952
2953
2954 static int snd_cs46xx_free(cs46xx_t *chip)
2955 {
2956         int idx;
2957
2958         snd_assert(chip != NULL, return -EINVAL);
2959
2960         if (chip->active_ctrl)
2961                 chip->active_ctrl(chip, 1);
2962
2963 #if defined(CONFIG_GAMEPORT) || defined(CONFIG_GAMEPORT_MODULE)
2964         if (chip->gameport) {
2965                 gameport_unregister_port(&chip->gameport->info);
2966                 kfree(chip->gameport);
2967         }
2968 #endif
2969
2970         if (chip->amplifier_ctrl)
2971                 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2972
2973         snd_cs46xx_proc_done(chip);
2974
2975         if (chip->region.idx[0].resource)
2976                 snd_cs46xx_hw_stop(chip);
2977
2978         for (idx = 0; idx < 5; idx++) {
2979                 snd_cs46xx_region_t *region = &chip->region.idx[idx];
2980                 if (region->remap_addr)
2981                         iounmap((void *) region->remap_addr);
2982                 if (region->resource) {
2983                         release_resource(region->resource);
2984                         kfree_nocheck(region->resource);
2985                 }
2986         }
2987         if (chip->irq >= 0)
2988                 free_irq(chip->irq, (void *)chip);
2989
2990         if (chip->active_ctrl)
2991                 chip->active_ctrl(chip, -chip->amplifier);
2992
2993 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2994         if (chip->dsp_spos_instance) {
2995                 cs46xx_dsp_spos_destroy(chip);
2996                 chip->dsp_spos_instance = NULL;
2997         }
2998 #endif
2999
3000         snd_magic_kfree(chip);
3001         return 0;
3002 }
3003
3004 static int snd_cs46xx_dev_free(snd_device_t *device)
3005 {
3006         cs46xx_t *chip = snd_magic_cast(cs46xx_t, device->device_data, return -ENXIO);
3007         return snd_cs46xx_free(chip);
3008 }
3009
3010 /*
3011  *  initialize chip
3012  */
3013 static int snd_cs46xx_chip_init(cs46xx_t *chip, int busywait)
3014 {
3015         int timeout;
3016
3017         /*
3018          *  First, blast the clock control register to zero so that the PLL starts
3019          *  out in a known state, and blast the master serial port control register
3020          *  to zero so that the serial ports also start out in a known state.
3021          */
3022         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
3023         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
3024
3025         /*
3026          *  If we are in AC97 mode, then we must set the part to a host controlled
3027          *  AC-link.  Otherwise, we won't be able to bring up the link.
3028          */
3029 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3030         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
3031                            SERACC_TWO_CODECS);  /* 2.00 dual codecs */
3032         /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
3033 #else
3034         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
3035 #endif
3036
3037         /*
3038          *  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
3039          *  spec) and then drive it high.  This is done for non AC97 modes since
3040          *  there might be logic external to the CS461x that uses the ARST# line
3041          *  for a reset.
3042          */
3043         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
3044 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3045         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
3046 #endif
3047         udelay(50);
3048         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
3049 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3050         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
3051 #endif
3052
3053         /*
3054          *  The first thing we do here is to enable sync generation.  As soon
3055          *  as we start receiving bit clock, we'll start producing the SYNC
3056          *  signal.
3057          */
3058         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
3059 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3060         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
3061 #endif
3062
3063         /*
3064          *  Now wait for a short while to allow the AC97 part to start
3065          *  generating bit clock (so we don't try to start the PLL without an
3066          *  input clock).
3067          */
3068         mdelay(10);
3069
3070         /*
3071          *  Set the serial port timing configuration, so that
3072          *  the clock control circuit gets its clock from the correct place.
3073          */
3074         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
3075
3076         /*
3077          *  Write the selected clock control setup to the hardware.  Do not turn on
3078          *  SWCE yet (if requested), so that the devices clocked by the output of
3079          *  PLL are not clocked until the PLL is stable.
3080          */
3081         snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3082         snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3083         snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3084
3085         /*
3086          *  Power up the PLL.
3087          */
3088         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3089
3090         /*
3091          *  Wait until the PLL has stabilized.
3092          */
3093         mdelay(100); /* FIXME: schedule? */
3094
3095         /*
3096          *  Turn on clocking of the core so that we can setup the serial ports.
3097          */
3098         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3099
3100         /*
3101          * Enable FIFO  Host Bypass
3102          */
3103         snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3104
3105         /*
3106          *  Fill the serial port FIFOs with silence.
3107          */
3108         snd_cs46xx_clear_serial_FIFOs(chip);
3109
3110         /*
3111          *  Set the serial port FIFO pointer to the first sample in the FIFO.
3112          */
3113         /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3114
3115         /*
3116          *  Write the serial port configuration to the part.  The master
3117          *  enable bit is not set until all other values have been written.
3118          */
3119         snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3120         snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3121         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3122
3123
3124 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3125         snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3126         snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3127         snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3128         snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3129         snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3130 #endif
3131
3132         mdelay(5);
3133
3134
3135         /*
3136          * Wait for the codec ready signal from the AC97 codec.
3137          */
3138         timeout = 150;
3139         while (timeout-- > 0) {
3140                 /*
3141                  *  Read the AC97 status register to see if we've seen a CODEC READY
3142                  *  signal from the AC97 codec.
3143                  */
3144                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3145                         goto ok1;
3146                 if (busywait)
3147                         mdelay(10);
3148                 else {
3149                         set_current_state(TASK_UNINTERRUPTIBLE);
3150                         schedule_timeout((HZ+99)/100);
3151                 }
3152         }
3153
3154
3155         snd_printk("create - never read codec ready from AC'97\n");
3156         snd_printk("it is not probably bug, try to use CS4236 driver\n");
3157         return -EIO;
3158  ok1:
3159 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3160         {
3161                 int count;
3162                 for (count = 0; count < 150; count++) {
3163                         /* First, we want to wait for a short time. */
3164                         udelay(25);
3165
3166                         if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3167                                 break;
3168                 }
3169
3170                 /*
3171                  *  Make sure CODEC is READY.
3172                  */
3173                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3174                         snd_printdd("cs46xx: never read card ready from secondary AC'97\n");
3175         }
3176 #endif
3177
3178         /*
3179          *  Assert the vaid frame signal so that we can start sending commands
3180          *  to the AC97 codec.
3181          */
3182         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3183 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3184         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3185 #endif
3186
3187
3188         /*
3189          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
3190          *  the codec is pumping ADC data across the AC-link.
3191          */
3192         timeout = 150;
3193         while (timeout-- > 0) {
3194                 /*
3195                  *  Read the input slot valid register and see if input slots 3 and
3196                  *  4 are valid yet.
3197                  */
3198                 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3199                         goto ok2;
3200                 if (busywait)
3201                         mdelay(10);
3202                 else {
3203                         set_current_state(TASK_UNINTERRUPTIBLE);
3204                         schedule_timeout((HZ+99)/100);
3205                 }
3206         }
3207
3208 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3209         snd_printk("create - never read ISV3 & ISV4 from AC'97\n");
3210         return -EIO;
3211 #else
3212         /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3213            Reloading the driver may help, if there's other soundcards
3214            with the same problem I would like to know. (Benny) */
3215
3216         snd_printk("ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n");
3217         snd_printk("       Try reloading the ALSA driver, if you find something\n");
3218         snd_printk("       broken or not working on your soundcard upon\n");
3219         snd_printk("       this message please report to alsa-devel@lists.sourceforge.net\n");
3220
3221         return -EIO;
3222 #endif
3223  ok2:
3224
3225         /*
3226          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
3227          *  commense the transfer of digital audio data to the AC97 codec.
3228          */
3229
3230         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3231
3232
3233         /*
3234          *  Power down the DAC and ADC.  We will power them up (if) when we need
3235          *  them.
3236          */
3237         /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3238
3239         /*
3240          *  Turn off the Processor by turning off the software clock enable flag in
3241          *  the clock control register.
3242          */
3243         /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3244         /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3245
3246         return 0;
3247 }
3248
3249 /*
3250  *  start and load DSP
3251  */
3252 int __devinit snd_cs46xx_start_dsp(cs46xx_t *chip)
3253 {
3254         unsigned int tmp;
3255         /*
3256          *  Reset the processor.
3257          */
3258         snd_cs46xx_reset(chip);
3259         /*
3260          *  Download the image to the processor.
3261          */
3262 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3263 #if 0
3264         if (cs46xx_dsp_load_module(chip, &cwcemb80_module) < 0) {
3265                 snd_printk(KERN_ERR "image download error\n");
3266                 return -EIO;
3267         }
3268 #endif
3269
3270         if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) {
3271                 snd_printk(KERN_ERR "image download error [cwc4630]\n");
3272                 return -EIO;
3273         }
3274
3275         if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) {
3276                 snd_printk(KERN_ERR "image download error [cwcasync]\n");
3277                 return -EIO;
3278         }
3279
3280         if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) {
3281                 snd_printk(KERN_ERR "image download error [cwcsnoop]\n");
3282                 return -EIO;
3283         }
3284
3285         if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) {
3286                 snd_printk(KERN_ERR "image download error [cwcbinhack]\n");
3287                 return -EIO;
3288         }
3289
3290         if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) {
3291                 snd_printk(KERN_ERR "image download error [cwcdma]\n");
3292                 return -EIO;
3293         }
3294
3295         if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3296                 return -EIO;
3297 #else
3298         /* old image */
3299         if (snd_cs46xx_download_image(chip) < 0) {
3300                 snd_printk("image download error\n");
3301                 return -EIO;
3302         }
3303
3304         /*
3305          *  Stop playback DMA.
3306          */
3307         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3308         chip->play_ctl = tmp & 0xffff0000;
3309         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3310 #endif
3311
3312         /*
3313          *  Stop capture DMA.
3314          */
3315         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3316         chip->capt.ctl = tmp & 0x0000ffff;
3317         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3318
3319         mdelay(5);
3320
3321         snd_cs46xx_set_play_sample_rate(chip, 8000);
3322         snd_cs46xx_set_capture_sample_rate(chip, 8000);
3323
3324         snd_cs46xx_proc_start(chip);
3325
3326         /*
3327          *  Enable interrupts on the part.
3328          */
3329         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3330
3331         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3332         tmp &= ~0x0000f03f;
3333         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt enable */
3334
3335         tmp = snd_cs46xx_peek(chip, BA1_CIE);
3336         tmp &= ~0x0000003f;
3337         tmp |=  0x00000001;
3338         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt enable */
3339
3340 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3341         /* set the attenuation to 0dB */
3342         snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3343         snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3344 #endif
3345
3346         return 0;
3347 }
3348
3349
3350 /*
3351  *      AMP control - null AMP
3352  */
3353
3354 static void amp_none(cs46xx_t *chip, int change)
3355 {
3356 }
3357
3358 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3359 static int voyetra_setup_eapd_slot(cs46xx_t *chip)
3360 {
3361
3362         u32 idx, valid_slots,tmp,powerdown = 0;
3363         u16 modem_power,pin_config,logic_type;
3364
3365         snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n");
3366
3367         /*
3368          *  See if the devices are powered down.  If so, we must power them up first
3369          *  or they will not respond.
3370          */
3371         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3372
3373         if (!(tmp & CLKCR1_SWCE)) {
3374                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3375                 powerdown = 1;
3376         }
3377
3378         /*
3379          * Clear PRA.  The Bonzo chip will be used for GPIO not for modem
3380          * stuff.
3381          */
3382         if(chip->nr_ac97_codecs != 2) {
3383                 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3384                 return -EINVAL;
3385         }
3386
3387         modem_power = snd_cs46xx_codec_read (chip,
3388                                              AC97_EXTENDED_MSTATUS,
3389                                              CS46XX_SECONDARY_CODEC_INDEX);
3390         modem_power &=0xFEFF;
3391
3392         snd_cs46xx_codec_write(chip,
3393                                AC97_EXTENDED_MSTATUS, modem_power,
3394                                CS46XX_SECONDARY_CODEC_INDEX);
3395
3396         /*
3397          * Set GPIO pin's 7 and 8 so that they are configured for output.
3398          */
3399         pin_config = snd_cs46xx_codec_read (chip,
3400                                             AC97_GPIO_CFG,
3401                                             CS46XX_SECONDARY_CODEC_INDEX);
3402         pin_config &=0x27F;
3403
3404         snd_cs46xx_codec_write(chip,
3405                                AC97_GPIO_CFG, pin_config,
3406                                CS46XX_SECONDARY_CODEC_INDEX);
3407
3408         /*
3409          * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3410          */
3411
3412         logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3413                                            CS46XX_SECONDARY_CODEC_INDEX);
3414         logic_type &=0x27F;
3415
3416         snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3417                                 CS46XX_SECONDARY_CODEC_INDEX);
3418
3419         valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3420         valid_slots |= 0x200;
3421         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3422
3423         if ( cs46xx_wait_for_fifo(chip,1) ) {
3424           snd_printdd("FIFO is busy\n");
3425
3426           return -EINVAL;
3427         }
3428
3429         /*
3430          * Fill slots 12 with the correct value for the GPIO pins.
3431          */
3432         for(idx = 0x90; idx <= 0x9F; idx++) {
3433                 /*
3434                  * Initialize the fifo so that bits 7 and 8 are on.
3435                  *
3436                  * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3437                  * the left.  0x1800 corresponds to bits 7 and 8.
3438                  */
3439                 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3440
3441                 /*
3442                  * Wait for command to complete
3443                  */
3444                 if ( cs46xx_wait_for_fifo(chip,200) ) {
3445                         snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx);
3446
3447                         return -EINVAL;
3448                 }
3449
3450                 /*
3451                  * Write the serial port FIFO index.
3452                  */
3453                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3454
3455                 /*
3456                  * Tell the serial port to load the new value into the FIFO location.
3457                  */
3458                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3459         }
3460
3461         /* wait for last command to complete */
3462         cs46xx_wait_for_fifo(chip,200);
3463
3464         /*
3465          *  Now, if we powered up the devices, then power them back down again.
3466          *  This is kinda ugly, but should never happen.
3467          */
3468         if (powerdown)
3469                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3470
3471         return 0;
3472 }
3473 #endif
3474
3475 /*
3476  *      Crystal EAPD mode
3477  */
3478
3479 static void amp_voyetra(cs46xx_t *chip, int change)
3480 {
3481         /* Manage the EAPD bit on the Crystal 4297
3482            and the Analog AD1885 */
3483
3484 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3485         int old = chip->amplifier;
3486 #endif
3487         int oval, val;
3488
3489         chip->amplifier += change;
3490         oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3491                                      CS46XX_PRIMARY_CODEC_INDEX);
3492         val = oval;
3493         if (chip->amplifier) {
3494                 /* Turn the EAPD amp on */
3495                 val |= 0x8000;
3496         } else {
3497                 /* Turn the EAPD amp off */
3498                 val &= ~0x8000;
3499         }
3500         if (val != oval) {
3501                 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3502                                        CS46XX_PRIMARY_CODEC_INDEX);
3503                 if (chip->eapd_switch)
3504                         snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3505                                        &chip->eapd_switch->id);
3506         }
3507
3508 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3509         if (chip->amplifier && !old) {
3510                 voyetra_setup_eapd_slot(chip);
3511         }
3512 #endif
3513 }
3514
3515 static void hercules_init(cs46xx_t *chip)
3516 {
3517         /* default: AMP off, and SPDIF input optical */
3518         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3519         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3520 }
3521
3522
3523 /*
3524  *      Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3525  */
3526 static void amp_hercules(cs46xx_t *chip, int change)
3527 {
3528         int old = chip->amplifier;
3529         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3530         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3531
3532         chip->amplifier += change;
3533         if (chip->amplifier && !old) {
3534                 snd_printdd ("Hercules amplifier ON\n");
3535
3536                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3537                                    EGPIODR_GPOE2 | val1);     /* enable EGPIO2 output */
3538                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3539                                    EGPIOPTR_GPPT2 | val2);   /* open-drain on output */
3540         } else if (old && !chip->amplifier) {
3541                 snd_printdd ("Hercules amplifier OFF\n");
3542                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE2); /* disable */
3543                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3544         }
3545 }
3546
3547 static void voyetra_mixer_init (cs46xx_t *chip)
3548 {
3549         snd_printdd ("initializing Voyetra mixer\n");
3550
3551         /* Enable SPDIF out */
3552         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3553         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3554 }
3555
3556 static void hercules_mixer_init (cs46xx_t *chip)
3557 {
3558 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3559         unsigned int idx;
3560         int err;
3561         snd_card_t *card = chip->card;
3562 #endif
3563
3564         /* set EGPIO to default */
3565         hercules_init(chip);
3566
3567         snd_printdd ("initializing Hercules mixer\n");
3568
3569 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3570         for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3571                 snd_kcontrol_t *kctl;
3572
3573                 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3574                 if ((err = snd_ctl_add(card, kctl)) < 0) {
3575                         printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err);
3576                         break;
3577                 }
3578         }
3579 #endif
3580 }
3581
3582
3583 #if 0
3584 /*
3585  *      Untested
3586  */
3587
3588 static void amp_voyetra_4294(cs46xx_t *chip, int change)
3589 {
3590         chip->amplifier += change;
3591
3592         if (chip->amplifier) {
3593                 /* Switch the GPIO pins 7 and 8 to open drain */
3594                 snd_cs46xx_codec_write(chip, 0x4C,
3595                                        snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3596                 snd_cs46xx_codec_write(chip, 0x4E,
3597                                        snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3598                 /* Now wake the AMP (this might be backwards) */
3599                 snd_cs46xx_codec_write(chip, 0x54,
3600                                        snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3601         } else {
3602                 snd_cs46xx_codec_write(chip, 0x54,
3603                                        snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3604         }
3605 }
3606 #endif
3607
3608
3609 /*
3610  * piix4 pci ids
3611  */
3612 #ifndef PCI_VENDOR_ID_INTEL
3613 #define PCI_VENDOR_ID_INTEL 0x8086
3614 #endif /* PCI_VENDOR_ID_INTEL */
3615
3616 #ifndef PCI_DEVICE_ID_INTEL_82371AB_3
3617 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
3618 #endif /* PCI_DEVICE_ID_INTEL_82371AB_3 */
3619
3620 /*
3621  *      Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3622  *      whenever we need to beat on the chip.
3623  *
3624  *      The original idea and code for this hack comes from David Kaiser at
3625  *      Linuxcare. Perhaps one day Crystal will document their chips well
3626  *      enough to make them useful.
3627  */
3628
3629 static void clkrun_hack(cs46xx_t *chip, int change)
3630 {
3631         u16 control, nval;
3632
3633         if (chip->acpi_dev == NULL)
3634                 return;
3635
3636         chip->amplifier += change;
3637
3638         /* Read ACPI port */
3639         nval = control = inw(chip->acpi_port + 0x10);
3640
3641         /* Flip CLKRUN off while running */
3642         if (! chip->amplifier)
3643                 nval |= 0x2000;
3644         else
3645                 nval &= ~0x2000;
3646         if (nval != control)
3647                 outw(nval, chip->acpi_port + 0x10);
3648 }
3649
3650
3651 /*
3652  * detect intel piix4
3653  */
3654 static void clkrun_init(cs46xx_t *chip)
3655 {
3656         u8 pp;
3657
3658         chip->acpi_dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3659         if (chip->acpi_dev == NULL)
3660                 return;         /* Not a thinkpad thats for sure */
3661
3662         /* Find the control port */
3663         pci_read_config_byte(chip->acpi_dev, 0x41, &pp);
3664         chip->acpi_port = pp << 8;
3665 }
3666
3667
3668 /*
3669  * Card subid table
3670  */
3671
3672 struct cs_card_type
3673 {
3674         u16 vendor;
3675         u16 id;
3676         char *name;
3677         void (*init)(cs46xx_t *);
3678         void (*amp)(cs46xx_t *, int);
3679         void (*active)(cs46xx_t *, int);
3680         void (*mixer_init)(cs46xx_t *);
3681 };
3682
3683 static struct cs_card_type __devinitdata cards[] = {
3684         {
3685                 .vendor = 0x1489,
3686                 .id = 0x7001,
3687                 .name = "Genius Soundmaker 128 value",
3688                 /* nothing special */
3689         },
3690         {
3691                 .vendor = 0x5053,
3692                 .id = 0x3357,
3693                 .name = "Voyetra",
3694                 .amp = amp_voyetra,
3695                 .mixer_init = voyetra_mixer_init,
3696         },
3697         {
3698                 .vendor = 0x1071,
3699                 .id = 0x6003,
3700                 .name = "Mitac MI6020/21",
3701                 .amp = amp_voyetra,
3702         },
3703         {
3704                 .vendor = 0x14AF,
3705                 .id = 0x0050,
3706                 .name = "Hercules Game Theatre XP",
3707                 .amp = amp_hercules,
3708                 .mixer_init = hercules_mixer_init,
3709         },
3710         {
3711                 .vendor = 0x1681,
3712                 .id = 0x0050,
3713                 .name = "Hercules Game Theatre XP",
3714                 .amp = amp_hercules,
3715                 .mixer_init = hercules_mixer_init,
3716         },
3717         {
3718                 .vendor = 0x1681,
3719                 .id = 0x0051,
3720                 .name = "Hercules Game Theatre XP",
3721                 .amp = amp_hercules,
3722                 .mixer_init = hercules_mixer_init,
3723
3724         },
3725         {
3726                 .vendor = 0x1681,
3727                 .id = 0x0052,
3728                 .name = "Hercules Game Theatre XP",
3729                 .amp = amp_hercules,
3730                 .mixer_init = hercules_mixer_init,
3731         },
3732         {
3733                 .vendor = 0x1681,
3734                 .id = 0x0053,
3735                 .name = "Hercules Game Theatre XP",
3736                 .amp = amp_hercules,
3737                 .mixer_init = hercules_mixer_init,
3738         },
3739         {
3740                 .vendor = 0x1681,
3741                 .id = 0x0054,
3742                 .name = "Hercules Game Theatre XP",
3743                 .amp = amp_hercules,
3744                 .mixer_init = hercules_mixer_init,
3745         },
3746         /* Teratec */
3747         {
3748                 .vendor = 0x153b,
3749                 .id = 0x1136,
3750                 .name = "Terratec SiXPack 5.1",
3751         },
3752         /* Not sure if the 570 needs the clkrun hack */
3753         {
3754                 .vendor = PCI_VENDOR_ID_IBM,
3755                 .id = 0x0132,
3756                 .name = "Thinkpad 570",
3757                 .init = clkrun_init,
3758                 .active = clkrun_hack,
3759         },
3760         {
3761                 .vendor = PCI_VENDOR_ID_IBM,
3762                 .id = 0x0153,
3763                 .name = "Thinkpad 600X/A20/T20",
3764                 .init = clkrun_init,
3765                 .active = clkrun_hack,
3766         },
3767         {
3768                 .vendor = PCI_VENDOR_ID_IBM,
3769                 .id = 0x1010,
3770                 .name = "Thinkpad 600E (unsupported)",
3771         },
3772         {} /* terminator */
3773 };
3774
3775
3776 /*
3777  * APM support
3778  */
3779 #ifdef CONFIG_PM
3780 void snd_cs46xx_suspend(cs46xx_t *chip)
3781 {
3782         int amp_saved;
3783
3784         snd_card_t *card = chip->card;
3785
3786         if (card->power_state == SNDRV_CTL_POWER_D3hot)
3787                 return;
3788         snd_pcm_suspend_all(chip->pcm);
3789         // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3790         // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3791         amp_saved = chip->amplifier;
3792         /* turn off amp */
3793         chip->amplifier_ctrl(chip, -chip->amplifier);
3794         snd_cs46xx_hw_stop(chip);
3795         /* disable CLKRUN */
3796         chip->active_ctrl(chip, -chip->amplifier);
3797         chip->amplifier = amp_saved; /* restore the status */
3798         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3799 }
3800
3801 void snd_cs46xx_resume(cs46xx_t *chip)
3802 {
3803         snd_card_t *card = chip->card;
3804         int amp_saved;
3805
3806         if (card->power_state == SNDRV_CTL_POWER_D0)
3807                 return;
3808
3809         pci_enable_device(chip->pci);
3810         amp_saved = chip->amplifier;
3811         chip->amplifier = 0;
3812         chip->active_ctrl(chip, 1); /* force to on */
3813
3814         snd_cs46xx_chip_init(chip, 1);
3815
3816 #if 0
3817         snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3818                                chip->ac97_general_purpose);
3819         snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3820                                chip->ac97_powerdown);
3821         mdelay(10);
3822         snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3823                                chip->ac97_powerdown);
3824         mdelay(5);
3825 #endif
3826
3827         snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3828
3829         if (amp_saved)
3830                 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3831         else
3832                 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3833         chip->amplifier = amp_saved;
3834         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3835 }
3836
3837 static int snd_cs46xx_set_power_state(snd_card_t *card, unsigned int power_state)
3838 {
3839         cs46xx_t *chip = snd_magic_cast(cs46xx_t, card->power_state_private_data, return -ENXIO);
3840
3841         switch (power_state) {
3842         case SNDRV_CTL_POWER_D0:
3843         case SNDRV_CTL_POWER_D1:
3844         case SNDRV_CTL_POWER_D2:
3845                 snd_cs46xx_resume(chip);
3846                 break;
3847         case SNDRV_CTL_POWER_D3hot:
3848         case SNDRV_CTL_POWER_D3cold:
3849                 snd_cs46xx_suspend(chip);
3850                 break;
3851         default:
3852                 return -EINVAL;
3853         }
3854         return 0;
3855 }
3856 #endif /* CONFIG_PM */
3857
3858
3859 /*
3860  */
3861
3862 int __devinit snd_cs46xx_create(snd_card_t * card,
3863                       struct pci_dev * pci,
3864                       int external_amp, int thinkpad,
3865                       cs46xx_t ** rchip)
3866 {
3867         cs46xx_t *chip;
3868         int err, idx;
3869         snd_cs46xx_region_t *region;
3870         struct cs_card_type *cp;
3871         u16 ss_card, ss_vendor;
3872         static snd_device_ops_t ops = {
3873                 .dev_free =     snd_cs46xx_dev_free,
3874         };
3875
3876         *rchip = NULL;
3877
3878         /* enable PCI device */
3879         if ((err = pci_enable_device(pci)) < 0)
3880                 return err;
3881
3882         chip = snd_magic_kcalloc(cs46xx_t, 0, GFP_KERNEL);
3883         if (chip == NULL)
3884                 return -ENOMEM;
3885         spin_lock_init(&chip->reg_lock);
3886 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3887         init_MUTEX(&chip->spos_mutex);
3888 #endif
3889         chip->card = card;
3890         chip->pci = pci;
3891         chip->capt.hw_size = PAGE_SIZE;
3892         chip->irq = -1;
3893         chip->ba0_addr = pci_resource_start(pci, 0);
3894         chip->ba1_addr = pci_resource_start(pci, 1);
3895         if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3896             chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3897                 snd_cs46xx_free(chip);
3898                 snd_printk("wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n", chip->ba0_addr, chip->ba1_addr);
3899                 return -ENOMEM;
3900         }
3901
3902         region = &chip->region.name.ba0;
3903         strcpy(region->name, "CS46xx_BA0");
3904         region->base = chip->ba0_addr;
3905         region->size = CS46XX_BA0_SIZE;
3906
3907         region = &chip->region.name.data0;
3908         strcpy(region->name, "CS46xx_BA1_data0");
3909         region->base = chip->ba1_addr + BA1_SP_DMEM0;
3910         region->size = CS46XX_BA1_DATA0_SIZE;
3911
3912         region = &chip->region.name.data1;
3913         strcpy(region->name, "CS46xx_BA1_data1");
3914         region->base = chip->ba1_addr + BA1_SP_DMEM1;
3915         region->size = CS46XX_BA1_DATA1_SIZE;
3916
3917         region = &chip->region.name.pmem;
3918         strcpy(region->name, "CS46xx_BA1_pmem");
3919         region->base = chip->ba1_addr + BA1_SP_PMEM;
3920         region->size = CS46XX_BA1_PRG_SIZE;
3921
3922         region = &chip->region.name.reg;
3923         strcpy(region->name, "CS46xx_BA1_reg");
3924         region->base = chip->ba1_addr + BA1_SP_REG;
3925         region->size = CS46XX_BA1_REG_SIZE;
3926
3927         /* set up amp and clkrun hack */
3928         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3929         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3930
3931         for (cp = &cards[0]; cp->name; cp++) {
3932                 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3933                         snd_printdd ("hack for %s enabled\n", cp->name);
3934
3935                         chip->amplifier_ctrl = cp->amp;
3936                         chip->active_ctrl = cp->active;
3937                         chip->mixer_init = cp->mixer_init;
3938
3939                         if (cp->init)
3940                                 cp->init(chip);
3941                         break;
3942                 }
3943         }
3944
3945         if (external_amp) {
3946                 snd_printk("Crystal EAPD support forced on.\n");
3947                 chip->amplifier_ctrl = amp_voyetra;
3948         }
3949
3950         if (thinkpad) {
3951                 snd_printk("Activating CLKRUN hack for Thinkpad.\n");
3952                 chip->active_ctrl = clkrun_hack;
3953                 clkrun_init(chip);
3954         }
3955
3956         if (chip->amplifier_ctrl == NULL)
3957                 chip->amplifier_ctrl = amp_none;
3958         if (chip->active_ctrl == NULL)
3959                 chip->active_ctrl = amp_none;
3960
3961         chip->active_ctrl(chip, 1); /* enable CLKRUN */
3962
3963         pci_set_master(pci);
3964
3965         for (idx = 0; idx < 5; idx++) {
3966                 region = &chip->region.idx[idx];
3967                 if ((region->resource = request_mem_region(region->base, region->size, region->name)) == NULL) {
3968                         snd_printk("unable to request memory region 0x%lx-0x%lx\n", region->base, region->base + region->size - 1);
3969                         snd_cs46xx_free(chip);
3970                         return -EBUSY;
3971                 }
3972                 region->remap_addr = (unsigned long) ioremap_nocache(region->base, region->size);
3973                 if (region->remap_addr == 0) {
3974                         snd_printk("%s ioremap problem\n", region->name);
3975                         snd_cs46xx_free(chip);
3976                         return -ENOMEM;
3977                 }
3978         }
3979
3980         if (request_irq(pci->irq, snd_cs46xx_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS46XX", (void *) chip)) {
3981                 snd_printk("unable to grab IRQ %d\n", pci->irq);
3982                 snd_cs46xx_free(chip);
3983                 return -EBUSY;
3984         }
3985         chip->irq = pci->irq;
3986
3987 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3988         chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3989         if (chip->dsp_spos_instance == NULL) {
3990                 snd_cs46xx_free(chip);
3991                 return -ENOMEM;
3992         }
3993 #endif
3994
3995         err = snd_cs46xx_chip_init(chip, 0);
3996         if (err < 0) {
3997                 snd_cs46xx_free(chip);
3998                 return err;
3999         }
4000
4001         snd_cs46xx_proc_init(card, chip);
4002
4003 #ifdef CONFIG_PM
4004         card->set_power_state = snd_cs46xx_set_power_state;
4005         card->power_state_private_data = chip;
4006 #endif
4007
4008         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
4009                 snd_cs46xx_free(chip);
4010                 return err;
4011         }
4012
4013         chip->active_ctrl(chip, -1); /* disable CLKRUN */
4014
4015         *rchip = chip;
4016         return 0;
4017 }