3 bool "Hardware crypto devices"
6 Say Y here to get to see options for hardware crypto devices and
7 processors. This option alone does not add any kernel code.
9 If you say N, all options in this submenu will be skipped and disabled.
13 config CRYPTO_DEV_PADLOCK
14 tristate "Support for VIA PadLock ACE"
15 depends on X86 && !UML
17 Some VIA processors come with an integrated crypto engine
18 (so called VIA PadLock ACE, Advanced Cryptography Engine)
19 that provides instructions for very fast cryptographic
20 operations with supported algorithms.
22 The instructions are used only when the CPU supports them.
23 Otherwise software encryption is used.
25 config CRYPTO_DEV_PADLOCK_AES
26 tristate "PadLock driver for AES algorithm"
27 depends on CRYPTO_DEV_PADLOCK
28 select CRYPTO_BLKCIPHER
31 Use VIA PadLock for AES algorithm.
33 Available in VIA C3 and newer CPUs.
35 If unsure say M. The compiled module will be
38 config CRYPTO_DEV_PADLOCK_SHA
39 tristate "PadLock driver for SHA1 and SHA256 algorithms"
40 depends on CRYPTO_DEV_PADLOCK
45 Use VIA PadLock for SHA1/SHA256 algorithms.
47 Available in VIA C7 and newer processors.
49 If unsure say M. The compiled module will be
52 config CRYPTO_DEV_GEODE
53 tristate "Support for the Geode LX AES engine"
54 depends on X86_32 && PCI
56 select CRYPTO_BLKCIPHER
58 Say 'Y' here to use the AMD Geode LX processor on-board AES
59 engine for the CryptoAPI AES algorithm.
61 To compile this driver as a module, choose M here: the module
62 will be called geode-aes.
65 tristate "Support for PCI-attached cryptographic adapters"
67 select ZCRYPT_MONOLITHIC if ZCRYPT="y"
70 Select this option if you want to use a PCI-attached cryptographic
72 + PCI Cryptographic Accelerator (PCICA)
73 + PCI Cryptographic Coprocessor (PCICC)
74 + PCI-X Cryptographic Coprocessor (PCIXCC)
75 + Crypto Express2 Coprocessor (CEX2C)
76 + Crypto Express2 Accelerator (CEX2A)
78 config ZCRYPT_MONOLITHIC
79 bool "Monolithic zcrypt module"
82 Select this option if you want to have a single module z90crypt,
83 that contains all parts of the crypto device driver (ap bus,
84 request router and all the card drivers).
86 config CRYPTO_SHA1_S390
87 tristate "SHA1 digest algorithm"
91 This is the s390 hardware accelerated implementation of the
92 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
94 config CRYPTO_SHA256_S390
95 tristate "SHA256 digest algorithm"
99 This is the s390 hardware accelerated implementation of the
100 SHA256 secure hash standard (DFIPS 180-2).
102 This version of SHA implements a 256 bit hash with 128 bits of
103 security against collision attacks.
105 config CRYPTO_SHA512_S390
106 tristate "SHA384 and SHA512 digest algorithm"
110 This is the s390 hardware accelerated implementation of the
111 SHA512 secure hash standard.
113 This version of SHA implements a 512 bit hash with 256 bits of
114 security against collision attacks. The code also includes SHA-384,
115 a 384 bit hash with 192 bits of security against collision attacks.
118 config CRYPTO_DES_S390
119 tristate "DES and Triple DES cipher algorithms"
122 select CRYPTO_BLKCIPHER
124 This us the s390 hardware accelerated implementation of the
125 DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
127 config CRYPTO_AES_S390
128 tristate "AES cipher algorithms"
131 select CRYPTO_BLKCIPHER
133 This is the s390 hardware accelerated implementation of the
134 AES cipher algorithms (FIPS-197). AES uses the Rijndael
137 Rijndael appears to be consistently a very good performer in
138 both hardware and software across a wide range of computing
139 environments regardless of its use in feedback or non-feedback
140 modes. Its key setup time is excellent, and its key agility is
141 good. Rijndael's very low memory requirements make it very well
142 suited for restricted-space environments, in which it also
143 demonstrates excellent performance. Rijndael's operations are
144 among the easiest to defend against power and timing attacks.
146 On s390 the System z9-109 currently only supports the key size
150 tristate "Pseudo random number generator device driver"
154 Select this option if you want to use the s390 pseudo random number
155 generator. The PRNG is part of the cryptographic processor functions
156 and uses triple-DES to generate secure random numbers like the
157 ANSI X9.17 standard. The PRNG is usable via the char device
160 config CRYPTO_DEV_MV_CESA
161 tristate "Marvell's Cryptographic Engine"
162 depends on PLAT_ORION
165 select CRYPTO_BLKCIPHER2
167 This driver allows you to utilize the Cryptographic Engines and
168 Security Accelerator (CESA) which can be found on the Marvell Orion
169 and Kirkwood SoCs, such as QNAP's TS-209.
171 Currently the driver supports AES in ECB and CBC mode without DMA.
173 config CRYPTO_DEV_NIAGARA2
174 tristate "Niagara2 Stream Processing Unit driver"
179 Each core of a Niagara2 processor contains a Stream
180 Processing Unit, which itself contains several cryptographic
181 sub-units. One set provides the Modular Arithmetic Unit,
182 used for SSL offload. The other set provides the Cipher
183 Group, which can perform encryption, decryption, hashing,
184 checksumming, and raw copies.
186 config CRYPTO_DEV_HIFN_795X
187 tristate "Driver HIFN 795x crypto accelerator chips"
190 select CRYPTO_BLKCIPHER
191 select HW_RANDOM if CRYPTO_DEV_HIFN_795X_RNG
194 This option allows you to have support for HIFN 795x crypto adapters.
196 config CRYPTO_DEV_HIFN_795X_RNG
197 bool "HIFN 795x random number generator"
198 depends on CRYPTO_DEV_HIFN_795X
200 Select this option if you want to enable the random number generator
201 on the HIFN 795x crypto adapters.
203 source drivers/crypto/caam/Kconfig
205 config CRYPTO_DEV_TALITOS
206 tristate "Talitos Freescale Security Engine (SEC)"
208 select CRYPTO_AUTHENC
212 Say 'Y' here to use the Freescale Security Engine (SEC)
213 to offload cryptographic algorithm computation.
215 The Freescale SEC is present on PowerQUICC 'E' processors, such
216 as the MPC8349E and MPC8548E.
218 To compile this driver as a module, choose M here: the module
219 will be called talitos.
221 config CRYPTO_DEV_IXP4XX
222 tristate "Driver for IXP4xx crypto hardware acceleration"
223 depends on ARCH_IXP4XX
226 select CRYPTO_AUTHENC
227 select CRYPTO_BLKCIPHER
229 Driver for the IXP4xx NPE crypto engine.
231 config CRYPTO_DEV_PPC4XX
232 tristate "Driver AMCC PPC4xx crypto accelerator"
233 depends on PPC && 4xx
236 select CRYPTO_BLKCIPHER
238 This option allows you to have support for AMCC crypto acceleration.
240 config CRYPTO_DEV_OMAP_SHAM
241 tristate "Support for OMAP SHA1/MD5 hw accelerator"
242 depends on ARCH_OMAP2 || ARCH_OMAP3
246 OMAP processors have SHA1/MD5 hw accelerator. Select this if you
247 want to use the OMAP module for SHA1/MD5 algorithms.
249 config CRYPTO_DEV_OMAP_AES
250 tristate "Support for OMAP AES hw engine"
251 depends on ARCH_OMAP2 || ARCH_OMAP3
254 OMAP processors have AES module accelerator. Select this if you
255 want to use the OMAP module for AES algorithms.
257 config CRYPTO_DEV_PICOXCELL
258 tristate "Support for picoXcell IPSEC and Layer2 crypto engines"
259 depends on ARCH_PICOXCELL
261 select CRYPTO_AUTHENC
268 This option enables support for the hardware offload engines in the
269 Picochip picoXcell SoC devices. Select this for IPSEC ESP offload
270 and for 3gpp Layer 2 ciphering support.
272 Saying m here will build a module named pipcoxcell_crypto.
274 config CRYPTO_DEV_S5P
275 tristate "Support for Samsung S5PV210 crypto accelerator"
276 depends on ARCH_S5PV210
279 select CRYPTO_BLKCIPHER
281 This option allows you to have support for S5P crypto acceleration.
282 Select this to offload Samsung S5PV210 or S5PC110 from AES
283 algorithms execution.