drivers/net/wireless/b43/main.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6   Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
   7   Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
   8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10   Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
  11
  12   SDIO support
  13   Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
  14
  15   Some parts of the code in this file are derived from the ipw2200
  16   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  17
  18   This program is free software; you can redistribute it and/or modify
  19   it under the terms of the GNU General Public License as published by
  20   the Free Software Foundation; either version 2 of the License, or
  21   (at your option) any later version.
  22
  23   This program is distributed in the hope that it will be useful,
  24   but WITHOUT ANY WARRANTY; without even the implied warranty of
  25   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26   GNU General Public License for more details.
  27
  28   You should have received a copy of the GNU General Public License
  29   along with this program; see the file COPYING.  If not, write to
  30   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  31   Boston, MA 02110-1301, USA.
  32
  33 */
  34
  35 #include <linux/delay.h>
  36 #include <linux/init.h>
  37 #include <linux/module.h>
  38 #include <linux/if_arp.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/firmware.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/skbuff.h>
  43 #include <linux/io.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/slab.h>
  46 #include <asm/unaligned.h>
  47
  48 #include "b43.h"
  49 #include "main.h"
  50 #include "debugfs.h"
  51 #include "phy_common.h"
  52 #include "phy_g.h"
  53 #include "phy_n.h"
  54 #include "dma.h"
  55 #include "pio.h"
  56 #include "sysfs.h"
  57 #include "xmit.h"
  58 #include "lo.h"
  59 #include "pcmcia.h"
  60 #include "sdio.h"
  61 #include <linux/mmc/sdio_func.h>
  62
  63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  64 MODULE_AUTHOR("Martin Langer");
  65 MODULE_AUTHOR("Stefano Brivio");
  66 MODULE_AUTHOR("Michael Buesch");
  67 MODULE_AUTHOR("Gábor Stefanik");
  68 MODULE_AUTHOR("Rafał Miłecki");
  69 MODULE_LICENSE("GPL");
  70
  71 MODULE_FIRMWARE("b43/ucode11.fw");
  72 MODULE_FIRMWARE("b43/ucode13.fw");
  73 MODULE_FIRMWARE("b43/ucode14.fw");
  74 MODULE_FIRMWARE("b43/ucode15.fw");
  75 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
  76 MODULE_FIRMWARE("b43/ucode5.fw");
  77 MODULE_FIRMWARE("b43/ucode9.fw");
  78
  79 static int modparam_bad_frames_preempt;
  80 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  81 MODULE_PARM_DESC(bad_frames_preempt,
  82                  "enable(1) / disable(0) Bad Frames Preemption");
  83
  84 static char modparam_fwpostfix[16];
  85 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  86 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  87
  88 static int modparam_hwpctl;
  89 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  90 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  91
  92 static int modparam_nohwcrypt;
  93 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  94 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  95
  96 static int modparam_hwtkip;
  97 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
  98 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
  99
 100 static int modparam_qos = 1;
 101 module_param_named(qos, modparam_qos, int, 0444);
 102 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
 103
 104 static int modparam_btcoex = 1;
 105 module_param_named(btcoex, modparam_btcoex, int, 0444);
 106 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
 107
 108 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
 109 module_param_named(verbose, b43_modparam_verbose, int, 0644);
 110 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
 111
 112 static int b43_modparam_pio = 0;
 113 module_param_named(pio, b43_modparam_pio, int, 0644);
 114 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
 115
 116 #ifdef CONFIG_B43_BCMA
 117 static const struct bcma_device_id b43_bcma_tbl[] = {
 118         BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
 119 #ifdef CONFIG_B43_BCMA_EXTRA
 120         BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
 121         BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
 122 #endif
 123         BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
 124         BCMA_CORETABLE_END
 125 };
 126 MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
 127 #endif
 128
 129 #ifdef CONFIG_B43_SSB
 130 static const struct ssb_device_id b43_ssb_tbl[] = {
 131         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
 132         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
 133         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
 134         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
 135         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
 136         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
 137         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
 138         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
 139         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
 140         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
 141         SSB_DEVTABLE_END
 142 };
 143 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
 144 #endif
 145
 146 /* Channel and ratetables are shared for all devices.
 147  * They can't be const, because ieee80211 puts some precalculated
 148  * data in there. This data is the same for all devices, so we don't
 149  * get concurrency issues */
 150 #define RATETAB_ENT(_rateid, _flags) \
 151         {                                                               \
 152                 .bitrate        = B43_RATE_TO_BASE100KBPS(_rateid),     \
 153                 .hw_value       = (_rateid),                            \
 154                 .flags          = (_flags),                             \
 155         }
 156
 157 /*
 158  * NOTE: When changing this, sync with xmit.c's
 159  *       b43_plcp_get_bitrate_idx_* functions!
 160  */
 161 static struct ieee80211_rate __b43_ratetable[] = {
 162         RATETAB_ENT(B43_CCK_RATE_1MB, 0),
 163         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
 164         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
 165         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
 166         RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
 167         RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
 168         RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
 169         RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
 170         RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
 171         RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
 172         RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
 173         RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
 174 };
 175
 176 #define b43_a_ratetable         (__b43_ratetable + 4)
 177 #define b43_a_ratetable_size    8
 178 #define b43_b_ratetable         (__b43_ratetable + 0)
 179 #define b43_b_ratetable_size    4
 180 #define b43_g_ratetable         (__b43_ratetable + 0)
 181 #define b43_g_ratetable_size    12
 182
 183 #define CHAN4G(_channel, _freq, _flags) {                       \
 184         .band                   = IEEE80211_BAND_2GHZ,          \
 185         .center_freq            = (_freq),                      \
 186         .hw_value               = (_channel),                   \
 187         .flags                  = (_flags),                     \
 188         .max_antenna_gain       = 0,                            \
 189         .max_power              = 30,                           \
 190 }
 191 static struct ieee80211_channel b43_2ghz_chantable[] = {
 192         CHAN4G(1, 2412, 0),
 193         CHAN4G(2, 2417, 0),
 194         CHAN4G(3, 2422, 0),
 195         CHAN4G(4, 2427, 0),
 196         CHAN4G(5, 2432, 0),
 197         CHAN4G(6, 2437, 0),
 198         CHAN4G(7, 2442, 0),
 199         CHAN4G(8, 2447, 0),
 200         CHAN4G(9, 2452, 0),
 201         CHAN4G(10, 2457, 0),
 202         CHAN4G(11, 2462, 0),
 203         CHAN4G(12, 2467, 0),
 204         CHAN4G(13, 2472, 0),
 205         CHAN4G(14, 2484, 0),
 206 };
 207 #undef CHAN4G
 208
 209 #define CHAN5G(_channel, _flags) {                              \
 210         .band                   = IEEE80211_BAND_5GHZ,          \
 211         .center_freq            = 5000 + (5 * (_channel)),      \
 212         .hw_value               = (_channel),                   \
 213         .flags                  = (_flags),                     \
 214         .max_antenna_gain       = 0,                            \
 215         .max_power              = 30,                           \
 216 }
 217 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
 218         CHAN5G(32, 0),          CHAN5G(34, 0),
 219         CHAN5G(36, 0),          CHAN5G(38, 0),
 220         CHAN5G(40, 0),          CHAN5G(42, 0),
 221         CHAN5G(44, 0),          CHAN5G(46, 0),
 222         CHAN5G(48, 0),          CHAN5G(50, 0),
 223         CHAN5G(52, 0),          CHAN5G(54, 0),
 224         CHAN5G(56, 0),          CHAN5G(58, 0),
 225         CHAN5G(60, 0),          CHAN5G(62, 0),
 226         CHAN5G(64, 0),          CHAN5G(66, 0),
 227         CHAN5G(68, 0),          CHAN5G(70, 0),
 228         CHAN5G(72, 0),          CHAN5G(74, 0),
 229         CHAN5G(76, 0),          CHAN5G(78, 0),
 230         CHAN5G(80, 0),          CHAN5G(82, 0),
 231         CHAN5G(84, 0),          CHAN5G(86, 0),
 232         CHAN5G(88, 0),          CHAN5G(90, 0),
 233         CHAN5G(92, 0),          CHAN5G(94, 0),
 234         CHAN5G(96, 0),          CHAN5G(98, 0),
 235         CHAN5G(100, 0),         CHAN5G(102, 0),
 236         CHAN5G(104, 0),         CHAN5G(106, 0),
 237         CHAN5G(108, 0),         CHAN5G(110, 0),
 238         CHAN5G(112, 0),         CHAN5G(114, 0),
 239         CHAN5G(116, 0),         CHAN5G(118, 0),
 240         CHAN5G(120, 0),         CHAN5G(122, 0),
 241         CHAN5G(124, 0),         CHAN5G(126, 0),
 242         CHAN5G(128, 0),         CHAN5G(130, 0),
 243         CHAN5G(132, 0),         CHAN5G(134, 0),
 244         CHAN5G(136, 0),         CHAN5G(138, 0),
 245         CHAN5G(140, 0),         CHAN5G(142, 0),
 246         CHAN5G(144, 0),         CHAN5G(145, 0),
 247         CHAN5G(146, 0),         CHAN5G(147, 0),
 248         CHAN5G(148, 0),         CHAN5G(149, 0),
 249         CHAN5G(150, 0),         CHAN5G(151, 0),
 250         CHAN5G(152, 0),         CHAN5G(153, 0),
 251         CHAN5G(154, 0),         CHAN5G(155, 0),
 252         CHAN5G(156, 0),         CHAN5G(157, 0),
 253         CHAN5G(158, 0),         CHAN5G(159, 0),
 254         CHAN5G(160, 0),         CHAN5G(161, 0),
 255         CHAN5G(162, 0),         CHAN5G(163, 0),
 256         CHAN5G(164, 0),         CHAN5G(165, 0),
 257         CHAN5G(166, 0),         CHAN5G(168, 0),
 258         CHAN5G(170, 0),         CHAN5G(172, 0),
 259         CHAN5G(174, 0),         CHAN5G(176, 0),
 260         CHAN5G(178, 0),         CHAN5G(180, 0),
 261         CHAN5G(182, 0),         CHAN5G(184, 0),
 262         CHAN5G(186, 0),         CHAN5G(188, 0),
 263         CHAN5G(190, 0),         CHAN5G(192, 0),
 264         CHAN5G(194, 0),         CHAN5G(196, 0),
 265         CHAN5G(198, 0),         CHAN5G(200, 0),
 266         CHAN5G(202, 0),         CHAN5G(204, 0),
 267         CHAN5G(206, 0),         CHAN5G(208, 0),
 268         CHAN5G(210, 0),         CHAN5G(212, 0),
 269         CHAN5G(214, 0),         CHAN5G(216, 0),
 270         CHAN5G(218, 0),         CHAN5G(220, 0),
 271         CHAN5G(222, 0),         CHAN5G(224, 0),
 272         CHAN5G(226, 0),         CHAN5G(228, 0),
 273 };
 274
 275 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
 276         CHAN5G(34, 0),          CHAN5G(36, 0),
 277         CHAN5G(38, 0),          CHAN5G(40, 0),
 278         CHAN5G(42, 0),          CHAN5G(44, 0),
 279         CHAN5G(46, 0),          CHAN5G(48, 0),
 280         CHAN5G(52, 0),          CHAN5G(56, 0),
 281         CHAN5G(60, 0),          CHAN5G(64, 0),
 282         CHAN5G(100, 0),         CHAN5G(104, 0),
 283         CHAN5G(108, 0),         CHAN5G(112, 0),
 284         CHAN5G(116, 0),         CHAN5G(120, 0),
 285         CHAN5G(124, 0),         CHAN5G(128, 0),
 286         CHAN5G(132, 0),         CHAN5G(136, 0),
 287         CHAN5G(140, 0),         CHAN5G(149, 0),
 288         CHAN5G(153, 0),         CHAN5G(157, 0),
 289         CHAN5G(161, 0),         CHAN5G(165, 0),
 290         CHAN5G(184, 0),         CHAN5G(188, 0),
 291         CHAN5G(192, 0),         CHAN5G(196, 0),
 292         CHAN5G(200, 0),         CHAN5G(204, 0),
 293         CHAN5G(208, 0),         CHAN5G(212, 0),
 294         CHAN5G(216, 0),
 295 };
 296 #undef CHAN5G
 297
 298 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
 299         .band           = IEEE80211_BAND_5GHZ,
 300         .channels       = b43_5ghz_nphy_chantable,
 301         .n_channels     = ARRAY_SIZE(b43_5ghz_nphy_chantable),
 302         .bitrates       = b43_a_ratetable,
 303         .n_bitrates     = b43_a_ratetable_size,
 304 };
 305
 306 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
 307         .band           = IEEE80211_BAND_5GHZ,
 308         .channels       = b43_5ghz_aphy_chantable,
 309         .n_channels     = ARRAY_SIZE(b43_5ghz_aphy_chantable),
 310         .bitrates       = b43_a_ratetable,
 311         .n_bitrates     = b43_a_ratetable_size,
 312 };
 313
 314 static struct ieee80211_supported_band b43_band_2GHz = {
 315         .band           = IEEE80211_BAND_2GHZ,
 316         .channels       = b43_2ghz_chantable,
 317         .n_channels     = ARRAY_SIZE(b43_2ghz_chantable),
 318         .bitrates       = b43_g_ratetable,
 319         .n_bitrates     = b43_g_ratetable_size,
 320 };
 321
 322 static void b43_wireless_core_exit(struct b43_wldev *dev);
 323 static int b43_wireless_core_init(struct b43_wldev *dev);
 324 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
 325 static int b43_wireless_core_start(struct b43_wldev *dev);
 326 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
 327                                     struct ieee80211_vif *vif,
 328                                     struct ieee80211_bss_conf *conf,
 329                                     u32 changed);
 330
 331 static int b43_ratelimit(struct b43_wl *wl)
 332 {
 333         if (!wl || !wl->current_dev)
 334                 return 1;
 335         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
 336                 return 1;
 337         /* We are up and running.
 338          * Ratelimit the messages to avoid DoS over the net. */
 339         return net_ratelimit();
 340 }
 341
 342 void b43info(struct b43_wl *wl, const char *fmt, ...)
 343 {
 344         struct va_format vaf;
 345         va_list args;
 346
 347         if (b43_modparam_verbose < B43_VERBOSITY_INFO)
 348                 return;
 349         if (!b43_ratelimit(wl))
 350                 return;
 351
 352         va_start(args, fmt);
 353
 354         vaf.fmt = fmt;
 355         vaf.va = &args;
 356
 357         printk(KERN_INFO "b43-%s: %pV",
 358                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 359
 360         va_end(args);
 361 }
 362
 363 void b43err(struct b43_wl *wl, const char *fmt, ...)
 364 {
 365         struct va_format vaf;
 366         va_list args;
 367
 368         if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
 369                 return;
 370         if (!b43_ratelimit(wl))
 371                 return;
 372
 373         va_start(args, fmt);
 374
 375         vaf.fmt = fmt;
 376         vaf.va = &args;
 377
 378         printk(KERN_ERR "b43-%s ERROR: %pV",
 379                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 380
 381         va_end(args);
 382 }
 383
 384 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 385 {
 386         struct va_format vaf;
 387         va_list args;
 388
 389         if (b43_modparam_verbose < B43_VERBOSITY_WARN)
 390                 return;
 391         if (!b43_ratelimit(wl))
 392                 return;
 393
 394         va_start(args, fmt);
 395
 396         vaf.fmt = fmt;
 397         vaf.va = &args;
 398
 399         printk(KERN_WARNING "b43-%s warning: %pV",
 400                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 401
 402         va_end(args);
 403 }
 404
 405 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 406 {
 407         struct va_format vaf;
 408         va_list args;
 409
 410         if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
 411                 return;
 412
 413         va_start(args, fmt);
 414
 415         vaf.fmt = fmt;
 416         vaf.va = &args;
 417
 418         printk(KERN_DEBUG "b43-%s debug: %pV",
 419                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 420
 421         va_end(args);
 422 }
 423
 424 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
 425 {
 426         u32 macctl;
 427
 428         B43_WARN_ON(offset % 4 != 0);
 429
 430         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 431         if (macctl & B43_MACCTL_BE)
 432                 val = swab32(val);
 433
 434         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
 435         mmiowb();
 436         b43_write32(dev, B43_MMIO_RAM_DATA, val);
 437 }
 438
 439 static inline void b43_shm_control_word(struct b43_wldev *dev,
 440                                         u16 routing, u16 offset)
 441 {
 442         u32 control;
 443
 444         /* "offset" is the WORD offset. */
 445         control = routing;
 446         control <<= 16;
 447         control |= offset;
 448         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
 449 }
 450
 451 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
 452 {
 453         u32 ret;
 454
 455         if (routing == B43_SHM_SHARED) {
 456                 B43_WARN_ON(offset & 0x0001);
 457                 if (offset & 0x0003) {
 458                         /* Unaligned access */
 459                         b43_shm_control_word(dev, routing, offset >> 2);
 460                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 461                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 462                         ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
 463
 464                         goto out;
 465                 }
 466                 offset >>= 2;
 467         }
 468         b43_shm_control_word(dev, routing, offset);
 469         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
 470 out:
 471         return ret;
 472 }
 473
 474 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
 475 {
 476         u16 ret;
 477
 478         if (routing == B43_SHM_SHARED) {
 479                 B43_WARN_ON(offset & 0x0001);
 480                 if (offset & 0x0003) {
 481                         /* Unaligned access */
 482                         b43_shm_control_word(dev, routing, offset >> 2);
 483                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 484
 485                         goto out;
 486                 }
 487                 offset >>= 2;
 488         }
 489         b43_shm_control_word(dev, routing, offset);
 490         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
 491 out:
 492         return ret;
 493 }
 494
 495 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
 496 {
 497         if (routing == B43_SHM_SHARED) {
 498                 B43_WARN_ON(offset & 0x0001);
 499                 if (offset & 0x0003) {
 500                         /* Unaligned access */
 501                         b43_shm_control_word(dev, routing, offset >> 2);
 502                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
 503                                     value & 0xFFFF);
 504                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 505                         b43_write16(dev, B43_MMIO_SHM_DATA,
 506                                     (value >> 16) & 0xFFFF);
 507                         return;
 508                 }
 509                 offset >>= 2;
 510         }
 511         b43_shm_control_word(dev, routing, offset);
 512         b43_write32(dev, B43_MMIO_SHM_DATA, value);
 513 }
 514
 515 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
 516 {
 517         if (routing == B43_SHM_SHARED) {
 518                 B43_WARN_ON(offset & 0x0001);
 519                 if (offset & 0x0003) {
 520                         /* Unaligned access */
 521                         b43_shm_control_word(dev, routing, offset >> 2);
 522                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
 523                         return;
 524                 }
 525                 offset >>= 2;
 526         }
 527         b43_shm_control_word(dev, routing, offset);
 528         b43_write16(dev, B43_MMIO_SHM_DATA, value);
 529 }
 530
 531 /* Read HostFlags */
 532 u64 b43_hf_read(struct b43_wldev *dev)
 533 {
 534         u64 ret;
 535
 536         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
 537         ret <<= 16;
 538         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
 539         ret <<= 16;
 540         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
 541
 542         return ret;
 543 }
 544
 545 /* Write HostFlags */
 546 void b43_hf_write(struct b43_wldev *dev, u64 value)
 547 {
 548         u16 lo, mi, hi;
 549
 550         lo = (value & 0x00000000FFFFULL);
 551         mi = (value & 0x0000FFFF0000ULL) >> 16;
 552         hi = (value & 0xFFFF00000000ULL) >> 32;
 553         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
 554         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
 555         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
 556 }
 557
 558 /* Read the firmware capabilities bitmask (Opensource firmware only) */
 559 static u16 b43_fwcapa_read(struct b43_wldev *dev)
 560 {
 561         B43_WARN_ON(!dev->fw.opensource);
 562         return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
 563 }
 564
 565 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
 566 {
 567         u32 low, high;
 568
 569         B43_WARN_ON(dev->dev->core_rev < 3);
 570
 571         /* The hardware guarantees us an atomic read, if we
 572          * read the low register first. */
 573         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
 574         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 575
 576         *tsf = high;
 577         *tsf <<= 32;
 578         *tsf |= low;
 579 }
 580
 581 static void b43_time_lock(struct b43_wldev *dev)
 582 {
 583         b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
 584         /* Commit the write */
 585         b43_read32(dev, B43_MMIO_MACCTL);
 586 }
 587
 588 static void b43_time_unlock(struct b43_wldev *dev)
 589 {
 590         b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
 591         /* Commit the write */
 592         b43_read32(dev, B43_MMIO_MACCTL);
 593 }
 594
 595 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
 596 {
 597         u32 low, high;
 598
 599         B43_WARN_ON(dev->dev->core_rev < 3);
 600
 601         low = tsf;
 602         high = (tsf >> 32);
 603         /* The hardware guarantees us an atomic write, if we
 604          * write the low register first. */
 605         b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
 606         mmiowb();
 607         b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
 608         mmiowb();
 609 }
 610
 611 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
 612 {
 613         b43_time_lock(dev);
 614         b43_tsf_write_locked(dev, tsf);
 615         b43_time_unlock(dev);
 616 }
 617
 618 static
 619 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
 620 {
 621         static const u8 zero_addr[ETH_ALEN] = { 0 };
 622         u16 data;
 623
 624         if (!mac)
 625                 mac = zero_addr;
 626
 627         offset |= 0x0020;
 628         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
 629
 630         data = mac[0];
 631         data |= mac[1] << 8;
 632         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 633         data = mac[2];
 634         data |= mac[3] << 8;
 635         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 636         data = mac[4];
 637         data |= mac[5] << 8;
 638         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 639 }
 640
 641 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
 642 {
 643         const u8 *mac;
 644         const u8 *bssid;
 645         u8 mac_bssid[ETH_ALEN * 2];
 646         int i;
 647         u32 tmp;
 648
 649         bssid = dev->wl->bssid;
 650         mac = dev->wl->mac_addr;
 651
 652         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
 653
 654         memcpy(mac_bssid, mac, ETH_ALEN);
 655         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 656
 657         /* Write our MAC address and BSSID to template ram */
 658         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 659                 tmp = (u32) (mac_bssid[i + 0]);
 660                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
 661                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
 662                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
 663                 b43_ram_write(dev, 0x20 + i, tmp);
 664         }
 665 }
 666
 667 static void b43_upload_card_macaddress(struct b43_wldev *dev)
 668 {
 669         b43_write_mac_bssid_templates(dev);
 670         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
 671 }
 672
 673 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
 674 {
 675         /* slot_time is in usec. */
 676         /* This test used to exit for all but a G PHY. */
 677         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
 678                 return;
 679         b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
 680         /* Shared memory location 0x0010 is the slot time and should be
 681          * set to slot_time; however, this register is initially 0 and changing
 682          * the value adversely affects the transmit rate for BCM4311
 683          * devices. Until this behavior is unterstood, delete this step
 684          *
 685          * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
 686          */
 687 }
 688
 689 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
 690 {
 691         b43_set_slot_time(dev, 9);
 692 }
 693
 694 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
 695 {
 696         b43_set_slot_time(dev, 20);
 697 }
 698
 699 /* DummyTransmission function, as documented on
 700  * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
 701  */
 702 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
 703 {
 704         struct b43_phy *phy = &dev->phy;
 705         unsigned int i, max_loop;
 706         u16 value;
 707         u32 buffer[5] = {
 708                 0x00000000,
 709                 0x00D40000,
 710                 0x00000000,
 711                 0x01000000,
 712                 0x00000000,
 713         };
 714
 715         if (ofdm) {
 716                 max_loop = 0x1E;
 717                 buffer[0] = 0x000201CC;
 718         } else {
 719                 max_loop = 0xFA;
 720                 buffer[0] = 0x000B846E;
 721         }
 722
 723         for (i = 0; i < 5; i++)
 724                 b43_ram_write(dev, i * 4, buffer[i]);
 725
 726         b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
 727
 728         if (dev->dev->core_rev < 11)
 729                 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
 730         else
 731                 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
 732
 733         value = (ofdm ? 0x41 : 0x40);
 734         b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
 735         if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
 736             phy->type == B43_PHYTYPE_LCN)
 737                 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
 738
 739         b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
 740         b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
 741
 742         b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
 743         b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
 744         b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
 745         b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
 746
 747         if (!pa_on && phy->type == B43_PHYTYPE_N)
 748                 ; /*b43_nphy_pa_override(dev, false) */
 749
 750         switch (phy->type) {
 751         case B43_PHYTYPE_N:
 752         case B43_PHYTYPE_LCN:
 753                 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
 754                 break;
 755         case B43_PHYTYPE_LP:
 756                 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
 757                 break;
 758         default:
 759                 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
 760         }
 761         b43_read16(dev, B43_MMIO_TXE0_AUX);
 762
 763         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 764                 b43_radio_write16(dev, 0x0051, 0x0017);
 765         for (i = 0x00; i < max_loop; i++) {
 766                 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
 767                 if (value & 0x0080)
 768                         break;
 769                 udelay(10);
 770         }
 771         for (i = 0x00; i < 0x0A; i++) {
 772                 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
 773                 if (value & 0x0400)
 774                         break;
 775                 udelay(10);
 776         }
 777         for (i = 0x00; i < 0x19; i++) {
 778                 value = b43_read16(dev, B43_MMIO_IFSSTAT);
 779                 if (!(value & 0x0100))
 780                         break;
 781                 udelay(10);
 782         }
 783         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 784                 b43_radio_write16(dev, 0x0051, 0x0037);
 785 }
 786
 787 static void key_write(struct b43_wldev *dev,
 788                       u8 index, u8 algorithm, const u8 *key)
 789 {
 790         unsigned int i;
 791         u32 offset;
 792         u16 value;
 793         u16 kidx;
 794
 795         /* Key index/algo block */
 796         kidx = b43_kidx_to_fw(dev, index);
 797         value = ((kidx << 4) | algorithm);
 798         b43_shm_write16(dev, B43_SHM_SHARED,
 799                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
 800
 801         /* Write the key to the Key Table Pointer offset */
 802         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
 803         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
 804                 value = key[i];
 805                 value |= (u16) (key[i + 1]) << 8;
 806                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
 807         }
 808 }
 809
 810 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
 811 {
 812         u32 addrtmp[2] = { 0, 0, };
 813         u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
 814
 815         if (b43_new_kidx_api(dev))
 816                 pairwise_keys_start = B43_NR_GROUP_KEYS;
 817
 818         B43_WARN_ON(index < pairwise_keys_start);
 819         /* We have four default TX keys and possibly four default RX keys.
 820          * Physical mac 0 is mapped to physical key 4 or 8, depending
 821          * on the firmware version.
 822          * So we must adjust the index here.
 823          */
 824         index -= pairwise_keys_start;
 825         B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
 826
 827         if (addr) {
 828                 addrtmp[0] = addr[0];
 829                 addrtmp[0] |= ((u32) (addr[1]) << 8);
 830                 addrtmp[0] |= ((u32) (addr[2]) << 16);
 831                 addrtmp[0] |= ((u32) (addr[3]) << 24);
 832                 addrtmp[1] = addr[4];
 833                 addrtmp[1] |= ((u32) (addr[5]) << 8);
 834         }
 835
 836         /* Receive match transmitter address (RCMTA) mechanism */
 837         b43_shm_write32(dev, B43_SHM_RCMTA,
 838                         (index * 2) + 0, addrtmp[0]);
 839         b43_shm_write16(dev, B43_SHM_RCMTA,
 840                         (index * 2) + 1, addrtmp[1]);
 841 }
 842
 843 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
 844  * When a packet is received, the iv32 is checked.
 845  * - if it doesn't the packet is returned without modification (and software
 846  *   decryption can be done). That's what happen when iv16 wrap.
 847  * - if it does, the rc4 key is computed, and decryption is tried.
 848  *   Either it will success and B43_RX_MAC_DEC is returned,
 849  *   either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
 850  *   and the packet is not usable (it got modified by the ucode).
 851  * So in order to never have B43_RX_MAC_DECERR, we should provide
 852  * a iv32 and phase1key that match. Because we drop packets in case of
 853  * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
 854  * packets will be lost without higher layer knowing (ie no resync possible
 855  * until next wrap).
 856  *
 857  * NOTE : this should support 50 key like RCMTA because
 858  * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
 859  */
 860 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
 861                 u16 *phase1key)
 862 {
 863         unsigned int i;
 864         u32 offset;
 865         u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
 866
 867         if (!modparam_hwtkip)
 868                 return;
 869
 870         if (b43_new_kidx_api(dev))
 871                 pairwise_keys_start = B43_NR_GROUP_KEYS;
 872
 873         B43_WARN_ON(index < pairwise_keys_start);
 874         /* We have four default TX keys and possibly four default RX keys.
 875          * Physical mac 0 is mapped to physical key 4 or 8, depending
 876          * on the firmware version.
 877          * So we must adjust the index here.
 878          */
 879         index -= pairwise_keys_start;
 880         B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
 881
 882         if (b43_debug(dev, B43_DBG_KEYS)) {
 883                 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
 884                                 index, iv32);
 885         }
 886         /* Write the key to the  RX tkip shared mem */
 887         offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
 888         for (i = 0; i < 10; i += 2) {
 889                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
 890                                 phase1key ? phase1key[i / 2] : 0);
 891         }
 892         b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
 893         b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
 894 }
 895
 896 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
 897                                    struct ieee80211_vif *vif,
 898                                    struct ieee80211_key_conf *keyconf,
 899                                    struct ieee80211_sta *sta,
 900                                    u32 iv32, u16 *phase1key)
 901 {
 902         struct b43_wl *wl = hw_to_b43_wl(hw);
 903         struct b43_wldev *dev;
 904         int index = keyconf->hw_key_idx;
 905
 906         if (B43_WARN_ON(!modparam_hwtkip))
 907                 return;
 908
 909         /* This is only called from the RX path through mac80211, where
 910          * our mutex is already locked. */
 911         B43_WARN_ON(!mutex_is_locked(&wl->mutex));
 912         dev = wl->current_dev;
 913         B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
 914
 915         keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
 916
 917         rx_tkip_phase1_write(dev, index, iv32, phase1key);
 918         /* only pairwise TKIP keys are supported right now */
 919         if (WARN_ON(!sta))
 920                 return;
 921         keymac_write(dev, index, sta->addr);
 922 }
 923
 924 static void do_key_write(struct b43_wldev *dev,
 925                          u8 index, u8 algorithm,
 926                          const u8 *key, size_t key_len, const u8 *mac_addr)
 927 {
 928         u8 buf[B43_SEC_KEYSIZE] = { 0, };
 929         u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
 930
 931         if (b43_new_kidx_api(dev))
 932                 pairwise_keys_start = B43_NR_GROUP_KEYS;
 933
 934         B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
 935         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
 936
 937         if (index >= pairwise_keys_start)
 938                 keymac_write(dev, index, NULL); /* First zero out mac. */
 939         if (algorithm == B43_SEC_ALGO_TKIP) {
 940                 /*
 941                  * We should provide an initial iv32, phase1key pair.
 942                  * We could start with iv32=0 and compute the corresponding
 943                  * phase1key, but this means calling ieee80211_get_tkip_key
 944                  * with a fake skb (or export other tkip function).
 945                  * Because we are lazy we hope iv32 won't start with
 946                  * 0xffffffff and let's b43_op_update_tkip_key provide a
 947                  * correct pair.
 948                  */
 949                 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
 950         } else if (index >= pairwise_keys_start) /* clear it */
 951                 rx_tkip_phase1_write(dev, index, 0, NULL);
 952         if (key)
 953                 memcpy(buf, key, key_len);
 954         key_write(dev, index, algorithm, buf);
 955         if (index >= pairwise_keys_start)
 956                 keymac_write(dev, index, mac_addr);
 957
 958         dev->key[index].algorithm = algorithm;
 959 }
 960
 961 static int b43_key_write(struct b43_wldev *dev,
 962                          int index, u8 algorithm,
 963                          const u8 *key, size_t key_len,
 964                          const u8 *mac_addr,
 965                          struct ieee80211_key_conf *keyconf)
 966 {
 967         int i;
 968         int pairwise_keys_start;
 969
 970         /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
 971          *      - Temporal Encryption Key (128 bits)
 972          *      - Temporal Authenticator Tx MIC Key (64 bits)
 973          *      - Temporal Authenticator Rx MIC Key (64 bits)
 974          *
 975          *      Hardware only store TEK
 976          */
 977         if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
 978                 key_len = 16;
 979         if (key_len > B43_SEC_KEYSIZE)
 980                 return -EINVAL;
 981         for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
 982                 /* Check that we don't already have this key. */
 983                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
 984         }
 985         if (index < 0) {
 986                 /* Pairwise key. Get an empty slot for the key. */
 987                 if (b43_new_kidx_api(dev))
 988                         pairwise_keys_start = B43_NR_GROUP_KEYS;
 989                 else
 990                         pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
 991                 for (i = pairwise_keys_start;
 992                      i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
 993                      i++) {
 994                         B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
 995                         if (!dev->key[i].keyconf) {
 996                                 /* found empty */
 997                                 index = i;
 998                                 break;
 999                         }
1000                 }
1001                 if (index < 0) {
1002                         b43warn(dev->wl, "Out of hardware key memory\n");
1003                         return -ENOSPC;
1004                 }
1005         } else
1006                 B43_WARN_ON(index > 3);
1007
1008         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1009         if ((index <= 3) && !b43_new_kidx_api(dev)) {
1010                 /* Default RX key */
1011                 B43_WARN_ON(mac_addr);
1012                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1013         }
1014         keyconf->hw_key_idx = index;
1015         dev->key[index].keyconf = keyconf;
1016
1017         return 0;
1018 }
1019
1020 static int b43_key_clear(struct b43_wldev *dev, int index)
1021 {
1022         if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1023                 return -EINVAL;
1024         do_key_write(dev, index, B43_SEC_ALGO_NONE,
1025                      NULL, B43_SEC_KEYSIZE, NULL);
1026         if ((index <= 3) && !b43_new_kidx_api(dev)) {
1027                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1028                              NULL, B43_SEC_KEYSIZE, NULL);
1029         }
1030         dev->key[index].keyconf = NULL;
1031
1032         return 0;
1033 }
1034
1035 static void b43_clear_keys(struct b43_wldev *dev)
1036 {
1037         int i, count;
1038
1039         if (b43_new_kidx_api(dev))
1040                 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1041         else
1042                 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1043         for (i = 0; i < count; i++)
1044                 b43_key_clear(dev, i);
1045 }
1046
1047 static void b43_dump_keymemory(struct b43_wldev *dev)
1048 {
1049         unsigned int i, index, count, offset, pairwise_keys_start;
1050         u8 mac[ETH_ALEN];
1051         u16 algo;
1052         u32 rcmta0;
1053         u16 rcmta1;
1054         u64 hf;
1055         struct b43_key *key;
1056
1057         if (!b43_debug(dev, B43_DBG_KEYS))
1058                 return;
1059
1060         hf = b43_hf_read(dev);
1061         b43dbg(dev->wl, "Hardware key memory dump:  USEDEFKEYS=%u\n",
1062                !!(hf & B43_HF_USEDEFKEYS));
1063         if (b43_new_kidx_api(dev)) {
1064                 pairwise_keys_start = B43_NR_GROUP_KEYS;
1065                 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1066         } else {
1067                 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1068                 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1069         }
1070         for (index = 0; index < count; index++) {
1071                 key = &(dev->key[index]);
1072                 printk(KERN_DEBUG "Key slot %02u: %s",
1073                        index, (key->keyconf == NULL) ? " " : "*");
1074                 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1075                 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1076                         u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1077                         printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1078                 }
1079
1080                 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1081                                       B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1082                 printk("   Algo: %04X/%02X", algo, key->algorithm);
1083
1084                 if (index >= pairwise_keys_start) {
1085                         if (key->algorithm == B43_SEC_ALGO_TKIP) {
1086                                 printk("   TKIP: ");
1087                                 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1088                                 for (i = 0; i < 14; i += 2) {
1089                                         u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1090                                         printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1091                                 }
1092                         }
1093                         rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1094                                                 ((index - pairwise_keys_start) * 2) + 0);
1095                         rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1096                                                 ((index - pairwise_keys_start) * 2) + 1);
1097                         *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1098                         *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1099                         printk("   MAC: %pM", mac);
1100                 } else
1101                         printk("   DEFAULT KEY");
1102                 printk("\n");
1103         }
1104 }
1105
1106 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1107 {
1108         u32 macctl;
1109         u16 ucstat;
1110         bool hwps;
1111         bool awake;
1112         int i;
1113
1114         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1115                     (ps_flags & B43_PS_DISABLED));
1116         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1117
1118         if (ps_flags & B43_PS_ENABLED) {
1119                 hwps = true;
1120         } else if (ps_flags & B43_PS_DISABLED) {
1121                 hwps = false;
1122         } else {
1123                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1124                 //      and thus is not an AP and we are associated, set bit 25
1125         }
1126         if (ps_flags & B43_PS_AWAKE) {
1127                 awake = true;
1128         } else if (ps_flags & B43_PS_ASLEEP) {
1129                 awake = false;
1130         } else {
1131                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1132                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
1133                 //      successful, set bit26
1134         }
1135
1136 /* FIXME: For now we force awake-on and hwps-off */
1137         hwps = false;
1138         awake = true;
1139
1140         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1141         if (hwps)
1142                 macctl |= B43_MACCTL_HWPS;
1143         else
1144                 macctl &= ~B43_MACCTL_HWPS;
1145         if (awake)
1146                 macctl |= B43_MACCTL_AWAKE;
1147         else
1148                 macctl &= ~B43_MACCTL_AWAKE;
1149         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1150         /* Commit write */
1151         b43_read32(dev, B43_MMIO_MACCTL);
1152         if (awake && dev->dev->core_rev >= 5) {
1153                 /* Wait for the microcode to wake up. */
1154                 for (i = 0; i < 100; i++) {
1155                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1156                                                 B43_SHM_SH_UCODESTAT);
1157                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1158                                 break;
1159                         udelay(10);
1160                 }
1161         }
1162 }
1163
1164 #ifdef CONFIG_B43_BCMA
1165 static void b43_bcma_phy_reset(struct b43_wldev *dev)
1166 {
1167         u32 flags;
1168
1169         /* Put PHY into reset */
1170         flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1171         flags |= B43_BCMA_IOCTL_PHY_RESET;
1172         flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1173         bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1174         udelay(2);
1175
1176         /* Take PHY out of reset */
1177         flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1178         flags &= ~B43_BCMA_IOCTL_PHY_RESET;
1179         flags |= BCMA_IOCTL_FGC;
1180         bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1181         udelay(1);
1182
1183         /* Do not force clock anymore */
1184         flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1185         flags &= ~BCMA_IOCTL_FGC;
1186         bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1187         udelay(1);
1188 }
1189
1190 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1191 {
1192         b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1193         bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1194         b43_bcma_phy_reset(dev);
1195         bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true);
1196 }
1197 #endif
1198
1199 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1200 {
1201         struct ssb_device *sdev = dev->dev->sdev;
1202         u32 tmslow;
1203         u32 flags = 0;
1204
1205         if (gmode)
1206                 flags |= B43_TMSLOW_GMODE;
1207         flags |= B43_TMSLOW_PHYCLKEN;
1208         flags |= B43_TMSLOW_PHYRESET;
1209         if (dev->phy.type == B43_PHYTYPE_N)
1210                 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1211         b43_device_enable(dev, flags);
1212         msleep(2);              /* Wait for the PLL to turn on. */
1213
1214         /* Now take the PHY out of Reset again */
1215         tmslow = ssb_read32(sdev, SSB_TMSLOW);
1216         tmslow |= SSB_TMSLOW_FGC;
1217         tmslow &= ~B43_TMSLOW_PHYRESET;
1218         ssb_write32(sdev, SSB_TMSLOW, tmslow);
1219         ssb_read32(sdev, SSB_TMSLOW);   /* flush */
1220         msleep(1);
1221         tmslow &= ~SSB_TMSLOW_FGC;
1222         ssb_write32(sdev, SSB_TMSLOW, tmslow);
1223         ssb_read32(sdev, SSB_TMSLOW);   /* flush */
1224         msleep(1);
1225 }
1226
1227 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1228 {
1229         u32 macctl;
1230
1231         switch (dev->dev->bus_type) {
1232 #ifdef CONFIG_B43_BCMA
1233         case B43_BUS_BCMA:
1234                 b43_bcma_wireless_core_reset(dev, gmode);
1235                 break;
1236 #endif
1237 #ifdef CONFIG_B43_SSB
1238         case B43_BUS_SSB:
1239                 b43_ssb_wireless_core_reset(dev, gmode);
1240                 break;
1241 #endif
1242         }
1243
1244         /* Turn Analog ON, but only if we already know the PHY-type.
1245          * This protects against very early setup where we don't know the
1246          * PHY-type, yet. wireless_core_reset will be called once again later,
1247          * when we know the PHY-type. */
1248         if (dev->phy.ops)
1249                 dev->phy.ops->switch_analog(dev, 1);
1250
1251         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1252         macctl &= ~B43_MACCTL_GMODE;
1253         if (gmode)
1254                 macctl |= B43_MACCTL_GMODE;
1255         macctl |= B43_MACCTL_IHR_ENABLED;
1256         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1257 }
1258
1259 static void handle_irq_transmit_status(struct b43_wldev *dev)
1260 {
1261         u32 v0, v1;
1262         u16 tmp;
1263         struct b43_txstatus stat;
1264
1265         while (1) {
1266                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1267                 if (!(v0 & 0x00000001))
1268                         break;
1269                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1270
1271                 stat.cookie = (v0 >> 16);
1272                 stat.seq = (v1 & 0x0000FFFF);
1273                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1274                 tmp = (v0 & 0x0000FFFF);
1275                 stat.frame_count = ((tmp & 0xF000) >> 12);
1276                 stat.rts_count = ((tmp & 0x0F00) >> 8);
1277                 stat.supp_reason = ((tmp & 0x001C) >> 2);
1278                 stat.pm_indicated = !!(tmp & 0x0080);
1279                 stat.intermediate = !!(tmp & 0x0040);
1280                 stat.for_ampdu = !!(tmp & 0x0020);
1281                 stat.acked = !!(tmp & 0x0002);
1282
1283                 b43_handle_txstatus(dev, &stat);
1284         }
1285 }
1286
1287 static void drain_txstatus_queue(struct b43_wldev *dev)
1288 {
1289         u32 dummy;
1290
1291         if (dev->dev->core_rev < 5)
1292                 return;
1293         /* Read all entries from the microcode TXstatus FIFO
1294          * and throw them away.
1295          */
1296         while (1) {
1297                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1298                 if (!(dummy & 0x00000001))
1299                         break;
1300                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1301         }
1302 }
1303
1304 static u32 b43_jssi_read(struct b43_wldev *dev)
1305 {
1306         u32 val = 0;
1307
1308         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1309         val <<= 16;
1310         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1311
1312         return val;
1313 }
1314
1315 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1316 {
1317         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1318         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1319 }
1320
1321 static void b43_generate_noise_sample(struct b43_wldev *dev)
1322 {
1323         b43_jssi_write(dev, 0x7F7F7F7F);
1324         b43_write32(dev, B43_MMIO_MACCMD,
1325                     b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1326 }
1327
1328 static void b43_calculate_link_quality(struct b43_wldev *dev)
1329 {
1330         /* Top half of Link Quality calculation. */
1331
1332         if (dev->phy.type != B43_PHYTYPE_G)
1333                 return;
1334         if (dev->noisecalc.calculation_running)
1335                 return;
1336         dev->noisecalc.calculation_running = true;
1337         dev->noisecalc.nr_samples = 0;
1338
1339         b43_generate_noise_sample(dev);
1340 }
1341
1342 static void handle_irq_noise(struct b43_wldev *dev)
1343 {
1344         struct b43_phy_g *phy = dev->phy.g;
1345         u16 tmp;
1346         u8 noise[4];
1347         u8 i, j;
1348         s32 average;
1349
1350         /* Bottom half of Link Quality calculation. */
1351
1352         if (dev->phy.type != B43_PHYTYPE_G)
1353                 return;
1354
1355         /* Possible race condition: It might be possible that the user
1356          * changed to a different channel in the meantime since we
1357          * started the calculation. We ignore that fact, since it's
1358          * not really that much of a problem. The background noise is
1359          * an estimation only anyway. Slightly wrong results will get damped
1360          * by the averaging of the 8 sample rounds. Additionally the
1361          * value is shortlived. So it will be replaced by the next noise
1362          * calculation round soon. */
1363
1364         B43_WARN_ON(!dev->noisecalc.calculation_running);
1365         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1366         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1367             noise[2] == 0x7F || noise[3] == 0x7F)
1368                 goto generate_new;
1369
1370         /* Get the noise samples. */
1371         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1372         i = dev->noisecalc.nr_samples;
1373         noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1374         noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1375         noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1376         noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1377         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1378         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1379         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1380         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1381         dev->noisecalc.nr_samples++;
1382         if (dev->noisecalc.nr_samples == 8) {
1383                 /* Calculate the Link Quality by the noise samples. */
1384                 average = 0;
1385                 for (i = 0; i < 8; i++) {
1386                         for (j = 0; j < 4; j++)
1387                                 average += dev->noisecalc.samples[i][j];
1388                 }
1389                 average /= (8 * 4);
1390                 average *= 125;
1391                 average += 64;
1392                 average /= 128;
1393                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1394                 tmp = (tmp / 128) & 0x1F;
1395                 if (tmp >= 8)
1396                         average += 2;
1397                 else
1398                         average -= 25;
1399                 if (tmp == 8)
1400                         average -= 72;
1401                 else
1402                         average -= 48;
1403
1404                 dev->stats.link_noise = average;
1405                 dev->noisecalc.calculation_running = false;
1406                 return;
1407         }
1408 generate_new:
1409         b43_generate_noise_sample(dev);
1410 }
1411
1412 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1413 {
1414         if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1415                 ///TODO: PS TBTT
1416         } else {
1417                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1418                         b43_power_saving_ctl_bits(dev, 0);
1419         }
1420         if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1421                 dev->dfq_valid = true;
1422 }
1423
1424 static void handle_irq_atim_end(struct b43_wldev *dev)
1425 {
1426         if (dev->dfq_valid) {
1427                 b43_write32(dev, B43_MMIO_MACCMD,
1428                             b43_read32(dev, B43_MMIO_MACCMD)
1429                             | B43_MACCMD_DFQ_VALID);
1430                 dev->dfq_valid = false;
1431         }
1432 }
1433
1434 static void handle_irq_pmq(struct b43_wldev *dev)
1435 {
1436         u32 tmp;
1437
1438         //TODO: AP mode.
1439
1440         while (1) {
1441                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1442                 if (!(tmp & 0x00000008))
1443                         break;
1444         }
1445         /* 16bit write is odd, but correct. */
1446         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1447 }
1448
1449 static void b43_write_template_common(struct b43_wldev *dev,
1450                                       const u8 *data, u16 size,
1451                                       u16 ram_offset,
1452                                       u16 shm_size_offset, u8 rate)
1453 {
1454         u32 i, tmp;
1455         struct b43_plcp_hdr4 plcp;
1456
1457         plcp.data = 0;
1458         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1459         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1460         ram_offset += sizeof(u32);
1461         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1462          * So leave the first two bytes of the next write blank.
1463          */
1464         tmp = (u32) (data[0]) << 16;
1465         tmp |= (u32) (data[1]) << 24;
1466         b43_ram_write(dev, ram_offset, tmp);
1467         ram_offset += sizeof(u32);
1468         for (i = 2; i < size; i += sizeof(u32)) {
1469                 tmp = (u32) (data[i + 0]);
1470                 if (i + 1 < size)
1471                         tmp |= (u32) (data[i + 1]) << 8;
1472                 if (i + 2 < size)
1473                         tmp |= (u32) (data[i + 2]) << 16;
1474                 if (i + 3 < size)
1475                         tmp |= (u32) (data[i + 3]) << 24;
1476                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1477         }
1478         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1479                         size + sizeof(struct b43_plcp_hdr6));
1480 }
1481
1482 /* Check if the use of the antenna that ieee80211 told us to
1483  * use is possible. This will fall back to DEFAULT.
1484  * "antenna_nr" is the antenna identifier we got from ieee80211. */
1485 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1486                                   u8 antenna_nr)
1487 {
1488         u8 antenna_mask;
1489
1490         if (antenna_nr == 0) {
1491                 /* Zero means "use default antenna". That's always OK. */
1492                 return 0;
1493         }
1494
1495         /* Get the mask of available antennas. */
1496         if (dev->phy.gmode)
1497                 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1498         else
1499                 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1500
1501         if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1502                 /* This antenna is not available. Fall back to default. */
1503                 return 0;
1504         }
1505
1506         return antenna_nr;
1507 }
1508
1509 /* Convert a b43 antenna number value to the PHY TX control value. */
1510 static u16 b43_antenna_to_phyctl(int antenna)
1511 {
1512         switch (antenna) {
1513         case B43_ANTENNA0:
1514                 return B43_TXH_PHY_ANT0;
1515         case B43_ANTENNA1:
1516                 return B43_TXH_PHY_ANT1;
1517         case B43_ANTENNA2:
1518                 return B43_TXH_PHY_ANT2;
1519         case B43_ANTENNA3:
1520                 return B43_TXH_PHY_ANT3;
1521         case B43_ANTENNA_AUTO0:
1522         case B43_ANTENNA_AUTO1:
1523                 return B43_TXH_PHY_ANT01AUTO;
1524         }
1525         B43_WARN_ON(1);
1526         return 0;
1527 }
1528
1529 static void b43_write_beacon_template(struct b43_wldev *dev,
1530                                       u16 ram_offset,
1531                                       u16 shm_size_offset)
1532 {
1533         unsigned int i, len, variable_len;
1534         const struct ieee80211_mgmt *bcn;
1535         const u8 *ie;
1536         bool tim_found = false;
1537         unsigned int rate;
1538         u16 ctl;
1539         int antenna;
1540         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1541
1542         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1543         len = min((size_t) dev->wl->current_beacon->len,
1544                   0x200 - sizeof(struct b43_plcp_hdr6));
1545         rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1546
1547         b43_write_template_common(dev, (const u8 *)bcn,
1548                                   len, ram_offset, shm_size_offset, rate);
1549
1550         /* Write the PHY TX control parameters. */
1551         antenna = B43_ANTENNA_DEFAULT;
1552         antenna = b43_antenna_to_phyctl(antenna);
1553         ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1554         /* We can't send beacons with short preamble. Would get PHY errors. */
1555         ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1556         ctl &= ~B43_TXH_PHY_ANT;
1557         ctl &= ~B43_TXH_PHY_ENC;
1558         ctl |= antenna;
1559         if (b43_is_cck_rate(rate))
1560                 ctl |= B43_TXH_PHY_ENC_CCK;
1561         else
1562                 ctl |= B43_TXH_PHY_ENC_OFDM;
1563         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1564
1565         /* Find the position of the TIM and the DTIM_period value
1566          * and write them to SHM. */
1567         ie = bcn->u.beacon.variable;
1568         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1569         for (i = 0; i < variable_len - 2; ) {
1570                 uint8_t ie_id, ie_len;
1571
1572                 ie_id = ie[i];
1573                 ie_len = ie[i + 1];
1574                 if (ie_id == 5) {
1575                         u16 tim_position;
1576                         u16 dtim_period;
1577                         /* This is the TIM Information Element */
1578
1579                         /* Check whether the ie_len is in the beacon data range. */
1580                         if (variable_len < ie_len + 2 + i)
1581                                 break;
1582                         /* A valid TIM is at least 4 bytes long. */
1583                         if (ie_len < 4)
1584                                 break;
1585                         tim_found = true;
1586
1587                         tim_position = sizeof(struct b43_plcp_hdr6);
1588                         tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1589                         tim_position += i;
1590
1591                         dtim_period = ie[i + 3];
1592
1593                         b43_shm_write16(dev, B43_SHM_SHARED,
1594                                         B43_SHM_SH_TIMBPOS, tim_position);
1595                         b43_shm_write16(dev, B43_SHM_SHARED,
1596                                         B43_SHM_SH_DTIMPER, dtim_period);
1597                         break;
1598                 }
1599                 i += ie_len + 2;
1600         }
1601         if (!tim_found) {
1602                 /*
1603                  * If ucode wants to modify TIM do it behind the beacon, this
1604                  * will happen, for example, when doing mesh networking.
1605                  */
1606                 b43_shm_write16(dev, B43_SHM_SHARED,
1607                                 B43_SHM_SH_TIMBPOS,
1608                                 len + sizeof(struct b43_plcp_hdr6));
1609                 b43_shm_write16(dev, B43_SHM_SHARED,
1610                                 B43_SHM_SH_DTIMPER, 0);
1611         }
1612         b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1613 }
1614
1615 static void b43_upload_beacon0(struct b43_wldev *dev)
1616 {
1617         struct b43_wl *wl = dev->wl;
1618
1619         if (wl->beacon0_uploaded)
1620                 return;
1621         b43_write_beacon_template(dev, 0x68, 0x18);
1622         wl->beacon0_uploaded = true;
1623 }
1624
1625 static void b43_upload_beacon1(struct b43_wldev *dev)
1626 {
1627         struct b43_wl *wl = dev->wl;
1628
1629         if (wl->beacon1_uploaded)
1630                 return;
1631         b43_write_beacon_template(dev, 0x468, 0x1A);
1632         wl->beacon1_uploaded = true;
1633 }
1634
1635 static void handle_irq_beacon(struct b43_wldev *dev)
1636 {
1637         struct b43_wl *wl = dev->wl;
1638         u32 cmd, beacon0_valid, beacon1_valid;
1639
1640         if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1641             !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1642             !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
1643                 return;
1644
1645         /* This is the bottom half of the asynchronous beacon update. */
1646
1647         /* Ignore interrupt in the future. */
1648         dev->irq_mask &= ~B43_IRQ_BEACON;
1649
1650         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1651         beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1652         beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1653
1654         /* Schedule interrupt manually, if busy. */
1655         if (beacon0_valid && beacon1_valid) {
1656                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1657                 dev->irq_mask |= B43_IRQ_BEACON;
1658                 return;
1659         }
1660
1661         if (unlikely(wl->beacon_templates_virgin)) {
1662                 /* We never uploaded a beacon before.
1663                  * Upload both templates now, but only mark one valid. */
1664                 wl->beacon_templates_virgin = false;
1665                 b43_upload_beacon0(dev);
1666                 b43_upload_beacon1(dev);
1667                 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1668                 cmd |= B43_MACCMD_BEACON0_VALID;
1669                 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1670         } else {
1671                 if (!beacon0_valid) {
1672                         b43_upload_beacon0(dev);
1673                         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1674                         cmd |= B43_MACCMD_BEACON0_VALID;
1675                         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1676                 } else if (!beacon1_valid) {
1677                         b43_upload_beacon1(dev);
1678                         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1679                         cmd |= B43_MACCMD_BEACON1_VALID;
1680                         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1681                 }
1682         }
1683 }
1684
1685 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1686 {
1687         u32 old_irq_mask = dev->irq_mask;
1688
1689         /* update beacon right away or defer to irq */
1690         handle_irq_beacon(dev);
1691         if (old_irq_mask != dev->irq_mask) {
1692                 /* The handler updated the IRQ mask. */
1693                 B43_WARN_ON(!dev->irq_mask);
1694                 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1695                         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1696                 } else {
1697                         /* Device interrupts are currently disabled. That means
1698                          * we just ran the hardirq handler and scheduled the
1699                          * IRQ thread. The thread will write the IRQ mask when
1700                          * it finished, so there's nothing to do here. Writing
1701                          * the mask _here_ would incorrectly re-enable IRQs. */
1702                 }
1703         }
1704 }
1705
1706 static void b43_beacon_update_trigger_work(struct work_struct *work)
1707 {
1708         struct b43_wl *wl = container_of(work, struct b43_wl,
1709                                          beacon_update_trigger);
1710         struct b43_wldev *dev;
1711
1712         mutex_lock(&wl->mutex);
1713         dev = wl->current_dev;
1714         if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1715                 if (b43_bus_host_is_sdio(dev->dev)) {
1716                         /* wl->mutex is enough. */
1717                         b43_do_beacon_update_trigger_work(dev);
1718                         mmiowb();
1719                 } else {
1720                         spin_lock_irq(&wl->hardirq_lock);
1721                         b43_do_beacon_update_trigger_work(dev);
1722                         mmiowb();
1723                         spin_unlock_irq(&wl->hardirq_lock);
1724                 }
1725         }
1726         mutex_unlock(&wl->mutex);
1727 }
1728
1729 /* Asynchronously update the packet templates in template RAM.
1730  * Locking: Requires wl->mutex to be locked. */
1731 static void b43_update_templates(struct b43_wl *wl)
1732 {
1733         struct sk_buff *beacon;
1734
1735         /* This is the top half of the ansynchronous beacon update.
1736          * The bottom half is the beacon IRQ.
1737          * Beacon update must be asynchronous to avoid sending an
1738          * invalid beacon. This can happen for example, if the firmware
1739          * transmits a beacon while we are updating it. */
1740
1741         /* We could modify the existing beacon and set the aid bit in
1742          * the TIM field, but that would probably require resizing and
1743          * moving of data within the beacon template.
1744          * Simply request a new beacon and let mac80211 do the hard work. */
1745         beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1746         if (unlikely(!beacon))
1747                 return;
1748
1749         if (wl->current_beacon)
1750                 dev_kfree_skb_any(wl->current_beacon);
1751         wl->current_beacon = beacon;
1752         wl->beacon0_uploaded = false;
1753         wl->beacon1_uploaded = false;
1754         ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1755 }
1756
1757 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1758 {
1759         b43_time_lock(dev);
1760         if (dev->dev->core_rev >= 3) {
1761                 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1762                 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1763         } else {
1764                 b43_write16(dev, 0x606, (beacon_int >> 6));
1765                 b43_write16(dev, 0x610, beacon_int);
1766         }
1767         b43_time_unlock(dev);
1768         b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1769 }
1770
1771 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1772 {
1773         u16 reason;
1774
1775         /* Read the register that contains the reason code for the panic. */
1776         reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1777         b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1778
1779         switch (reason) {
1780         default:
1781                 b43dbg(dev->wl, "The panic reason is unknown.\n");
1782                 /* fallthrough */
1783         case B43_FWPANIC_DIE:
1784                 /* Do not restart the controller or firmware.
1785                  * The device is nonfunctional from now on.
1786                  * Restarting would result in this panic to trigger again,
1787                  * so we avoid that recursion. */
1788                 break;
1789         case B43_FWPANIC_RESTART:
1790                 b43_controller_restart(dev, "Microcode panic");
1791                 break;
1792         }
1793 }
1794
1795 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1796 {
1797         unsigned int i, cnt;
1798         u16 reason, marker_id, marker_line;
1799         __le16 *buf;
1800
1801         /* The proprietary firmware doesn't have this IRQ. */
1802         if (!dev->fw.opensource)
1803                 return;
1804
1805         /* Read the register that contains the reason code for this IRQ. */
1806         reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1807
1808         switch (reason) {
1809         case B43_DEBUGIRQ_PANIC:
1810                 b43_handle_firmware_panic(dev);
1811                 break;
1812         case B43_DEBUGIRQ_DUMP_SHM:
1813                 if (!B43_DEBUG)
1814                         break; /* Only with driver debugging enabled. */
1815                 buf = kmalloc(4096, GFP_ATOMIC);
1816                 if (!buf) {
1817                         b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1818                         goto out;
1819                 }
1820                 for (i = 0; i < 4096; i += 2) {
1821                         u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1822                         buf[i / 2] = cpu_to_le16(tmp);
1823                 }
1824                 b43info(dev->wl, "Shared memory dump:\n");
1825                 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1826                                16, 2, buf, 4096, 1);
1827                 kfree(buf);
1828                 break;
1829         case B43_DEBUGIRQ_DUMP_REGS:
1830                 if (!B43_DEBUG)
1831                         break; /* Only with driver debugging enabled. */
1832                 b43info(dev->wl, "Microcode register dump:\n");
1833                 for (i = 0, cnt = 0; i < 64; i++) {
1834                         u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1835                         if (cnt == 0)
1836                                 printk(KERN_INFO);
1837                         printk("r%02u: 0x%04X  ", i, tmp);
1838                         cnt++;
1839                         if (cnt == 6) {
1840                                 printk("\n");
1841                                 cnt = 0;
1842                         }
1843                 }
1844                 printk("\n");
1845                 break;
1846         case B43_DEBUGIRQ_MARKER:
1847                 if (!B43_DEBUG)
1848                         break; /* Only with driver debugging enabled. */
1849                 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1850                                            B43_MARKER_ID_REG);
1851                 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1852                                              B43_MARKER_LINE_REG);
1853                 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1854                         "at line number %u\n",
1855                         marker_id, marker_line);
1856                 break;
1857         default:
1858                 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1859                        reason);
1860         }
1861 out:
1862         /* Acknowledge the debug-IRQ, so the firmware can continue. */
1863         b43_shm_write16(dev, B43_SHM_SCRATCH,
1864                         B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1865 }
1866
1867 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1868 {
1869         u32 reason;
1870         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1871         u32 merged_dma_reason = 0;
1872         int i;
1873
1874         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1875                 return;
1876
1877         reason = dev->irq_reason;
1878         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1879                 dma_reason[i] = dev->dma_reason[i];
1880                 merged_dma_reason |= dma_reason[i];
1881         }
1882
1883         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1884                 b43err(dev->wl, "MAC transmission error\n");
1885
1886         if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1887                 b43err(dev->wl, "PHY transmission error\n");
1888                 rmb();
1889                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1890                         atomic_set(&dev->phy.txerr_cnt,
1891                                    B43_PHY_TX_BADNESS_LIMIT);
1892                         b43err(dev->wl, "Too many PHY TX errors, "
1893                                         "restarting the controller\n");
1894                         b43_controller_restart(dev, "PHY TX errors");
1895                 }
1896         }
1897
1898         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1899                                           B43_DMAIRQ_NONFATALMASK))) {
1900                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1901                         b43err(dev->wl, "Fatal DMA error: "
1902                                "0x%08X, 0x%08X, 0x%08X, "
1903                                "0x%08X, 0x%08X, 0x%08X\n",
1904                                dma_reason[0], dma_reason[1],
1905                                dma_reason[2], dma_reason[3],
1906                                dma_reason[4], dma_reason[5]);
1907                         b43err(dev->wl, "This device does not support DMA "
1908                                "on your system. It will now be switched to PIO.\n");
1909                         /* Fall back to PIO transfers if we get fatal DMA errors! */
1910                         dev->use_pio = true;
1911                         b43_controller_restart(dev, "DMA error");
1912                         return;
1913                 }
1914                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1915                         b43err(dev->wl, "DMA error: "
1916                                "0x%08X, 0x%08X, 0x%08X, "
1917                                "0x%08X, 0x%08X, 0x%08X\n",
1918                                dma_reason[0], dma_reason[1],
1919                                dma_reason[2], dma_reason[3],
1920                                dma_reason[4], dma_reason[5]);
1921                 }
1922         }
1923
1924         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1925                 handle_irq_ucode_debug(dev);
1926         if (reason & B43_IRQ_TBTT_INDI)
1927                 handle_irq_tbtt_indication(dev);
1928         if (reason & B43_IRQ_ATIM_END)
1929                 handle_irq_atim_end(dev);
1930         if (reason & B43_IRQ_BEACON)
1931                 handle_irq_beacon(dev);
1932         if (reason & B43_IRQ_PMQ)
1933                 handle_irq_pmq(dev);
1934         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1935                 ;/* TODO */
1936         if (reason & B43_IRQ_NOISESAMPLE_OK)
1937                 handle_irq_noise(dev);
1938
1939         /* Check the DMA reason registers for received data. */
1940         if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1941                 if (b43_using_pio_transfers(dev))
1942                         b43_pio_rx(dev->pio.rx_queue);
1943                 else
1944                         b43_dma_rx(dev->dma.rx_ring);
1945         }
1946         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1947         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1948         B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1949         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1950         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1951
1952         if (reason & B43_IRQ_TX_OK)
1953                 handle_irq_transmit_status(dev);
1954
1955         /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1956         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1957
1958 #if B43_DEBUG
1959         if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1960                 dev->irq_count++;
1961                 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1962                         if (reason & (1 << i))
1963                                 dev->irq_bit_count[i]++;
1964                 }
1965         }
1966 #endif
1967 }
1968
1969 /* Interrupt thread handler. Handles device interrupts in thread context. */
1970 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1971 {
1972         struct b43_wldev *dev = dev_id;
1973
1974         mutex_lock(&dev->wl->mutex);
1975         b43_do_interrupt_thread(dev);
1976         mmiowb();
1977         mutex_unlock(&dev->wl->mutex);
1978
1979         return IRQ_HANDLED;
1980 }
1981
1982 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1983 {
1984         u32 reason;
1985
1986         /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1987          * On SDIO, this runs under wl->mutex. */
1988
1989         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1990         if (reason == 0xffffffff)       /* shared IRQ */
1991                 return IRQ_NONE;
1992         reason &= dev->irq_mask;
1993         if (!reason)
1994                 return IRQ_NONE;
1995
1996         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1997             & 0x0001DC00;
1998         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1999             & 0x0000DC00;
2000         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2001             & 0x0000DC00;
2002         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2003             & 0x0001DC00;
2004         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2005             & 0x0000DC00;
2006 /* Unused ring
2007         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2008             & 0x0000DC00;
2009 */
2010
2011         /* ACK the interrupt. */
2012         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2013         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2014         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2015         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2016         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2017         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2018 /* Unused ring
2019         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2020 */
2021
2022         /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2023         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2024         /* Save the reason bitmasks for the IRQ thread handler. */
2025         dev->irq_reason = reason;
2026
2027         return IRQ_WAKE_THREAD;
2028 }
2029
2030 /* Interrupt handler top-half. This runs with interrupts disabled. */
2031 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2032 {
2033         struct b43_wldev *dev = dev_id;
2034         irqreturn_t ret;
2035
2036         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2037                 return IRQ_NONE;
2038
2039         spin_lock(&dev->wl->hardirq_lock);
2040         ret = b43_do_interrupt(dev);
2041         mmiowb();
2042         spin_unlock(&dev->wl->hardirq_lock);
2043
2044         return ret;
2045 }
2046
2047 /* SDIO interrupt handler. This runs in process context. */
2048 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2049 {
2050         struct b43_wl *wl = dev->wl;
2051         irqreturn_t ret;
2052
2053         mutex_lock(&wl->mutex);
2054
2055         ret = b43_do_interrupt(dev);
2056         if (ret == IRQ_WAKE_THREAD)
2057                 b43_do_interrupt_thread(dev);
2058
2059         mutex_unlock(&wl->mutex);
2060 }
2061
2062 void b43_do_release_fw(struct b43_firmware_file *fw)
2063 {
2064         release_firmware(fw->data);
2065         fw->data = NULL;
2066         fw->filename = NULL;
2067 }
2068
2069 static void b43_release_firmware(struct b43_wldev *dev)
2070 {
2071         b43_do_release_fw(&dev->fw.ucode);
2072         b43_do_release_fw(&dev->fw.pcm);
2073         b43_do_release_fw(&dev->fw.initvals);
2074         b43_do_release_fw(&dev->fw.initvals_band);
2075 }
2076
2077 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2078 {
2079         const char text[] =
2080                 "Please open a terminal and enter the command " \
2081                 "\"sudo /usr/sbin/install_bcm43xx_firmware\" to download " \
2082                 "the correct firmware for this driver version. " \
2083                 "For an off-line installation, go to " \
2084                 "http://en.opensuse.org/HCL/Network_Adapters_(Wireless)/" \
2085                 "Broadcom_BCM43xx and follow the instructions in the " \
2086                 "\"Installing firmware from RPM packages\" section.\n";
2087
2088         if (error)
2089                 b43err(wl, text);
2090         else
2091                 b43warn(wl, text);
2092 }
2093
2094 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2095                       const char *name,
2096                       struct b43_firmware_file *fw)
2097 {
2098         const struct firmware *blob;
2099         struct b43_fw_header *hdr;
2100         u32 size;
2101         int err;
2102
2103         if (!name) {
2104                 /* Don't fetch anything. Free possibly cached firmware. */
2105                 /* FIXME: We should probably keep it anyway, to save some headache
2106                  * on suspend/resume with multiband devices. */
2107                 b43_do_release_fw(fw);
2108                 return 0;
2109         }
2110         if (fw->filename) {
2111                 if ((fw->type == ctx->req_type) &&
2112                     (strcmp(fw->filename, name) == 0))
2113                         return 0; /* Already have this fw. */
2114                 /* Free the cached firmware first. */
2115                 /* FIXME: We should probably do this later after we successfully
2116                  * got the new fw. This could reduce headache with multiband devices.
2117                  * We could also redesign this to cache the firmware for all possible
2118                  * bands all the time. */
2119                 b43_do_release_fw(fw);
2120         }
2121
2122         switch (ctx->req_type) {
2123         case B43_FWTYPE_PROPRIETARY:
2124                 snprintf(ctx->fwname, sizeof(ctx->fwname),
2125                          "b43%s/%s.fw",
2126                          modparam_fwpostfix, name);
2127                 break;
2128         case B43_FWTYPE_OPENSOURCE:
2129                 snprintf(ctx->fwname, sizeof(ctx->fwname),
2130                          "b43-open%s/%s.fw",
2131                          modparam_fwpostfix, name);
2132                 break;
2133         default:
2134                 B43_WARN_ON(1);
2135                 return -ENOSYS;
2136         }
2137         err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2138         if (err == -ENOENT) {
2139                 snprintf(ctx->errors[ctx->req_type],
2140                          sizeof(ctx->errors[ctx->req_type]),
2141                          "Firmware file \"%s\" not found\n", ctx->fwname);
2142                 return err;
2143         } else if (err) {
2144                 snprintf(ctx->errors[ctx->req_type],
2145                          sizeof(ctx->errors[ctx->req_type]),
2146                          "Firmware file \"%s\" request failed (err=%d)\n",
2147                          ctx->fwname, err);
2148                 return err;
2149         }
2150         if (blob->size < sizeof(struct b43_fw_header))
2151                 goto err_format;
2152         hdr = (struct b43_fw_header *)(blob->data);
2153         switch (hdr->type) {
2154         case B43_FW_TYPE_UCODE:
2155         case B43_FW_TYPE_PCM:
2156                 size = be32_to_cpu(hdr->size);
2157                 if (size != blob->size - sizeof(struct b43_fw_header))
2158                         goto err_format;
2159                 /* fallthrough */
2160         case B43_FW_TYPE_IV:
2161                 if (hdr->ver != 1)
2162                         goto err_format;
2163                 break;
2164         default:
2165                 goto err_format;
2166         }
2167
2168         fw->data = blob;
2169         fw->filename = name;
2170         fw->type = ctx->req_type;
2171
2172         return 0;
2173
2174 err_format:
2175         snprintf(ctx->errors[ctx->req_type],
2176                  sizeof(ctx->errors[ctx->req_type]),
2177                  "Firmware file \"%s\" format error.\n", ctx->fwname);
2178         release_firmware(blob);
2179
2180         return -EPROTO;
2181 }
2182
2183 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2184 {
2185         struct b43_wldev *dev = ctx->dev;
2186         struct b43_firmware *fw = &ctx->dev->fw;
2187         const u8 rev = ctx->dev->dev->core_rev;
2188         const char *filename;
2189         u32 tmshigh;
2190         int err;
2191
2192         /* Files for HT and LCN were found by trying one by one */
2193
2194         /* Get microcode */
2195         if ((rev >= 5) && (rev <= 10)) {
2196                 filename = "ucode5";
2197         } else if ((rev >= 11) && (rev <= 12)) {
2198                 filename = "ucode11";
2199         } else if (rev == 13) {
2200                 filename = "ucode13";
2201         } else if (rev == 14) {
2202                 filename = "ucode14";
2203         } else if (rev == 15) {
2204                 filename = "ucode15";
2205         } else {
2206                 switch (dev->phy.type) {
2207                 case B43_PHYTYPE_N:
2208                         if (rev >= 16)
2209                                 filename = "ucode16_mimo";
2210                         else
2211                                 goto err_no_ucode;
2212                         break;
2213                 case B43_PHYTYPE_HT:
2214                         if (rev == 29)
2215                                 filename = "ucode29_mimo";
2216                         else
2217                                 goto err_no_ucode;
2218                         break;
2219                 case B43_PHYTYPE_LCN:
2220                         if (rev == 24)
2221                                 filename = "ucode24_mimo";
2222                         else
2223                                 goto err_no_ucode;
2224                         break;
2225                 default:
2226                         goto err_no_ucode;
2227                 }
2228         }
2229         err = b43_do_request_fw(ctx, filename, &fw->ucode);
2230         if (err)
2231                 goto err_load;
2232
2233         /* Get PCM code */
2234         if ((rev >= 5) && (rev <= 10))
2235                 filename = "pcm5";
2236         else if (rev >= 11)
2237                 filename = NULL;
2238         else
2239                 goto err_no_pcm;
2240         fw->pcm_request_failed = false;
2241         err = b43_do_request_fw(ctx, filename, &fw->pcm);
2242         if (err == -ENOENT) {
2243                 /* We did not find a PCM file? Not fatal, but
2244                  * core rev <= 10 must do without hwcrypto then. */
2245                 fw->pcm_request_failed = true;
2246         } else if (err)
2247                 goto err_load;
2248
2249         /* Get initvals */
2250         switch (dev->phy.type) {
2251         case B43_PHYTYPE_A:
2252                 if ((rev >= 5) && (rev <= 10)) {
2253                         tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2254                         if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2255                                 filename = "a0g1initvals5";
2256                         else
2257                                 filename = "a0g0initvals5";
2258                 } else
2259                         goto err_no_initvals;
2260                 break;
2261         case B43_PHYTYPE_G:
2262                 if ((rev >= 5) && (rev <= 10))
2263                         filename = "b0g0initvals5";
2264                 else if (rev >= 13)
2265                         filename = "b0g0initvals13";
2266                 else
2267                         goto err_no_initvals;
2268                 break;
2269         case B43_PHYTYPE_N:
2270                 if (rev >= 16)
2271                         filename = "n0initvals16";
2272                 else if ((rev >= 11) && (rev <= 12))
2273                         filename = "n0initvals11";
2274                 else
2275                         goto err_no_initvals;
2276                 break;
2277         case B43_PHYTYPE_LP:
2278                 if (rev == 13)
2279                         filename = "lp0initvals13";
2280                 else if (rev == 14)
2281                         filename = "lp0initvals14";
2282                 else if (rev >= 15)
2283                         filename = "lp0initvals15";
2284                 else
2285                         goto err_no_initvals;
2286                 break;
2287         case B43_PHYTYPE_HT:
2288                 if (rev == 29)
2289                         filename = "ht0initvals29";
2290                 else
2291                         goto err_no_initvals;
2292                 break;
2293         case B43_PHYTYPE_LCN:
2294                 if (rev == 24)
2295                         filename = "lcn0initvals24";
2296                 else
2297                         goto err_no_initvals;
2298                 break;
2299         default:
2300                 goto err_no_initvals;
2301         }
2302         err = b43_do_request_fw(ctx, filename, &fw->initvals);
2303         if (err)
2304                 goto err_load;
2305
2306         /* Get bandswitch initvals */
2307         switch (dev->phy.type) {
2308         case B43_PHYTYPE_A:
2309                 if ((rev >= 5) && (rev <= 10)) {
2310                         tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2311                         if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2312                                 filename = "a0g1bsinitvals5";
2313                         else
2314                                 filename = "a0g0bsinitvals5";
2315                 } else if (rev >= 11)
2316                         filename = NULL;
2317                 else
2318                         goto err_no_initvals;
2319                 break;
2320         case B43_PHYTYPE_G:
2321                 if ((rev >= 5) && (rev <= 10))
2322                         filename = "b0g0bsinitvals5";
2323                 else if (rev >= 11)
2324                         filename = NULL;
2325                 else
2326                         goto err_no_initvals;
2327                 break;
2328         case B43_PHYTYPE_N:
2329                 if (rev >= 16)
2330                         filename = "n0bsinitvals16";
2331                 else if ((rev >= 11) && (rev <= 12))
2332                         filename = "n0bsinitvals11";
2333                 else
2334                         goto err_no_initvals;
2335                 break;
2336         case B43_PHYTYPE_LP:
2337                 if (rev == 13)
2338                         filename = "lp0bsinitvals13";
2339                 else if (rev == 14)
2340                         filename = "lp0bsinitvals14";
2341                 else if (rev >= 15)
2342                         filename = "lp0bsinitvals15";
2343                 else
2344                         goto err_no_initvals;
2345                 break;
2346         case B43_PHYTYPE_HT:
2347                 if (rev == 29)
2348                         filename = "ht0bsinitvals29";
2349                 else
2350                         goto err_no_initvals;
2351                 break;
2352         case B43_PHYTYPE_LCN:
2353                 if (rev == 24)
2354                         filename = "lcn0bsinitvals24";
2355                 else
2356                         goto err_no_initvals;
2357                 break;
2358         default:
2359                 goto err_no_initvals;
2360         }
2361         err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2362         if (err)
2363                 goto err_load;
2364
2365         return 0;
2366
2367 err_no_ucode:
2368         err = ctx->fatal_failure = -EOPNOTSUPP;
2369         b43err(dev->wl, "The driver does not know which firmware (ucode) "
2370                "is required for your device (wl-core rev %u)\n", rev);
2371         goto error;
2372
2373 err_no_pcm:
2374         err = ctx->fatal_failure = -EOPNOTSUPP;
2375         b43err(dev->wl, "The driver does not know which firmware (PCM) "
2376                "is required for your device (wl-core rev %u)\n", rev);
2377         goto error;
2378
2379 err_no_initvals:
2380         err = ctx->fatal_failure = -EOPNOTSUPP;
2381         b43err(dev->wl, "The driver does not know which firmware (initvals) "
2382                "is required for your device (wl-core rev %u)\n", rev);
2383         goto error;
2384
2385 err_load:
2386         /* We failed to load this firmware image. The error message
2387          * already is in ctx->errors. Return and let our caller decide
2388          * what to do. */
2389         goto error;
2390
2391 error:
2392         b43_release_firmware(dev);
2393         return err;
2394 }
2395
2396 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2397 static void b43_one_core_detach(struct b43_bus_dev *dev);
2398
2399 static void b43_request_firmware(struct work_struct *work)
2400 {
2401         struct b43_wl *wl = container_of(work,
2402                             struct b43_wl, firmware_load);
2403         struct b43_wldev *dev = wl->current_dev;
2404         struct b43_request_fw_context *ctx;
2405         unsigned int i;
2406         int err;
2407         const char *errmsg;
2408
2409         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2410         if (!ctx)
2411                 return;
2412         ctx->dev = dev;
2413
2414         ctx->req_type = B43_FWTYPE_PROPRIETARY;
2415         err = b43_try_request_fw(ctx);
2416         if (!err)
2417                 goto start_ieee80211; /* Successfully loaded it. */
2418         /* Was fw version known? */
2419         if (ctx->fatal_failure)
2420                 goto out;
2421
2422         /* proprietary fw not found, try open source */
2423         ctx->req_type = B43_FWTYPE_OPENSOURCE;
2424         err = b43_try_request_fw(ctx);
2425         if (!err)
2426                 goto start_ieee80211; /* Successfully loaded it. */
2427         if(ctx->fatal_failure)
2428                 goto out;
2429
2430         /* Could not find a usable firmware. Print the errors. */
2431         for (i = 0; i < B43_NR_FWTYPES; i++) {
2432                 errmsg = ctx->errors[i];
2433                 if (strlen(errmsg))
2434                         b43err(dev->wl, errmsg);
2435         }
2436         b43_print_fw_helptext(dev->wl, 1);
2437         goto out;
2438
2439 start_ieee80211:
2440         err = ieee80211_register_hw(wl->hw);
2441         if (err)
2442                 goto err_one_core_detach;
2443         b43_leds_register(wl->current_dev);
2444         goto out;
2445
2446 err_one_core_detach:
2447         b43_one_core_detach(dev->dev);
2448
2449 out:
2450         kfree(ctx);
2451 }
2452
2453 static int b43_upload_microcode(struct b43_wldev *dev)
2454 {
2455         struct wiphy *wiphy = dev->wl->hw->wiphy;
2456         const size_t hdr_len = sizeof(struct b43_fw_header);
2457         const __be32 *data;
2458         unsigned int i, len;
2459         u16 fwrev, fwpatch, fwdate, fwtime;
2460         u32 tmp, macctl;
2461         int err = 0;
2462
2463         /* Jump the microcode PSM to offset 0 */
2464         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2465         B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2466         macctl |= B43_MACCTL_PSM_JMP0;
2467         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2468         /* Zero out all microcode PSM registers and shared memory. */
2469         for (i = 0; i < 64; i++)
2470                 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2471         for (i = 0; i < 4096; i += 2)
2472                 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2473
2474         /* Upload Microcode. */
2475         data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2476         len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2477         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2478         for (i = 0; i < len; i++) {
2479                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2480                 udelay(10);
2481         }
2482
2483         if (dev->fw.pcm.data) {
2484                 /* Upload PCM data. */
2485                 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2486                 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2487                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2488                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2489                 /* No need for autoinc bit in SHM_HW */
2490                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2491                 for (i = 0; i < len; i++) {
2492                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2493                         udelay(10);
2494                 }
2495         }
2496
2497         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2498
2499         /* Start the microcode PSM */
2500         b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2501                       B43_MACCTL_PSM_RUN);
2502
2503         /* Wait for the microcode to load and respond */
2504         i = 0;
2505         while (1) {
2506                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2507                 if (tmp == B43_IRQ_MAC_SUSPENDED)
2508                         break;
2509                 i++;
2510                 if (i >= 20) {
2511                         b43err(dev->wl, "Microcode not responding\n");
2512                         b43_print_fw_helptext(dev->wl, 1);
2513                         err = -ENODEV;
2514                         goto error;
2515                 }
2516                 msleep(50);
2517         }
2518         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
2519
2520         /* Get and check the revisions. */
2521         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2522         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2523         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2524         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2525
2526         if (fwrev <= 0x128) {
2527                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2528                        "binary drivers older than version 4.x is unsupported. "
2529                        "You must upgrade your firmware files.\n");
2530                 b43_print_fw_helptext(dev->wl, 1);
2531                 err = -EOPNOTSUPP;
2532                 goto error;
2533         }
2534         dev->fw.rev = fwrev;
2535         dev->fw.patch = fwpatch;
2536         if (dev->fw.rev >= 598)
2537                 dev->fw.hdr_format = B43_FW_HDR_598;
2538         else if (dev->fw.rev >= 410)
2539                 dev->fw.hdr_format = B43_FW_HDR_410;
2540         else
2541                 dev->fw.hdr_format = B43_FW_HDR_351;
2542         dev->fw.opensource = (fwdate == 0xFFFF);
2543
2544         /* Default to use-all-queues. */
2545         dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2546         dev->qos_enabled = !!modparam_qos;
2547         /* Default to firmware/hardware crypto acceleration. */
2548         dev->hwcrypto_enabled = true;
2549
2550         if (dev->fw.opensource) {
2551                 u16 fwcapa;
2552
2553                 /* Patchlevel info is encoded in the "time" field. */
2554                 dev->fw.patch = fwtime;
2555                 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2556                         dev->fw.rev, dev->fw.patch);
2557
2558                 fwcapa = b43_fwcapa_read(dev);
2559                 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2560                         b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2561                         /* Disable hardware crypto and fall back to software crypto. */
2562                         dev->hwcrypto_enabled = false;
2563                 }
2564                 if (!(fwcapa & B43_FWCAPA_QOS)) {
2565                         b43info(dev->wl, "QoS not supported by firmware\n");
2566                         /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2567                          * ieee80211_unregister to make sure the networking core can
2568                          * properly free possible resources. */
2569                         dev->wl->hw->queues = 1;
2570                         dev->qos_enabled = false;
2571                 }
2572         } else {
2573                 b43info(dev->wl, "Loading firmware version %u.%u "
2574                         "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2575                         fwrev, fwpatch,
2576                         (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2577                         (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2578                 if (dev->fw.pcm_request_failed) {
2579                         b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2580                                 "Hardware accelerated cryptography is disabled.\n");
2581                         b43_print_fw_helptext(dev->wl, 0);
2582                 }
2583         }
2584
2585         snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2586                         dev->fw.rev, dev->fw.patch);
2587         wiphy->hw_version = dev->dev->core_id;
2588
2589         if (dev->fw.hdr_format == B43_FW_HDR_351) {
2590                 /* We're over the deadline, but we keep support for old fw
2591                  * until it turns out to be in major conflict with something new. */
2592                 b43warn(dev->wl, "You are using an old firmware image. "
2593                         "Support for old firmware will be removed soon "
2594                         "(official deadline was July 2008).\n");
2595                 b43_print_fw_helptext(dev->wl, 0);
2596         }
2597
2598         return 0;
2599
2600 error:
2601         /* Stop the microcode PSM. */
2602         b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2603                       B43_MACCTL_PSM_JMP0);
2604
2605         return err;
2606 }
2607
2608 static int b43_write_initvals(struct b43_wldev *dev,
2609                               const struct b43_iv *ivals,
2610                               size_t count,
2611                               size_t array_size)
2612 {
2613         const struct b43_iv *iv;
2614         u16 offset;
2615         size_t i;
2616         bool bit32;
2617
2618         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2619         iv = ivals;
2620         for (i = 0; i < count; i++) {
2621                 if (array_size < sizeof(iv->offset_size))
2622                         goto err_format;
2623                 array_size -= sizeof(iv->offset_size);
2624                 offset = be16_to_cpu(iv->offset_size);
2625                 bit32 = !!(offset & B43_IV_32BIT);
2626                 offset &= B43_IV_OFFSET_MASK;
2627                 if (offset >= 0x1000)
2628                         goto err_format;
2629                 if (bit32) {
2630                         u32 value;
2631
2632                         if (array_size < sizeof(iv->data.d32))
2633                                 goto err_format;
2634                         array_size -= sizeof(iv->data.d32);
2635
2636                         value = get_unaligned_be32(&iv->data.d32);
2637                         b43_write32(dev, offset, value);
2638
2639                         iv = (const struct b43_iv *)((const uint8_t *)iv +
2640                                                         sizeof(__be16) +
2641                                                         sizeof(__be32));
2642                 } else {
2643                         u16 value;
2644
2645                         if (array_size < sizeof(iv->data.d16))
2646                                 goto err_format;
2647                         array_size -= sizeof(iv->data.d16);
2648
2649                         value = be16_to_cpu(iv->data.d16);
2650                         b43_write16(dev, offset, value);
2651
2652                         iv = (const struct b43_iv *)((const uint8_t *)iv +
2653                                                         sizeof(__be16) +
2654                                                         sizeof(__be16));
2655                 }
2656         }
2657         if (array_size)
2658                 goto err_format;
2659
2660         return 0;
2661
2662 err_format:
2663         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2664         b43_print_fw_helptext(dev->wl, 1);
2665
2666         return -EPROTO;
2667 }
2668
2669 static int b43_upload_initvals(struct b43_wldev *dev)
2670 {
2671         const size_t hdr_len = sizeof(struct b43_fw_header);
2672         const struct b43_fw_header *hdr;
2673         struct b43_firmware *fw = &dev->fw;
2674         const struct b43_iv *ivals;
2675         size_t count;
2676         int err;
2677
2678         hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2679         ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2680         count = be32_to_cpu(hdr->size);
2681         err = b43_write_initvals(dev, ivals, count,
2682                                  fw->initvals.data->size - hdr_len);
2683         if (err)
2684                 goto out;
2685         if (fw->initvals_band.data) {
2686                 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2687                 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2688                 count = be32_to_cpu(hdr->size);
2689                 err = b43_write_initvals(dev, ivals, count,
2690                                          fw->initvals_band.data->size - hdr_len);
2691                 if (err)
2692                         goto out;
2693         }
2694 out:
2695
2696         return err;
2697 }
2698
2699 /* Initialize the GPIOs
2700  * http://bcm-specs.sipsolutions.net/GPIO
2701  */
2702 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2703 {
2704         struct ssb_bus *bus = dev->dev->sdev->bus;
2705
2706 #ifdef CONFIG_SSB_DRIVER_PCICORE
2707         return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2708 #else
2709         return bus->chipco.dev;
2710 #endif
2711 }
2712
2713 static int b43_gpio_init(struct b43_wldev *dev)
2714 {
2715         struct ssb_device *gpiodev;
2716         u32 mask, set;
2717
2718         b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2719         b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
2720
2721         mask = 0x0000001F;
2722         set = 0x0000000F;
2723         if (dev->dev->chip_id == 0x4301) {
2724                 mask |= 0x0060;
2725                 set |= 0x0060;
2726         }
2727         if (dev->dev->chip_id == 0x5354)
2728                 set &= 0xff02;
2729         if (0 /* FIXME: conditional unknown */ ) {
2730                 b43_write16(dev, B43_MMIO_GPIO_MASK,
2731                             b43_read16(dev, B43_MMIO_GPIO_MASK)
2732                             | 0x0100);
2733                 mask |= 0x0180;
2734                 set |= 0x0180;
2735         }
2736         if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2737                 b43_write16(dev, B43_MMIO_GPIO_MASK,
2738                             b43_read16(dev, B43_MMIO_GPIO_MASK)
2739                             | 0x0200);
2740                 mask |= 0x0200;
2741                 set |= 0x0200;
2742         }
2743         if (dev->dev->core_rev >= 2)
2744                 mask |= 0x0010; /* FIXME: This is redundant. */
2745
2746         switch (dev->dev->bus_type) {
2747 #ifdef CONFIG_B43_BCMA
2748         case B43_BUS_BCMA:
2749                 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2750                                 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2751                                         BCMA_CC_GPIOCTL) & mask) | set);
2752                 break;
2753 #endif
2754 #ifdef CONFIG_B43_SSB
2755         case B43_BUS_SSB:
2756                 gpiodev = b43_ssb_gpio_dev(dev);
2757                 if (gpiodev)
2758                         ssb_write32(gpiodev, B43_GPIO_CONTROL,
2759                                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2760                                     & mask) | set);
2761                 break;
2762 #endif
2763         }
2764
2765         return 0;
2766 }
2767
2768 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2769 static void b43_gpio_cleanup(struct b43_wldev *dev)
2770 {
2771         struct ssb_device *gpiodev;
2772
2773         switch (dev->dev->bus_type) {
2774 #ifdef CONFIG_B43_BCMA
2775         case B43_BUS_BCMA:
2776                 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2777                                 0);
2778                 break;
2779 #endif
2780 #ifdef CONFIG_B43_SSB
2781         case B43_BUS_SSB:
2782                 gpiodev = b43_ssb_gpio_dev(dev);
2783                 if (gpiodev)
2784                         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2785                 break;
2786 #endif
2787         }
2788 }
2789
2790 /* http://bcm-specs.sipsolutions.net/EnableMac */
2791 void b43_mac_enable(struct b43_wldev *dev)
2792 {
2793         if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2794                 u16 fwstate;
2795
2796                 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2797                                          B43_SHM_SH_UCODESTAT);
2798                 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2799                     (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2800                         b43err(dev->wl, "b43_mac_enable(): The firmware "
2801                                "should be suspended, but current state is %u\n",
2802                                fwstate);
2803                 }
2804         }
2805
2806         dev->mac_suspended--;
2807         B43_WARN_ON(dev->mac_suspended < 0);
2808         if (dev->mac_suspended == 0) {
2809                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
2810                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2811                             B43_IRQ_MAC_SUSPENDED);
2812                 /* Commit writes */
2813                 b43_read32(dev, B43_MMIO_MACCTL);
2814                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2815                 b43_power_saving_ctl_bits(dev, 0);
2816         }
2817 }
2818
2819 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2820 void b43_mac_suspend(struct b43_wldev *dev)
2821 {
2822         int i;
2823         u32 tmp;
2824
2825         might_sleep();
2826         B43_WARN_ON(dev->mac_suspended < 0);
2827
2828         if (dev->mac_suspended == 0) {
2829                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2830                 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
2831                 /* force pci to flush the write */
2832                 b43_read32(dev, B43_MMIO_MACCTL);
2833                 for (i = 35; i; i--) {
2834                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2835                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2836                                 goto out;
2837                         udelay(10);
2838                 }
2839                 /* Hm, it seems this will take some time. Use msleep(). */
2840                 for (i = 40; i; i--) {
2841                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2842                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2843                                 goto out;
2844                         msleep(1);
2845                 }
2846                 b43err(dev->wl, "MAC suspend failed\n");
2847         }
2848 out:
2849         dev->mac_suspended++;
2850 }
2851
2852 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2853 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2854 {
2855         u32 tmp;
2856
2857         switch (dev->dev->bus_type) {
2858 #ifdef CONFIG_B43_BCMA
2859         case B43_BUS_BCMA:
2860                 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
2861                 if (on)
2862                         tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2863                 else
2864                         tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
2865                 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
2866                 break;
2867 #endif
2868 #ifdef CONFIG_B43_SSB
2869         case B43_BUS_SSB:
2870                 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2871                 if (on)
2872                         tmp |= B43_TMSLOW_MACPHYCLKEN;
2873                 else
2874                         tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2875                 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2876                 break;
2877 #endif
2878         }
2879 }
2880
2881 static void b43_adjust_opmode(struct b43_wldev *dev)
2882 {
2883         struct b43_wl *wl = dev->wl;
2884         u32 ctl;
2885         u16 cfp_pretbtt;
2886
2887         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2888         /* Reset status to STA infrastructure mode. */
2889         ctl &= ~B43_MACCTL_AP;
2890         ctl &= ~B43_MACCTL_KEEP_CTL;
2891         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2892         ctl &= ~B43_MACCTL_KEEP_BAD;
2893         ctl &= ~B43_MACCTL_PROMISC;
2894         ctl &= ~B43_MACCTL_BEACPROMISC;
2895         ctl |= B43_MACCTL_INFRA;
2896
2897         if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2898             b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2899                 ctl |= B43_MACCTL_AP;
2900         else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2901                 ctl &= ~B43_MACCTL_INFRA;
2902
2903         if (wl->filter_flags & FIF_CONTROL)
2904                 ctl |= B43_MACCTL_KEEP_CTL;
2905         if (wl->filter_flags & FIF_FCSFAIL)
2906                 ctl |= B43_MACCTL_KEEP_BAD;
2907         if (wl->filter_flags & FIF_PLCPFAIL)
2908                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2909         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2910                 ctl |= B43_MACCTL_PROMISC;
2911         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2912                 ctl |= B43_MACCTL_BEACPROMISC;
2913
2914         /* Workaround: On old hardware the HW-MAC-address-filter
2915          * doesn't work properly, so always run promisc in filter
2916          * it in software. */
2917         if (dev->dev->core_rev <= 4)
2918                 ctl |= B43_MACCTL_PROMISC;
2919
2920         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2921
2922         cfp_pretbtt = 2;
2923         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2924                 if (dev->dev->chip_id == 0x4306 &&
2925                     dev->dev->chip_rev == 3)
2926                         cfp_pretbtt = 100;
2927                 else
2928                         cfp_pretbtt = 50;
2929         }
2930         b43_write16(dev, 0x612, cfp_pretbtt);
2931
2932         /* FIXME: We don't currently implement the PMQ mechanism,
2933          *        so always disable it. If we want to implement PMQ,
2934          *        we need to enable it here (clear DISCPMQ) in AP mode.
2935          */
2936         if (0  /* ctl & B43_MACCTL_AP */)
2937                 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
2938         else
2939                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
2940 }
2941
2942 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2943 {
2944         u16 offset;
2945
2946         if (is_ofdm) {
2947                 offset = 0x480;
2948                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2949         } else {
2950                 offset = 0x4C0;
2951                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2952         }
2953         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2954                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2955 }
2956
2957 static void b43_rate_memory_init(struct b43_wldev *dev)
2958 {
2959         switch (dev->phy.type) {
2960         case B43_PHYTYPE_A:
2961         case B43_PHYTYPE_G:
2962         case B43_PHYTYPE_N:
2963         case B43_PHYTYPE_LP:
2964         case B43_PHYTYPE_HT:
2965         case B43_PHYTYPE_LCN:
2966                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2967                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2968                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2969                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2970                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2971                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2972                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2973                 if (dev->phy.type == B43_PHYTYPE_A)
2974                         break;
2975                 /* fallthrough */
2976         case B43_PHYTYPE_B:
2977                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2978                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2979                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2980                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2981                 break;
2982         default:
2983                 B43_WARN_ON(1);
2984         }
2985 }
2986
2987 /* Set the default values for the PHY TX Control Words. */
2988 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2989 {
2990         u16 ctl = 0;
2991
2992         ctl |= B43_TXH_PHY_ENC_CCK;
2993         ctl |= B43_TXH_PHY_ANT01AUTO;
2994         ctl |= B43_TXH_PHY_TXPWR;
2995
2996         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2997         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2998         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2999 }
3000
3001 /* Set the TX-Antenna for management frames sent by firmware. */
3002 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3003 {
3004         u16 ant;
3005         u16 tmp;
3006
3007         ant = b43_antenna_to_phyctl(antenna);
3008
3009         /* For ACK/CTS */
3010         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3011         tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3012         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3013         /* For Probe Resposes */
3014         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3015         tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3016         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3017 }
3018
3019 /* This is the opposite of b43_chip_init() */
3020 static void b43_chip_exit(struct b43_wldev *dev)
3021 {
3022         b43_phy_exit(dev);
3023         b43_gpio_cleanup(dev);
3024         /* firmware is released later */
3025 }
3026
3027 /* Initialize the chip
3028  * http://bcm-specs.sipsolutions.net/ChipInit
3029  */
3030 static int b43_chip_init(struct b43_wldev *dev)
3031 {
3032         struct b43_phy *phy = &dev->phy;
3033         int err;
3034         u32 macctl;
3035         u16 value16;
3036
3037         /* Initialize the MAC control */
3038         macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3039         if (dev->phy.gmode)
3040                 macctl |= B43_MACCTL_GMODE;
3041         macctl |= B43_MACCTL_INFRA;
3042         b43_write32(dev, B43_MMIO_MACCTL, macctl);
3043
3044         err = b43_upload_microcode(dev);
3045         if (err)
3046                 goto out;       /* firmware is released later */
3047
3048         err = b43_gpio_init(dev);
3049         if (err)
3050                 goto out;       /* firmware is released later */
3051
3052         err = b43_upload_initvals(dev);
3053         if (err)
3054                 goto err_gpio_clean;
3055
3056         /* Turn the Analog on and initialize the PHY. */
3057         phy->ops->switch_analog(dev, 1);
3058         err = b43_phy_init(dev);
3059         if (err)
3060                 goto err_gpio_clean;
3061
3062         /* Disable Interference Mitigation. */
3063         if (phy->ops->interf_mitigation)
3064                 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3065
3066         /* Select the antennae */
3067         if (phy->ops->set_rx_antenna)
3068                 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3069         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3070
3071         if (phy->type == B43_PHYTYPE_B) {
3072                 value16 = b43_read16(dev, 0x005E);
3073                 value16 |= 0x0004;
3074                 b43_write16(dev, 0x005E, value16);
3075         }
3076         b43_write32(dev, 0x0100, 0x01000000);
3077         if (dev->dev->core_rev < 5)
3078                 b43_write32(dev, 0x010C, 0x01000000);
3079
3080         b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3081         b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
3082
3083         /* Probe Response Timeout value */
3084         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3085         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
3086
3087         /* Initially set the wireless operation mode. */
3088         b43_adjust_opmode(dev);
3089
3090         if (dev->dev->core_rev < 3) {
3091                 b43_write16(dev, 0x060E, 0x0000);
3092                 b43_write16(dev, 0x0610, 0x8000);
3093                 b43_write16(dev, 0x0604, 0x0000);
3094                 b43_write16(dev, 0x0606, 0x0200);
3095         } else {
3096                 b43_write32(dev, 0x0188, 0x80000000);
3097                 b43_write32(dev, 0x018C, 0x02000000);
3098         }
3099         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3100         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
3101         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3102         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3103         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3104         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3105         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3106
3107         b43_mac_phy_clock_set(dev, true);
3108
3109         switch (dev->dev->bus_type) {
3110 #ifdef CONFIG_B43_BCMA
3111         case B43_BUS_BCMA:
3112                 /* FIXME: 0xE74 is quite common, but should be read from CC */
3113                 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3114                 break;
3115 #endif
3116 #ifdef CONFIG_B43_SSB
3117         case B43_BUS_SSB:
3118                 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3119                             dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3120                 break;
3121 #endif
3122         }
3123
3124         err = 0;
3125         b43dbg(dev->wl, "Chip initialized\n");
3126 out:
3127         return err;
3128
3129 err_gpio_clean:
3130         b43_gpio_cleanup(dev);
3131         return err;
3132 }
3133
3134 static void b43_periodic_every60sec(struct b43_wldev *dev)
3135 {
3136         const struct b43_phy_operations *ops = dev->phy.ops;
3137
3138         if (ops->pwork_60sec)
3139                 ops->pwork_60sec(dev);
3140
3141         /* Force check the TX power emission now. */
3142         b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3143 }
3144
3145 static void b43_periodic_every30sec(struct b43_wldev *dev)
3146 {
3147         /* Update device statistics. */
3148         b43_calculate_link_quality(dev);
3149 }
3150
3151 static void b43_periodic_every15sec(struct b43_wldev *dev)
3152 {
3153         struct b43_phy *phy = &dev->phy;
3154         u16 wdr;
3155
3156         if (dev->fw.opensource) {
3157                 /* Check if the firmware is still alive.
3158                  * It will reset the watchdog counter to 0 in its idle loop. */
3159                 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3160                 if (unlikely(wdr)) {
3161                         b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3162                         b43_controller_restart(dev, "Firmware watchdog");
3163                         return;
3164                 } else {
3165                         b43_shm_write16(dev, B43_SHM_SCRATCH,
3166                                         B43_WATCHDOG_REG, 1);
3167                 }
3168         }
3169
3170         if (phy->ops->pwork_15sec)
3171                 phy->ops->pwork_15sec(dev);
3172
3173         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3174         wmb();
3175
3176 #if B43_DEBUG
3177         if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3178                 unsigned int i;
3179
3180                 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3181                        dev->irq_count / 15,
3182                        dev->tx_count / 15,
3183                        dev->rx_count / 15);
3184                 dev->irq_count = 0;
3185                 dev->tx_count = 0;
3186                 dev->rx_count = 0;
3187                 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3188                         if (dev->irq_bit_count[i]) {
3189                                 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3190                                        dev->irq_bit_count[i] / 15, i, (1 << i));
3191                                 dev->irq_bit_count[i] = 0;
3192                         }
3193                 }
3194         }
3195 #endif
3196 }
3197
3198 static void do_periodic_work(struct b43_wldev *dev)
3199 {
3200         unsigned int state;
3201
3202         state = dev->periodic_state;
3203         if (state % 4 == 0)
3204                 b43_periodic_every60sec(dev);
3205         if (state % 2 == 0)
3206                 b43_periodic_every30sec(dev);
3207         b43_periodic_every15sec(dev);
3208 }
3209
3210 /* Periodic work locking policy:
3211  *      The whole periodic work handler is protected by
3212  *      wl->mutex. If another lock is needed somewhere in the
3213  *      pwork callchain, it's acquired in-place, where it's needed.
3214  */
3215 static void b43_periodic_work_handler(struct work_struct *work)
3216 {
3217         struct b43_wldev *dev = container_of(work, struct b43_wldev,
3218                                              periodic_work.work);
3219         struct b43_wl *wl = dev->wl;
3220         unsigned long delay;
3221
3222         mutex_lock(&wl->mutex);
3223
3224         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3225                 goto out;
3226         if (b43_debug(dev, B43_DBG_PWORK_STOP))
3227                 goto out_requeue;
3228
3229         do_periodic_work(dev);
3230
3231         dev->periodic_state++;
3232 out_requeue:
3233         if (b43_debug(dev, B43_DBG_PWORK_FAST))
3234                 delay = msecs_to_jiffies(50);
3235         else
3236                 delay = round_jiffies_relative(HZ * 15);
3237         ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3238 out:
3239         mutex_unlock(&wl->mutex);
3240 }
3241
3242 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3243 {
3244         struct delayed_work *work = &dev->periodic_work;
3245
3246         dev->periodic_state = 0;
3247         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3248         ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3249 }
3250
3251 /* Check if communication with the device works correctly. */
3252 static int b43_validate_chipaccess(struct b43_wldev *dev)
3253 {
3254         u32 v, backup0, backup4;
3255
3256         backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3257         backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3258
3259         /* Check for read/write and endianness problems. */
3260         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3261         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3262                 goto error;
3263         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3264         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3265                 goto error;
3266
3267         /* Check if unaligned 32bit SHM_SHARED access works properly.
3268          * However, don't bail out on failure, because it's noncritical. */
3269         b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3270         b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3271         b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3272         b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3273         if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3274                 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3275         b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3276         if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3277             b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3278             b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3279             b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3280                 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3281
3282         b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3283         b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3284
3285         if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3286                 /* The 32bit register shadows the two 16bit registers
3287                  * with update sideeffects. Validate this. */
3288                 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3289                 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3290                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3291                         goto error;
3292                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3293                         goto error;
3294         }
3295         b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3296
3297         v = b43_read32(dev, B43_MMIO_MACCTL);
3298         v |= B43_MACCTL_GMODE;
3299         if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3300                 goto error;
3301
3302         return 0;
3303 error:
3304         b43err(dev->wl, "Failed to validate the chipaccess\n");
3305         return -ENODEV;
3306 }
3307
3308 static void b43_security_init(struct b43_wldev *dev)
3309 {
3310         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3311         /* KTP is a word address, but we address SHM bytewise.
3312          * So multiply by two.
3313          */
3314         dev->ktp *= 2;
3315         /* Number of RCMTA address slots */
3316         b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3317         /* Clear the key memory. */
3318         b43_clear_keys(dev);
3319 }
3320
3321 #ifdef CONFIG_B43_HWRNG
3322 static int b43_rng_read(struct hwrng *rng, u32 *data)
3323 {
3324         struct b43_wl *wl = (struct b43_wl *)rng->priv;
3325         struct b43_wldev *dev;
3326         int count = -ENODEV;
3327
3328         mutex_lock(&wl->mutex);
3329         dev = wl->current_dev;
3330         if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3331                 *data = b43_read16(dev, B43_MMIO_RNG);
3332                 count = sizeof(u16);
3333         }
3334         mutex_unlock(&wl->mutex);
3335
3336         return count;
3337 }
3338 #endif /* CONFIG_B43_HWRNG */
3339
3340 static void b43_rng_exit(struct b43_wl *wl)
3341 {
3342 #ifdef CONFIG_B43_HWRNG
3343         if (wl->rng_initialized)
3344                 hwrng_unregister(&wl->rng);
3345 #endif /* CONFIG_B43_HWRNG */
3346 }
3347
3348 static int b43_rng_init(struct b43_wl *wl)
3349 {
3350         int err = 0;
3351
3352 #ifdef CONFIG_B43_HWRNG
3353         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3354                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3355         wl->rng.name = wl->rng_name;
3356         wl->rng.data_read = b43_rng_read;
3357         wl->rng.priv = (unsigned long)wl;
3358         wl->rng_initialized = true;
3359         err = hwrng_register(&wl->rng);
3360         if (err) {
3361                 wl->rng_initialized = false;
3362                 b43err(wl, "Failed to register the random "
3363                        "number generator (%d)\n", err);
3364         }
3365 #endif /* CONFIG_B43_HWRNG */
3366
3367         return err;
3368 }
3369
3370 static void b43_tx_work(struct work_struct *work)
3371 {
3372         struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3373         struct b43_wldev *dev;
3374         struct sk_buff *skb;
3375         int queue_num;
3376         int err = 0;
3377
3378         mutex_lock(&wl->mutex);
3379         dev = wl->current_dev;
3380         if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3381                 mutex_unlock(&wl->mutex);
3382                 return;
3383         }
3384
3385         for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3386                 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3387                         skb = skb_dequeue(&wl->tx_queue[queue_num]);
3388                         if (b43_using_pio_transfers(dev))
3389                                 err = b43_pio_tx(dev, skb);
3390                         else
3391                                 err = b43_dma_tx(dev, skb);
3392                         if (err == -ENOSPC) {
3393                                 wl->tx_queue_stopped[queue_num] = 1;
3394                                 ieee80211_stop_queue(wl->hw, queue_num);
3395                                 skb_queue_head(&wl->tx_queue[queue_num], skb);
3396                                 break;
3397                         }
3398                         if (unlikely(err))
3399                                 dev_kfree_skb(skb); /* Drop it */
3400                         err = 0;
3401                 }
3402
3403                 if (!err)
3404                         wl->tx_queue_stopped[queue_num] = 0;
3405         }
3406
3407 #if B43_DEBUG
3408         dev->tx_count++;
3409 #endif
3410         mutex_unlock(&wl->mutex);
3411 }
3412
3413 static void b43_op_tx(struct ieee80211_hw *hw,
3414                      struct sk_buff *skb)
3415 {
3416         struct b43_wl *wl = hw_to_b43_wl(hw);
3417
3418         if (unlikely(skb->len < 2 + 2 + 6)) {
3419                 /* Too short, this can't be a valid frame. */
3420                 dev_kfree_skb_any(skb);
3421                 return;
3422         }
3423         B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3424
3425         skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3426         if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3427                 ieee80211_queue_work(wl->hw, &wl->tx_work);
3428         } else {
3429                 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3430         }
3431 }
3432
3433 static void b43_qos_params_upload(struct b43_wldev *dev,
3434                                   const struct ieee80211_tx_queue_params *p,
3435                                   u16 shm_offset)
3436 {
3437         u16 params[B43_NR_QOSPARAMS];
3438         int bslots, tmp;
3439         unsigned int i;
3440
3441         if (!dev->qos_enabled)
3442                 return;
3443
3444         bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3445
3446         memset(&params, 0, sizeof(params));
3447
3448         params[B43_QOSPARAM_TXOP] = p->txop * 32;
3449         params[B43_QOSPARAM_CWMIN] = p->cw_min;
3450         params[B43_QOSPARAM_CWMAX] = p->cw_max;
3451         params[B43_QOSPARAM_CWCUR] = p->cw_min;
3452         params[B43_QOSPARAM_AIFS] = p->aifs;
3453         params[B43_QOSPARAM_BSLOTS] = bslots;
3454         params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3455
3456         for (i = 0; i < ARRAY_SIZE(params); i++) {
3457                 if (i == B43_QOSPARAM_STATUS) {
3458                         tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3459                                              shm_offset + (i * 2));
3460                         /* Mark the parameters as updated. */
3461                         tmp |= 0x100;
3462                         b43_shm_write16(dev, B43_SHM_SHARED,
3463                                         shm_offset + (i * 2),
3464                                         tmp);
3465                 } else {
3466                         b43_shm_write16(dev, B43_SHM_SHARED,
3467                                         shm_offset + (i * 2),
3468                                         params[i]);
3469                 }
3470         }
3471 }
3472
3473 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3474 static const u16 b43_qos_shm_offsets[] = {
3475         /* [mac80211-queue-nr] = SHM_OFFSET, */
3476         [0] = B43_QOS_VOICE,
3477         [1] = B43_QOS_VIDEO,
3478         [2] = B43_QOS_BESTEFFORT,
3479         [3] = B43_QOS_BACKGROUND,
3480 };
3481
3482 /* Update all QOS parameters in hardware. */
3483 static void b43_qos_upload_all(struct b43_wldev *dev)
3484 {
3485         struct b43_wl *wl = dev->wl;
3486         struct b43_qos_params *params;
3487         unsigned int i;
3488
3489         if (!dev->qos_enabled)
3490                 return;
3491
3492         BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3493                      ARRAY_SIZE(wl->qos_params));
3494
3495         b43_mac_suspend(dev);
3496         for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3497                 params = &(wl->qos_params[i]);
3498                 b43_qos_params_upload(dev, &(params->p),
3499                                       b43_qos_shm_offsets[i]);
3500         }
3501         b43_mac_enable(dev);
3502 }
3503
3504 static void b43_qos_clear(struct b43_wl *wl)
3505 {
3506         struct b43_qos_params *params;
3507         unsigned int i;
3508
3509         /* Initialize QoS parameters to sane defaults. */
3510
3511         BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3512                      ARRAY_SIZE(wl->qos_params));
3513
3514         for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3515                 params = &(wl->qos_params[i]);
3516
3517                 switch (b43_qos_shm_offsets[i]) {
3518                 case B43_QOS_VOICE:
3519                         params->p.txop = 0;
3520                         params->p.aifs = 2;
3521                         params->p.cw_min = 0x0001;
3522                         params->p.cw_max = 0x0001;
3523                         break;
3524                 case B43_QOS_VIDEO:
3525                         params->p.txop = 0;
3526                         params->p.aifs = 2;
3527                         params->p.cw_min = 0x0001;
3528                         params->p.cw_max = 0x0001;
3529                         break;
3530                 case B43_QOS_BESTEFFORT:
3531                         params->p.txop = 0;
3532                         params->p.aifs = 3;
3533                         params->p.cw_min = 0x0001;
3534                         params->p.cw_max = 0x03FF;
3535                         break;
3536                 case B43_QOS_BACKGROUND:
3537                         params->p.txop = 0;
3538                         params->p.aifs = 7;
3539                         params->p.cw_min = 0x0001;
3540                         params->p.cw_max = 0x03FF;
3541                         break;
3542                 default:
3543                         B43_WARN_ON(1);
3544                 }
3545         }
3546 }
3547
3548 /* Initialize the core's QOS capabilities */
3549 static void b43_qos_init(struct b43_wldev *dev)
3550 {
3551         if (!dev->qos_enabled) {
3552                 /* Disable QOS support. */
3553                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3554                 b43_write16(dev, B43_MMIO_IFSCTL,
3555                             b43_read16(dev, B43_MMIO_IFSCTL)
3556                             & ~B43_MMIO_IFSCTL_USE_EDCF);
3557                 b43dbg(dev->wl, "QoS disabled\n");
3558                 return;
3559         }
3560
3561         /* Upload the current QOS parameters. */
3562         b43_qos_upload_all(dev);
3563
3564         /* Enable QOS support. */
3565         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3566         b43_write16(dev, B43_MMIO_IFSCTL,
3567                     b43_read16(dev, B43_MMIO_IFSCTL)
3568                     | B43_MMIO_IFSCTL_USE_EDCF);
3569         b43dbg(dev->wl, "QoS enabled\n");
3570 }
3571
3572 static int b43_op_conf_tx(struct ieee80211_hw *hw,
3573                           struct ieee80211_vif *vif, u16 _queue,
3574                           const struct ieee80211_tx_queue_params *params)
3575 {
3576         struct b43_wl *wl = hw_to_b43_wl(hw);
3577         struct b43_wldev *dev;
3578         unsigned int queue = (unsigned int)_queue;
3579         int err = -ENODEV;
3580
3581         if (queue >= ARRAY_SIZE(wl->qos_params)) {
3582                 /* Queue not available or don't support setting
3583                  * params on this queue. Return success to not
3584                  * confuse mac80211. */
3585                 return 0;
3586         }
3587         BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3588                      ARRAY_SIZE(wl->qos_params));
3589
3590         mutex_lock(&wl->mutex);
3591         dev = wl->current_dev;
3592         if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3593                 goto out_unlock;
3594
3595         memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3596         b43_mac_suspend(dev);
3597         b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3598                               b43_qos_shm_offsets[queue]);
3599         b43_mac_enable(dev);
3600         err = 0;
3601
3602 out_unlock:
3603         mutex_unlock(&wl->mutex);
3604
3605         return err;
3606 }
3607
3608 static int b43_op_get_stats(struct ieee80211_hw *hw,
3609                             struct ieee80211_low_level_stats *stats)
3610 {
3611         struct b43_wl *wl = hw_to_b43_wl(hw);
3612
3613         mutex_lock(&wl->mutex);
3614         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3615         mutex_unlock(&wl->mutex);
3616
3617         return 0;
3618 }
3619
3620 static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3621 {
3622         struct b43_wl *wl = hw_to_b43_wl(hw);
3623         struct b43_wldev *dev;
3624         u64 tsf;
3625
3626         mutex_lock(&wl->mutex);
3627         dev = wl->current_dev;
3628
3629         if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3630                 b43_tsf_read(dev, &tsf);
3631         else
3632                 tsf = 0;
3633
3634         mutex_unlock(&wl->mutex);
3635
3636         return tsf;
3637 }
3638
3639 static void b43_op_set_tsf(struct ieee80211_hw *hw,
3640                            struct ieee80211_vif *vif, u64 tsf)
3641 {
3642         struct b43_wl *wl = hw_to_b43_wl(hw);
3643         struct b43_wldev *dev;
3644
3645         mutex_lock(&wl->mutex);
3646         dev = wl->current_dev;
3647
3648         if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3649                 b43_tsf_write(dev, tsf);
3650
3651         mutex_unlock(&wl->mutex);
3652 }
3653
3654 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3655 {
3656         u32 tmp;
3657
3658         switch (dev->dev->bus_type) {
3659 #ifdef CONFIG_B43_BCMA
3660         case B43_BUS_BCMA:
3661                 b43err(dev->wl,
3662                        "Putting PHY into reset not supported on BCMA\n");
3663                 break;
3664 #endif
3665 #ifdef CONFIG_B43_SSB
3666         case B43_BUS_SSB:
3667                 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3668                 tmp &= ~B43_TMSLOW_GMODE;
3669                 tmp |= B43_TMSLOW_PHYRESET;
3670                 tmp |= SSB_TMSLOW_FGC;
3671                 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3672                 msleep(1);
3673
3674                 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3675                 tmp &= ~SSB_TMSLOW_FGC;
3676                 tmp |= B43_TMSLOW_PHYRESET;
3677                 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3678                 msleep(1);
3679
3680                 break;
3681 #endif
3682         }
3683 }
3684
3685 static const char *band_to_string(enum ieee80211_band band)
3686 {
3687         switch (band) {
3688         case IEEE80211_BAND_5GHZ:
3689                 return "5";
3690         case IEEE80211_BAND_2GHZ:
3691                 return "2.4";
3692         default:
3693                 break;
3694         }
3695         B43_WARN_ON(1);
3696         return "";
3697 }
3698
3699 /* Expects wl->mutex locked */
3700 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3701 {
3702         struct b43_wldev *up_dev = NULL;
3703         struct b43_wldev *down_dev;
3704         struct b43_wldev *d;
3705         int err;
3706         bool uninitialized_var(gmode);
3707         int prev_status;
3708
3709         /* Find a device and PHY which supports the band. */
3710         list_for_each_entry(d, &wl->devlist, list) {
3711                 switch (chan->band) {
3712                 case IEEE80211_BAND_5GHZ:
3713                         if (d->phy.supports_5ghz) {
3714                                 up_dev = d;
3715                                 gmode = false;
3716                         }
3717                         break;
3718                 case IEEE80211_BAND_2GHZ:
3719                         if (d->phy.supports_2ghz) {
3720                                 up_dev = d;
3721                                 gmode = true;
3722                         }
3723                         break;
3724                 default:
3725                         B43_WARN_ON(1);
3726                         return -EINVAL;
3727                 }
3728                 if (up_dev)
3729                         break;
3730         }
3731         if (!up_dev) {
3732                 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3733                        band_to_string(chan->band));
3734                 return -ENODEV;
3735         }
3736         if ((up_dev == wl->current_dev) &&
3737             (!!wl->current_dev->phy.gmode == !!gmode)) {
3738                 /* This device is already running. */
3739                 return 0;
3740         }
3741         b43dbg(wl, "Switching to %s-GHz band\n",
3742                band_to_string(chan->band));
3743         down_dev = wl->current_dev;
3744
3745         prev_status = b43_status(down_dev);
3746         /* Shutdown the currently running core. */
3747         if (prev_status >= B43_STAT_STARTED)
3748                 down_dev = b43_wireless_core_stop(down_dev);
3749         if (prev_status >= B43_STAT_INITIALIZED)
3750                 b43_wireless_core_exit(down_dev);
3751
3752         if (down_dev != up_dev) {
3753                 /* We switch to a different core, so we put PHY into
3754                  * RESET on the old core. */
3755                 b43_put_phy_into_reset(down_dev);
3756         }
3757
3758         /* Now start the new core. */
3759         up_dev->phy.gmode = gmode;
3760         if (prev_status >= B43_STAT_INITIALIZED) {
3761                 err = b43_wireless_core_init(up_dev);
3762                 if (err) {
3763                         b43err(wl, "Fatal: Could not initialize device for "
3764                                "selected %s-GHz band\n",
3765                                band_to_string(chan->band));
3766                         goto init_failure;
3767                 }
3768         }
3769         if (prev_status >= B43_STAT_STARTED) {
3770                 err = b43_wireless_core_start(up_dev);
3771                 if (err) {
3772                         b43err(wl, "Fatal: Coult not start device for "
3773                                "selected %s-GHz band\n",
3774                                band_to_string(chan->band));
3775                         b43_wireless_core_exit(up_dev);
3776                         goto init_failure;
3777                 }
3778         }
3779         B43_WARN_ON(b43_status(up_dev) != prev_status);
3780
3781         wl->current_dev = up_dev;
3782
3783         return 0;
3784 init_failure:
3785         /* Whoops, failed to init the new core. No core is operating now. */
3786         wl->current_dev = NULL;
3787         return err;
3788 }
3789
3790 /* Write the short and long frame retry limit values. */
3791 static void b43_set_retry_limits(struct b43_wldev *dev,
3792                                  unsigned int short_retry,
3793                                  unsigned int long_retry)
3794 {
3795         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3796          * the chip-internal counter. */
3797         short_retry = min(short_retry, (unsigned int)0xF);
3798         long_retry = min(long_retry, (unsigned int)0xF);
3799
3800         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3801                         short_retry);
3802         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3803                         long_retry);
3804 }
3805
3806 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3807 {
3808         struct b43_wl *wl = hw_to_b43_wl(hw);
3809         struct b43_wldev *dev;
3810         struct b43_phy *phy;
3811         struct ieee80211_conf *conf = &hw->conf;
3812         int antenna;
3813         int err = 0;
3814         bool reload_bss = false;
3815
3816         mutex_lock(&wl->mutex);
3817
3818         dev = wl->current_dev;
3819
3820         /* Switch the band (if necessary). This might change the active core. */
3821         err = b43_switch_band(wl, conf->channel);
3822         if (err)
3823                 goto out_unlock_mutex;
3824
3825         /* Need to reload all settings if the core changed */
3826         if (dev != wl->current_dev) {
3827                 dev = wl->current_dev;
3828                 changed = ~0;
3829                 reload_bss = true;
3830         }
3831
3832         phy = &dev->phy;
3833
3834         if (conf_is_ht(conf))
3835                 phy->is_40mhz =
3836                         (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3837         else
3838                 phy->is_40mhz = false;
3839
3840         b43_mac_suspend(dev);
3841
3842         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3843                 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3844                                           conf->long_frame_max_tx_count);
3845         changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3846         if (!changed)
3847                 goto out_mac_enable;
3848
3849         /* Switch to the requested channel.
3850          * The firmware takes care of races with the TX handler. */
3851         if (conf->channel->hw_value != phy->channel)
3852                 b43_switch_channel(dev, conf->channel->hw_value);
3853
3854         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3855
3856         /* Adjust the desired TX power level. */
3857         if (conf->power_level != 0) {
3858                 if (conf->power_level != phy->desired_txpower) {
3859                         phy->desired_txpower = conf->power_level;
3860                         b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3861                                                    B43_TXPWR_IGNORE_TSSI);
3862                 }
3863         }
3864
3865         /* Antennas for RX and management frame TX. */
3866         antenna = B43_ANTENNA_DEFAULT;
3867         b43_mgmtframe_txantenna(dev, antenna);
3868         antenna = B43_ANTENNA_DEFAULT;
3869         if (phy->ops->set_rx_antenna)
3870                 phy->ops->set_rx_antenna(dev, antenna);
3871
3872         if (wl->radio_enabled != phy->radio_on) {
3873                 if (wl->radio_enabled) {
3874                         b43_software_rfkill(dev, false);
3875                         b43info(dev->wl, "Radio turned on by software\n");
3876                         if (!dev->radio_hw_enable) {
3877                                 b43info(dev->wl, "The hardware RF-kill button "
3878                                         "still turns the radio physically off. "
3879                                         "Press the button to turn it on.\n");
3880                         }
3881                 } else {
3882                         b43_software_rfkill(dev, true);
3883                         b43info(dev->wl, "Radio turned off by software\n");
3884                 }
3885         }
3886
3887 out_mac_enable:
3888         b43_mac_enable(dev);
3889 out_unlock_mutex:
3890         mutex_unlock(&wl->mutex);
3891
3892         if (wl->vif && reload_bss)
3893                 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
3894
3895         return err;
3896 }
3897
3898 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3899 {
3900         struct ieee80211_supported_band *sband =
3901                 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3902         struct ieee80211_rate *rate;
3903         int i;
3904         u16 basic, direct, offset, basic_offset, rateptr;
3905
3906         for (i = 0; i < sband->n_bitrates; i++) {
3907                 rate = &sband->bitrates[i];
3908
3909                 if (b43_is_cck_rate(rate->hw_value)) {
3910                         direct = B43_SHM_SH_CCKDIRECT;
3911                         basic = B43_SHM_SH_CCKBASIC;
3912                         offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3913                         offset &= 0xF;
3914                 } else {
3915                         direct = B43_SHM_SH_OFDMDIRECT;
3916                         basic = B43_SHM_SH_OFDMBASIC;
3917                         offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3918                         offset &= 0xF;
3919                 }
3920
3921                 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3922
3923                 if (b43_is_cck_rate(rate->hw_value)) {
3924                         basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3925                         basic_offset &= 0xF;
3926                 } else {
3927                         basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3928                         basic_offset &= 0xF;
3929                 }
3930
3931                 /*
3932                  * Get the pointer that we need to point to
3933                  * from the direct map
3934                  */
3935                 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3936                                          direct + 2 * basic_offset);
3937                 /* and write it to the basic map */
3938                 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3939                                 rateptr);
3940         }
3941 }
3942
3943 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3944                                     struct ieee80211_vif *vif,
3945                                     struct ieee80211_bss_conf *conf,
3946                                     u32 changed)
3947 {
3948         struct b43_wl *wl = hw_to_b43_wl(hw);
3949         struct b43_wldev *dev;
3950
3951         mutex_lock(&wl->mutex);
3952
3953         dev = wl->current_dev;
3954         if (!dev || b43_status(dev) < B43_STAT_STARTED)
3955                 goto out_unlock_mutex;
3956
3957         B43_WARN_ON(wl->vif != vif);
3958
3959         if (changed & BSS_CHANGED_BSSID) {
3960                 if (conf->bssid)
3961                         memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3962                 else
3963                         memset(wl->bssid, 0, ETH_ALEN);
3964         }
3965
3966         if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3967                 if (changed & BSS_CHANGED_BEACON &&
3968                     (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3969                      b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3970                      b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3971                         b43_update_templates(wl);
3972
3973                 if (changed & BSS_CHANGED_BSSID)
3974                         b43_write_mac_bssid_templates(dev);
3975         }
3976
3977         b43_mac_suspend(dev);
3978
3979         /* Update templates for AP/mesh mode. */
3980         if (changed & BSS_CHANGED_BEACON_INT &&
3981             (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3982              b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3983              b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
3984             conf->beacon_int)
3985                 b43_set_beacon_int(dev, conf->beacon_int);
3986
3987         if (changed & BSS_CHANGED_BASIC_RATES)
3988                 b43_update_basic_rates(dev, conf->basic_rates);
3989
3990         if (changed & BSS_CHANGED_ERP_SLOT) {
3991                 if (conf->use_short_slot)
3992                         b43_short_slot_timing_enable(dev);
3993                 else
3994                         b43_short_slot_timing_disable(dev);
3995         }
3996
3997         b43_mac_enable(dev);
3998 out_unlock_mutex:
3999         mutex_unlock(&wl->mutex);
4000 }
4001
4002 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4003                           struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4004                           struct ieee80211_key_conf *key)
4005 {
4006         struct b43_wl *wl = hw_to_b43_wl(hw);
4007         struct b43_wldev *dev;
4008         u8 algorithm;
4009         u8 index;
4010         int err;
4011         static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4012
4013         if (modparam_nohwcrypt)
4014                 return -ENOSPC; /* User disabled HW-crypto */
4015
4016         mutex_lock(&wl->mutex);
4017
4018         dev = wl->current_dev;
4019         err = -ENODEV;
4020         if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4021                 goto out_unlock;
4022
4023         if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4024                 /* We don't have firmware for the crypto engine.
4025                  * Must use software-crypto. */
4026                 err = -EOPNOTSUPP;
4027                 goto out_unlock;
4028         }
4029
4030         err = -EINVAL;
4031         switch (key->cipher) {
4032         case WLAN_CIPHER_SUITE_WEP40:
4033                 algorithm = B43_SEC_ALGO_WEP40;
4034                 break;
4035         case WLAN_CIPHER_SUITE_WEP104:
4036                 algorithm = B43_SEC_ALGO_WEP104;
4037                 break;
4038         case WLAN_CIPHER_SUITE_TKIP:
4039                 algorithm = B43_SEC_ALGO_TKIP;
4040                 break;
4041         case WLAN_CIPHER_SUITE_CCMP:
4042                 algorithm = B43_SEC_ALGO_AES;
4043                 break;
4044         default:
4045                 B43_WARN_ON(1);
4046                 goto out_unlock;
4047         }
4048         index = (u8) (key->keyidx);
4049         if (index > 3)
4050                 goto out_unlock;
4051
4052         switch (cmd) {
4053         case SET_KEY:
4054                 if (algorithm == B43_SEC_ALGO_TKIP &&
4055                     (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4056                     !modparam_hwtkip)) {
4057                         /* We support only pairwise key */
4058                         err = -EOPNOTSUPP;
4059                         goto out_unlock;
4060                 }
4061
4062                 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4063                         if (WARN_ON(!sta)) {
4064                                 err = -EOPNOTSUPP;
4065                                 goto out_unlock;
4066                         }
4067                         /* Pairwise key with an assigned MAC address. */
4068                         err = b43_key_write(dev, -1, algorithm,
4069                                             key->key, key->keylen,
4070                                             sta->addr, key);
4071                 } else {
4072                         /* Group key */
4073                         err = b43_key_write(dev, index, algorithm,
4074                                             key->key, key->keylen, NULL, key);
4075                 }
4076                 if (err)
4077                         goto out_unlock;
4078
4079                 if (algorithm == B43_SEC_ALGO_WEP40 ||
4080                     algorithm == B43_SEC_ALGO_WEP104) {
4081                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4082                 } else {
4083                         b43_hf_write(dev,
4084                                      b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4085                 }
4086                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4087                 if (algorithm == B43_SEC_ALGO_TKIP)
4088                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4089                 break;
4090         case DISABLE_KEY: {
4091                 err = b43_key_clear(dev, key->hw_key_idx);
4092                 if (err)
4093                         goto out_unlock;
4094                 break;
4095         }
4096         default:
4097                 B43_WARN_ON(1);
4098         }
4099
4100 out_unlock:
4101         if (!err) {
4102                 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4103                        "mac: %pM\n",
4104                        cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4105                        sta ? sta->addr : bcast_addr);
4106                 b43_dump_keymemory(dev);
4107         }
4108         mutex_unlock(&wl->mutex);
4109
4110         return err;
4111 }
4112
4113 static void b43_op_configure_filter(struct ieee80211_hw *hw,
4114                                     unsigned int changed, unsigned int *fflags,
4115                                     u64 multicast)
4116 {
4117         struct b43_wl *wl = hw_to_b43_wl(hw);
4118         struct b43_wldev *dev;
4119
4120         mutex_lock(&wl->mutex);
4121         dev = wl->current_dev;
4122         if (!dev) {
4123                 *fflags = 0;
4124                 goto out_unlock;
4125         }
4126
4127         *fflags &= FIF_PROMISC_IN_BSS |
4128                   FIF_ALLMULTI |
4129                   FIF_FCSFAIL |
4130                   FIF_PLCPFAIL |
4131                   FIF_CONTROL |
4132                   FIF_OTHER_BSS |
4133                   FIF_BCN_PRBRESP_PROMISC;
4134
4135         changed &= FIF_PROMISC_IN_BSS |
4136                    FIF_ALLMULTI |
4137                    FIF_FCSFAIL |
4138                    FIF_PLCPFAIL |
4139                    FIF_CONTROL |
4140                    FIF_OTHER_BSS |
4141                    FIF_BCN_PRBRESP_PROMISC;
4142
4143         wl->filter_flags = *fflags;
4144
4145         if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4146                 b43_adjust_opmode(dev);
4147
4148 out_unlock:
4149         mutex_unlock(&wl->mutex);
4150 }
4151
4152 /* Locking: wl->mutex
4153  * Returns the current dev. This might be different from the passed in dev,
4154  * because the core might be gone away while we unlocked the mutex. */
4155 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4156 {
4157         struct b43_wl *wl;
4158         struct b43_wldev *orig_dev;
4159         u32 mask;
4160         int queue_num;
4161
4162         if (!dev)
4163                 return NULL;
4164         wl = dev->wl;
4165 redo:
4166         if (!dev || b43_status(dev) < B43_STAT_STARTED)
4167                 return dev;
4168
4169         /* Cancel work. Unlock to avoid deadlocks. */
4170         mutex_unlock(&wl->mutex);
4171         cancel_delayed_work_sync(&dev->periodic_work);
4172         cancel_work_sync(&wl->tx_work);
4173         cancel_work_sync(&wl->firmware_load);
4174         mutex_lock(&wl->mutex);
4175         dev = wl->current_dev;
4176         if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4177                 /* Whoops, aliens ate up the device while we were unlocked. */
4178                 return dev;
4179         }
4180
4181         /* Disable interrupts on the device. */
4182         b43_set_status(dev, B43_STAT_INITIALIZED);
4183         if (b43_bus_host_is_sdio(dev->dev)) {
4184                 /* wl->mutex is locked. That is enough. */
4185                 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4186                 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4187         } else {
4188                 spin_lock_irq(&wl->hardirq_lock);
4189                 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4190                 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4191                 spin_unlock_irq(&wl->hardirq_lock);
4192         }
4193         /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4194         orig_dev = dev;
4195         mutex_unlock(&wl->mutex);
4196         if (b43_bus_host_is_sdio(dev->dev)) {
4197                 b43_sdio_free_irq(dev);
4198         } else {
4199                 synchronize_irq(dev->dev->irq);
4200                 free_irq(dev->dev->irq, dev);
4201         }
4202         mutex_lock(&wl->mutex);
4203         dev = wl->current_dev;
4204         if (!dev)
4205                 return dev;
4206         if (dev != orig_dev) {
4207                 if (b43_status(dev) >= B43_STAT_STARTED)
4208                         goto redo;
4209                 return dev;
4210         }
4211         mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4212         B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4213
4214         /* Drain all TX queues. */
4215         for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
4216                 while (skb_queue_len(&wl->tx_queue[queue_num]))
4217                         dev_kfree_skb(skb_dequeue(&wl->tx_queue[queue_num]));
4218         }
4219
4220         b43_mac_suspend(dev);
4221         b43_leds_exit(dev);
4222         b43dbg(wl, "Wireless interface stopped\n");
4223
4224         return dev;
4225 }
4226
4227 /* Locking: wl->mutex */
4228 static int b43_wireless_core_start(struct b43_wldev *dev)
4229 {
4230         int err;
4231
4232         B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4233
4234         drain_txstatus_queue(dev);
4235         if (b43_bus_host_is_sdio(dev->dev)) {
4236                 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4237                 if (err) {
4238                         b43err(dev->wl, "Cannot request SDIO IRQ\n");
4239                         goto out;
4240                 }
4241         } else {
4242                 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4243                                            b43_interrupt_thread_handler,
4244                                            IRQF_SHARED, KBUILD_MODNAME, dev);
4245                 if (err) {
4246                         b43err(dev->wl, "Cannot request IRQ-%d\n",
4247                                dev->dev->irq);
4248                         goto out;
4249                 }
4250         }
4251
4252         /* We are ready to run. */
4253         ieee80211_wake_queues(dev->wl->hw);
4254         b43_set_status(dev, B43_STAT_STARTED);
4255
4256         /* Start data flow (TX/RX). */
4257         b43_mac_enable(dev);
4258         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4259
4260         /* Start maintenance work */
4261         b43_periodic_tasks_setup(dev);
4262
4263         b43_leds_init(dev);
4264
4265         b43dbg(dev->wl, "Wireless interface started\n");
4266 out:
4267         return err;
4268 }
4269
4270 /* Get PHY and RADIO versioning numbers */
4271 static int b43_phy_versioning(struct b43_wldev *dev)
4272 {
4273         struct b43_phy *phy = &dev->phy;
4274         u32 tmp;
4275         u8 analog_type;
4276         u8 phy_type;
4277         u8 phy_rev;
4278         u16 radio_manuf;
4279         u16 radio_ver;
4280         u16 radio_rev;
4281         int unsupported = 0;
4282
4283         /* Get PHY versioning */
4284         tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4285         analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4286         phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4287         phy_rev = (tmp & B43_PHYVER_VERSION);
4288         switch (phy_type) {
4289         case B43_PHYTYPE_A:
4290                 if (phy_rev >= 4)
4291                         unsupported = 1;
4292                 break;
4293         case B43_PHYTYPE_B:
4294                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4295                     && phy_rev != 7)
4296                         unsupported = 1;
4297                 break;
4298         case B43_PHYTYPE_G:
4299                 if (phy_rev > 9)
4300                         unsupported = 1;
4301                 break;
4302 #ifdef CONFIG_B43_PHY_N
4303         case B43_PHYTYPE_N:
4304                 if (phy_rev > 9)
4305                         unsupported = 1;
4306                 break;
4307 #endif
4308 #ifdef CONFIG_B43_PHY_LP
4309         case B43_PHYTYPE_LP:
4310                 if (phy_rev > 2)
4311                         unsupported = 1;
4312                 break;
4313 #endif
4314 #ifdef CONFIG_B43_PHY_HT
4315         case B43_PHYTYPE_HT:
4316                 if (phy_rev > 1)
4317                         unsupported = 1;
4318                 break;
4319 #endif
4320 #ifdef CONFIG_B43_PHY_LCN
4321         case B43_PHYTYPE_LCN:
4322                 if (phy_rev > 1)
4323                         unsupported = 1;
4324                 break;
4325 #endif
4326         default:
4327                 unsupported = 1;
4328         }
4329         if (unsupported) {
4330                 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4331                        "(Analog %u, Type %u, Revision %u)\n",
4332                        analog_type, phy_type, phy_rev);
4333                 return -EOPNOTSUPP;
4334         }
4335         b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4336                analog_type, phy_type, phy_rev);
4337
4338         /* Get RADIO versioning */
4339         if (dev->dev->core_rev >= 24) {
4340                 u16 radio24[3];
4341
4342                 for (tmp = 0; tmp < 3; tmp++) {
4343                         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4344                         radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4345                 }
4346
4347                 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4348                 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4349
4350                 radio_manuf = 0x17F;
4351                 radio_ver = (radio24[2] << 8) | radio24[1];
4352                 radio_rev = (radio24[0] & 0xF);
4353         } else {
4354                 if (dev->dev->chip_id == 0x4317) {
4355                         if (dev->dev->chip_rev == 0)
4356                                 tmp = 0x3205017F;
4357                         else if (dev->dev->chip_rev == 1)
4358                                 tmp = 0x4205017F;
4359                         else
4360                                 tmp = 0x5205017F;
4361                 } else {
4362                         b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4363                                     B43_RADIOCTL_ID);
4364                         tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4365                         b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4366                                     B43_RADIOCTL_ID);
4367                         tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4368                                 << 16;
4369                 }
4370                 radio_manuf = (tmp & 0x00000FFF);
4371                 radio_ver = (tmp & 0x0FFFF000) >> 12;
4372                 radio_rev = (tmp & 0xF0000000) >> 28;
4373         }
4374
4375         if (radio_manuf != 0x17F /* Broadcom */)
4376                 unsupported = 1;
4377         switch (phy_type) {
4378         case B43_PHYTYPE_A:
4379                 if (radio_ver != 0x2060)
4380                         unsupported = 1;
4381                 if (radio_rev != 1)
4382                         unsupported = 1;
4383                 if (radio_manuf != 0x17F)
4384                         unsupported = 1;
4385                 break;
4386         case B43_PHYTYPE_B:
4387                 if ((radio_ver & 0xFFF0) != 0x2050)
4388                         unsupported = 1;
4389                 break;
4390         case B43_PHYTYPE_G:
4391                 if (radio_ver != 0x2050)
4392                         unsupported = 1;
4393                 break;
4394         case B43_PHYTYPE_N:
4395                 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4396                         unsupported = 1;
4397                 break;
4398         case B43_PHYTYPE_LP:
4399                 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4400                         unsupported = 1;
4401                 break;
4402         case B43_PHYTYPE_HT:
4403                 if (radio_ver != 0x2059)
4404                         unsupported = 1;
4405                 break;
4406         case B43_PHYTYPE_LCN:
4407                 if (radio_ver != 0x2064)
4408                         unsupported = 1;
4409                 break;
4410         default:
4411                 B43_WARN_ON(1);
4412         }
4413         if (unsupported) {
4414                 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4415                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4416                        radio_manuf, radio_ver, radio_rev);
4417                 return -EOPNOTSUPP;
4418         }
4419         b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4420                radio_manuf, radio_ver, radio_rev);
4421
4422         phy->radio_manuf = radio_manuf;
4423         phy->radio_ver = radio_ver;
4424         phy->radio_rev = radio_rev;
4425
4426         phy->analog = analog_type;
4427         phy->type = phy_type;
4428         phy->rev = phy_rev;
4429
4430         return 0;
4431 }
4432
4433 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4434                                       struct b43_phy *phy)
4435 {
4436         phy->hardware_power_control = !!modparam_hwpctl;
4437         phy->next_txpwr_check_time = jiffies;
4438         /* PHY TX errors counter. */
4439         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4440
4441 #if B43_DEBUG
4442         phy->phy_locked = false;
4443         phy->radio_locked = false;
4444 #endif
4445 }
4446
4447 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4448 {
4449         dev->dfq_valid = false;
4450
4451         /* Assume the radio is enabled. If it's not enabled, the state will
4452          * immediately get fixed on the first periodic work run. */
4453         dev->radio_hw_enable = true;
4454
4455         /* Stats */
4456         memset(&dev->stats, 0, sizeof(dev->stats));
4457
4458         setup_struct_phy_for_init(dev, &dev->phy);
4459
4460         /* IRQ related flags */
4461         dev->irq_reason = 0;
4462         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4463         dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4464         if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4465                 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4466
4467         dev->mac_suspended = 1;
4468
4469         /* Noise calculation context */
4470         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4471 }
4472
4473 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4474 {
4475         struct ssb_sprom *sprom = dev->dev->bus_sprom;
4476         u64 hf;
4477
4478         if (!modparam_btcoex)
4479                 return;
4480         if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4481                 return;
4482         if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4483                 return;
4484
4485         hf = b43_hf_read(dev);
4486         if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4487                 hf |= B43_HF_BTCOEXALT;
4488         else
4489                 hf |= B43_HF_BTCOEX;
4490         b43_hf_write(dev, hf);
4491 }
4492
4493 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4494 {
4495         if (!modparam_btcoex)
4496                 return;
4497         //TODO
4498 }
4499
4500 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4501 {
4502         struct ssb_bus *bus;
4503         u32 tmp;
4504
4505         if (dev->dev->bus_type != B43_BUS_SSB)
4506                 return;
4507
4508         bus = dev->dev->sdev->bus;
4509
4510         if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4511             (bus->chip_id == 0x4312)) {
4512                 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4513                 tmp &= ~SSB_IMCFGLO_REQTO;
4514                 tmp &= ~SSB_IMCFGLO_SERTO;
4515                 tmp |= 0x3;
4516                 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4517                 ssb_commit_settings(bus);
4518         }
4519 }
4520
4521 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4522 {
4523         u16 pu_delay;
4524
4525         /* The time value is in microseconds. */
4526         if (dev->phy.type == B43_PHYTYPE_A)
4527                 pu_delay = 3700;
4528         else
4529                 pu_delay = 1050;
4530         if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4531                 pu_delay = 500;
4532         if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4533                 pu_delay = max(pu_delay, (u16)2400);
4534
4535         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4536 }
4537
4538 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4539 static void b43_set_pretbtt(struct b43_wldev *dev)
4540 {
4541         u16 pretbtt;
4542
4543         /* The time value is in microseconds. */
4544         if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4545                 pretbtt = 2;
4546         } else {
4547                 if (dev->phy.type == B43_PHYTYPE_A)
4548                         pretbtt = 120;
4549                 else
4550                         pretbtt = 250;
4551         }
4552         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4553         b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4554 }
4555
4556 /* Shutdown a wireless core */
4557 /* Locking: wl->mutex */
4558 static void b43_wireless_core_exit(struct b43_wldev *dev)
4559 {
4560         B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4561         if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4562                 return;
4563
4564         /* Unregister HW RNG driver */
4565         b43_rng_exit(dev->wl);
4566
4567         b43_set_status(dev, B43_STAT_UNINIT);
4568
4569         /* Stop the microcode PSM. */
4570         b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4571                       B43_MACCTL_PSM_JMP0);
4572
4573         b43_dma_free(dev);
4574         b43_pio_free(dev);
4575         b43_chip_exit(dev);
4576         dev->phy.ops->switch_analog(dev, 0);
4577         if (dev->wl->current_beacon) {
4578                 dev_kfree_skb_any(dev->wl->current_beacon);
4579                 dev->wl->current_beacon = NULL;
4580         }
4581
4582         b43_device_disable(dev, 0);
4583         b43_bus_may_powerdown(dev);
4584 }
4585
4586 /* Initialize a wireless core */
4587 static int b43_wireless_core_init(struct b43_wldev *dev)
4588 {
4589         struct ssb_sprom *sprom = dev->dev->bus_sprom;
4590         struct b43_phy *phy = &dev->phy;
4591         int err;
4592         u64 hf;
4593
4594         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4595
4596         err = b43_bus_powerup(dev, 0);
4597         if (err)
4598                 goto out;
4599         if (!b43_device_is_enabled(dev))
4600                 b43_wireless_core_reset(dev, phy->gmode);
4601
4602         /* Reset all data structures. */
4603         setup_struct_wldev_for_init(dev);
4604         phy->ops->prepare_structs(dev);
4605
4606         /* Enable IRQ routing to this device. */
4607         switch (dev->dev->bus_type) {
4608 #ifdef CONFIG_B43_BCMA
4609         case B43_BUS_BCMA:
4610                 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4611                                       dev->dev->bdev, true);
4612                 break;
4613 #endif
4614 #ifdef CONFIG_B43_SSB
4615         case B43_BUS_SSB:
4616                 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4617                                                dev->dev->sdev);
4618                 break;
4619 #endif
4620         }
4621
4622         b43_imcfglo_timeouts_workaround(dev);
4623         b43_bluetooth_coext_disable(dev);
4624         if (phy->ops->prepare_hardware) {
4625                 err = phy->ops->prepare_hardware(dev);
4626                 if (err)
4627                         goto err_busdown;
4628         }
4629         err = b43_chip_init(dev);
4630         if (err)
4631                 goto err_busdown;
4632         b43_shm_write16(dev, B43_SHM_SHARED,
4633                         B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4634         hf = b43_hf_read(dev);
4635         if (phy->type == B43_PHYTYPE_G) {
4636                 hf |= B43_HF_SYMW;
4637                 if (phy->rev == 1)
4638                         hf |= B43_HF_GDCW;
4639                 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4640                         hf |= B43_HF_OFDMPABOOST;
4641         }
4642         if (phy->radio_ver == 0x2050) {
4643                 if (phy->radio_rev == 6)
4644                         hf |= B43_HF_4318TSSI;
4645                 if (phy->radio_rev < 6)
4646                         hf |= B43_HF_VCORECALC;
4647         }
4648         if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4649                 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4650 #ifdef CONFIG_SSB_DRIVER_PCICORE
4651         if (dev->dev->bus_type == B43_BUS_SSB &&
4652             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4653             dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4654                 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4655 #endif
4656         hf &= ~B43_HF_SKCFPUP;
4657         b43_hf_write(dev, hf);
4658
4659         b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4660                              B43_DEFAULT_LONG_RETRY_LIMIT);
4661         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4662         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4663
4664         /* Disable sending probe responses from firmware.
4665          * Setting the MaxTime to one usec will always trigger
4666          * a timeout, so we never send any probe resp.
4667          * A timeout of zero is infinite. */
4668         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4669
4670         b43_rate_memory_init(dev);
4671         b43_set_phytxctl_defaults(dev);
4672
4673         /* Minimum Contention Window */
4674         if (phy->type == B43_PHYTYPE_B)
4675                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4676         else
4677                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4678         /* Maximum Contention Window */
4679         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4680
4681         if (b43_bus_host_is_pcmcia(dev->dev) ||
4682             b43_bus_host_is_sdio(dev->dev)) {
4683                 dev->__using_pio_transfers = true;
4684                 err = b43_pio_init(dev);
4685         } else if (dev->use_pio) {
4686                 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4687                         "This should not be needed and will result in lower "
4688                         "performance.\n");
4689                 dev->__using_pio_transfers = true;
4690                 err = b43_pio_init(dev);
4691         } else {
4692                 dev->__using_pio_transfers = false;
4693                 err = b43_dma_init(dev);
4694         }
4695         if (err)
4696                 goto err_chip_exit;
4697         b43_qos_init(dev);
4698         b43_set_synth_pu_delay(dev, 1);
4699         b43_bluetooth_coext_enable(dev);
4700
4701         b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4702         b43_upload_card_macaddress(dev);
4703         b43_security_init(dev);
4704
4705         ieee80211_wake_queues(dev->wl->hw);
4706
4707         b43_set_status(dev, B43_STAT_INITIALIZED);
4708
4709         /* Register HW RNG driver */
4710         b43_rng_init(dev->wl);
4711
4712 out:
4713         return err;
4714
4715 err_chip_exit:
4716         b43_chip_exit(dev);
4717 err_busdown:
4718         b43_bus_may_powerdown(dev);
4719         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4720         return err;
4721 }
4722
4723 static int b43_op_add_interface(struct ieee80211_hw *hw,
4724                                 struct ieee80211_vif *vif)
4725 {
4726         struct b43_wl *wl = hw_to_b43_wl(hw);
4727         struct b43_wldev *dev;
4728         int err = -EOPNOTSUPP;
4729
4730         /* TODO: allow WDS/AP devices to coexist */
4731
4732         if (vif->type != NL80211_IFTYPE_AP &&
4733             vif->type != NL80211_IFTYPE_MESH_POINT &&
4734             vif->type != NL80211_IFTYPE_STATION &&
4735             vif->type != NL80211_IFTYPE_WDS &&
4736             vif->type != NL80211_IFTYPE_ADHOC)
4737                 return -EOPNOTSUPP;
4738
4739         mutex_lock(&wl->mutex);
4740         if (wl->operating)
4741                 goto out_mutex_unlock;
4742
4743         b43dbg(wl, "Adding Interface type %d\n", vif->type);
4744
4745         dev = wl->current_dev;
4746         wl->operating = true;
4747         wl->vif = vif;
4748         wl->if_type = vif->type;
4749         memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4750
4751         b43_adjust_opmode(dev);
4752         b43_set_pretbtt(dev);
4753         b43_set_synth_pu_delay(dev, 0);
4754         b43_upload_card_macaddress(dev);
4755
4756         err = 0;
4757  out_mutex_unlock:
4758         mutex_unlock(&wl->mutex);
4759
4760         if (err == 0)
4761                 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4762
4763         return err;
4764 }
4765
4766 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4767                                     struct ieee80211_vif *vif)
4768 {
4769         struct b43_wl *wl = hw_to_b43_wl(hw);
4770         struct b43_wldev *dev = wl->current_dev;
4771
4772         b43dbg(wl, "Removing Interface type %d\n", vif->type);
4773
4774         mutex_lock(&wl->mutex);
4775
4776         B43_WARN_ON(!wl->operating);
4777         B43_WARN_ON(wl->vif != vif);
4778         wl->vif = NULL;
4779
4780         wl->operating = false;
4781
4782         b43_adjust_opmode(dev);
4783         memset(wl->mac_addr, 0, ETH_ALEN);
4784         b43_upload_card_macaddress(dev);
4785
4786         mutex_unlock(&wl->mutex);
4787 }
4788
4789 static int b43_op_start(struct ieee80211_hw *hw)
4790 {
4791         struct b43_wl *wl = hw_to_b43_wl(hw);
4792         struct b43_wldev *dev = wl->current_dev;
4793         int did_init = 0;
4794         int err = 0;
4795
4796         /* Kill all old instance specific information to make sure
4797          * the card won't use it in the short timeframe between start
4798          * and mac80211 reconfiguring it. */
4799         memset(wl->bssid, 0, ETH_ALEN);
4800         memset(wl->mac_addr, 0, ETH_ALEN);
4801         wl->filter_flags = 0;
4802         wl->radiotap_enabled = false;
4803         b43_qos_clear(wl);
4804         wl->beacon0_uploaded = false;
4805         wl->beacon1_uploaded = false;
4806         wl->beacon_templates_virgin = true;
4807         wl->radio_enabled = true;
4808
4809         mutex_lock(&wl->mutex);
4810
4811         if (b43_status(dev) < B43_STAT_INITIALIZED) {
4812                 err = b43_wireless_core_init(dev);
4813                 if (err)
4814                         goto out_mutex_unlock;
4815                 did_init = 1;
4816         }
4817
4818         if (b43_status(dev) < B43_STAT_STARTED) {
4819                 err = b43_wireless_core_start(dev);
4820                 if (err) {
4821                         if (did_init)
4822                                 b43_wireless_core_exit(dev);
4823                         goto out_mutex_unlock;
4824                 }
4825         }
4826
4827         /* XXX: only do if device doesn't support rfkill irq */
4828         wiphy_rfkill_start_polling(hw->wiphy);
4829
4830  out_mutex_unlock:
4831         mutex_unlock(&wl->mutex);
4832
4833         /*
4834          * Configuration may have been overwritten during initialization.
4835          * Reload the configuration, but only if initialization was
4836          * successful. Reloading the configuration after a failed init
4837          * may hang the system.
4838          */
4839         if (!err)
4840                 b43_op_config(hw, ~0);
4841
4842         return err;
4843 }
4844
4845 static void b43_op_stop(struct ieee80211_hw *hw)
4846 {
4847         struct b43_wl *wl = hw_to_b43_wl(hw);
4848         struct b43_wldev *dev = wl->current_dev;
4849
4850         cancel_work_sync(&(wl->beacon_update_trigger));
4851
4852         if (!dev)
4853                 goto out;
4854
4855         mutex_lock(&wl->mutex);
4856         if (b43_status(dev) >= B43_STAT_STARTED) {
4857                 dev = b43_wireless_core_stop(dev);
4858                 if (!dev)
4859                         goto out_unlock;
4860         }
4861         b43_wireless_core_exit(dev);
4862         wl->radio_enabled = false;
4863
4864 out_unlock:
4865         mutex_unlock(&wl->mutex);
4866 out:
4867         cancel_work_sync(&(wl->txpower_adjust_work));
4868 }
4869
4870 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4871                                  struct ieee80211_sta *sta, bool set)
4872 {
4873         struct b43_wl *wl = hw_to_b43_wl(hw);
4874
4875         /* FIXME: add locking */
4876         b43_update_templates(wl);
4877
4878         return 0;
4879 }
4880
4881 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4882                               struct ieee80211_vif *vif,
4883                               enum sta_notify_cmd notify_cmd,
4884                               struct ieee80211_sta *sta)
4885 {
4886         struct b43_wl *wl = hw_to_b43_wl(hw);
4887
4888         B43_WARN_ON(!vif || wl->vif != vif);
4889 }
4890
4891 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4892 {
4893         struct b43_wl *wl = hw_to_b43_wl(hw);
4894         struct b43_wldev *dev;
4895
4896         mutex_lock(&wl->mutex);
4897         dev = wl->current_dev;
4898         if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4899                 /* Disable CFP update during scan on other channels. */
4900                 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4901         }
4902         mutex_unlock(&wl->mutex);
4903 }
4904
4905 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4906 {
4907         struct b43_wl *wl = hw_to_b43_wl(hw);
4908         struct b43_wldev *dev;
4909
4910         mutex_lock(&wl->mutex);
4911         dev = wl->current_dev;
4912         if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4913                 /* Re-enable CFP update. */
4914                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4915         }
4916         mutex_unlock(&wl->mutex);
4917 }
4918
4919 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4920                              struct survey_info *survey)
4921 {
4922         struct b43_wl *wl = hw_to_b43_wl(hw);
4923         struct b43_wldev *dev = wl->current_dev;
4924         struct ieee80211_conf *conf = &hw->conf;
4925
4926         if (idx != 0)
4927                 return -ENOENT;
4928
4929         survey->channel = conf->channel;
4930         survey->filled = SURVEY_INFO_NOISE_DBM;
4931         survey->noise = dev->stats.link_noise;
4932
4933         return 0;
4934 }
4935
4936 static const struct ieee80211_ops b43_hw_ops = {
4937         .tx                     = b43_op_tx,
4938         .conf_tx                = b43_op_conf_tx,
4939         .add_interface          = b43_op_add_interface,
4940         .remove_interface       = b43_op_remove_interface,
4941         .config                 = b43_op_config,
4942         .bss_info_changed       = b43_op_bss_info_changed,
4943         .configure_filter       = b43_op_configure_filter,
4944         .set_key                = b43_op_set_key,
4945         .update_tkip_key        = b43_op_update_tkip_key,
4946         .get_stats              = b43_op_get_stats,
4947         .get_tsf                = b43_op_get_tsf,
4948         .set_tsf                = b43_op_set_tsf,
4949         .start                  = b43_op_start,
4950         .stop                   = b43_op_stop,
4951         .set_tim                = b43_op_beacon_set_tim,
4952         .sta_notify             = b43_op_sta_notify,
4953         .sw_scan_start          = b43_op_sw_scan_start_notifier,
4954         .sw_scan_complete       = b43_op_sw_scan_complete_notifier,
4955         .get_survey             = b43_op_get_survey,
4956         .rfkill_poll            = b43_rfkill_poll,
4957 };
4958
4959 /* Hard-reset the chip. Do not call this directly.
4960  * Use b43_controller_restart()
4961  */
4962 static void b43_chip_reset(struct work_struct *work)
4963 {
4964         struct b43_wldev *dev =
4965             container_of(work, struct b43_wldev, restart_work);
4966         struct b43_wl *wl = dev->wl;
4967         int err = 0;
4968         int prev_status;
4969
4970         mutex_lock(&wl->mutex);
4971
4972         prev_status = b43_status(dev);
4973         /* Bring the device down... */
4974         if (prev_status >= B43_STAT_STARTED) {
4975                 dev = b43_wireless_core_stop(dev);
4976                 if (!dev) {
4977                         err = -ENODEV;
4978                         goto out;
4979                 }
4980         }
4981         if (prev_status >= B43_STAT_INITIALIZED)
4982                 b43_wireless_core_exit(dev);
4983
4984         /* ...and up again. */
4985         if (prev_status >= B43_STAT_INITIALIZED) {
4986                 err = b43_wireless_core_init(dev);
4987                 if (err)
4988                         goto out;
4989         }
4990         if (prev_status >= B43_STAT_STARTED) {
4991                 err = b43_wireless_core_start(dev);
4992                 if (err) {
4993                         b43_wireless_core_exit(dev);
4994                         goto out;
4995                 }
4996         }
4997 out:
4998         if (err)
4999                 wl->current_dev = NULL; /* Failed to init the dev. */
5000         mutex_unlock(&wl->mutex);
5001
5002         if (err) {
5003                 b43err(wl, "Controller restart FAILED\n");
5004                 return;
5005         }
5006
5007         /* reload configuration */
5008         b43_op_config(wl->hw, ~0);
5009         if (wl->vif)
5010                 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5011
5012         b43info(wl, "Controller restarted\n");
5013 }
5014
5015 static int b43_setup_bands(struct b43_wldev *dev,
5016                            bool have_2ghz_phy, bool have_5ghz_phy)
5017 {
5018         struct ieee80211_hw *hw = dev->wl->hw;
5019
5020         if (have_2ghz_phy)
5021                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
5022         if (dev->phy.type == B43_PHYTYPE_N) {
5023                 if (have_5ghz_phy)
5024                         hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
5025         } else {
5026                 if (have_5ghz_phy)
5027                         hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5028         }
5029
5030         dev->phy.supports_2ghz = have_2ghz_phy;
5031         dev->phy.supports_5ghz = have_5ghz_phy;
5032
5033         return 0;
5034 }
5035
5036 static void b43_wireless_core_detach(struct b43_wldev *dev)
5037 {
5038         /* We release firmware that late to not be required to re-request
5039          * is all the time when we reinit the core. */
5040         b43_release_firmware(dev);
5041         b43_phy_free(dev);
5042 }
5043
5044 static int b43_wireless_core_attach(struct b43_wldev *dev)
5045 {
5046         struct b43_wl *wl = dev->wl;
5047         struct pci_dev *pdev = NULL;
5048         int err;
5049         u32 tmp;
5050         bool have_2ghz_phy = false, have_5ghz_phy = false;
5051
5052         /* Do NOT do any device initialization here.
5053          * Do it in wireless_core_init() instead.
5054          * This function is for gathering basic information about the HW, only.
5055          * Also some structs may be set up here. But most likely you want to have
5056          * that in core_init(), too.
5057          */
5058
5059 #ifdef CONFIG_B43_SSB
5060         if (dev->dev->bus_type == B43_BUS_SSB &&
5061             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5062                 pdev = dev->dev->sdev->bus->host_pci;
5063 #endif
5064
5065         err = b43_bus_powerup(dev, 0);
5066         if (err) {
5067                 b43err(wl, "Bus powerup failed\n");
5068                 goto out;
5069         }
5070
5071         /* Get the PHY type. */
5072         switch (dev->dev->bus_type) {
5073 #ifdef CONFIG_B43_BCMA
5074         case B43_BUS_BCMA:
5075                 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5076                 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5077                 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5078                 break;
5079 #endif
5080 #ifdef CONFIG_B43_SSB
5081         case B43_BUS_SSB:
5082                 if (dev->dev->core_rev >= 5) {
5083                         tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5084                         have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5085                         have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5086                 } else
5087                         B43_WARN_ON(1);
5088                 break;
5089 #endif
5090         }
5091
5092         dev->phy.gmode = have_2ghz_phy;
5093         dev->phy.radio_on = true;
5094         b43_wireless_core_reset(dev, dev->phy.gmode);
5095
5096         err = b43_phy_versioning(dev);
5097         if (err)
5098                 goto err_powerdown;
5099         /* Check if this device supports multiband. */
5100         if (!pdev ||
5101             (pdev->device != 0x4312 &&
5102              pdev->device != 0x4319 && pdev->device != 0x4324)) {
5103                 /* No multiband support. */
5104                 have_2ghz_phy = false;
5105                 have_5ghz_phy = false;
5106                 switch (dev->phy.type) {
5107                 case B43_PHYTYPE_A:
5108                         have_5ghz_phy = true;
5109                         break;
5110                 case B43_PHYTYPE_LP: //FIXME not always!
5111 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
5112                         have_5ghz_phy = 1;
5113 #endif
5114                 case B43_PHYTYPE_G:
5115                 case B43_PHYTYPE_N:
5116                 case B43_PHYTYPE_HT:
5117                 case B43_PHYTYPE_LCN:
5118                         have_2ghz_phy = true;
5119                         break;
5120                 default:
5121                         B43_WARN_ON(1);
5122                 }
5123         }
5124         if (dev->phy.type == B43_PHYTYPE_A) {
5125                 /* FIXME */
5126                 b43err(wl, "IEEE 802.11a devices are unsupported\n");
5127                 err = -EOPNOTSUPP;
5128                 goto err_powerdown;
5129         }
5130         if (1 /* disable A-PHY */) {
5131                 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
5132                 if (dev->phy.type != B43_PHYTYPE_N &&
5133                     dev->phy.type != B43_PHYTYPE_LP) {
5134                         have_2ghz_phy = true;
5135                         have_5ghz_phy = false;
5136                 }
5137         }
5138
5139         err = b43_phy_allocate(dev);
5140         if (err)
5141                 goto err_powerdown;
5142
5143         dev->phy.gmode = have_2ghz_phy;
5144         b43_wireless_core_reset(dev, dev->phy.gmode);
5145
5146         err = b43_validate_chipaccess(dev);
5147         if (err)
5148                 goto err_phy_free;
5149         err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5150         if (err)
5151                 goto err_phy_free;
5152
5153         /* Now set some default "current_dev" */
5154         if (!wl->current_dev)
5155                 wl->current_dev = dev;
5156         INIT_WORK(&dev->restart_work, b43_chip_reset);
5157
5158         dev->phy.ops->switch_analog(dev, 0);
5159         b43_device_disable(dev, 0);
5160         b43_bus_may_powerdown(dev);
5161
5162 out:
5163         return err;
5164
5165 err_phy_free:
5166         b43_phy_free(dev);
5167 err_powerdown:
5168         b43_bus_may_powerdown(dev);
5169         return err;
5170 }
5171
5172 static void b43_one_core_detach(struct b43_bus_dev *dev)
5173 {
5174         struct b43_wldev *wldev;
5175         struct b43_wl *wl;
5176
5177         /* Do not cancel ieee80211-workqueue based work here.
5178          * See comment in b43_remove(). */
5179
5180         wldev = b43_bus_get_wldev(dev);
5181         wl = wldev->wl;
5182         b43_debugfs_remove_device(wldev);
5183         b43_wireless_core_detach(wldev);
5184         list_del(&wldev->list);
5185         wl->nr_devs--;
5186         b43_bus_set_wldev(dev, NULL);
5187         kfree(wldev);
5188 }
5189
5190 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5191 {
5192         struct b43_wldev *wldev;
5193         int err = -ENOMEM;
5194
5195         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5196         if (!wldev)
5197                 goto out;
5198
5199         wldev->use_pio = b43_modparam_pio;
5200         wldev->dev = dev;
5201         wldev->wl = wl;
5202         b43_set_status(wldev, B43_STAT_UNINIT);
5203         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5204         INIT_LIST_HEAD(&wldev->list);
5205
5206         err = b43_wireless_core_attach(wldev);
5207         if (err)
5208                 goto err_kfree_wldev;
5209
5210         list_add(&wldev->list, &wl->devlist);
5211         wl->nr_devs++;
5212         b43_bus_set_wldev(dev, wldev);
5213         b43_debugfs_add_device(wldev);
5214
5215       out:
5216         return err;
5217
5218       err_kfree_wldev:
5219         kfree(wldev);
5220         return err;
5221 }
5222
5223 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice)         ( \
5224         (pdev->vendor == PCI_VENDOR_ID_##_vendor) &&                    \
5225         (pdev->device == _device) &&                                    \
5226         (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) &&       \
5227         (pdev->subsystem_device == _subdevice)                          )
5228
5229 static void b43_sprom_fixup(struct ssb_bus *bus)
5230 {
5231         struct pci_dev *pdev;
5232
5233         /* boardflags workarounds */
5234         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5235             bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
5236                 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5237         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5238             bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
5239                 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5240         if (bus->bustype == SSB_BUSTYPE_PCI) {
5241                 pdev = bus->host_pci;
5242                 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5243                     IS_PDEV(pdev, BROADCOM, 0x4320,    DELL, 0x0003) ||
5244                     IS_PDEV(pdev, BROADCOM, 0x4320,      HP, 0x12f8) ||
5245                     IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5246                     IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5247                     IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5248                     IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5249                         bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5250         }
5251 }
5252
5253 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5254 {
5255         struct ieee80211_hw *hw = wl->hw;
5256
5257         ssb_set_devtypedata(dev->sdev, NULL);
5258         ieee80211_free_hw(hw);
5259 }
5260
5261 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5262 {
5263         struct ssb_sprom *sprom = dev->bus_sprom;
5264         struct ieee80211_hw *hw;
5265         struct b43_wl *wl;
5266         char chip_name[6];
5267         int queue_num;
5268
5269         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5270         if (!hw) {
5271                 b43err(NULL, "Could not allocate ieee80211 device\n");
5272                 return ERR_PTR(-ENOMEM);
5273         }
5274         wl = hw_to_b43_wl(hw);
5275
5276         /* fill hw info */
5277         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
5278                     IEEE80211_HW_SIGNAL_DBM;
5279
5280         hw->wiphy->interface_modes =
5281                 BIT(NL80211_IFTYPE_AP) |
5282                 BIT(NL80211_IFTYPE_MESH_POINT) |
5283                 BIT(NL80211_IFTYPE_STATION) |
5284                 BIT(NL80211_IFTYPE_WDS) |
5285                 BIT(NL80211_IFTYPE_ADHOC);
5286
5287         hw->queues = modparam_qos ? B43_QOS_QUEUE_NUM : 1;
5288         wl->mac80211_initially_registered_queues = hw->queues;
5289         hw->max_rates = 2;
5290         SET_IEEE80211_DEV(hw, dev->dev);
5291         if (is_valid_ether_addr(sprom->et1mac))
5292                 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5293         else
5294                 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5295
5296         /* Initialize struct b43_wl */
5297         wl->hw = hw;
5298         mutex_init(&wl->mutex);
5299         spin_lock_init(&wl->hardirq_lock);
5300         INIT_LIST_HEAD(&wl->devlist);
5301         INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5302         INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5303         INIT_WORK(&wl->tx_work, b43_tx_work);
5304
5305         /* Initialize queues and flags. */
5306         for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5307                 skb_queue_head_init(&wl->tx_queue[queue_num]);
5308                 wl->tx_queue_stopped[queue_num] = 0;
5309         }
5310
5311         snprintf(chip_name, ARRAY_SIZE(chip_name),
5312                  (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5313         b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5314                 dev->core_rev);
5315         return wl;
5316 }
5317
5318 #ifdef CONFIG_B43_BCMA
5319 static int b43_bcma_probe(struct bcma_device *core)
5320 {
5321         struct b43_bus_dev *dev;
5322         struct b43_wl *wl;
5323         int err;
5324
5325         dev = b43_bus_dev_bcma_init(core);
5326         if (!dev)
5327                 return -ENODEV;
5328
5329         wl = b43_wireless_init(dev);
5330         if (IS_ERR(wl)) {
5331                 err = PTR_ERR(wl);
5332                 goto bcma_out;
5333         }
5334
5335         err = b43_one_core_attach(dev, wl);
5336         if (err)
5337                 goto bcma_err_wireless_exit;
5338
5339         /* setup and start work to load firmware */
5340         INIT_WORK(&wl->firmware_load, b43_request_firmware);
5341         schedule_work(&wl->firmware_load);
5342
5343 bcma_out:
5344         return err;
5345
5346 bcma_err_wireless_exit:
5347         ieee80211_free_hw(wl->hw);
5348         return err;
5349 }
5350
5351 static void b43_bcma_remove(struct bcma_device *core)
5352 {
5353         struct b43_wldev *wldev = bcma_get_drvdata(core);
5354         struct b43_wl *wl = wldev->wl;
5355
5356         /* We must cancel any work here before unregistering from ieee80211,
5357          * as the ieee80211 unreg will destroy the workqueue. */
5358         cancel_work_sync(&wldev->restart_work);
5359
5360         /* Restore the queues count before unregistering, because firmware detect
5361          * might have modified it. Restoring is important, so the networking
5362          * stack can properly free resources. */
5363         wl->hw->queues = wl->mac80211_initially_registered_queues;
5364         b43_leds_stop(wldev);
5365         ieee80211_unregister_hw(wl->hw);
5366
5367         b43_one_core_detach(wldev->dev);
5368
5369         b43_leds_unregister(wl);
5370
5371         ieee80211_free_hw(wl->hw);
5372 }
5373
5374 static struct bcma_driver b43_bcma_driver = {
5375         .name           = KBUILD_MODNAME,
5376         .id_table       = b43_bcma_tbl,
5377         .probe          = b43_bcma_probe,
5378         .remove         = b43_bcma_remove,
5379 };
5380 #endif
5381
5382 #ifdef CONFIG_B43_SSB
5383 static
5384 int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5385 {
5386         struct b43_bus_dev *dev;
5387         struct b43_wl *wl;
5388         int err;
5389         int first = 0;
5390
5391         dev = b43_bus_dev_ssb_init(sdev);
5392         if (!dev)
5393                 return -ENOMEM;
5394
5395         wl = ssb_get_devtypedata(sdev);
5396         if (!wl) {
5397                 /* Probing the first core. Must setup common struct b43_wl */
5398                 first = 1;
5399                 b43_sprom_fixup(sdev->bus);
5400                 wl = b43_wireless_init(dev);
5401                 if (IS_ERR(wl)) {
5402                         err = PTR_ERR(wl);
5403                         goto out;
5404                 }
5405                 ssb_set_devtypedata(sdev, wl);
5406                 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5407         }
5408         err = b43_one_core_attach(dev, wl);
5409         if (err)
5410                 goto err_wireless_exit;
5411
5412         /* setup and start work to load firmware */
5413         INIT_WORK(&wl->firmware_load, b43_request_firmware);
5414         schedule_work(&wl->firmware_load);
5415
5416       out:
5417         return err;
5418
5419       err_wireless_exit:
5420         if (first)
5421                 b43_wireless_exit(dev, wl);
5422         return err;
5423 }
5424
5425 static void b43_ssb_remove(struct ssb_device *sdev)
5426 {
5427         struct b43_wl *wl = ssb_get_devtypedata(sdev);
5428         struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5429         struct b43_bus_dev *dev = wldev->dev;
5430
5431         /* We must cancel any work here before unregistering from ieee80211,
5432          * as the ieee80211 unreg will destroy the workqueue. */
5433         cancel_work_sync(&wldev->restart_work);
5434
5435         B43_WARN_ON(!wl);
5436         if (wl->current_dev == wldev) {
5437                 /* Restore the queues count before unregistering, because firmware detect
5438                  * might have modified it. Restoring is important, so the networking
5439                  * stack can properly free resources. */
5440                 wl->hw->queues = wl->mac80211_initially_registered_queues;
5441                 b43_leds_stop(wldev);
5442                 ieee80211_unregister_hw(wl->hw);
5443         }
5444
5445         b43_one_core_detach(dev);
5446
5447         if (list_empty(&wl->devlist)) {
5448                 b43_leds_unregister(wl);
5449                 /* Last core on the chip unregistered.
5450                  * We can destroy common struct b43_wl.
5451                  */
5452                 b43_wireless_exit(dev, wl);
5453         }
5454 }
5455
5456 static struct ssb_driver b43_ssb_driver = {
5457         .name           = KBUILD_MODNAME,
5458         .id_table       = b43_ssb_tbl,
5459         .probe          = b43_ssb_probe,
5460         .remove         = b43_ssb_remove,
5461 };
5462 #endif /* CONFIG_B43_SSB */
5463
5464 /* Perform a hardware reset. This can be called from any context. */
5465 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5466 {
5467         /* Must avoid requeueing, if we are in shutdown. */
5468         if (b43_status(dev) < B43_STAT_INITIALIZED)
5469                 return;
5470         b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5471         ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5472 }
5473
5474 static void b43_print_driverinfo(void)
5475 {
5476         const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5477                    *feat_leds = "", *feat_sdio = "";
5478
5479 #ifdef CONFIG_B43_PCI_AUTOSELECT
5480         feat_pci = "P";
5481 #endif
5482 #ifdef CONFIG_B43_PCMCIA
5483         feat_pcmcia = "M";
5484 #endif
5485 #ifdef CONFIG_B43_PHY_N
5486         feat_nphy = "N";
5487 #endif
5488 #ifdef CONFIG_B43_LEDS
5489         feat_leds = "L";
5490 #endif
5491 #ifdef CONFIG_B43_SDIO
5492         feat_sdio = "S";
5493 #endif
5494         printk(KERN_INFO "Broadcom 43xx driver loaded "
5495                "[ Features: %s%s%s%s%s ]\n",
5496                feat_pci, feat_pcmcia, feat_nphy,
5497                feat_leds, feat_sdio);
5498 }
5499
5500 static int __init b43_init(void)
5501 {
5502         int err;
5503
5504         b43_debugfs_init();
5505         err = b43_pcmcia_init();
5506         if (err)
5507                 goto err_dfs_exit;
5508         err = b43_sdio_init();
5509         if (err)
5510                 goto err_pcmcia_exit;
5511 #ifdef CONFIG_B43_BCMA
5512         err = bcma_driver_register(&b43_bcma_driver);
5513         if (err)
5514                 goto err_sdio_exit;
5515 #endif
5516 #ifdef CONFIG_B43_SSB
5517         err = ssb_driver_register(&b43_ssb_driver);
5518         if (err)
5519                 goto err_bcma_driver_exit;
5520 #endif
5521         b43_print_driverinfo();
5522
5523         return err;
5524
5525 #ifdef CONFIG_B43_SSB
5526 err_bcma_driver_exit:
5527 #endif
5528 #ifdef CONFIG_B43_BCMA
5529         bcma_driver_unregister(&b43_bcma_driver);
5530 err_sdio_exit:
5531 #endif
5532         b43_sdio_exit();
5533 err_pcmcia_exit:
5534         b43_pcmcia_exit();
5535 err_dfs_exit:
5536         b43_debugfs_exit();
5537         return err;
5538 }
5539
5540 static void __exit b43_exit(void)
5541 {
5542 #ifdef CONFIG_B43_SSB
5543         ssb_driver_unregister(&b43_ssb_driver);
5544 #endif
5545 #ifdef CONFIG_B43_BCMA
5546         bcma_driver_unregister(&b43_bcma_driver);
5547 #endif
5548         b43_sdio_exit();
5549         b43_pcmcia_exit();
5550         b43_debugfs_exit();
5551 }
5552
5553 module_init(b43_init)
5554 module_exit(b43_exit)